FDMM256GBC-5700

# **microSD 7.1 Specification** 

**(Fx Premium, 3D TLC)** 

**Version 1.0** 

Address: 28 Genting Lane, #09-03/04/05 Platinum 28, Singapore 349585 Tel : +65-6493 5035 Fax : +65-6493 5037 Website: http://www.flexxon.com Email: flexxon@flexxon.com 

ALL RIGHTS ARE STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSLATED TO ANY OTHER FORMS WITHOUT PERMISSION FROM FLEXXON . 

## **Table of Contents** 

||**Table of Contents**|
|---|---|
|**1.**|**General Description ..................................................................................... 3**|
|1.1.|Introduction ...................................................................................................................... 3|
|1.2.|Product Overview ............................................................................................................ 4|
|**2.**|**Product Specifications................................................................................. 5**|
|2.1.|Performance ..................................................................................................................... 5|
|2.2.|Power ............................................................................................................................... 5|
|2.3.|MTBF ............................................................................................................................... 5|
|2.4.|Data Retention.................................................................................................................. 5|
|**3.**|**Environmental Specifications ..................................................................... 6**|
|**4.**|**Electrical Specifications .............................................................................. 7**|
|4.1.|DC Characteristics ........................................................................................................... 7|
|4.1.1.|Bus Operation Conditions .................................................................................... 7|
|4.1.2.|Bus Operation Conditions for PCIe ..................................................................... 8|
|4.1.3.|Bus Signal Line Load ........................................................................................... 8|
|4.1.4.|Power Up Time of Host ....................................................................................... 9|
|4.1.5.|Power Up Time of Card ..................................................................................... 10|
|4.2.|AC Characteristic ........................................................................................................... 10|
|4.2.1.|SD Interface timing (Default) ............................................................................ 11|
|4.2.2.|SD Interface Timing (High-Speed Mode) .......................................................... 12|
|4.2.3.|SD Interface timing (SDR12, SDR25, SDR50 and SDR104 Modes) ............... 13|
|4.2.4.|SD Interface timing (DDR50 Mode) ................................................................. 15|
|**5.**|**Pad Assignment ......................................................................................... 17**|
|5.1.|Pad Assignment and Descriptions.................................................................................. 17|
|5.2.<br>**6.**<br>6.1.<br>**7.**|PCIe Bus ........................................................................................................................ 18<br>**Registers ................................................................................................... 19**<br>Card Register.................................................................................................................. 19<br>**Physical Dimension ................................................................................... 20**|
|**8.**|**Ordering Information ................................................................................ 23**|



## **1. GENERAL DESCRIPTION** 

## **1.1. Introduction** 

Fx Premium microSD 7.0 card comes with 17-pin interface, designed to operate at PCIe interface with a maximum throughput (logical/ Idea performance) to 985MB/s (Gen3x1 Lane). It can alternate communication protocol between the SD Express mode, SD mode and SPI mode. Backward compatible with UHS-I hosts. 

Fx Premium microSD 7.0 card is the first SD card implements PCIe/NVMe interface and protocol. It is the slimmest SSD like storage device with maximum speed of 985MB/s. It is designed for those applications that need extreme high performance like burst mode photo shooting, 8K 10K video recording, mobile devices, VR/AR, drones, gaming application, data-intense wireless communication, mobile computing devices, multi-channel IoT devices and automotive storage. 

3 

## **1.2. Product Overview** 

**==> picture [449 x 633] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||
|---|---|
|❖|Flash|
|￭|3D TLC|
|❖|Capacity|
|￭|128GB up to 256GB|
|❖|Support SD SPI mode|
|❖|Non-Copyrights Protection Mechanism|
|❖|Card removal during read operation will never harm the content|
|❖|Password Protection of cards (optional)|
|❖|Designed for read intensive and write intensive cards|
|❖|Write Protect feature using mechanical switch|
|❖|Built-in write protection features (permanent and temporary) (SD mode only)|
|❖|Write Protect feature using mechanical switch (Full SD Card only)|
|❖|Operation voltage range:|
|￭|VDD1: 2.7V~3.6V, VDD2: 1.70V~1.95V|
|❖|Temperature Range|
|￭|
|Operation: -25°C ~ 85°C|
|￭|
|Storage: -40°C ~ 85°C|
|❖|RoHS Compliant|
|❖|Bus Speed Mode (use PCIe Differential Interface Lines)|
|￭|PCIe with Gen 3 x 1 Lan – Up to 985MB/s|
|￭|Gen3 x1 bus, two differential I/O (1 RX/ 1TX) of 8Gbps transfer for each direction|
|(~1.5% overhead due to 128/120 encoding)|
|❖|Bus Speed Mode (use 4 parallel data lines)|
|￭|UHS-I mode|
|➢|SDR12: SDR up to 25MHz, 1.8V signaling|
|➢|SDR25: SDR up to 50MHz, 1.8V signaling|
|➢|SDR50: 1.8V signaling, frequency up to 100MHz, up to 50 MB/sec|
|➢|SDR104: 1.8V signaling, frequency up to 208MHz, up to 104 MB/sec|
|➢|DDR50: 1.8V signaling, frequency up to 50MHz, sampled on both clock edges, up to 50|
|MB/sec|

**----- End of picture text -----**<br>


4 

## **2. PRODUCT SPECIFICATIONS** 

## **2.1. Performance** 

**Table 2-1 Performance of microSD (Fx Premium)** 

|**Capacity**|**Sequential (Burst Mode)**|**Sequential (Burst Mode)**|**Sequential (Sustained Mode)**|**Sequential (Sustained Mode)**|
|---|---|---|---|---|
||**Read (MB/s)**|**Write (MB/s)**|**Read (MB/s)**|**Write (MB/s)**|
|128GB|810|500|650|60|
|256GB|810|700|650|60|



## **NOTES:** 

1. The performance is obtained from CrystalDiskMark 

2. Samples are made of 3D TLC Flash. 

3. Performance may vary from flash configuration and platform. 

4. The PCIe performance was measured by direct connecting to mother board reader 

5. The Burst mode size is the 1/8 capacity. 

## **2.2. Power** 

**Table 2-2 Maximum Power Consumption of microSD (Fx Premium)** 

|**Capacity**|**Read (mA)**|**Write (mA)**|**Standby**<br>**(mA)**|
|---|---|---|---|
|128GB|400|400|1|
|256GB|400|400|1|



## **NOTES:** 

1. Power consumption may vary from flash configuration and platform. 

## **2.3. MTBF** 

MTBF, an acronym for Mean Time Between Failures, is a measure of a device’s reliability. Its value represents the average time between a repair and the next failure. The higher the MTBF value, the higher the reliability of the device. The predicted result of FLEXXON’s SD Express Series SD is more than 3,000,000 hours. 

## **2.4. Data Retention** 

- 10 years if > 90% life remaining (@25C) 

- 1 year if < 10% life remaining (@25C) 

5 

## **3. ENVIRONMENTAL SPECIFICATIONS** 

|**Test Items**|**Test Conditions**|
|---|---|
|**Storage Temperature**|-40°C ~ 85°C|
|**Operating Temperature**|-25°C ~ 85°C|
|**Storage Humidity**|40°C, 93% RH|
|**Operating Humidity**|25°C, 95% RH|
|**Shock**|500G, Half Sin Pulse Duration 1ms|
|**Vibration**|80Hz ~ 2000Hz/20G, 20Hz ~ 80Hz/1.52mm, 3 axis/30min|
|**Drop**|150cm free fall, 6 face of each unit|
|**Bending**|≥ 10N, Hold 1 min/5 times|
|**Torque**|0.15N-m or +/-2.5 deg, Hold 30 seconds/5 times|
|**Salt Spray**|Concentration: 3% NaCl, Temperature: 35°C, 24hours|
|**Waterproof**|Water temperature: 25°C<br>Water depth: The lowest point of unit is locating<br>1000mm below surface.<br>Storage for 30 mins|
|**X-Ray**|0.1 Gy of medium-energy radiation (70 keV to 140 keV,<br>cumulative dose per year) to both sides of the card<br>Storage for 30 mins|
|**Durability**|10,000 times|
|**ESD**|Contact: +/- 4KV each item 25 times<br>Air: +/- 8KV 10 times|



6 

## **4. ELECTRICAL SPECIFICATIONS** 

## **4.1. DC Characteristics** 

## **4.1.1. Bus Operation Conditions** 

**Table 4-1 Threshold Level for High Voltage Range** 

|**Parameter**|**Symbol**|**Min.**|**Max**|**Unit**|**Condition**|
|---|---|---|---|---|---|
|Supply Voltage|VDD|2.7|3.6|V||
|Output High Voltage|VOH|0.75*VDD||V|IOH=-2mA VDDMin|
|Output Low Voltage|VOL||0.125*VDD|V|IOL=2mA VDDMin|
|Input High Voltage|VIH|0.625*VDD|VDD+0.3|V||
|Input Low Voltage|VIL|VSS-0.3|0.25*VDD|V||
|Power Up Time|||250|ms|From 0V to VDDmin|



**Table 4-2 Peak Voltage and Leakage Current** 

|**Parameter**|**Symbol**|**Min**|**Max.**|**Unit**|**Remarks**|
|---|---|---|---|---|---|
|Peak voltage on all lines||-0.3|VDD+0.3|V||
|**All Inputs**||||||
|Input Leakage Current||-10|10|uA||
|**All Outputs**||||||
|Output Leakage Current||-10|10|uA||



**Table 4-3 Threshold Level for 1.8V Signaling** 

|**Parameter**|**Symbol**|**Min.**|**Max**|**Unit**|**Condition**|
|---|---|---|---|---|---|
|Supply Voltage|VDD|2.7|3.6|V||
|Regulator Voltage|VDDIO|1.7|1.95|V|Generated by VDD|
|Output High Voltage|VOH|1.4|-|V|IOH=-2mA|
|Output Low Voltage|VOL|-|0.45|V|IOL=2mA|
|Input High Voltage|VIH|1.27|2.00|V||
|Input Low Voltage|VIL|Vss-0.3|0.58|V||



## **Table 4-4 Input Leakage Current for 1.8V Signaling** 

|**Parameter**|**Symbol**|**Min**|**Max.**|**Unit**|**Remarks**|
|---|---|---|---|---|---|
|Input Leakage Current||-2|2|uA|DAT3 pull-up is<br>disconnected.|



7 

## **4.1.2. Bus Operation Conditions for PCIe** 

**Table 4-5 Bus Operation Conditions of VDD3** 

|**Parameter**|**Symbol**|**Min**|**Max.**|**Unit**|**Remarks**|
|---|---|---|---|---|---|
|Supply Voltage|**VDD2**|1.14|1.3|**V**|**-**|
|Capacitance connected to<br>VDD2|**CC2**|-|2|**uF**|**-**|
|Host capacitance<br>recommended for VDD3|**Ch3**|22|-|**uF**|**-**|



## **4.1.3. Bus Signal Line Load** 

## **Bus Operation Conditions – Signal Line’s Load** 

Total Bus Capacitance = CHOST + CBUS + N CCARD 

|**Parameter**|**symbol**|**Min**|**Max**|**Unit**|**Remark**|
|---|---|---|---|---|---|
|Pull-up resistance|RCMD<br>RDAT|10|100|kΩ|to prevent bus floating|
|Total bus capacitance for each signal<br>line|CL||40|pF|1 card<br>CHOST+CBUSshall<br>not exceed 30 pF|
|Card Capacitance for each signal pin|CCARD||10|pF||
|Maximum signal line inductance|||16|nH||
|Pull-up resistance inside card (pin1)|RDAT3|10|90|kΩ|May be used for card<br>detection|
|Capacity Connected to Power Line|CC||5|uF|To prevent inrush current|



8 

## **4.1.4. Power Up Time of Host** 

Host needs to keep power line level less than 0.5V and more than 1ms before power ramp up. 

## **Power On or Power Cycle** 

Followings are requirements for Power on and Power cycle to assure a reliable SD Card hard reset. 

- (1) Voltage level shall be below 0.5V 

- (2) Duration shall be at least 1ms. 

## **Power Supply Ramp Up** 

The power ramp up time is defined from 0.5V threshold level up to the operating supply voltage which is stable between VDD (min.) and VDD (max.) and host can supply SDCLK. 

Followings are recommendation of Power ramp up: 

- (1) Voltage of power ramp up should be monotonic as much as possible. 

- (2) The minimum ramp up time should be 0.1ms. 

- (3) The maximum ramp up time should be 35ms for 2.7-3.6V power supply. 

- (4) Host shall wait until VDD is stable. 

- (5) After 1ms VDD stable time, host provides at least 74 clocks before issuing the first command. 

## **Power Down and Power Cycle** 

- When the host shuts down the power, the card VDD shall be lowered to less than 0.5Volt for a minimum period of 1ms. During power down, DAT, CMD, and CLK should be disconnected or driven to logical 0 by the host to avoid a situation that the operating current is drawn through the signal lines. 

- If the host needs to change the operating voltage, a power cycle is required. Power cycle means the power is turned off and supplied again. Power cycle is also needed for accessing cards that are already in _Inactive State._ To create a power cycle the host shall follow the power down description before power up the card (i.e. the card VDD shall be once lowered to less than 0.5Volt for a minimum period of 1ms). 

9 

## **4.1.5. Power Up Time of Card** 

A device shall be ready to accept the first command within 1ms from detecting VDD min. Device may use up to 74 clocks for preparation before receiving the first command. 

## **4.2. AC Characteristic** 

10 

## **4.2.1. SD Interface timing (Default)** 

|**Parameter**|**Symbol**|**Min**|**Max**|**Unit**|**Remark**|
|---|---|---|---|---|---|
|**Clock CLK(All values are referred to min(VIH) and max(VIL)**||||||
|Clock frequency Data<br>Transfer Mode|fPP|0|25|MHz|Ccard≤ 10 pF<br>(1 card)|
|Clock frequency<br>Identification Mode|fOD|0(1)/100|400|KHz|Ccard≤ 10 pF<br> (1 card)|
|Clock low time|tWL|10||ns|Ccard≤ 10 pF<br> (1 card)|
|Clock high time|tWH|10||ns|Ccard≤ 10 pF<br> (1 card)|
|Clock rise time|tTLH||10|ns|Ccard≤ 10 pF<br> (1 card)|
|Clock fall time|tTHL||10|ns|Ccard≤ 10 pF<br> (1 card)|
|**Inputs CMD, DAT(referenced to CLK)**||||||
|Input set-up time|tISU|5||ns|Ccard≤ 10 pF<br> (1 card)|



11 

|FLIESOn"||||||
|---|---|---|---|---|---|
|Input hold time|tIH|5||ns|Ccard≤ 10 pF<br> (1 card)|
|**Outputs CMD, DAT(referenced to CLK)**||||||
|Output Delay time during<br>Data Transfer Mode|tODLY|0|14|ns|CL≤ 40 pF<br>(1 card)|
|Output Delay time during<br>Identification Mode|tODLY|0|50|ns|CL≤ 40 pF<br>(1 card)|



(1) 0Hz means to stop the clock. The given minimum frequency range is for cases where continues clock is required. 

## **4.2.2. SD Interface Timing (High-Speed Mode)** 

12 

|**Parameter**<br>~~Pf~~|**Symbol**<br>~~Pf~~|**Min**<br>~~Pf~~|**Max**<br>~~Pf~~|**Unit**<br>~~Pf~~|**Remark**<br>~~Pf~~|
|---|---|---|---|---|---|
|**Clock CLK(All values are referred to min(VIH) and max(VIL)**<br>~~|~~||||||
|Clock frequency Data Transfer Mode<br>~~|~~|fPP<br>~~|~~|0<br>~~|~~|50<br>~~|~~|MHz<br>~~|~~|Ccard≤ 10 pF<br>(1 card)<br>~~|~~|
|Clock low time|tWL|7||ns|Ccard≤ 10 pF<br> (1 card)|
|Clock high time|tWH|7||ns|Ccard≤ 10 pF<br> (1 card)|
|Clock rise time|tTLH||3|ns|Ccard≤ 10 pF<br> (1 card)|
|Clock fall time|tTHL||3|ns|Ccard≤ 10 pF<br> (1 card)|
|**Inputs CMD, DAT(referenced to CLK)**<br>~~Ae~~||||||
|Input set-up time|tISU|6||ns|Ccard≤ 10 pF<br> (1 card)|
|Input hold time|tIH|2|~~>~~|ns|Ccard≤ 10 pF<br> (1 card)|
|**Outputs CMD, DAT(referenced to CLK)**<br>~~ee,~~<br>~~>~~||||||
|Output Delay time during Data<br>Transfer Mode<br>~~ee,~~|tODLY<br>~~ee,~~|~~ee,~~|14<br>~~ee,~~<br>~~>~~|ns<br>~~ee,~~|CL≤ 40 pF<br>(1 card)<br>~~ee,~~|
|Output Hold time|TOH|2.5||ns|CL≤ 15 pF<br>(1 card)|
|Total System capacitance of each<br>line¹|CL||40|pF|CL ≤ 15 pF<br>(1 card)|



(1) In order to satisfy severe timing, the host shall drive only one card. 

## **4.2.3. SD Interface timing (SDR12, SDR25, SDR50 and SDR104 Modes)** 

## _**Input:**_ 

|**Symbol**|**Min**|**Max**|**Unit**|**Remark**|
|---|---|---|---|---|
|tCLK|4.80|-|ns|208MHz(Max.),Between risingedge,VCT= 0.975V|
|tCR, tCF|-|0.2* tCLK|ns|tCR, tCF< 0.96ns (max.) at 208MHz, CCARD=10pF<br>tCR, tCF< 2.00ns (max.) at 100MHz, CCARD=10pF<br>The absolute maximum value of tCR, tCFis 10ns<br>regardless of clock frequency|
|Clock Duty|30|70|%||



13 

**==> picture [243 x 11] intentionally omitted <==**

**----- Start of picture text -----**<br>
SDR12, SDR25, SDR50 and SDR104 Input Timing:<br>**----- End of picture text -----**<br>


|**Symbol**|**Min**|**Max**|**Unit**|**SDR104 Mode**|
|---|---|---|---|---|
|tIS|1.40|-|ns|CCARD=10pF,VCT= 0.975V|
|tIH|0.8|-|ns|CCARD= 5pF,VCT= 0.975V|
|**Symbol**|**Min**|**Max**|**Unit**|**SDR50 Mode**|
|tIS|3.00|-|ns|CCARD=10pF,VCT= 0.975V|
|tIH|0.8|-|ns|CCARD= 5pF,VCT= 0.975V|



## _**Output**_ **(SDR12, SDR25, SDR50)** _**:**_ 

|**Symbol**|**Min**|**Max**|**Unit**|**Remark**|
|---|---|---|---|---|
|tODLY|-|7.5|ns|tCLK>=10.0ns,CL=30pF,usingdriver Type B,for SDR50|
|tODLY|-|14|ns|tCLK>=20.0ns, CL=40pF, using driver Type B, for SDR25 and<br>SDR12,|
|TOH|1.5|-|ns|Hold time at the tODLY (min.),CL=15pF|



14 

## _**Output (SDR104 Mode):**_ 

||**Symbol**|**Min**|**Max**|**Unit**||**Remark**|
|---|---|---|---|---|---|---|
||tOP|0|2|Ul||Card Output Phase|
||△tOP|-350|+1550|ps||Delayvariable due to temperature change after tuning|
||tODW|0.60|-|Ul||tODW= 2.88ns at 208MHz|
|**4.2.4. SD Interface timing (DDR50 Mode)**|||||**SD Interface timing (DDR50 Mode)**||



|**Symbol**|**Min**|**Max**|**Unit**|**Remark**|
|---|---|---|---|---|
|tCLK|20|-|ns|50MHz (Max.), Between rising edge|
|tCR, tCF|-|0.2* tCLK|ns|tCR, tCF< 4.00ns (max.) at 50MHz, CCARD=10pF|
|Clock Duty|45|55|%||



15 

|**Parameter**|**Symbol**|**Min**|**Max**|**Unit**|**Remark**|
|---|---|---|---|---|---|
|**Input CMD**(referenced to CLK risingedge)||||||
|Input set-up time|tISU|3|-|ns|Ccard≤ 10 pF<br> (1 card)|
|Input hold time|tIH|0.8|-|ns|Ccard≤ 10 pF<br> (1 card)|
|**Output CMD**(referenced to CLK risingedge)||||||
|Output Delay time<br>during Data Transfer<br>Mode|tODLY||13.7|ns|CL≤ 30 pF<br>(1 card)|
|Output Hold time|TOH|1.5|-|ns|CL≥ 15 pF<br>(1 card)|
|**Inputs DAT**(referenced to CLK risingand fallingedges)||||||
|Input set-up time|tISU2x|3|-|ns|Ccard≤ 10 pF<br> (1 card)|
|Input hold time|tIH2x|0.8|-|ns|Ccard≤ 10 pF<br> (1 card)|
|**Outputs DAT**(referenced to CLK risingand fallingedges)||||||
|Output Delay time<br>during Data Transfer<br>Mode|tODLY2x|-|7.0|ns|CL≤ 25 pF<br>(1 card)|
|Output Hold time|TOH2x|1.5|-|ns|CL≥ 15 pF<br>(1 card)|



16 

## **5. PAD ASSIGNMENT** 

## **5.1. Pad Assignment and Descriptions** 

**Table 5-1 1-Lane microSD Express Interface Memory Card Pad Assignment** 

|**pin**<br>~~a~~|**SD Mode**<br>~~a~~<br>~~a~~|**SD Mode**<br>~~a~~<br>~~a~~|**SD Mode**<br>~~a~~<br>~~a~~|**PCIe Mode**<br>~~a~~<br>~~a~~|**PCIe Mode**<br>~~a~~<br>~~a~~|**PCIe Mode**<br>~~a~~<br>~~a~~|
|---|---|---|---|---|---|---|
||**Name**<br>~~a~~|**Type1 **<br>~~a~~|**Description**<br>~~a~~|**Name**<br>|**Type**<br>~~a~~|**Description**<br>~~a~~|
|**1**<br>~~a~~|DAT2<br>~~a~~|I/O<br>~~a~~|Data Line<br>~~a~~|DAT2/CLKREQ#<br>|I/O<br>~~a~~|Data Line/Reference<br>clock request signal.<br>~~a~~|
|**2**<br>~~a~~|CD/DAT3<br>~~a~~|I/O<br>~~a~~|Card Detect/Data Line<br>~~a ~~|CD/DAT3/PERST#<br>|I/O<br> ~~a~~|Card Detect/Data<br>Line/Power Enable<br>Reset<br>~~a~~|
|**3**<br>~~ee~~<br>~~|~~|CDM<br>~~ee~~<br>~~|~~|I/O<br>~~ee~~<br>~~fp~~|Command/Response<br>~~ee~~<br>~~fpONS~~|CMD<br>~~ee~~<br>~~ONS~~|I/O<br>~~ee~~|Command/Response<br>~~ee~~|
|**4**<br>~~ee~~<br>~~|~~<br>~~_~~<br>~~|~~|VDD<br>~~ee~~<br>~~|~~<br>~~|~~|S<br>~~ee~~<br>~~fp~~<br>||Supply voltage (3.3V)<br>~~ee~~<br>~~fpONS~~<br>~~Nee~~|VDD1<br>~~ee~~<br>~~ONS~~|S<br>~~ee~~|Supply voltage (3.3V)<br>~~ee~~|
|**5**<br>~~|~~<br>~~_~~<br>~~|~~<br>~~p~~<br>~~|~~|CLK<br>~~|~~<br>~~|~~<br>~~|~~|I<br>~~fp~~<br>|<br>~~Li~~|Clock<br>~~fp ONS~~<br>~~Nee~~<br>~~Li\y~~|CLK<br>~~ONS~~<br>~~|~~|I|Clock|
|**6**<br>~~_~~<br>~~|~~<br>~~p~~<br>~~|~~<br>~~p~~<br>~~|~~|VSS<br>~~|~~<br>~~|~~<br>~~|~~|S<br>|<br>~~Li~~<br>~~aN~~|Supply voltage ground<br>~~Nee~~<br>~~Li\y~~<br>~~aN~~|VSS<br>~~|~~<br>~~aN~~|S<br>~~aN~~|Supply voltage ground<br>~~aN~~|
|**7**<br>~~p~~<br>~~|~~<br>~~p~~<br>~~|~~<br>~~|~~|DAT0<br>~~|~~<br>~~|~~<br>~~[4~~|I/O<br>~~Li~~<br>~~aN~~<br>~~[4[Ss~~|Data Line<br>~~Li \y ~~<br>~~aN~~<br>~~[Ss~~<br>~~|~~|DAT0/REFCLK+<br> ~~|~~<br>~~aN~~<br>~~|~~|I/O<br>~~aN~~|Data Line/PCIe Ref Clock<br>~~aN~~|
|**8**<br>~~p~~<br>~~|~~<br>~~|~~<br>~~a~~|DAT1<br>~~|~~<br>~~[4~~<br>~~a~~|I/O<br>~~aN~~<br>~~[4[Ss~~<br>~~ie a~~|Data Line<br>~~aN~~<br>~~[Ss~~<br>~~|~~<br>~~a~~|DAT1/REFCLK-<br>~~aN~~<br>~~|~~|I/O<br>~~aN~~|Data Line/PCIe Ref Clock<br>~~aN~~|
|**9**<br>~~|~~<br>~~a~~<br>~~|~~|-<br>~~[4~~<br>~~a~~<br>~~Ap~~|-<br>~~[4 [Ss~~<br>~~ie a~~<br>~~ApYP~~|Not Used<br>~~[Ss~~<br>~~|~~<br>~~a~~<br>~~YP~~<br>~~UP~~|VDD2<br>~~|~~<br>~~UP~~|S|Supply voltage (1.8V)|
|**10**<br>~~a~~<br>~~|~~<br>~~le~~|-<br>~~a ~~<br>~~Ap~~<br>~~le~~|-<br> ~~ie a~~<br>~~ApYP~~<br>|Not Used<br>~~a~~<br>~~YP~~<br>~~UP~~<br>|VSS<br>~~UP~~<br>|S<br>|Supply voltage ground<br>|
|**11**<br>~~|~~<br>~~le~~<br>~~ANY~~|-<br>~~Ap~~<br>~~le“NAT~~<br>~~ANY~~|-<br>~~Ap YP~~<br>~~“NAT~~<br>~~ANY |~~|Not Used<br>~~YP~~<br>~~UP~~<br>~~“NAT~~<br>~~|~~|PCIe_Tx+<br>~~UP~~<br>~~“NAT~~|I<br>~~“NAT~~|PCIe transmit lane<br>~~“NAT~~|
|**12**<br>~~le~~<br>~~ANY~~|-<br>~~le~~<br>~~ANY~~|-<br><br>~~ANY |~~|Not Used<br><br>~~|~~|PCIe_Tx-<br>|I<br>|PCIe transmit lane<br>|
|**13**<br>~~ANY~~<br>~~ee~~|-<br>~~ANY~~<br>~~ee~~|-<br>~~ANY |~~<br>~~ee~~|Not Used<br>~~|~~<br>~~ee~~|VSS<br>~~ee~~|S<br>~~ee~~|Supply voltage ground<br>~~ee~~|
|**14**<br>~~a~~|-<br>~~a~~|-|Not Used|PCIe_Rx-|O|PCIe receive lane|
|**15**<br>~~|~~|-<br>~~|~~||-<br>~~fp~~|Not Used<br>~~fp~~|PCIe_Rx+|O|PCIe receive lane|
|**16**<br>~~|~~<br>~~|}~~|-<br>|<br>~~|}~~|-<br>~~fp~~<br>~~|}|~~|Not Used<br>~~fp~~<br>~~|~~|VSS|S|Supply voltage ground|
|**17**<br>~~|}~~|-<br>~~|}~~|-<br>~~|}|~~|Not Used<br>~~|~~|-|-|Not Used|



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- (1)  S: power supply, I: input; O: output using push-pull drivers; PP: I/O using push-pull drivers; OD: I/O using Open Drain drivers; IDS: Input Differential Signal; ODS: Output Differential Signal. 

- (2)  The extended DAT lines (DAT1-DAT3) are input on power up. They start to operate as DAT lines after SET_BUS_WIDTH command. The Host shall keep its own DAT1-DAT3 lines in input mode as well while they are not used. It is defined so in order to keep compatibility to MultiMedia Cards. 

- (3)  At power up, this line has a 50KOhm pull up enabled in the card. This resistor serves two functions: Card detection and Mode Selection. For Mode Selection, the host can drive the line high or let it be pulled high to select SD mode. If the host wants to select SPI mode, it should drive the line low. For Card detection, the host detects that the line is pulled high. This pull-up should be disconnected by the user during regular data transfer with SET_CLR_CARD_DETECT (ACMD42) command. 

- (4)  Pin2 and Pin5 shall not be kept open by host in PCIe Mode. 

## **5.2. PCIe Bus** 

Refer to PCI Express standard defined by the PCI-SIG. The command layer used by the PCIe interface is NM Express(NVMe) and standard defined by the NVM Express. 

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## **6. REGISTERS** 

## **6.1. Card Register** 

|**Name**|**Width**|**Description**|
|---|---|---|
|CID|128bit|Card identification number; card individual number for identification.|
|RCA1|16bit|Relative card address; local system address of a card, dynamically<br>suggested by the card and approved by the host during initialization.|
|DSR|16bit|Driver Stage Register; to configure the card’s output drivers.|
|CSD|128bit|Card Specific Data; Information about the card operation conditions.|
|SCR|64bit|SD Configuration Register; Information about the SD Memory Card's<br>Special Features capabilities|
|OCR|32bit|Operation conditions register.|
|SSR|512bit|SD Status; Information about the card proprietary features.|
|CSR|32bit|Card Status; Information about the card status.|



(1) RCA register is not used (or available) in SPI mode. 

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## **7. PHYSICAL DIMENSION** 

**Dimension: 15mm(L) x 11mm(W) x 1mm(H)** 

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iNENSION J. 

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## **8. ORDERING INFORMATION** 

|**Capacity**|**MPN**|
|---|---|
|128GB|FDMM128GBC-5700|
|256GB|FDMM256GBC-5700|



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**==> picture [287 x 67] intentionally omitted <==**

**----- Start of picture text -----**<br>
Revision History<br>Revision  Release Date  Description<br>1.0  2024/12  First release<br>**----- End of picture text -----**<br>


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