FDMM064GBC-3200

## **microSD 6.10 Specification** 

**(FxAdv II Series, 3D TLC)** 

**Version 1.3** 

Address: 28 Genting Lane, #09-03/04/05 Platinum 28, Singapore 349585 Tel : +65-6493 5035 Fax : +65-6493 5037 Website: http://www.flexxon.com Email: flexxon@flexxon.com 

ALL RIGHTS ARE STRICTLY RESERVED. ANY PORTION OF THIS PAPER SHALL NOT BE REPRODUCED, COPIED, OR TRANSLATED TO ANY OTHER FORMS WITHOUT PERMISSION FROM FLEXXON. 

## **Table of Contents** 

||**Table of Contents**|
|---|---|
|**1.**|**General Description ................................................................................... 3**|
|1.1.|Introduction ...................................................................................................................... 3|
|1.2.|Product Overview ............................................................................................................ 3|
|**2.**|**Product Specifications ............................................................................... 5**|
|2.1.|Performance ..................................................................................................................... 5|
|2.2.|Power ............................................................................................................................... 5|
|2.3.|MTBF ............................................................................................................................... 6|
|2.4.|Data Retention.................................................................................................................. 6|
|**3.**|**Environmental Specifications ..................................................................... 7**|
|**4.**|**Electrical Specifications ............................................................................. 8**|
|4.1.|Absolute Maximum Rating .............................................................................................. 8|
|4.2.|DC Characteristics ........................................................................................................... 8|
|4.2.1.|Bus Operation Conditions for 3.3V Signaling ..................................................... 8|
|4.2.2.|Bus Signal Line Load ........................................................................................... 9|
|4.2.3.|Power Up Time of Host ....................................................................................... 9|
|4.2.4.|Power Up Time of Card ..................................................................................... 10|
|4.3.|AC Characteristic ........................................................................................................... 11|
|4.3.1.|microSD Interface timing (Default) ................................................................... 11|
|4.3.2.|microSD Interface Timing (High-Speed Mode) ................................................ 13|
|4.3.3.|microSD Interface timing (SDR12, SDR25, SDR50 and SDR104 Modes) ...... 14|
|4.3.4.|microSD Interface timing (DDR50 Mode) ........................................................ 16|
|**5.**|**Pad Assignment ....................................................................................... 18**|
|**6.**|**Registers .................................................................................................. 19**|
|**7.**<br>**8.**|**Physical Dimension .................................................................................. 20**<br>**Ordering Information ............................................................................... 22**|



2 

## **1. GENERAL DESCRIPTION** 

## **1.1. Introduction** 

FLEXXON FxAdv II Series microSD 6.1 card is designed for excellent random performance applications, which has good sequential performance, ultimate random performance, high reliability and wide compatibility. It is compliant with the Application performance class (A2) which supports high random performance of at least 4000 read IOPS and 2000 write IOPS. It is suitable for Full HD and 4K Video Recording application. 

## **1.2. Product Overview** 

❖ **Flash** ￭ 3D TLC ❖ **Capacity** ￭ 32GB up to 512GB ❖ **Support SD system specification version 6.10** ❖ **Support SD SPI mode** ❖ **Support CPRM (Content Protection for Recordable Media) of SD Card (optional)** ❖ **Card removal during read operation will never harm the content** ❖ **Password Protection of cards (optional)** ❖ **Built-in write protection features (permanent and temporary)** ❖ **Support Dynamic and Static Wear Leveling** ❖ **Temperature Range** ￭ Operation: -25°C ~ 85°C ￭ Storage: -40°C ~ 85°C ❖ **RoHS Compliant** 

3 

## ❖ **Bus Speed Mode** 

- ￭ **UHS-I mode** 

   - ➢ SDR12: SDR up to 25MHz, 1.8V signaling 

   - ➢ SDR25: SDR up to 50MHz, 1.8V signaling 

   - ➢ SDR50: 1.8V signaling, frequency up to 100MHz, up to 50 MB/sec 

   - ➢ SDR104: 1.8V signaling, frequency up to 208MHz, up to 104 MB/sec 

   - ➢ DDR50: 1.8V signaling, frequency up to 50MHz, sampled on both clock edges, up to 50 

      - MB/sec 

4 

## **2. PRODUCT SPECIFICATIONS** 

## **2.1. Performance** 

## **Table 2-1 Performance of microSD (FxAdv II)** 

|**Capacity**|**A2**|**A2**|**Sequential**|**Sequential**|
|---|---|---|---|---|
||**Read (IOPS)**|**Write (IOPS)**|**Read (MB/s)**|**Write (MB/s)**|
|32GB|9800|2300|100|53|
|64GB|9800|2300|100|53|
|128GB|9800|2600|100|90|
|256GB|9800|2700|100|90|
|512GB|9800|2700|100|90|



## **NOTES:** 

1. The performance is obtained from TestMetrix Test. 

2. Samples are made of Toshiba 3D NAND Flash. 

3. Performance may vary from flash configuration and platform. 

## **2.2. Power** 

**Table 2-2 Typical Power Consumption of microSD (FxAdv II)** 

|**Capacity**|**Read (mA)**|**Write (mA)**|**Standby**<br>**(mA)**|
|---|---|---|---|
|32GB|80|80|0.1|
|64GB|80|80|0.1|
|128GB|100|100|0.1|
|256GB|100|100|0.1|
|512GB|100|100|0.1|



## **NOTES:** 

1. Power consumption may vary from flash configuration and platform. 

5 

## **2.3. MTBF** 

MTBF, an acronym for Mean Time Between Failures, is a measure of a device’s reliability. Its value represents the average time between a repair and the next failure. The higher the MTBF value, the higher the reliability of the device. The predicted result of FLEXXON’s FxAdv II Series microSD is more than 2,000,000 hours. 

## **2.4. Data Retention** 

- 10 years if > 90% life remaining (@40C) 

- 1 year if < 10% life remaining (@40C) 

6 

## **3. ENVIRONMENTAL SPECIFICATIONS** 

|**Test Items**|**Test Conditions**|
|---|---|
|**Storage Temperature**|-40°C ~ 85°C|
|**Operating Temperature**|-25°C ~ 85°C|
|**Storage Humidity**|40°C, 93% RH|
|**Operating Humidity**|25°C, 95% RH|
|**Shock**|1500G, Half Sin Pulse Duration 0.5ms|
|**Vibration**|80Hz ~ 2000Hz/20G, 20Hz ~ 80Hz/1.52mm, 3 axis/30min|
|**Drop**|150cm free fall, 6 face of each unit|
|**Bending**|≥ 10N, Hold 1 min/5 times|
|**Torque**|0.1N-m or +/-2.5 deg, Hold 30 seconds/5 times|
|**ESD**|Contact: +/- 4KV each item 25 times<br>Air: +/- 8KV 10 times|



7 

## **4. ELECTRICAL SPECIFICATIONS** 

## **4.1. Absolute Maximum Rating** 

|**Item**|**Symbol**|**Parameter**|**MIN**|**MAX**|**Unit**|
|---|---|---|---|---|---|
|1|VDD|Supply Voltage|2.7|3.6|V|
|2|Ta|Operating Temperature|-25|+85|℃|
|3|Tst|Storage Temperature|-40|+85|℃|



## **4.2. DC Characteristics** 

## **4.2.1. Bus Operation Conditions for 3.3V Signaling** 

**Table 4-1 Threshold Level for High Voltage Range** 

|**Parameter**|**Symbol**|**Min.**|**Max**|**Unit**|**Condition**|
|---|---|---|---|---|---|
|Supply Voltage|VDD|2.7|3.6|V||
|Output High Voltage|VOH|0.75*VDD||V|IOH=-2mA VDDMin|
|Output Low Voltage|VOL||0.125*VDD|V|IOL=2mA VDDMin|
|Input High Voltage|VIH|0.625*VDD|VDD+0.3|V||
|Input Low Voltage|VIL|VSS-0.3|0.25*VDD|V||
|Power Up Time|||250|ms|From 0V to VDDmin|



**Table 4-2 Peak Voltage and Leakage Current** 

|**Parameter**|**Symbol**|**Min**|**Max.**|**Unit**|**Remarks**|
|---|---|---|---|---|---|
|Peak voltage on all lines||-0.3|VDD+0.3|V||
|**All Inputs**||||||
|Input Leakage Current||-10|10|uA||
|**All Outputs**||||||
|Output Leakage Current||-10|10|uA||



**Table 4-3 Threshold Level for 1.8V Signaling** 

|**Parameter**<br>~~es es~~|**Symbol**<br>~~es~~|**Min.**|**Max**|**Unit**|~~8~~<br>**Condition**|
|---|---|---|---|---|---|



~~8~~ 

|Supply Voltage|VDD|2.7|3.6|V||
|---|---|---|---|---|---|
|Regulator Voltage|VDDIO|1.7|1.95|V|Generated by VDD|
|Output High Voltage|VOH|1.4|-|V|IOH=-2mA|
|Output Low Voltage|VOL|-|0.45|V|IOL=2mA|
|Input High Voltage|VIH|1.27|2.00|V||
|Input Low Voltage|VIL|Vss-0.3|0.58|V||



**Table 4-4 Input Leakage Current for 1.8V Signaling** 

|**Parameter**|**Symbol**|**Min**|**Max.**|**Unit**|**Remarks**|
|---|---|---|---|---|---|
|Input Leakage Current||-2|2|uA|DAT3 pull-up is<br>disconnected.|



## **4.2.2. Bus Signal Line Load** 

## **Bus Operation Conditions – Signal Line’s Load** 

Total Bus Capacitance = CHOST + CBUS + N CCARD 

|**Parameter**|**symbol**|**Min**|**Max**|**Unit**|**Remark**|
|---|---|---|---|---|---|
|Pull-up resistance|RCMD<br>RDAT|10|100|kΩ|to prevent bus floating|
|Total bus capacitance for each signal<br>line|CL||40|pF|1 card<br>CHOST+CBUSshall<br>not exceed 30 pF|
|Card Capacitance for each signal pin|CCARD||10|pF||
|Maximum signal line inductance|||16|nH||
|Pull-up resistance inside card (pin1)|RDAT3|10|90|kΩ|May be used for card<br>detection|
|Capacity Connected to Power Line|CC||5|uF|To prevent inrush current|



## **4.2.3. Power Up Time of Host** 

Host needs to keep power line level less than 0.5V and more than 1ms before power ramp up. 

9 

## **Power On or Power Cycle** 

Followings are requirements for Power on and Power cycle to assure a reliable SD Card hard reset. 

- (1) Voltage level shall be below 0.5V 

- (2) Duration shall be at least 1ms. 

## **Power Supply Ramp Up** 

The power ramp up time is defined from 0.5V threshold level up to the operating supply voltage which is stable between VDD (min.) and VDD (max.) and host can supply SDCLK. Followings are recommendation of Power ramp up: 

- (1) Voltage of power ramp up should be monotonic as much as possible. 

- (2) The minimum ramp up time should be 0.1ms. 

- (3) The maximum ramp up time should be 35ms for 2.7-3.6V power supply. 

- (4) Host shall wait until VDD is stable. 

- (5) After 1ms VDD stable time, host provides at least 74 clocks before issuing the first command. 

## **Power Down and Power Cycle** 

- When the host shuts down the power, the card VDD shall be lowered to less than 0.5Volt for a minimum period of 1ms. During power down, DAT, CMD, and CLK should be disconnected or driven to logical 0 by the host to avoid a situation that the operating current is drawn through the signal lines. 

- If the host needs to change the operating voltage, a power cycle is required. Power cycle means the power is turned off and supplied again. Power cycle is also needed for accessing cards that are already in _Inactive State._ To create a power cycle the host shall follow the power down description before power up the card (i.e. the card VDD shall be once lowered to less than 0.5Volt for a minimum period of 1ms). 

## **4.2.4. Power Up Time of Card** 

A device shall be ready to accept the first command within 1ms from detecting VDD min. 

10 

Device may use up to 74 clocks for preparation before receiving the first command. 

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4.3. AC Characteristic<br>4.3.1. microSD Interface timing (Default)<br>**----- End of picture text -----**<br>


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Parameter  Symbol  Min  Max  Unit  Remark<br>Clock CLK (All values are referred to min(VIH) and max(VIL)<br>Clock frequency Data  fPP 0  25  MHz  Ccard≤ 10 pF<br>**----- End of picture text -----**<br>


11 

~~ee~~ Transfer Mode (1 card) Clock frequency Ccard≤ 10 pF fOD 0(1)/100 400 KHz ~~a~~ Identification Mode ~~ee ee~~ Ccard(1 card ~~ee~~ ≤ 10 pF ) Clock low time tWL 10 ns ~~aee ee~~ Ccard(1 card≤ 10 pF ) Clock high time tWH 10 ns ~~a~~ (1 card) Ccard≤ 10 pF Clock rise time tTLH 10 ns ~~a ee ee~~ (1 card) ~~ee ee~~ Ccard ~~ee~~ ≤ 10 pF Clock fall time tTHL 10 ns ~~ee~~ **Inputs CMD** ~~ee~~ **, DAT (referenced to CLK** ~~ee~~ **)** (1 card) Ccard≤ 10 pF Input set-up time tISU 5 ns (1 card) ~~a ee ee~~ C ~~ae~~ card≤ 10 pF Input hold time tIH 5 ns ~~ee~~ **Outputs CMD** ~~ee~~ **, DAT (referenced to CLK** ~~ee~~ **)** ~~See~~ (1 card) Output Delay time during CL≤ 40 pF Data Transfer Mode tODLY 0 14 ns (1 card) ~~es~~ Output Delay time during ~~ee eee~~ CL≤ 40 pF ~~a~~ Identification Mode t ~~ee~~ ODLY 0 ~~ee~~ 50 ns (1 card) 

(1) 0Hz means to stop the clock. The given minimum frequency range is for cases where continues clock is required. 

12 

## **4.3.2. microSD Interface Timing (High-Speed Mode)** 

|**Parameter**|**Symbol**|**Min**|**Max**|**Unit**|**Remark**|
|---|---|---|---|---|---|
|**Clock CLK(All values are referred to min(VIH) and max(VIL)**||||||
|Clock frequency Data Transfer Mode|fPP|0|50|MHz|Ccard≤ 10 pF<br>(1 card)|
|Clock low time|tWL|7||ns|Ccard≤ 10 pF<br> (1 card)|
|Clock high time|tWH|7||ns|Ccard≤ 10 pF<br> (1 card)|
|Clock rise time|tTLH||3|ns|Ccard≤ 10 pF<br> (1 card)|
|Clock fall time|tTHL||3|ns|Ccard≤ 10 pF<br> (1 card)|
|**Inputs CMD, DAT(referenced to CLK)**||||||
|Input set-up time|tISU|6||ns|Ccard≤ 10 pF<br> (1 card)|
|Input hold time|tIH|2||ns|Ccard≤ 10 pF<br> (1 card)|
|**Outputs CMD, DAT(referenced to CLK)**||||||
|Output Delay time during Data<br>Transfer Mode|tODLY||14|ns|CL≤ 40 pF<br>(1 card)|
|Output Hold time|TOH|2.5||ns|CL≤ 15 pF<br>(1 card)|
|Total System capacitance of each line¹|CL||40|pF|CL ≤ 15 pF<br>(1 card)|



(1) In order to satisfy severe timing, the host shall drive only one card. 

13 

## **4.3.3. microSD Interface timing (SDR12, SDR25, SDR50 and SDR104 Modes)** 

**==> picture [39 x 13] intentionally omitted <==**

**----- Start of picture text -----**<br>
Input:<br>**----- End of picture text -----**<br>


|**Symbol**|**Min**||**Max**|**Unit**||**Remark**|
|---|---|---|---|---|---|---|
|tCLK|4.80||-|ns|208MHz(Max.),Between risingedge,VCT= 0.975V||
|tCR, tCF|-||0.2* tCLK|ns|tCR, tCF< 0.96ns (max.) at 208MHz, C<br>tCR, tCF< 2.00ns (max.) at 100MHz, C<br>The absolute maximum value of t|< 0.96ns (max.) at 208MHz, CCARD=10pF<br>< 2.00ns (max.) at 100MHz, CCARD=10pF<br>The absolute maximum value of tCR, tCFis 10ns regardless<br>of clock frequency|
|Clock Duty|30||70|%|||
|||||Clock Signal Timing|Clock Signal Timing|Clock Signal Timing|
|**SDR50 and SDR104 Input Timing:**|**SDR50 and SDR104 Input Timing:**|**SDR50 and SDR104 Input Timing:**|||||



|**Symbol**|**Min**|**Max**|**Unit**|**SDR104 Mode**|
|---|---|---|---|---|
|tIS|1.40|-|ns|CCARD=10pF,VCT= 0.975V|
|tIH|0.8|-|ns|CCARD= 5pF,VCT= 0.975V|
|**Symbol**|**Min**|**Max**|**Unit**|**SDR50 Mode**|
|tIS|3.00|-|ns|CCARD=10pF,VCT= 0.975V|
|tIH|0.8|-|ns|CCARD= 5pF,VCT= 0.975V|



14 

## _**Output (SDR12, SDR25, SDR50):**_ 

|**Symbol**|**Min**|**Max**|**Unit**|**Remark**|
|---|---|---|---|---|
|tODLY|-|7.5|ns|tCLK>=10.0ns,CL=30pF,usingdriver Type B,for SDR50|
|tODLY|-|14|ns|tCLK>=20.0ns, CL=40pF, using driver Type B, for SDR25 and<br>SDR12,|
|TOH|1.5|-|ns|Hold time at the tODLY (min.),CL=15pF|



## _**Output (SDR104 Mode):**_ 

|**Symbol**|**Min**|**Max**|**Unit**|**Remark**|
|---|---|---|---|---|
|tOP|0|2|Ul|Card Output Phase|
|△tOP|-350|+1550|ps|Delayvariable due to temperature change after tuning|
|tODW|0.60|-|Ul|tODW= 2.88ns at 208MHz|



15 

## **4.3.4. microSD Interface timing (DDR50 Mode)** 

|**Symbol**|**Min**|**Max**|**Unit**|**Remark**|
|---|---|---|---|---|
|tCLK|20|-|ns|50MHz (Max.), Between rising edge|
|tCR, tCF|-|0.2* tCLK|ns|tCR, tCF< 4.00ns (max.) at 50MHz, CCARD=10pF|
|Clock Duty|45|55|%||



16 

**Bus Timings – Parameters Values (DDR50 Mode)** 

|**Parameter**<br>~~po~~|**Symbol**|**Min**|**Max**|**Unit**|**Remark**|
|---|---|---|---|---|---|
|**Input CMD**(referenced to CLK risingedge)<br>~~po~~||||||
|Input set-up time<br>~~a~~|tISU<br>~~ee~~|3<br>~~ee~~|-<br>~~ee~~|ns<br>~~ee~~|Ccard≤ 10 pF<br> (1 card)<br>~~ee~~|
|Input hold time<br>~~a ~~<br>~~a~~|tIH<br> ~~ee~~<br>~~ee~~|0.8<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~<br>~~ee~~|Ccard≤ 10 pF<br> (1 card)<br>~~ee~~<br>~~ee~~|
|**Output CMD**(referenced to CLK risingedge)<br>~~a ee~~||||||
|Output Delay time<br>during Data Transfer<br>Mode<br>~~**a**~~|tODLY<br>~~ee~~|~~ee~~|13.7<br>~~ee~~|ns<br>~~ee~~|CL≤ 30 pF<br>(1 card)<br>~~eee~~|
|Output Hold time<br>~~**a**~~|TOH<br>~~ee~~|1.5<br>~~ee~~|-<br>~~ee~~|ns<br>~~ee~~|CL≥ 15 pF<br>(1 card)<br>~~eee~~|
|**Inputs DAT**(referenced to CLK risingand fallingedges)<br>~~**a**~~<br>~~ee ee~~<br>~~eee~~<br>~~eeee~~<br>~~eee~~||||||
|Input set-up time<br>~~ee~~<br>~~ee~~|tISU2x<br>~~ee~~<br>~~ee~~|3<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~|Ccard≤ 10 pF<br> (1 card)<br>~~eee~~<br>~~ee~~|
|Input hold time<br>~~ee ~~<br>~~ee~~|tIH2x<br> ~~ee~~<br>~~ee~~|0.8<br>~~ee~~<br>~~ee~~|-<br>~~ee~~<br>~~ee~~|ns<br>~~ee~~|Ccard≤ 10 pF<br> (1 card)<br>~~eee~~<br>~~ee~~|
|**Outputs DAT**(referenced to CLK risingand fallingedges)<br>~~ee ee~~<br>~~ee~~||||||
|Output Delay time<br>during Data Transfer<br>Mode|tODLY2x|-|7.0|ns|CL≤ 25 pF<br>(1 card)|
|Output Hold time<br>~~a~~|TOH2x<br>~~eS~~|1.5<br>~~eS ~~|-<br> ~~ee~~|ns<br>~~ee~~|CL≥ 15 pF<br>(1 card)|



17 

**5. PAD ASSIGNMENT** $e 

## **Table 5-1 microSD Memory Card Pad Assignment** 

|**pin**<br>~~ee~~|**SD Mode**<br>~~es~~<br>~~eeeeee~~|**SD Mode**<br>~~es~~<br>~~eeeeee~~|**SD Mode**<br>~~es~~<br>~~eeeeee~~|**SPI Mode**<br>~~es~~<br>~~ereree~~|**SPI Mode**<br>~~es~~<br>~~ereree~~|**SPI Mode**<br>~~es~~<br>~~ereree~~|
|---|---|---|---|---|---|---|
||**Name**<br>~~ee~~|**Type1 **<br>~~ee~~|**Description**<br>~~ee~~|**Name**<br>~~er~~|**Type**<br>~~er~~|**Description**<br>~~ee~~|
|1<br>~~ee~~<br>~~a~~|DAT2<br>~~ee ~~<br>~~a~~|I/O/PP<br> ~~ee ~~<br>~~a~~|Data Line[bit2]<br> ~~ee~~<br>~~a~~|RSV<br>~~er ~~<br>~~on~~|~~er~~<br>~~on~~|~~ee~~<br>~~on~~|
|2<br>~~a~~<br>~~a~~|CD/DAT3**2**<br>~~a~~<br>~~ee~~|I/O/PP<br>3<br>~~a~~<br>~~ee~~|Card Detect/<br>Data Line[bit3]<br>~~a~~<br>~~ee~~|CS<br>~~on~~|I3<br>~~on~~|Chip Select (neg<br>true)<br>~~on~~|
|3<br>~~a~~<br>~~a~~<br>~~a~~|CMD<br>~~a~~<br>~~ee~~<br>~~ee~~|PP<br>~~a~~<br>~~ee~~<br>~~ee~~|Command/Response<br>~~a ~~<br>~~ee~~<br>~~ee~~|DI<br> ~~on~~|I<br>~~on~~|Data In<br>~~on~~<br>~~ee~~|
|4<br>~~a~~<br>~~a~~<br>~~nS~~|VDD<br>~~ee~~<br>~~ee~~<br>~~nS~~|S<br>~~ee~~<br>~~ee~~<br>~~nS~~|Supply voltage<br>~~ee~~<br>~~ee~~<br>~~ee~~|VDD|S|Supply voltage<br>~~ee~~|
|5<br>~~a~~<br>~~nS~~|CLK<br>~~ee~~<br>~~nS~~|I<br>~~ee~~<br>~~nS~~|Clock<br>~~ee~~<br>~~ee~~|SCLK|I|Clock<br>~~ee~~|
|6<br>~~nS~~<br>~~ee~~|VSS<br>~~nS~~<br>~~a~~|S<br>~~nS~~<br>~~es~~|Supply voltage<br>ground<br>~~ee~~<br>~~ee~~|VSS<br>~~eee~~|S<br>~~eee~~|Supply voltage<br>ground<br>~~eee~~|
|7<br>~~nS~~<br>~~ee~~<br>~~a~~|DAT0<br>~~nS~~<br>~~a~~<br>~~a~~|I/O/PP<br>~~nS ~~<br>~~es~~<br>~~ee~~|Data Line[bit0]<br> ~~ee~~<br>~~ee~~<br>~~ee~~|DO<br>~~eee~~|O/PP<br>~~eee~~|Data Out<br>~~eee~~|
|8<br>~~ee ~~<br>~~a~~|DAT1<br> ~~a~~<br>~~a~~|I/O/PP<br>~~es~~<br>~~ee~~|Data Line[bit1]<br>~~ee~~<br>~~ee~~|RSV<br>~~eee~~|~~eee~~|~~eee~~|



(1)  S: power supply, I: input; O: output using push-pull drivers; PP: I/O using push-pull drivers 

(2)  The extended DAT lines (DAT1-DAT3) are input on power up. They start to operate as DAT lines after SET_BUS_WIDTH command. The Host shall keep its own DAT1-DAT3 lines in input mode, as well, while they are not used. It is defined so, in order to keep compatibility to MultiMedia Cards. 

(3)  At power up this line has a 50KOhm pull up enabled in the card. This resistor serves two functions: Card detection and Mode Selection. For Mode Selection, the host can drive the line high or let it be pulled high to select SD mode. If the host wants to select SPI mode it should drive the line low. For Card detection, the host detects that the line is pulled high. This pull-up should be disconnected by the user during regular data transfer period, with SET_CLR_CARD_DETECT (ACMD42) command. 

18 

## **6. REGISTERS** 

|**Name**|**Width**|**Description**|
|---|---|---|
|CID|128bit|Card identification number; card individual number for identification.|
|RCA|16bit|Relative card address; local system address of a card, dynamically<br>suggested by the card and approved by the host during initialization.|
|DSR|16bit|Driver Stage Register; to configure the card’s output drivers.|
|CSD|128bit|Card Specific Data; Information about the card operation conditions.|
|SCR|64bit|SD Configuration Register; Information about the SD Memory Card’s<br>Special Features capabilities|
|OCR|32bit|Operation conditions register.|
|SSR|512bit|SD Status; Information about the card proprietary features.|
|OCR|32bit|Card Status; Information about the card status.|



19 

## **7. PHYSICAL DIMENSION** as 

**Dimension: 15mm (L) x 11mm (W) x 1mm (H)** 

20 

21 

## **8. ORDERING INFORMATION** 

|**Capacity**|**MPN**|
|---|---|
|32GB|FDMM032GBC-3200|
|64GB|FDMM064GBC-3200|
|128GB|FDMM128GBC-3200|
|256GB|FDMM256GBC-3200|
|512GB|FDMM512GBC-3200|



22 

## **Revision History** 

|**Revision**|**Release Date**|**Description**|
|---|---|---|
|1.0|2021/09|First release|
|1.1|2021/09|Update Capacity|
|1.2|2022/05|Add 32GB capacity|
|1.3|2022/09|Update Section 2.4|



23