FDMD8680

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## **FDMD8680** 

## **Dual N-Channel PowerTrench[®] MOSFET 80 V, 66 A, 4.7 m** Ω 

## **Features** 

Common Source Configuration to Eliminate PCB Routing 

Large Source Pad on Bottom of Package for Enhanced Thermals 

Max rDS(on) = 4.7 mΩ at VGS = 10 V, ID = 16 A 

Max rDS(on) = 6.4 mΩ at VGS = 8 V, ID = 14 A 

Ideal for Flexible Layout in Secondary Side Synchronous Rectification 

## **General Description** 

This package integrates two N-Channel devices connected internally in common-source configuration. This enables very low package parasitics and optimized thermal path to the common source pad on the bottom. Provides a very small footprint (5 x 6 mm) for higher power density. 

## **Applications** 

Isolated DC-DC Synchronous Rectifiers 

Common Ground Load Switches 

100% UIL Tested 

Termination is Lead-free and RoHS Compliant 

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Top Bottom<br>Pin 1 G1<br>Pin 1 D1 G1 1 8 D2<br>D1<br>D1<br>D1 2 7 D2<br>S1 / S2<br>D1 3 6 D2<br>D2<br>D2 D2 D1 4 5 G2<br>o<¢ G2 S1,S2 to backside<br>Power 5 x 6<br>MOSFET Maximum Ratings TA = 25 °C unless otherwise noted.<br>Symbol Parameter Ratings Units<br>VDS Drain to Source Voltage 80 V<br>VGS Gate to Source Voltage                                                                              ±20 V<br>Drain Current     -Continuous                                  TC = 25 °C               (Note 5) 66<br>ID                           -Continuous                                  T                             -Continuous                                      TC A = 100 °C             = 25 °C              (Note 1a(Note 5)) 1642 A<br>                          -Pulsed                                                                         (Note 4) 487<br>EAS Single Pulse Avalanche Energy (Note 3) 337 mJ<br>PD Power Dissipation                                                   TPower Dissipation                                                      TCA = 25 °C              = 25 °C            (Note 1a) 2.339 W<br>TJ, TSTG Operating and Storage Junction Temperature Range -55 to +150 °C<br>Thermal Characteristics<br>RθJC Thermal Resistance, Junction to Case                                                3.2<br>°C/W<br>RθJA Thermal Resistance, Junction to Ambient                                                 (Note 1a) 55<br>— [oe] Package Marking and Ordering Information<br>Device Marking Device Package Reel Size Tape Width Quantity<br>FDMD8680 FDMD8680 Power 5 x 6 13 ’’ 12 mm 3000 units<br>ee<br>**----- End of picture text -----**<br>


©2016 Fairchild Semiconductor Corporation **1** FDMD8680 Rev.1.0 

www.fairchildsemi.com 

## **Electrical Characteristics** TJ = 25 °C unless otherwise noted. 

|**Off Characteristics**<br>**On Characteristics**<br>**Dynamic Characteristics**<br>**Switching Characteristics**<br>**Drain-Source Diode Characteristics**<br>**Symbol**<br>**Parameter**<br>**Test Conditions**<br>**Min.**<br>**Typ.**<br>**Max.**<br>**Units**<br>BVDSS<br>Drain to Source Breakdown Voltage<br>ID= 250μA, VGS= 0 V<br>80<br>V<br>ΔBVDSS<br>ΔTJ<br>Breakdown Voltage Temperature<br>Coefficient<br>ID= 250μA, referenced to 25 °C<br>50<br>mV/°C<br>IDSS<br>Zero Gate Voltage Drain Current<br>VDS= 64 V, VGS= 0 V<br>1<br>μA<br>IGSS<br>Gate to Source Leakage Current<br>VGS= ±20 V, VDS= 0 V<br>±100<br>nA<br>VGS(th)<br>Gate to Source Threshold Voltage<br>VGS= VDS,  ID= 250μA<br>2.0<br>3.0<br>4.0<br>V<br>ΔVGS(th)<br>ΔTJ<br>Gate to Source Threshold Voltage<br>Temperature Coefficient<br>ID= 250μA, referenced to 25 °C<br>-10<br>mV/°C<br>rDS(on)<br>Static Drain to Source On Resistance<br>VGS= 10 V,  ID= 16 A<br>3.3<br>4.7<br>mΩ<br>VGS= 8 V,  ID= 14 A<br>3.9<br>6.4<br>VGS= 10 V,  ID= 16 A, TJ= 125 °C<br>5.6<br>8.0<br>gFS<br>Forward Transconductance<br>VDD= 10 V,  ID= 16 A<br>49<br>S<br>Ciss<br>Input Capacitance<br>VDS= 40 V, VGS= 0 V<br>f = 1 MHz<br>3805<br>5330<br>pF<br>Coss<br>Output Capacitance<br>657<br>920<br>pF<br>Crss<br>Reverse Transfer Capacitance<br>26<br>77<br>pF<br>Rg<br>Gate Resistance<br>0.1<br>1.7<br>3.4<br>Ω<br>td(on)<br>Turn-On DelayTime<br>VDD= 40 V, ID= 16 A<br>VGS= 10 V, RGEN= 6Ω<br>20<br>32<br>ns<br>tr<br>Rise Time<br>18<br>32<br>ns<br>td(off)<br>Turn-Off DelayTime<br>30<br>48<br>ns<br>tf<br>Fall Time<br>10<br>20<br>ns<br>Qg(TOT)<br>Total Gate Charge<br>VGS= 0 V to 10 V<br>VDD= 40 V<br>ID= 16 A<br>53<br>73<br>nC<br>Qgs<br>Gate to Source Charge<br>17<br>nC<br>Qgd<br>Gate to Drain “Miller” Charge<br>10<br>nC<br>VSD<br>Source to Drain Diode Forward Voltage<br>VGS= 0 V, IS= 16 A(Note 2)<br>0.8<br>1.3<br>V<br>VSD<br>Source to Drain Diode Forward Voltage<br>VGS= 0 V, IS= 2 A(Note 2)<br>0.7<br>1.2<br>V<br>trr<br>Reverse RecoveryTime<br>IF= 16 A, di/dt = 100 A/μs<br>48<br>77<br>ns<br>Qrr<br>Reverse RecoveryCharge<br>39<br>62<br>nC<br>NOTES:<br>1. RθJAis determined with the device mounted on a 1 in2pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθCAis determined by  the user's board design.<br>~~SS~~<br>~~eeaaae~~<br>~~==~~<br>~~EEE~~<br>~~eae~~<br>~~——a—~~<br>~~aes~~|
|---|
|a. 55 °C/W when mounted on<br>b.125 °C/W when mounted on|
|a 1 in2pad of  2 oz  copper<br>a minimum pad of  2 oz  copper|
|**G**<br>**DF**<br>**DS**<br>**SF**<br>**SS**|
|**G**<br>**DF**<br>**DS**<br>**SF**<br>**SS**|



2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %. 

3. EAS of 337 mJ is based on starting TJ = 25[o] C, L = 3 mH, IAS = 15 A, VDD = 80 V, VGS = 10 V. 100% tested at L = 0.1 mH, IAS = 49 A. 

4. Pulsed Id please refer to Fig 11 SOA graph for more details. 

5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design. 

www.fairchildsemi.com 

**2** 

©2016 Fairchild Semiconductor Corporation FDMD8680 Rev.1.0 

## **Typical Characteristics** TJ = 25 °C unless otherwise noted. 

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200 10<br>VGS = 10 V VGS =  5.5 V PULSE DURATION = 80  μ s<br>VGS = 8 V 8 DUTY CYCLE = 0.5% MAX<br>150 VGS =  7 V VGS = 6 V VGS = 6 V<br>6<br>100<br>VGS = 5.5 V 4<br>50 VGS =  7 V<br>2<br>PULSE DURATION = 80  μ s<br>0 DUTY CYCLE = 0.5% MAX 0 VGS = 8 V VGS = 10 V<br>0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 50 100 150 200<br>VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 1.  On-Region Characteristics Figure 2.  Normalized On-Resistance                                          Normalized On-Resistance<br>vs. Drain Current and Gate Voltage<br>2.0 40<br>1.8 ID = 16 A PULSE DURATION = 80 DUTY CYCLE = 0.5% MAX μ s<br>VGS = 10 V<br>30<br>1.6<br>ID = 16 A<br>1.4<br>20<br>1.2<br>1.0<br>10 TJ = 125  [o] C<br>0.8<br>TJ = 25  [o] C<br>0.6 0<br>-75 -50 -25 0 25 50 75 100 125 150 4 5 6 7 8 9 10<br>TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 3.  Normalized  On  Resistance                                 Figure 4.   On  Resistance  vs. Gate  to                                        On  Resistance  vs. Gate  to<br>vs. Junction Temperature Source Voltage<br>200 200<br>PULSE DURATION = 80  μ s 100 VGS = 0 V<br>DUTY CYCLE = 0.5% MAX<br>150 10<br>VDS = 5 V<br>1<br>100<br>TJ = 150  [o] C 0.1 TJ = 150  [o] C T J  = 25 [ o] C<br>TJ = 25  [o] C<br>50 0.01 T J  = -55  [o] C<br>TJ = -55  [o] C<br>0 0.001<br>2 3 4 5 6 7 8 0.0 0.2 0.4 0.6 0.8 1.0 1.2<br>VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)<br>NORMALIZED<br>, DRAIN CURRENT (A)<br>ID<br>DRAIN TO SOURCE ON-RESISTANCE<br>) Ω<br>(m<br>DRAIN TO<br>NORMALIZED rDS(on),<br>SOURCE ON-RESISTANCE<br> DRAIN TO SOURCE ON-RESISTANCE<br>, DRAIN CURRENT (A)<br>ID<br>, REVERSE DRAIN CURRENT (A)<br>IS<br>**----- End of picture text -----**<br>


**Figure 2.  Normalized On-Resistance                                          Normalized On-Resistance vs. Drain Current and Gate Voltage** 

**Figure 4.   On  Resistance  vs. Gate  to                                        On  Resistance  vs. Gate  to Source Voltage** 

**Figure 5.  Transfer Characteristics** 

**Figure 6.   Source to Drain  Diode Forward Voltage vs. Source Current** 

www.fairchildsemi.com 

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©2016 Fairchild Semiconductor Corporation FDMD8680 Rev.1.0 

**Typical Characteristics** TJ = 25 °C unless otherwise noted. 

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10 10000<br>ID = 16 A<br>8 Ciss<br>1000<br>VDD = 30 V VDD = 40 V<br>6 Coss<br>VDD = 50 V 100<br>4<br>2 10 f = 1 MHz Crss<br>VGS = 0 V<br>0 1<br>0 10 20 30 40 50 60 0.1 1 10 80<br>Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 7.  Gate Charge Characteristics      Figure 8.    Capacitance vs. Drain<br>to Source Voltage<br>100 80<br>60<br>VGS = 10 V<br>10 TJ = 100  [o] C 40<br>TJ = 125  [o] C TJ = 25 [ o] C<br>VGS = 8 V<br>20<br>R θ JC = 3.2  [o] C/W<br>1 0<br>0.001 0.01 0.1 1 10 100 500 25 50 75 100 125 150<br>tAV, TIME IN AVALANCHE (ms) TC, CASE TEMPERATURE (oC)<br>Figure 9.  Unclamped Inductive   Figure 10. Maximum Continuous Drain<br>Switching Capability Current  vs. Case Temperature<br>1000 20000<br>10000 SINGLE PULSE<br>R θ JC = 3.2  [o] C/W<br>100 10  μ s T C = 25  [o] C<br>1000<br>10<br>THIS AREA IS<br>LIMITED BY r DS(on) 100  μ s<br>SINGLE PULSE 100<br>1 TJ = MAX RATED 1 ms<br>R θ JC = 3.2 [ o] C/W CURVE BENT TO  10 ms<br>T C = 25  [o] C MEASURED DATA 100 ms<br>0.1 10<br>0.1 1 10 100 300 10-5 10-4 10-3 10-2 10-1 1<br>VDS, DRAIN to SOURCE VOLTAGE (V) t, PULSE WIDTH (sec)<br>Figure 11.  Forward Bias Safe    Figure 12.  Single  Pulse Maximum<br>Operating Area Power  Dissipation<br>CAPACITANCE (pF)<br>, GATE TO SOURCE VOLTAGE (V)<br>GS<br>V<br>DRAIN CURRENT (A)<br>,<br>ID<br>, AVALANCHE CURRENT (A)<br>IAS<br>, DRAIN CURRENT (A)<br>ID<br>PEAK TRANSIENT POWER (W)<br>,<br>(PK)<br>P<br>**----- End of picture text -----**<br>


www.fairchildsemi.com 

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©2016 Fairchild Semiconductor Corporation FDMD8680 Rev.1.0 

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Typical Characteristics  TJ = 25 °C unless otherwise noted.<br>2<br>DUTY CYCLE-DESCENDING ORDER<br>1<br>D = 0.5<br>      0.2<br>      0.1 P DM<br>0.1       0.05<br>      0.02<br>      0.01 t1<br>t 2<br>NOTES:<br>0.01 Z θ JC(t) = r(t) x R θ JC<br>R θ JC = 3.2 [o] C/W<br>SINGLE PULSE Peak T J  = P DM  x Z θ JC (t) + T C<br>Duty Cycle, D = t1 / t2<br>0.001<br>10-5 10-4 10-3 10-2 10-1 1<br>t, RECTANGULAR PULSE DURATION (sec)<br>Figure 13.  Junction-to-Case Transient Thermal Response Curve<br>THERMAL RESISTANCE<br>r(t), NORMALIZED EFFECTIVE TRANSIENT<br>**----- End of picture text -----**<br>


www.fairchildsemi.com 

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©2016 Fairchild Semiconductor Corporation FDMD8680 Rev.1.0 

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KEEP-OUT 3.81<br>0.10 C 5 .00±0.10 A AREA 1.91 1.27<br>2X<br>PKG 0.52 (8X)<br>CL B 8 7 6 5<br>8 5<br>0.72 (6X)<br>0.70 (2X)<br>1.79<br>PKG CL 6.00±0.10 0.30 (2X) 2.88 6.22<br>0.60 (2X)<br>1.72 (2X)<br>0.10 C<br>1 4 1 2 3 4<br>PIN #1 2X<br>0.97 1.79<br>INDICATOR TOP VIEW 3.58<br>5.00<br>SEE<br>DETAIL A<br>RECOMMENDED  LAND PATTERN<br>0.10 C<br>SIDE VIEW<br>0.80<br>0.70<br>0.10 C A B 0.08 C<br>0.39 TYP 1.27 C<br>0.05 C<br>(0.78)2X 1 2 3 4 0.42±.05 (6X) 0.300.20 0.050.00 SEATING<br>PLANE<br>0.56±.10 (6X)<br>1.56±.10 NOTES: (SCALE: 2X)<br>2X<br>(1.74) A)  PACKAGE  REFERENCE :<br>      TO JEDEC REGISTRATION, MO-240B,  VARIATION AA.<br>0.30±.05 3.48±.05<br>4X (1.04) B)  ALL DIMENSIONS ARE IN MILLIMETERS.<br>C)  DIMENSIONS DO NOT INCLUDE BURRS OR MOLD<br>FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED<br>0.70 TYP 0.10MM.<br>0.30±.05 D)  DIMENSIONING AND TOLERANCING PER ASME<br>2X Y14.5M-2009<br>8 7 6 5<br>0.76 (0.92) 2X E) IT IS RECOMMENDED TO HAVE  NO<br>3.42 (2X)      TRACES OR VIAS WITHIN THE KEEP-OUT AREA<br>3.48±.05 F) DRAWING FILE NAME: PQFN08OREV1<br>**----- End of picture text -----**<br>


TO JEDEC REGISTRATION, MO-240B,  VARIATION AA. 

- C)  DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. 

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ON Semiconductor and      are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 

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