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FDMD8560L
Dual MOSFET, PowerTrench, N Channel, 60 V, 93 A, 0.0032 ohm
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- Manufacturer: ONSEMI
- Product type: Dual MOSFETs
- Transistor Polarity:Dual N Channel; Continuous Drain Current Id:93A; Drain Source Voltage Vds:60V; On Resistance Rds(on):0.; Available until stocks are exhausted Alternative available
- MSL: MSL 1 - Unlimited
- No. of Pins: 8Pins
- Channel Type: N Channel
- Product Range: PowerTrench Series
- Qualification: -
- Transistor Case Style: PQFN
- Operating Temperature Max: 150°C
- Power Dissipation N Channel: 48W
- Power Dissipation P Channel: -
- Drain Source Voltage Vds N Channel: 60V
- Drain Source Voltage Vds P Channel: -
- Continuous Drain Current Id N Channel: 93A
- Continuous Drain Current Id P Channel: -
- Drain Source On State Resistance N Channel: 0.0032ohm
- Drain Source On State Resistance P Channel: -
| Delivery and price | |
|---|---|
| Units per pack | 1000 |
| Price | 1.64 € |
| Current stock | 1000+ |
| Lead time | 30 days |
Datasheet
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This literature is subject to all applicable copyright laws and is not for resale in any manner. **May 2016** ## **FDMD8560L** ## **Dual N-Channel PowerTrench[®] MOSFET Q1: 60 V, 22 A, 3.2 m** Ω **Q2: 60 V, 22 A, 3.2 m** Ω ## **Features** Q1: N-Channel i[|] Max rDS(on) = 3.2 mΩ at VGS = 10 V, ID = 22 A Max rDS(on) = 5.4 mΩ at VGS = 4.5 V, ID = 18 A Q2: N-Channel i[|] Max rDS(on) = 3.2 mΩ at VGS = 10 V, ID = 22 A Max rDS(on) = 5.4 mΩ at VGS = 4.5 V, ID = 18 A Ideal for Flexible Layout in Primary Side of Bridge Topology i[|] 100% UIL Tested Kelvin High Side MOSFET Drive Pin-out Capability RoHS Compliant ## **General Description** This device includes two 60V N-Channel MOSFETs in a dual power (5 mm X 6 mm) package. HS source and LS drain internally connected for half/full bridge, low source inductance package, low rDS(on)/Qg FOM silicon. ## **Applications** Synchronous Buck: Primary Switch of Half / Full Bridge Converter for Telecom Motor Bridge: Primary Switch of Half / Full Bridge Converter for BLDC Motor MV POL: 48V Synchronous Buck Switch Half/Full Bridge Secondary Synchronous Rectification **==> picture [468 x 335] intentionally omitted <==** **----- Start of picture text -----**<br> Top Bottom<br>D2/S1<br>Pin 1 D2/S1 G1 G2<br>D2/S1<br>S2 G2 GR D2/S1<br>D1 D1 D1 D2/S1<br>D1<br>D1 D2/S1<br>GR<br>G1 Pin 1<br>Power 5 x 6<br>MOSFET Maximum Ratings TA = 25 °C unless otherwise noted.<br>a Symbol Parameter Q1 Q2 Units<br>a VDS Drain to Source Voltage 60 60 V<br>a VGS Gate to Source Voltage ±20 ±20 V<br>Drain Current -Continuous TC = 25 °C (Note 5) 93 93<br>ID CTCT Drain Current -Continuous -Continuous T TA C = 25 °C = 100 °C (Note 5) 2259 [1a] 2259 [1b] A<br> -Pulsed (Note 4) 550 550<br>a EAS Single Pulse Avalanche Energy (Note 3) 384 384 mJ<br>——_———— PD Dp Power Dissipation Power Dissipation T TAC = 25 °C = 25 °C 2.248 [1a] 2.248 [1b] W<br>a TJ, TSTG Operating and Storage Junction Temperature Range -55 to +150 °C<br>Thermal Characteristics<br>RθJC Thermal Resistance, Junction-to-Case 2.6 2.6<br>°C/W<br>RθJA Thermal Resistance, Junction-to-Ambient 55 [1a] 55 [1b]<br>**----- End of picture text -----**<br> ## **Package Marking and Ordering Information** |**Device Marking**|**Device**|**Package**|**Reel Size**|**Tape Width**|**Quantity**| |---|---|---|---|---|---| |FDMD8560L|FDMD8560L|Power 5 x 6|13 ’’|12 mm|3000 units| www.fairchildsemi.com ©2016 Fairchild Semiconductor Corporation FDMD8560L Rev.1.0 **1** ## **Electrical Characteristics** TJ = 25 °C unless otherwise noted. |**Electri**|**cal Characteristics**TJ= 25 °C|unless otherwise noted.|||||| |---|---|---|---|---|---|---|---| |**Symbol**|**Parameter**|**Test Conditions**|**Type**|**Min.**|**Typ.**|**Max.**|**Units**| |**Off Characteristics**|||||||| |BVDSS|Drain to Source Breakdown Voltage|ID= 250μA, VGS= 0 V|Q1<br>Q2|60<br>60|||V| |ΔBVDSS<br>ΔTJ|Breakdown Voltage Temperature<br>Coefficient|ID= 250μA, referenced to 25 °C|Q1<br>Q2||32<br>32||mV/°C| |IDSS|Zero Gate Voltage Drain Current|VDS= 48 V, VGS= 0 V|Q1<br>Q2|||1<br>1|μA| |IGSS|Gate to Source Leakage Current|VGS= ±20 V, VDS= 0 V|Q1<br>Q2|||±100<br>±100|nA| |**On Characteristics**|||||||| |VGS(th)|Gate to Source Threshold Voltage|VGS= VDS, ID= 250μA|Q1<br>Q2|1.0<br>1.0|1.6<br>1.6|3.0<br>3.0|V| |ΔVGS(th)<br>ΔTJ|Gate to Source Threshold Voltage<br>Temperature Coefficient|ID= 250μA, referenced to 25 °C|Q1<br>Q2||-7<br>-7||mV/°C| |rDS(on)|Static Drain to Source On Resistance|VGS= 10 V, ID= 22 A|Q1||2.5|3.2|mΩ| |||VGS= 4.5 V, ID= 18A|||4.1|5.4|| |||VGS= 10 V, ID= 22 A, TJ= 125 °C|||3.9|5.0|| |||VGS= 10 V, ID= 22 A|Q2||2.5|3.2|| |||VGS= 4.5 V, ID= 18 A|||4.1|5.4|| |||VGS= 10 V, ID= 22 A, TJ= 125 °C|||3.9|5.0|| |gFS|Forward Transconductance|VDD= 5 V, ID= 22 A|Q1<br>Q2||98<br>98||S| |**Dynamic Characteristics**|||||||| |Ciss|Input Capacitance|VDS= 30 V, VGS= 0 V<br>f = 1 MHz|Q1<br>Q2||7420<br>7420|11130<br>11130|pF| |Coss|Output Capacitance||Q1<br>Q2||1110<br>1110|1665<br>1665|pF| |Crss|Reverse Transfer Capacitance||Q1<br>Q2||38<br>38|60<br>60|pF| |Rg|Gate Resistance||Q1<br>Q2|0.1<br>0.1|1.5<br>1.5|3.0<br>3.0|Ω| |**Switching Characteristics**|||||||| |td(on)|Turn-On Delay Time|VDD= 30 V, ID= 22 A<br>VGS= 10 V, RGEN= 6Ω|Q1<br>Q2||20<br>20|35<br>35|ns| |tr|Rise Time||Q1<br>Q2||15<br>15|26<br>26|ns| |td(off)|Turn-Off Delay Time||Q1<br>Q2||57<br>57|90<br>90|ns| |tf|Fall Time||Q1<br>Q2||11<br>11|20<br>20|ns| |Qg(TOT)|Total Gate Charge|VGS= 0 V to 10 V|Q1<br>Q2||92<br>92|128<br>128|nC| |Qg(TOT)|Total Gate Charge|VGS= 0 V to 4.5 V|Q1<br>Q2||42<br>42|59<br>59|nC| |Qgs|Gate to Source Charge||Q1<br>Q2||19<br>19||nC| |Qgd|Gate to Drain “Miller” Charge||Q1<br>Q2||7<br>7||nC| ©2016 Fairchild Semiconductor Corporation **2** www.fairchildsemi.com FDMD8560L Rev.1.0 ## **Electrical Characteristics** TJ = 25 °C unless otherwise noted. |VSD|Source to Drain Diode Forward Voltage|VGS= 0 V, IS= 22 A (Note 2)|Q1<br>Q2||0.8<br>0.8|1.3<br>1.3|V| |---|---|---|---|---|---|---|---| |VSD|Source to Drain Diode Forward Voltage|VGS= 0 V, IS= 2 A (Note 2)|Q1<br>Q2||0.7<br>0.7|1.2<br>1.2|V| |trr|Reverse Recovery Time|IF= 22 A, di/dt = 100 A/μs|Q1<br>Q2||53<br>53|84<br>84|ns| |Qrr|Reverse Recovery Charge||Q1<br>Q2||44<br>44|70<br>70|nC| NOTES: 1. RθJA is determined with the device mounted on a 1 in[2] pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. **==> picture [376 x 203] intentionally omitted <==** **----- Start of picture text -----**<br> a. 55 °C/W when mounted on b. 55 °C/W when mounted on<br> a 1 in [2 ] pad of 2 oz copper a 1 in [2 ] pad of 2 oz copper<br>c. 155 °C/W when mounted on d. 155 °C/W when mounted on<br> a minimum pad of 2 oz copper a minimum pad of 2 oz copper<br>nt dl<br>G DF DS SF SS G DF DS SF SS<br>G DF DS SF SS G DF DS SF SS<br>**----- End of picture text -----**<br> **==> picture [305 x 13] intentionally omitted <==** **----- Start of picture text -----**<br> c. 155 °C/W when mounted on d. 155 °C/W when mounted on<br> a minimum pad of 2 oz copper a minimum pad of 2 oz copper<br>**----- End of picture text -----**<br> 2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %. 3. Q1: EAS of 384 mJ is based on starting TJ = 25[o] C, L = 3 mH, IAS = 16 A, VDD = 60 V, VGS = 10 V. 100% tested at L = 0.1 mH, IAS = 51 A. Q2: EAS of 384 mJ is based on starting TJ = 25[o] C, L = 3 mH, IAS = 16 A, VDD = 60 V, VGS = 10 V. 100% tested at L = 0.1 mH, IAS = 51 A. 4. Pulsed Id please refer to Fig 11 and Fig 24 SOA graph for more details. 5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design. ©2016 Fairchild Semiconductor Corporation **3** www.fairchildsemi.com FDMD8560L Rev.1.0 ## **Typical Characteristics (Q1 N-Channel)** TJ = 25°C unless otherwise noted. **==> picture [455 x 584] intentionally omitted <==** **----- Start of picture text -----**<br> 180 6<br>VGS = 10 V PULSE DURATION = 80 μ s<br>150 VGS = 4.5 V DUTY CYCLE = 0.5% MAX<br>VGS = 4 V<br>120 VGS = 3.5 V 4<br>VGS = 3 V<br>90<br>VGS = 3 V VGS = 3.5 V VGS = 4 V<br>60 2<br>VGS = 4.5 V<br>30<br>PULSE DURATION = 80 μ s VGS = 10 V<br>DUTY CYCLE = 0.5% MAX<br>0 0<br>0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 30 60 90 120 150 180<br>VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 1. On Region Characteristics Figure 2. Normalized On-Resistance<br>vs. Drain Current and Gate Voltage<br>1.8 12<br>1.7 ID = 22 A PULSE DURATION = 80 μ s<br>1.6 VGS = 10 V DUTY CYCLE = 0.5% MAX<br>1.5 9<br>1.4 ID = 22 A<br>1.3<br>6<br>1.2<br>1.1 TJ = 125 [o] C<br>1.0 3<br>0.9<br>TJ = 25 [o] C<br>0.8<br>0.7 0<br>-75 -50 -25 0 25 50 75 100 125 150 2 3 4 5 6 7 8 9 10<br>TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 3. Normalized On Resistance Figure 4. On-Resistance vs. Gate to<br>vs. Junction Temperature Source Voltage<br>180 200<br>PULSE DURATION = 80 μ s 100 VGS = 0 V<br>DUTY CYCLE = 0.5% MAX<br>150<br>VDS = 5 V 10<br>120<br>TJ = 150 [o] C<br>1<br>90<br>TJ = 25 [ o] C<br>0.1<br>60<br>TJ = 150 [o] C TJ = 25 [o] C TJ = -55 [o] C<br>30 0.01<br>TJ = -55 [o] C<br>0 0.001<br>1 2 3 4 5 0.0 0.2 0.4 0.6 0.8 1.0 1.2<br>VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)<br>NORMALIZED<br>, DRAIN CURRENT (A)<br>ID<br>DRAIN TO SOURCE ON-RESISTANCE<br>) Ω<br>(m<br>DRAIN TO<br>NORMALIZED rDS(on),<br>SOURCE ON-RESISTANCE<br> DRAIN TO SOURCE ON-RESISTANCE<br>, DRAIN CURRENT (A)<br>ID<br>, REVERSE DRAIN CURRENT (A)<br>IS<br>**----- End of picture text -----**<br> **Figure 5. Transfer Characteristics** **Figure 6. Forward Voltage vs. Source Current** ©2016 Fairchild Semiconductor Corporation **4** www.fairchildsemi.com FDMD8560L Rev.1.0 ## **Typical Characteristics (Q1 N-Channel)** TJ = 25°C unless otherwise noted. **==> picture [463 x 607] intentionally omitted <==** **----- Start of picture text -----**<br> 10 10000<br>ID = 22 A Ciss<br>8<br>6 V DD = 20 V VDD = 30 V 1000<br>Coss<br>VDD = 40 V<br>4<br>100<br>2 f = 1 MHz<br>VGS = 0 V<br>Crss<br>0 10<br>0 20 40 60 80 100 0.1 1 10 100<br>Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs. Drain Capacitance vs. Drain<br>to Source Voltage<br>100 100<br>80<br>VGS = 10 V<br>TJ = 25 [ o] C TJ = 100 [o] C 60<br>10 VGS = 4.5 V<br>TJ = 125 [o] C 40<br>20<br>R θ JC = 2.6 [o] C/W<br>1 0<br>0.001 0.01 0.1 1 10 100 1000 25 50 75 100 125 150<br>tAV, TIME IN AVALANCHE (ms) TC, CASE TEMPERATURE (oC)<br>Figure 9. Unclamped Inductive Figure 10. Maximum Continuous Drain Maximum Continuous Drain<br>Switching Capability Current vs. Case Temperature<br>1000 105<br>SINGLE PULSE<br>100 R θ JC = 2.6 [o] C/W<br>10 μ s 104 TC = 25 [o] C<br>10<br>THIS AREA IS 100 μ s 103<br>1 LIMITED BY rDS(on) 1 ms<br>SINGLE PULSE 10 ms<br>0.1 T J = MAX RATED 100 m s 102<br>R θ JC = 2.6 [ o] C/W CURVE BENT TO<br>TC = 25 [o] C MEASURED DATA<br>0.01 10<br>0.01 0.1 1 10 100200 10-5 10-4 10-3 10-2 10-1 1<br>VDS, DRAIN to SOURCE VOLTAGE (V)<br>t, PULSE WIDTH (sec)<br>Figure 11. Forward Bias Safe Figure 12. Single Pulse Maximum Power<br>Operating Area Dissipation<br>CAPACITANCE (pF)<br>, GATE TO SOURCE VOLTAGE (V)<br>GS<br>V<br>DRAIN CURRENT (A)<br>,<br>ID<br>, AVALANCHE CURRENT (A)<br>IAS<br>, DRAIN CURRENT (A)<br>ID<br>PEAK TRANSIENT POWER (W)<br>,<br>(PK)<br>P<br>**----- End of picture text -----**<br> **==> picture [183 x 19] intentionally omitted <==** **----- Start of picture text -----**<br> Figure 8. Capacitance vs. Drain Capacitance vs. Drain<br>to Source Voltage<br>**----- End of picture text -----**<br> **Figure 10. Maximum Continuous Drain Maximum Continuous Drain Current vs. Case Temperature** ©2016 Fairchild Semiconductor Corporation **5** www.fairchildsemi.com FDMD8560L Rev.1.0 **==> picture [454 x 208] intentionally omitted <==** **----- Start of picture text -----**<br> Typical Characteristics (Q1 N-Channel) TJ = 25°C unless otherwise noted.<br>2<br>1 DUTY CYCLE-DESCENDING ORDER<br>D = 0.5<br> 0.2<br> 0.1<br>0.1 0.05 PDM<br> 0.02<br> 0.01<br>t 1<br>t 2<br>0.01 NOTES:<br>Z θ JC(t) = r(t) x R θ JC<br>SINGLE PULSE R θ JC = 2.6 [o] C/W<br>Peak T J = P DM x Z θ JC (t) + T C<br>Duty Cycle, D = t 1 / t 2<br>0.001<br>10-5 10-4 10-3 10-2 10-1 1<br>t, RECTANGULAR PULSE DURATION (sec)<br>Figure 13. Junction-to-Case Transient Thermal Response Curve<br>THERMAL RESISTANCE<br>r(t), NORMALIZED EFFECTIVE TRANSIENT<br>**----- End of picture text -----**<br> ©2016 Fairchild Semiconductor Corporation **6** www.fairchildsemi.com FDMD8560L Rev.1.0 **Typical Characteristics (Q2 N-Channel)** TJ = 25 °C unless otherwise noted. **==> picture [456 x 594] intentionally omitted <==** **----- Start of picture text -----**<br> 180 6<br>VGS = 10 V PULSE DURATION = 80 μ s<br>150 VGS = 4.5 V DUTY CYCLE = 0.5% MAX<br>VGS = 4 V<br>120 VGS = 3.5 V 4<br>VGS = 3 V<br>90<br>VGS = 3 V VGS = 3.5 V VGS = 4 V<br>60 2<br>VGS = 4.5 V<br>30<br>PULSE DURATION = 80 μ s VGS = 10 V<br>DUTY CYCLE = 0.5% MAX<br>0 0<br>0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 30 60 90 120 150 180<br>VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 14. On- Region Characteristics Figure 15. Normalized on-Resistance vs. Drain<br>Current and Gate Voltage<br>1.8 12<br>1.7 ID = 22 A PULSE DURATION = 80 μ s<br>1.6 VGS = 10 V DUTY CYCLE = 0.5% MAX<br>9<br>1.5<br>1.4 ID = 22 A<br>1.3<br>6<br>1.2<br>1.1 TJ = 125 [o] C<br>1.0 3<br>0.9<br>TJ = 25 [o] C<br>0.8<br>0.7 0<br>-75 -50 -25 0 25 50 75 100 125 150 2 3 4 5 6 7 8 9 10<br>TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 16. Normalized On-Resistance Figure 17. On-Resistance vs. Gate to<br> vs. Junction Temperature Source Voltage<br>180 200<br>PULSE DURATION = 80 μ s 100 VGS = 0 V<br>DUTY CYCLE = 0.5% MAX<br>150<br>VDS = 5 V 10<br>120<br>TJ = 150 [o] C<br>1<br>90<br>TJ = 25 [o] C<br>0.1<br>60<br>TJ = 150 [o] C TJ = 25 [o] C TJ = -55 [o] C<br>30 0.01<br>TJ = -55 [o] C<br>0 0.001<br>1 2 3 4 5 0.0 0.2 0.4 0.6 0.8 1.0 1.2<br>VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)<br>NORMALIZED<br>, DRAIN CURRENT (A)<br>ID<br>DRAIN TO SOURCE ON-RESISTANCE<br>) Ω<br>(m<br>DRAIN TO<br>NORMALIZED rDS(on),<br>SOURCE ON-RESISTANCE<br> DRAIN TO SOURCE ON-RESISTANCE<br>, DRAIN CURRENT (A)<br>ID<br>, REVERSE DRAIN CURRENT (A)<br>IS<br>**----- End of picture text -----**<br> **Figure 18. Transfer Characteristics** **Figure 19. Source to Drain Diode Forward Voltage vs. Source Current** ©2016 Fairchild Semiconductor Corporation **7** www.fairchildsemi.com FDMD8560L Rev.1.0 ## **Typical Characteristics (Q2 N-Channel)** TJ = 25°C unless otherwise noted. **==> picture [458 x 609] intentionally omitted <==** **----- Start of picture text -----**<br> 10 10000<br>ID = 22 A Ciss<br>8<br>6 V DD = 20 V VDD = 30 V 1000<br>Coss<br>VDD = 40 V<br>4<br>100<br>2 f = 1 MHz<br>VGS = 0 V<br>Crss<br>0 10<br>0 20 40 60 80 100 0.1 1 10 100<br>Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 20. Gate Charge Characteristics Figure 21. Capacitance vs. Drain<br>to Source Voltage<br>100 100<br>80<br>VGS = 10 V<br>TJ = 25 [ o] C TJ = 100 [o] C 60<br>10 VGS = 4.5 V<br>TJ = 125 [o] C 40<br>20<br>R θ JC = 2.6 [o] C/W<br>1 0<br>0.001 0.01 0.1 1 10 100 1000 25 50 75 100 125 150<br>tAV, TIME IN AVALANCHE (ms) TC, CASE TEMPERATURE (oC)<br>Figure 22. Unclamped Inductive Figure 23. Maximum Continuous Drain<br>Switching Capability Current vs. Case Temperature<br>1000 105<br>SINGLE PULSE<br>100 R θ JC = 2.6 [o] C/W<br>10 μ s 104 TC = 25 [o] C<br>10<br>THIS AREA IS 100 μ s 103<br>1 LIMITED BY rDS(on) 1 ms<br>10 ms<br>SINGLE PULSE<br>0.1 T J = MAX RATED 100 m s 102<br>R θ JC = 2.6 [ o] C/W CURVE BENT TO<br>TC = 25 [o] C MEASURED DATA<br>0.01 10<br>0.01 0.1 1 10 100200 10-5 10-4 10-3 10-2 10-1 1<br>VDS, DRAIN to SOURCE VOLTAGE (V)<br>t, PULSE WIDTH (sec)<br>Figure 24. Forward Bias Safe Figure 25. Single Pulse Maximum Power<br>Operating Area Dissipation<br>CAPACITANCE (pF)<br>, GATE TO SOURCE VOLTAGE (V)<br>GS<br>V<br>DRAIN CURRENT (A)<br>,<br>ID<br>, AVALANCHE CURRENT (A)<br>IAS<br>, DRAIN CURRENT (A)<br>ID<br>PEAK TRANSIENT POWER (W)<br>,<br>(PK)<br>P<br>**----- End of picture text -----**<br> ©2016 Fairchild Semiconductor Corporation **8** www.fairchildsemi.com FDMD8560L Rev.1.0 **==> picture [450 x 195] intentionally omitted <==** **----- Start of picture text -----**<br> Typical Characteristics (Q2 N-Channel) TJ = 25 °C unless otherwise noted.<br>2<br>1 DUTY CYCLE-DESCENDING ORDER<br>D = 0.5<br> 0.2<br> 0.1 PDM<br>0.1 0.05<br> 0.02<br> 0.01 t1<br>t 2<br>NOTES:<br>0.01<br>Z θ JC(t) = r(t) x R θ JC<br>SINGLE PULSE R θ JC = 2.6 [o] C/W<br>Peak TJ = PDM x Z θ JC(t) + TC<br>Duty Cycle, D = t1 / t2<br>0.001<br>10-5 10-4 10-3 10-2 10-1 1<br>t, RECTANGULAR PULSE DURATION (sec)<br>THERMAL RESISTANCE<br>r(t), NORMALIZED EFFECTIVE TRANSIENT<br>**----- End of picture text -----**<br> **Figure 26. Junction-to-Case Transient Thermal Response Curve** ©2016 Fairchild Semiconductor Corporation **9** www.fairchildsemi.com FDMD8560L Rev.1.0 **==> picture [95 x 114] intentionally omitted <==** **==> picture [83 x 126] intentionally omitted <==** **==> picture [95 x 114] intentionally omitted <==** **==> picture [82 x 44] intentionally omitted <==** ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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Updated at June 9, 2026
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