FDMD8530

## **Is Now Part of** 

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ON Semiconductor and the ON Semiconductor logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. 

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## **FDMD8530** 

## **Dual N-Channel PowerTrench[®] MOSFET Q1: 30 V, 201 A, 1.25 m** Ω **Q2: 30 V, 201 A, 1.25 m** Ω 

## **Features** 

Q1: N-Channel 

Max rDS(on) = 1.25 mΩ at VGS = 10 V, ID = 35 A 

Max rDS(on) = 1.5 mΩ at VGS = 4.5 V, ID = 32 A 

Q2: N-Channel 

Max rDS(on) = 1.25 mΩ at VGS = 10 V, ID = 35 A Max rDS(on) = 1.5 mΩ at VGS = 4.5 V, ID = 32 A 

## **General Description** 

This device includes two 30V N-Channel MOSFETs in a dual power (5 mm X 6 mm) package. HS source and LS drain internally connected for half/full bridge, low source inductance package, low rDS(on)/Qg FOM silicon. 

## **Applications** 

POL Synchronous Dual 

One Phase Motor Half Bridge 

Ideal for Flexible Layout in Primary Side of Bridge Topology 

Half/Full Bridge Secondary Synchronous Rectification 

100% UIL Tested 

Kelvin High Side MOSFET Drive Pin-out Capability RoHS Compliant 

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Top Bottom<br>D2/S1<br>Pin 1 D2/S1 G1 G2<br>D2/S1<br>S2 G2 GR D2/S1<br>D1 D1 D1 D2/S1<br>D1<br>D1 D2/S1<br>GR<br>G1 Pin 1<br>Power 5 x 6<br>MOSFET Maximum Ratings TA = 25 °C unless otherwise noted.<br>yO Symbol Parameter Q1 Q2 Units<br>a VDS Drain to Source Voltage 30 30 V<br>a VGS Gate to Source Voltage                                                                              ±20 ±20 V<br> a Drain Current     -Continuous                                      TC = 25 °C                (Note 5) 201 201<br>ID aa Drain Current     -Continuous                                  T                          -Continuous                                   TA C = 25 °C             = 100 °C            (Note 5) 35127 [1a] 35127 [1b] A<br>a                           -Pulsed                                                                         (Note 4) 1047 1047<br>EAS Single Pulse Avalanche Energy (Note 3) 661 661 mJ<br>a<br>—_——————EEE PD a Power Dissipation                                                   TPower Dissipation                                                   TAC = 25 °C              = 25 °C             2.278 [1a] 2.278 [1b] W<br>a TJ, TSTG Operating and Storage Junction Temperature Range -55 to +150 °C<br>Thermal Characteristics<br>RθJC Thermal Resistance, Junction-to-Case                                                1.6 1.6<br>°C/W<br>RθJA Thermal Resistance, Junction-to-Ambient                                                  55 [1a] 55  [1b]<br>Package Marking and Ordering Information<br>Device Marking Device Package Reel Size Tape Width Quantity<br>FDMD8530 FDMD8530 Power 5 x 6 13 ’’ 12 mm 3000 units<br>**----- End of picture text -----**<br>


©2015 Fairchild Semiconductor Corporation **1** www.fairchildsemi.com FDMD8530 Rev.1.0 

## **Electrical Characteristics** TJ = 25 °C unless otherwise noted. 

|**Electri**|**cal Characteristics**TJ= 25 °C|unless otherwise noted.||||||
|---|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test Conditions**|**Type**|**Min.**|**Typ.**|**Max.**|**Units**|
|**Off Characteristics**||||||||
|BVDSS|Drain to Source Breakdown Voltage|ID= 250μA, VGS= 0 V|Q1<br>Q2|30<br>30|||V|
|ΔBVDSS<br>ΔTJ|Breakdown Voltage Temperature<br>Coefficient|ID= 250μA, referenced to 25 °C|Q1<br>Q2||20<br>20||mV/°C|
|IDSS|Zero Gate Voltage Drain Current|VDS= 24 V, VGS= 0 V|Q1<br>Q2|||1<br>1|μA|
|IGSS|Gate to Source Leakage Current|VGS= ±20 V, VDS= 0 V|Q1<br>Q2|||±100<br>±100|nA|
|**On Characteristics**||||||||
|VGS(th)|Gate to Source Threshold Voltage|VGS= VDS,  ID= 250μA|Q1<br>Q2|1.0<br>1.0|1.5<br>1.5|3.0<br>3.0|V|
|ΔVGS(th)<br>ΔTJ|Gate to Source Threshold Voltage<br>Temperature Coefficient|ID= 250μA, referenced to 25 °C|Q1<br>Q2||-5<br>-5||mV/°C|
|rDS(on)|Static Drain to Source On Resistance|VGS= 10 V,  ID= 35 A|Q1||0.77|1.25|mΩ|
|||VGS= 4.5 V,  ID= 32 A|||0.96|1.5||
|||VGS= 10 V,  ID= 35 A, TJ= 125 °C|||1.1|1.8||
|||VGS= 10 V,  ID= 35 A|Q2||0.77|1.25||
|||VGS= 4.5 V,  ID= 32 A|||0.96|1.5||
|||VGS= 10 V,  ID= 35 A, TJ= 125 °C|||1.1|1.8||
|gFS|Forward Transconductance|VDD= 5 V,  ID= 35 A|Q1<br>Q2||259<br>259||S|
|**Dynamic Characteristics**||||||||
|Ciss|Input Capacitance|VDS= 15 V, VGS= 0 V<br>f = 1 MHz|Q1<br>Q2||7425<br>7425|10395<br>10395|pF|
|Coss|Output Capacitance||Q1<br>Q2||2190<br>2190|3070<br>3070|pF|
|Crss|Reverse Transfer Capacitance||Q1<br>Q2||220<br>220|310<br>310|pF|
|Rg|Gate Resistance||Q1<br>Q2|0.1<br>0.1|1.9<br>1.9|3.8<br>3.8|Ω|
|**Switching Characteristics**||||||||
|td(on)|Turn-On Delay Time|VDD= 15 V, ID= 35 A<br>VGS= 10 V, RGEN= 6Ω|Q1<br>Q2||14<br>14|25<br>25|ns|
|tr|Rise Time||Q1<br>Q2||13<br>13|24<br>24|ns|
|td(off)|Turn-Off Delay Time||Q1<br>Q2||71<br>71|114<br>114|ns|
|tf|Fall Time||Q1<br>Q2||21<br>21|34<br>34|ns|
|Qg(TOT)|Total Gate Charge|VGS= 0 V to 10 V|Q1<br>Q2||106<br>106|149<br>149|nC|
|Qg(TOT)|Total Gate Charge|VGS= 0 V to 4.5 V|Q1<br>Q2||50<br>50|70<br>70|nC|
|Qgs|Gate to Source Charge||Q1<br>Q2||16<br>16||nC|
|Qgd|Gate to Drain “Miller” Charge||Q1<br>Q2||13<br>13||nC|



©2015 Fairchild Semiconductor Corporation **2** www.fairchildsemi.com FDMD8530 Rev.1.0 

**Electrical Characteristics** TJ = 25 °C unless otherwise noted. 

|VSD|Source to Drain Diode Forward Voltage|VGS= 0 V, IS= 35 A                    (Note 2)|Q1<br>Q2||0.8<br>0.8|1.3<br>1.3|V|
|---|---|---|---|---|---|---|---|
|VSD|Source to Drain Diode Forward Voltage|VGS= 0 V, IS= 2 A                    (Note 2)|Q1<br>Q2||0.7<br>0.7|1.2<br>1.2|V|
|trr|Reverse Recovery Time|IF= 35 A, di/dt = 100 A/μs|Q1<br>Q2||54<br>54|87<br>87|ns|
|Qrr|Reverse Recovery Charge||Q1<br>Q2||39<br>39|63<br>63|nC|



NOTES: 

1. RθJA is determined with the device mounted on a 1 in[2] pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθCA is determined by the user's board design. 

a. 55 °C/W when mounted on b. 55 °C/W when mounted on a 1 in[2 ] pad of  2 oz  copper a 1 in[2 ] pad of  2 oz  copper 

c. 155 °C/W when mounted on d. 155 °C/W when mounted on a minimum pad of  2 oz  copper a minimum pad of  2 oz  copper 

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2. Pulse Test: Pulse Width < 30 0 μs, Duty cycle < 2.0 %. 

3. Q1: EAS of  661 mJ is based on starting TJ = 25[o] C, L = 3 mH, IAS = 21 A, VDD =  30 V, VGS = 10 V. 100% tested at L = 0.1 mH, IAS = 65 A. Q2: EAS of  661 mJ is based on starting TJ = 25[o] C, L = 3 mH, IAS = 21 A, VDD =  30 V, VGS =  10 V. 100% tested at L = 0.1 mH, IAS = 65 A. 

4. Pulsed Id please refer to Fig 11 SOA graph for more details. 

5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design. 

©2015 Fairchild Semiconductor Corporation **3** www.fairchildsemi.com FDMD8530 Rev.1.0 

## **Typical Characteristics (Q1 N-Channel)** TJ = 25°C unless otherwise noted. 

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150 20<br>PULSE DURATION = 80  μ s PULSE DURATION = 80  μ s<br>DUTY CYCLE = 0.5% MAX VGS = 2.5 V DUTY CYCLE = 0.5% MAX<br>120<br>VGS =  10 V 15<br>VGS =  4.5 V<br>90<br>VGS = 3.5 V 10<br>60<br>30 VGS =  3 V VGS = 2.5 V 5 V GS  = 10 V V GS  = 4.5 V V GS  =  3.5 V VGS = 3 V<br>0 0<br>0.0 0.2 0.4 0.6 0.8 1.0 0 30 60 90 120 150<br>VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 1.  On Region Characteristics Figure 2.  Normalized On-Resistance<br>vs. Drain Current and Gate Voltage<br>1.6 5<br>ID = 35 A PULSE DURATION = 80  μ s<br>1.5 V GS  = 10 V DUTY CYCLE = 0.5% MAX<br>4<br>1.4 ID = 35 A<br>1.3<br>3<br>1.2<br>2<br>1.1<br>TJ = 125  [o] C<br>1.0<br>1<br>0.9<br>TJ = 25  [o] C<br>0.8 0<br>-75 -50 -25 0 25 50 75 100 125 150 2 4 6 8 10<br>TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 3.  Normalized  On  Resistance                                         Figure 4.   On-Resistance vs.  Gate to<br>vs. Junction Temperature Source Voltage<br>150 200<br>PULSE DURATION = 80  μ s 100 VGS = 0 V<br>DUTY CYCLE = 0.5% MAX<br>120<br>VDS = 5 V TJ = 150  [o] C 10 TJ = 150  [o] C<br>90<br>1<br>TJ = 25  [o] C TJ = 25 [ o] C<br>60 0.1<br>30 0.01 T J  = -55  [o] C<br>TJ = -55  [o] C<br>0 0.001<br>1.0 1.5 2.0 2.5 3.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2<br>VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)<br>NORMALIZED<br>, DRAIN CURRENT (A)<br>ID<br>DRAIN TO SOURCE ON-RESISTANCE<br>) Ω<br>(m<br>DRAIN TO<br>NORMALIZED rDS(on),<br>SOURCE ON-RESISTANCE<br> DRAIN TO SOURCE ON-RESISTANCE<br>, DRAIN CURRENT (A)<br>ID<br>, REVERSE DRAIN CURRENT (A)<br>IS<br>**----- End of picture text -----**<br>


**Figure 5.  Transfer Characteristics** 

**Figure 6. Forward Voltage vs. Source Current** 

©2015 Fairchild Semiconductor Corporation **4** www.fairchildsemi.com FDMD8530 Rev.1.0 

## **Typical Characteristics (Q1 N-Channel)** TJ = 25°C unless otherwise noted. 

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10 10000<br>ID = 35 A Ciss<br>8<br>VDD = 15 V<br>6 VDD = 10 V VDD = 20 V 1000 Coss<br>4<br>2 f = 1 MHz<br>VGS = 0 V Crss<br>0 100<br>0 22 44 66 88 110 0.1 1 10 30<br>Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 7.  Gate Charge Characteristics Figure 8. Capacitance vs. Drain<br>to Source Voltage<br>100 210<br>180<br>T J  = 25 [ o] C VGS = 10 V<br>150<br>TJ = 100  [o] C<br>120<br>10 90 VGS = 4.5 V<br>TJ = 125  [o] C 60<br>30<br>R θ JC = 1.6  [o] C/W<br>1 0<br>0.001 0.01 0.1 1 10 100 1000 25 50 75 100 125 150<br>tAV, TIME IN AVALANCHE (ms) TC, CASE TEMPERATURE (oC)<br>Figure 9. Unclamped Inductive   Figure 10.  Maximum Continuous Drain<br>Switching Capability Current  vs. Case Temperature<br>2000 100000<br>1000 SINGLE PULSE<br>R θ JC = 1.6  [o] C/W<br>10  μ s 10000 TC = 25  [o] C<br>100<br>10 THIS AREA IS  100  μ s 1000<br>LIMITED BY r<br>DS(on)<br>1 ms<br>SINGLE PULSE<br>1 TJ = MAX RATED 10 ms 100<br>R θ JC = 1.6 [ o] C/W CURVE BENT TO  100 ms/DC<br>T C = 25  [o] C MEASURED DATA<br>0.1 10<br>0.1 1 10 100 200 10-5 10-4 10-3 10-2 10-1 1<br>VDS, DRAIN to SOURCE VOLTAGE (V) t, PULSE WIDTH (sec)<br>Figure 11.  Forward Bias Safe     Figure 12.  Single Pulse  Maximum Power<br>Operating Area Dissipation<br>CAPACITANCE (pF)<br>, GATE TO SOURCE VOLTAGE (V)<br>GS<br>V<br>DRAIN CURRENT (A)<br>,<br>ID<br>, AVALANCHE CURRENT (A)<br>IAS<br>, DRAIN CURRENT (A)<br>ID<br>PEAK TRANSIENT POWER (W)<br>,<br>(PK)<br>P<br>**----- End of picture text -----**<br>


©2015 Fairchild Semiconductor Corporation FDMD8530 Rev.1.0 

www.fairchildsemi.com 

**5** 

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Typical Characteristics (Q1 N-Channel)  TJ = 25°C unless otherwise noted.<br>2<br>1 DUTY CYCLE-DESCENDING ORDER<br>D = 0.5<br>      0.2<br>      0.1<br>0.1       0.05 PDM<br>      0.02<br>      0.01<br>t1<br>t 2<br>0.01 NOTES:<br>SINGLE PULSE<br>Z θ JC(t) = r(t) x R θ JC<br>R θ JC = 1.6  [o] C/W<br>Peak T J  = P DM  x Z θ JC (t) + T C<br>Duty Cycle, D = t 1  / t 2<br>0.001<br>10-5 10-4 10-3 10-2 10-1 1<br>t, RECTANGULAR PULSE DURATION (sec)<br>Figure 13.  Junction-to-Case Transient Thermal Response Curve<br>THERMAL RESISTANCE<br>r(t), NORMALIZED EFFECTIVE TRANSIENT<br>**----- End of picture text -----**<br>


©2015 Fairchild Semiconductor Corporation **6** www.fairchildsemi.com FDMD8530 Rev.1.0 

## **Typical Characteristics (Q2 N-Channel)** TJ = 25 °C unless otherwise noted. 

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150 20<br>PULSE DURATION = 80  μ s PULSE DURATION = 80  μ s<br>DUTY CYCLE = 0.5% MAX VGS = 2.5 V DUTY CYCLE = 0.5% MAX<br>120<br>VGS =  10 V 15<br>VGS =  4.5 V<br>90<br>VGS = 3.5 V 10<br>60<br>30 VGS =  3 V VGS = 2.5 V 5 V GS  = 10 V V GS  = 4.5 V V GS  =  3.5 V VGS = 3 V<br>0 0<br>0.0 0.2 0.4 0.6 0.8 1.0 0 30 60 90 120 150<br>VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 14. On- Region Characteristics Figure 15. Normalized on-Resistance vs. Drain<br>Current and Gate  Voltage<br>1.6 5<br>ID = 35 A PULSE DURATION = 80  μ s<br>1.5 V GS  = 10 V DUTY CYCLE = 0.5% MAX<br>4<br>1.4 ID = 35 A<br>1.3 3<br>1.2<br>2<br>1.1<br>TJ = 125  [o] C<br>1.0<br>1<br>0.9<br>TJ = 25  [o] C<br>0.8 0<br>-75 -50 -25 0 25 50 75 100 125 150 2 4 6 8 10<br>TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 16. Normalized On-Resistance  Figure 17. On-Resistance vs. Gate to<br> vs. Junction Temperature Source Voltage<br>150 200<br>PULSE DURATION = 80  μ s 100 VGS = 0 V<br>DUTY CYCLE = 0.5% MAX<br>120<br>VDS = 5 V TJ = 150  [o] C 10 TJ = 150  [o] C<br>90<br>1<br>TJ = 25  [o] C TJ = 25 [ o] C<br>60 0.1<br>30 0.01 T J  = -55  [o] C<br>TJ = -55  [o] C<br>0 0.001<br>1.0 1.5 2.0 2.5 3.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2<br>VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)<br>NORMALIZED<br>, DRAIN CURRENT (A)<br>ID<br>DRAIN TO SOURCE ON-RESISTANCE<br>) Ω<br>(m<br>DRAIN TO<br>NORMALIZED rDS(on),<br>SOURCE ON-RESISTANCE<br> DRAIN TO SOURCE ON-RESISTANCE<br>, DRAIN CURRENT (A)<br>ID<br>, REVERSE DRAIN CURRENT (A)<br>IS<br>**----- End of picture text -----**<br>


**Figure 18. Transfer Characteristics** 

**Figure 19. Source to Drain Diode Forward Voltage vs. Source Current** 

©2015 Fairchild Semiconductor Corporation **7** www.fairchildsemi.com FDMD8530 Rev.1.0 

## **Typical Characteristics (Q2 N-Channel)** TJ = 25°C unless otherwise noted. 

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10 10000<br>ID = 35 A Ciss<br>8<br>VDD = 15 V<br>6 VDD = 10 V VDD = 20 V 1000 Coss<br>4<br>2 f = 1 MHz<br>VGS = 0 V Crss<br>0 100<br>0 22 44 66 88 110 0.1 1 10 30<br>Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 20. Gate Charge Characteristics Figure 21. Capacitance vs. Drain<br>to Source Voltage<br>100 210<br>180<br>T J  = 25 [ o] C VGS = 10 V<br>150<br>TJ = 100  [o] C<br>120<br>10 90 VGS = 4.5 V<br>TJ = 125  [o] C 60<br>30<br>R θ JC = 1.6  [o] C/W<br>1 0<br>0.001 0.01 0.1 1 10 100 1000 25 50 75 100 125 150<br>tAV, TIME IN AVALANCHE (ms) TC, CASE TEMPERATURE (oC)<br>Figure 22. Unclamped Inductive  Figure 23. Maximum   Continuous   Drain<br>Switching Capability Current  vs. Case Temperature<br>2000 100000<br>1000 SINGLE PULSE<br>R θ JC = 1.6  [o] C/W<br>10  μ s 10000 TC = 25  [o] C<br>100<br>10 THIS AREA IS  100  μ s 1000<br>LIMITED BY rDS(on)<br>1 ms<br>SINGLE PULSE<br>1 TJ = MAX RATED 10 ms 100<br>R θ JC = 1.6 [ o] C/W CURVE BENT TO  100 ms/DC<br>T C = 25  [o] C MEASURED DATA<br>0.1 10<br>0.1 1 10 100 200 10-5 10-4 10-3 10-2 10-1 1<br>VDS, DRAIN to SOURCE VOLTAGE (V) t, PULSE WIDTH (sec)<br>CAPACITANCE (pF)<br>, GATE TO SOURCE VOLTAGE (V)<br>GS<br>V<br>DRAIN CURRENT (A)<br>,<br>ID<br>, AVALANCHE CURRENT (A)<br>IAS<br>, DRAIN CURRENT (A)<br>ID<br>PEAK TRANSIENT POWER (W)<br>,<br>(PK)<br>P<br>**----- End of picture text -----**<br>


**Operating Area** 

**Figure 25. Single Pulse  Maximum Power Dissipation** 

©2015 Fairchild Semiconductor Corporation **8** www.fairchildsemi.com FDMD8530 Rev.1.0 

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Typical Characteristics (Q2 N-Channel)  TJ = 25 °C unless otherwise noted.<br>2<br>1 DUTY CYCLE-DESCENDING ORDER<br>D = 0.5<br>      0.2<br>0.1       0.1       0.05 PDM<br>      0.02<br>      0.01<br>t 1<br>t2<br>0.01 NOTES:<br>SINGLE PULSE Z θ JC(t) = r(t) x R θ JC<br>R θ JC = 1.6  [o] C/W<br>Peak T J  = P DM  x Z θ JC (t) + T C<br>Duty Cycle, D = t1 / t2<br>0.001<br>10-5 10-4 10-3 10-2 10-1 1<br>t, RECTANGULAR PULSE DURATION (sec)<br>Figure 26. Junction-to-Case Transient Thermal Response Curve<br>THERMAL RESISTANCE<br>r(t), NORMALIZED EFFECTIVE TRANSIENT<br>**----- End of picture text -----**<br>


©2015 Fairchild Semiconductor Corporation **9** www.fairchildsemi.com FDMD8530 Rev.1.0 

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