FDMD82100L

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June 2014<br>**----- End of picture text -----**<br>


## **FDMD82100L** 

## **Dual N-Channel PowerTrench[®] MOSFET 100 V, 24 A, 19.5 m** Ω 

## **Features** 

Max rDS(on) = 19.5 mΩ at VGS = 10 V, ID = 7 A 

Max rDS(on) = 30 mΩ at VGS = 4.5 V, ID = 5.7 A 

Ideal for flexible layout in primary side of bridge topology 

Termination is Lead-free and RoHS Compliant 

## **General Description** 

This device includes two 100V N-Channel MOSFETs in a dual Power (3.3 mm X 5 mm) package. HS source and LS Drain internally connected for half/full bridge, low source inductance package, low rDS(on)/Qg FOM silicon. 

## **Applications** 

100% UIL tested 

Kelvin High Side MOSFET drive pin-out capability 

Synchronous Buck : Primary Switch of Half / Full bridge converter for telecom 

Motor Bridge : Primary Switch of Half / Full bridge converter for BLDC motor 

MV POL : 48V Synchronous Buck Switch 

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Pin 1<br>**----- End of picture text -----**<br>


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D1 1 - Le 12 G1<br>D1 2 > o 11 G1R<br>D1 3 10 D2/S1<br>G2 4 -- _ 9 D2/S1<br>_ --<br>S2 5 8 D2/S1<br>- -<br>S2 6 7 D2/S1<br>**----- End of picture text -----**<br>


**Power 3.3 x 5** 

## **MOSFET Maximum Ratings** TA = 25 °C unless otherwise noted 

|**Symbol**||**Parameter**||||**Ratings**|||**Units**|
|---|---|---|---|---|---|---|---|---|---|
|VDS|Drain to Source Voltage|||||100|||V|
|VGS|Gate to Source Voltage|e|e|e||±20|||V|
||Drain Current    -Continuous                                  T|Drain Current    -Continuous                                  TC = 25 °C||= 25 °C||24||||
|ID|-Continuous                                   T|-Continuous                                   TA= 25 °C||= 25 °C(Note 1a)||7|||A|
||-Pulsed                                          T|-Pulsed                                          TA= 25 °C|= 25 °C|= 25 °C(Note 4)||80||||
|EAS|Single Pulse Avalanche Energy|||(Note 3)||150|||mJ|
||Power Dissipation                                                   T|ation                                                   TC= 25 °C||= 25 °C||38||||
|PD|Power Dissipation                                                      T|ation                                                      TA= 25 °C||= 25 °C(Note 1a)||2.1|||W|
||Power Dissipation                                                      T|ation                                                      TA= 25 °C||= 25 °C(Note 1b)||1||||
|TJ, TSTG|Operatingand Storage Junction Temperature Range|||||-55 to +150|||°C|
|**Thermal Characteristics**||||||||||
|RθJC|Thermal Resistance, Junction to Case||Thermal Resistance, Junction to Case|Thermal Resistance, Junction to Case||3.3||||
|RθJA|Thermal Resistance, Junction to Ambient                                                 (Note 1a)||Thermal Resistance, Junction to Ambient                                                 (Note 1a)|Thermal Resistance, Junction to Ambient                                                 (Note 1a)||60|||°C/W|
|RθJA|Thermal Resistance, Junction to Ambient||Thermal Resistance, Junction to Ambient|Thermal Resistance, Junction to Ambient(Note 1b)||130||||
|**Package Marking and Ordering Information**||||||||||
|**Device Marking**<br>**Device**||**Package**||**Reel Size**||**Tape Width**||**Quantity**||
|82100L|FDMD82100L|Power 3.3 x 5||13 ’’||12 mm||3000 units||



## **Thermal Characteristics** 

## **Package Marking and Ordering Information** 

**1** 

©2014 Fairchild Semiconductor Corporation FDMD82100L Rev.C1 

www.fairchildsemi.com 

**Electrical Characteristics** TJ = 25 °C unless otherwise noted 

|**Electrical Characteristics**TJ = 25 °C unless otherwise notedJ = 25 °C unless otherwise noted= 25 °C unless otherwise noted|**Electrical Characteristics**TJ = 25 °C unless otherwise notedJ = 25 °C unless otherwise noted= 25 °C unless otherwise noted|
|---|---|
|**Off Characteristics**<br>**On Characteristics**<br>**Dynamic Characteristics**<br>**Switching Characteristics**<br>**Symbol**<br>**Parameter**<br>**Test Conditions**<br>**Min**<br>**Typ**<br>**Max**<br>**Units**<br>BVDSS<br>Drain to Source Breakdown Voltage<br>ID= 250μA, VGS= 0 V<br>100<br>V<br>ΔBVDSS<br>ΔTJ<br>Breakdown Voltage Temperature<br>Coefficient<br>ID= 250μA, referenced to 25 °C<br>70<br>mV/°C<br>IDSS<br>Zero Gate Voltage Drain Current<br>VDS= 80 V, VGS = 0 V<br>1<br>μA<br>IGSS<br>Gate to Source Leakage Current<br>VGS= ±20 V, VDS = 0 V<br>±100<br>nA<br>VGS(th)<br>Gate to Source Threshold Voltage<br>VGS= VDS,  ID= 250μA<br>1.0<br>1.7<br>3.0<br>V<br>ΔVGS(th)<br>ΔTJ<br>Gate to Source Threshold Voltage<br>Temperature Coefficient<br>ID= 250μA, referenced to 25 °C<br>-6<br>mV/°C<br>rDS(on)<br>Static Drain to Source On Resistance<br>VGS= 10 V,  ID= 7 A<br>13.5<br>19.5<br>mΩ<br>VGS= 4.5 V,  ID= 5.7 A<br>17.9<br>30<br>VGS= 10 V,  ID= 7 A, TJ= 125 °C<br>25<br>36<br>gFS<br>Forward Transconductance<br>VDD= 5 V,  ID= 7 A<br>29<br>S<br>Ciss<br>Input Capacitance<br>VDS= 50 V, VGS= 0 V<br>f = 1 MHz<br>1130<br>1585<br>pF<br>Coss<br>Output Capacitance<br>173<br>245<br>pF<br>Crss<br>Reverse Transfer Capacitance<br>8.1<br>15<br>pF<br>Rg<br>Gate Resistance<br>0.1<br>1.8<br>3.6<br>Ω<br>~~ee~~<br>~~————~~||
|td(on)<br>Turn-On DelayTime<br>VDD= 50 V, ID= 7 A<br>VGS= 10 V, RGEN= 6Ω<br>7.9<br>16<br>ns<br>tr<br>Rise Time<br>2.8<br>10<br>ns<br>td(off)<br>Turn-Off DelayTime<br>21<br>34<br>ns<br>tf<br>Fall Time<br>2.9<br>10<br>ns<br>Qg(TOT)<br>Total Gate Charge<br>VGS= 0 V to 10 V<br>VDD= 50 V<br>ID= 7 A<br>17<br>24<br>nC<br>Total Gate Charge<br>VGS= 0 V to 4.5 V<br>8<br>12<br>nC<br>Qgs<br>Gate to Source Charge<br>3<br>nC<br>Qgd<br>Gate to Drain “Miller” Charge<br>2.3<br>nC<br>~~eee~~<br>~~——————~~||
|**Drain-Source Diode Characteristics**||
|VSD<br>Source to Drain Diode Forward Voltage<br>VGS = 0 V, IS = 7 A(Note 2)<br>0.8<br>1.2<br>V<br>trr<br>Reverse RecoveryTime<br>IF= 7 A, di/dt = 100 A/μs<br>42<br>67<br>ns<br>Qrr<br>Reverse RecoveryCharge<br>39<br>62<br>nC<br>~~————————~~||
|NOTES:||
|1. RθJAis determined with the device mounted on a 1 in2pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJCis guaranteed by design while RθCAis determined by||
|the user's board design.||



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a. 60 °C/W when mounted on b. 130 °C/W when mounted on<br>      a 1 in [2 ] pad of  2 oz  copper              a minimum pad of  2 oz  copper<br>G DF DS SF SS<br>G DF DS SF SS<br>**----- End of picture text -----**<br>


2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %. 

3. EAS of 150 mJ is based on starting TJ = 25[o] C, L = 3 mH, IAS = 10 A, VDD = 90 V, VGS = 10 V.  100% tested at L = 0.1 mH, IAS = 31 A. 

4. Pulse Id refers to Figure.11 Forward Bias Safe Operation Area. 

©2014 Fairchild Semiconductor Corporation FDMD82100L Rev.C1 

www.fairchildsemi.com 

**2** 

**Typical Characteristics (N-Channel)** TJ = 25 °C unless otherwise noted 

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80 5<br>VGS = 10 V VGS =  6 V VGS =  3 V PULSE DURATION = 80DUTY CYCLE = 0.5% MAX  μ s<br>4<br>60 VGS = 4.5 V<br>VGS =  4 V 3 VGS = 3.5 V<br>40 VGS =  4 V<br>VGS = 3.5 V 2<br>20<br>1<br>VGS = 3 V PULSE DURATION = 80  μ s VGS = 4.5 V VGS = 6 V VGS = 10 V<br>DUTY CYCLE = 0.5% MAX<br>0 0<br>0 1 2 3 4 5 0 20 40 60 80<br>VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 1.  On Region Characteristics Figure 2.      Normalized On-Resistance<br>vs Drain Current and Gate Voltage<br>2.4 100<br>ID = 7 A PULSE DURATION = 80  μ s<br>VGS = 10 V DUTY CYCLE = 0.5% MAX<br>2.0 80<br>ID = 7 A<br>1.6 60<br>1.2 40<br>TJ = 125  [o] C<br>0.8 20<br>TJ = 25  [o] C<br>0.4 0<br>-75 -50 -25 0 25 50 75 100 125 150 2 4 6 8 10<br>TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 3.  Normalized  On  Resistance                                         Figure 4.   On-Resistance vs  Gate to<br>vs Junction Temperature Source Voltage<br>80 80<br>TJ = -55  [o] C VGS = 0 V<br>TJ = 150  [o] C 10<br>60 TJ = 150  [o] C<br>TJ = 25  [o] C 1<br>40 TJ = 25 [ o] C<br>VDS = 5 V 0.1<br>20 TJ = -55  [o] C<br>0.01<br>PULSE DURATION = 80  μ s<br>DUTY CYCLE = 0.5% MAX<br>0<br>0.001<br>1 2 3 4 5 6 7<br>0.0 0.2 0.4 0.6 0.8 1.0 1.2<br>VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)<br>NORMALIZED<br>, DRAIN CURRENT (A)<br>ID<br>DRAIN TO SOURCE ON-RESISTANCE<br>) Ω<br>(m<br>DRAIN TO<br>NORMALIZED rDS(on),<br>SOURCE ON-RESISTANCE<br> DRAIN TO SOURCE ON-RESISTANCE<br>, DRAIN CURRENT (A)ID<br>, REVERSE DRAIN CURRENT (A)<br>IS<br>**----- End of picture text -----**<br>


**Figure 5.  Transfer Characteristics** 

**Figure 6. Forward Voltage vs Source Current** 

©2014 Fairchild Semiconductor Corporation FDMD82100L Rev.C1 

www.fairchildsemi.com 

**3** 

## **Typical Characteristics (N-Channel)** TJ = 25 °C unless otherwise noted 

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10 2000<br>ID = 7 A 1000<br>Ciss<br>8<br>VDD = 75 V C oss<br>6 100<br>VDD = 50 V<br>4 Crss<br>VDD = 25 V 10<br>2<br>f = 1 MHz<br>VGS = 0 V<br>0 1<br>0 3 6 9 12 15 18 0.1 1 10 100<br>Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>CAPACITANCE (pF)<br>, GATE TO SOURCE VOLTAGE (V)<br>GS<br>V<br>**----- End of picture text -----**<br>


**Figure 7.  Gate Charge Characteristics** 

**Figure 8.      Capacitance vs Drain to Source Voltage** 

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100<br>TJ = 25 [ o] C<br>10 TJ = 100  [o] C<br>T J  = 150  [o] C<br>1<br>0.001 0.01 0.1 1 10 100<br>tAV, TIME IN AVALANCHE (ms)<br>Figure 9. Unclamped Inductive<br>Switching Capability<br>300<br>THIS AREA<br>100 IS LIMITED<br>BY rDS(on) 10  μ s<br>10<br>100  μ s<br>SINGLE PULSE<br>1 TJ = MAX RATED<br>1 ms<br>R θ JC = 3.3 [ o] C/W 10 ms<br>T C = 25  [o] C DC<br>0.1<br>CURVE BENT TO<br>MEASURED DATA<br>0.01<br>0.1 1 10 100 300<br>VDS, DRAIN to SOURCE VOLTAGE (V)<br>, AVALANCHE CURRENT (A)<br>IAS<br>, DRAIN CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


**Figure 9. Unclamped Inductive Switching Capability** 

**Figure 11.  Forward Bias Safe Operating Area** 

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40<br>R θ JC = 3.3  [o] C/W<br>30<br>VGS = 10 V<br>20<br>Limited by Package<br>VGS = 4.5 V<br>10<br>0<br>25 50 75 100 125 150<br>TC, CASE TEMPERATURE (oC)<br>Figure 10. Maximum Continuous Drain                                 Maximum Continuous Drain<br>Current  vs Case Temperature<br>10000<br>1000<br>SINGLE PULSE<br>R θ JC = 3.3  [o] C/W<br>TC = 25  [o] C<br>100<br>10<br>10-5 10-4 10-3 10-2 10-1 1<br>t, PULSE WIDTH (sec)<br>DRAIN CURRENT (A)<br>,<br>ID<br>PEAK TRANSIENT POWER (W)<br>,<br>(PK)<br>P<br>**----- End of picture text -----**<br>


**Figure 10. Maximum Continuous Drain                                 Maximum Continuous Drain Current  vs Case Temperature** 

**Figure 12.  Single  Pulse Maximum Power  Dissipation** 

©2014 Fairchild Semiconductor Corporation FDMD82100L Rev.C1 

www.fairchildsemi.com 

**4** 

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Typical Characteristics (N-Channel)  TJ = 25 °C unless otherwise noted<br>2<br>1 DUTY CYCLE-DESCENDING ORDER<br>D = 0.5<br>      0.2<br>      0.1<br>0.1       0.05 PDM<br>0.02<br>      0.01<br>t1<br>t 2<br>0.01 SINGLE PULSE NOTES:<br>Z θ JC(t) = r(t) x R θ JC<br>R θ JC = 3.3  [o] C/W<br>Peak T J  = P DM  x Z θ JC (t) + T C<br>Duty Cycle, D = t 1  / t 2<br>0.001<br>10-5 10-4 10-3 10-2 10-1 1<br>t, RECTANGULAR PULSE DURATION (sec)<br>Figure 13.  Junction-to-Ambient Transient Thermal Response Curve<br>THERMAL RESISTANCE<br>r(t), NORMALIZED EFFECTIVE TRANSIENT<br>**----- End of picture text -----**<br>


©2014 Fairchild Semiconductor Corporation FDMD82100L Rev.C1 

www.fairchildsemi.com 

**5** 

## **Dimensional Outline and Pad Layout** 

_Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products._ 

_Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: https://www.fairchildsemi.com/package/packageDetails.html?id=PN_PQDE$-X12_ 

©2014 Fairchild Semiconductor Corporation FDMD82100L Rev.C1 

www.fairchildsemi.com 

**6** 

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AccuPower™AX-CAP[®] * F-PFS™FRFET[®] tm[®] ®* [c SYSTEMGENERAL BitSiC™ Global Power Resource[SM] PowerTrench[®] Build it Now™ GreenBridge™ PowerXS™ TinyBoost[®] CorePLUS™ Green FPS™ Programmable Active Droop™ TinyBuck[®] CorePOWER™ Green FPS™ e-Series™ QFET[®] TinyCalc™ _CROSSVOLT_ ™ G _max_ ™ QS™ TinyLogic[®] TINYOPTO™ CTL™ GTO™ Quiet Series™ Current Transfer Logic™ IntelliMAX™ RapidConfigure™ TinyPower™ DEUXPEED[®] ISOPLANAR™ ™ TinyPWM™ Dual Cool™ Marking Small Speakers Sound Louder TinyWire™TranSiC™ EcoSPARK[®] and Better™ Saving our world, 1mW/W/kW at a time™ TriFault Detect™ EfficentMax™ MegaBuck™ SignalWise™ TRUECURRENT[®] * ESBC™ MICROCOUPLER™ SmartMax™ ® MicroFET™ SMART START™ μSerDes™ MicroPak™ Solutions for Your Success™ Fairchild ~~F~~[®] MicroPak2™ SPM[®] "74... Fairchild Semiconductor[®] MillerDrive™ STEALTH™ UHC[®] FACT Quiet Series™ MotionMax™ SuperFET[®] Ultra FRFET™ FACT[®] mWSaver[®] SuperSOT™-3 UniFET™ FAST[®] OptoHiT™ SuperSOT™-6 VCX™ FastvCore™ OPTOLOGIC[®] SuperSOT™-8 VisualMax™ FETBench™ OPTOPLANAR[®] SupreMOS[®] VoltagePlus™ FPS™ SyncFET™ XS™ Sync-Lock™ 仙童 ™ 

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## **PRODUCT STATUS DEFINITIONS Definition of Terms** 

|**Definition of Terms**|||
|---|---|---|
|**Datasheet Identification**|**Product Status**|**Definition**|
|Advance Information|Formative / In Design|Datasheet contains the design specifications for product development. Specifications<br>may change in any manner without notice.|
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Rev. I68 

©2014 Fairchild Semiconductor Corporation FDMD82100L Rev.C1 

www.fairchildsemi.com 

**7** 

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