FDMC7208S

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## **FDMC7208S** 

## **Dual N-Channel PowerTrench[®] MOSFET** 

## **Q1: 30 V, 12 A, 9.0 m** Ω **Q2: 30 V, 16 A, 6.4 m** Ω 

## **General Description** 

## **Features** 

Q1: N-Channel 

This device includes two 30V N-Channel MOSFETs in a dual Power 33 (3 mm X 3 mm MLP) package. The package is enhanced for exceptional thermal performance. **Applications** 

- Max rDS(on) = 9.0 mΩ at VGS = 10 V, ID = 12 A 

- Max rDS(on) = 11.0 mΩ at VGS = 4.5 V, ID = 11 A 

Q2: N-Channel 

Computing 

Max rDS(on) = 6.4 mΩ at VGS = 10 V, ID = 16 A 

Communications 

:a Max rDS(on) = 7.5 mΩ at VGS = 4.5 V, ID = 13.5 A Communications : Termination is Lead-free and RoHS Compliant[a] General Purpose Point of Load 

General Purpose Point of Load Notebook System 

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Pin 1<br>G1 S1 S1 S1<br>- =<br>D1<br>D2<br>G2 S2 S2 S2<br>Power 33<br>**----- End of picture text -----**<br>


**MOSFET Maximum Ratings** TA = 25 °C unless otherwise noted 

|**Symbol**|**Parameter**|||**Q1**|**Q2**|**Q2**||**Units**|
|---|---|---|---|---|---|---|---|---|
|VDS|Drain to Source Voltage|||30||30||V|
|VGS|Gate to Source Voltage|e(Note 4)||±20|±12|||V|
||Drain Current     -Continuous(Package limited)T|TC = 25 °C||22||26|||
|ID|-Continuous                                                                    T|-Continuous                                                                    TA= 25 °C||121a|161b|||A|
||-Pulsed|||60||80|||
|EAS|Single Pulse Avalanche Energy|(Note 3)||21||21||mJ|
|PD|Power Dissipation for Single Operation                                                  T<br>Power Dissipation for Single Operation                                                  T|eration                                                  TA= 25 °C<br>eration                                                  TA= 25 °C||1.91a<br>0.81c|1.91b<br>0.81d|||W|
|TJ, TSTG|Operatingand Storage Junction Temperature Range|||-55 to +150|-55 to +150|||°C|
|**Thermal Characteristics**|||||||||
|RθJA<br>RθJA|Thermal Resistance, Junction to Ambient<br>Thermal Resistance, Junction to Ambient|Thermal Resistance, Junction to Ambient<br>Thermal Resistance, Junction to Ambient||651a<br>1551c|651b<br>1551d|||°C/W|
|**Package Marking and Ordering Information**|||||||||
|**Device Marking**<br>**Device**<br>**Package**||**Reel Size**||**Tape Width**||**Quantity**|||
|FDMC7208S<br>FDMC7208S<br>Power 33||13 ”||12 mm||3000 units||3000 units|



## **Thermal Characteristics** 

## **Package Marking and Ordering Information** 

©2012 Fairchild Semiconductor Corporation **1** www.fairchildsemi.com FDMC7208S  Rev.C3 

## **Electrical Characteristics** TJ = 25 °C unless otherwise noted 

|**Electrica**|**l Characteristics**TJ= 25 °C u|nless otherwise noted||||||||
|---|---|---|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test Conditions**|**Type**|**Min**||**Typ**|**Max**||**Units**|
|**Off Characteristics**||||||||||
|BVDSS|Drain to Source Breakdown Voltage|ID= 250μA, VGS= 0 V<br>ID= 1 mA, VGS= 0 V|Q1<br>Q2|30<br>30|||||V|
|ΔBVDSS<br>ΔTJ|Breakdown Voltage Temperature<br>Coefficient|ID= 250μA, referenced to 25 °C<br>ID= 10 mA, referenced to 25 °C|Q1<br>Q2|||27<br>21|||mV/°C|
|IDSS|Zero Gate Voltage Drain Current|VDS= 24 V, VGS= 0 V|Q1<br>Q2||||1<br>500||μA|
|IGSS|Gate to Source Leakage Current,<br>Forward|VGS= 20 V, VDS= 0 V<br>VGS= 12 V, VDS= 0 V|Q1<br>Q2||||100<br>100||nA|
|**On Characteristics**||||||||||
|VGS(th)|Gate to Source Threshold Voltage|ID= 250μA, VGS= 0 V<br>ID= 1 mA, VGS= 0 V|Q1<br>Q2|1.2<br>1.2||1.7<br>1.6|3.0<br>3.0||V|
|ΔVGS(th)<br>ΔTJ|Gate to Source Threshold Voltage<br>Temperature Coefficient|ID= 250μA, referenced to 25 °C<br>ID= 10 mA, referenced to 25 °C|Q1<br>Q2|||-5<br>-3|||mV/°C|
|rDS(on)|Drain to Source On Resistance|VGS= 10 V, ID= 12 A<br>VGS= 4.5 V, ID= 11 A<br>VGS= 10 V, ID= 12 A, TJ= 125 °C|Q1|||6.7<br>8.8<br>9.2|9.0<br>11.0<br>12.4||mΩ|
|||VGS= 10 V, ID= 16 A<br>VGS= 4.5 V, ID= 13.5 A<br>VGS= 10 V, ID= 16 A , TJ= 125 °C|Q2|||4.7<br>5.3<br>6.4|6.4<br>7.5<br>6.8|||
|gFS|Forward Transconductance|VDS= 5 V,  ID= 12 A<br>VDS= 5 V,  ID= 16 A|Q1<br>Q2|||53<br>80|||S|
|**Dynamic Characteristics**||||||||||
|Ciss|Input Capacitance|Q1:<br>VDS= 15 V, VGS= 0 V, f = 1 MHZ<br>Q2:<br>VDS= 15 V, VGS= 0 V, f = 1 MHZ|Q1<br>Q2|||848<br>1685|1130<br>2245||pF|
|Coss|Output Capacitance||Q1<br>Q2|||270<br>432|360<br>575||pF|
|Crss|Reverse Transfer Capacitance||Q1<br>Q2|||36<br>42|55<br>65||pF|
|Rg|Gate Resistance||Q1<br>Q2|0.1<br>0.1||1.1<br>1.0|2.5<br>2.5||Ω|
|**Switching Characteristics**||||||||||
|td(on)|Turn-On Delay Time|Q1:<br>VDD= 15 V, ID= 12 A,  RGEN= 6Ω<br>Q2:<br>VDD= 15 V, ID= 16 A,  RGEN= 6Ω|Q1<br>Q2|||6<br>7||12<br>14|ns|
|tr|Rise Time||Q1<br>Q2|||2<br>3||10<br>10|ns|
|td(off)|Turn-Off Delay Time||Q1<br>Q2|||16<br>23||29<br>36|ns|
|tf|Fall Time||Q1<br>Q2|||2<br>2||10<br>10|ns|
|Qg|Total Gate Charge|VGS= 0  V to 10 V|Q1<br>Q2|||13<br>26||18<br>36|nC|
|Qg|Total Gate Charge|VGS= 0  V to 5 V|Q1<br>Q2|||6.7<br>14||9.4<br>20|nC|
|Qgs|Gate to Source Gate Charge||Q1<br>Q2|||2.3<br>3.9|||nC|
|Qgd|Gate to Drain “Miller” Charge||Q1<br>Q2|||1.8<br>2.7|||nC|



©2012 Fairchild Semiconductor Corporation **2** www.fairchildsemi.com FDMC7208S  Rev.C3 

## **Electrical Characteristics** TJ = 25 °C unless otherwise noted 

|**Drain-Source Diode Characteristics**<br>**Symbol**<br>**Parameter**<br>**Test Conditions**<br>**Type**<br>**Min**<br>**Typ**<br>VSD<br>Source to Drain Diode Forward Voltage<br>VGS= 0 V, IS= 2 A             (Note 2)<br>VGS= 0 V, IS= 12 A           (Note 2)<br>VGS= 0 V, IS= 2 A             (Note 2)<br>VGS = 0 V, IS = 16 A(Note 2)<br>Q1<br>Q1<br>Q2<br>Q2<br>0.72<br>0.82<br>0.70<br>0.82<br>trr<br>Reverse Recovery Time<br>Q1<br>IF= 12 A, di/dt = 100 A/μs<br>Q2<br>IF= 16 A, di/dt = 300 A/μs<br>Q1<br>Q2<br>21<br>21<br>Qrr<br>Reverse Recovery Charge<br>Q1<br>Q2<br>6<br>16<br>Notes:<br>1.RθJAis determined with the device mounted on a 1 in2pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJCis guaranteed by design while R<br>the user's board design.<br>a. 65 °C/W when mounted on<br>a 1 in2pad of  2 oz  copper<br>b. 65 °C/W when mounted on<br>a 1 in2pad of  2 oz  copper<br>**G**<br>**DF**<br>**DS**<br>**SF**<br>**SS**<br>**G**<br>**DF**<br>**DS**<br>**SF**<br>**SS**<br>00000|**Drain-Source Diode Characteristics**<br>**Symbol**<br>**Parameter**<br>**Test Conditions**<br>**Type**<br>**Min**<br>**Typ**<br>VSD<br>Source to Drain Diode Forward Voltage<br>VGS= 0 V, IS= 2 A             (Note 2)<br>VGS= 0 V, IS= 12 A           (Note 2)<br>VGS= 0 V, IS= 2 A             (Note 2)<br>VGS = 0 V, IS = 16 A(Note 2)<br>Q1<br>Q1<br>Q2<br>Q2<br>0.72<br>0.82<br>0.70<br>0.82<br>trr<br>Reverse Recovery Time<br>Q1<br>IF= 12 A, di/dt = 100 A/μs<br>Q2<br>IF= 16 A, di/dt = 300 A/μs<br>Q1<br>Q2<br>21<br>21<br>Qrr<br>Reverse Recovery Charge<br>Q1<br>Q2<br>6<br>16<br>Notes:<br>1.RθJAis determined with the device mounted on a 1 in2pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJCis guaranteed by design while R<br>the user's board design.<br>a. 65 °C/W when mounted on<br>a 1 in2pad of  2 oz  copper<br>b. 65 °C/W when mounted on<br>a 1 in2pad of  2 oz  copper<br>**G**<br>**DF**<br>**DS**<br>**SF**<br>**SS**<br>**G**<br>**DF**<br>**DS**<br>**SF**<br>**SS**<br>00000|**Max**<br>**Units**<br>1.2<br>1.2<br>1.2<br>1.2<br>V<br>34<br>33<br>ns<br>12<br>28<br>nC<br>is guaranteed by design while RθCAis determined by|**Max**<br>**Units**<br>1.2<br>1.2<br>1.2<br>1.2<br>V<br>34<br>33<br>ns<br>12<br>28<br>nC<br>is guaranteed by design while RθCAis determined by|**Max**<br>**Units**<br>1.2<br>1.2<br>1.2<br>1.2<br>V<br>34<br>33<br>ns<br>12<br>28<br>nC<br>is guaranteed by design while RθCAis determined by|
|---|---|---|---|---|
|c. 155 °C/W when mounted on  a|d. 155 °C/W when mounted on  a||d. 155 °C/W when mounted on  a||
|minimum pad of 2 oz copper|minimum pad of 2 oz copper||minimum pad of 2 oz copper||
|**G**<br>**DF**<br>**DS**<br>**SF**<br>**SS**<br>**G**<br>**DF**<br>**DS**<br>**SF**<br>**SS**<br>00000<br>00000|||||



2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%. 

3. Q1: EAS of  21 mJ is based on starting TJ = 25[o] C, L = 0.3 mH, IAS = 12 A, VDD = 27 V, VGS = 10 V. 100% tested at L = 3 mH, IAS = 5.2 A. Q1: EAS of  21 mJ is based on starting TJ = 25[o] C, L = 0.3 mH, IAS = 12 A, VDD = 27 V, VGS = 10 V. 100% tested at L = 3 mH, IAS = 5.4 A. 

4. As an N-ch device, the negative Vgs rating is for low duty cycle pulse occurrence only. No continuous rating is implied 

©2012 Fairchild Semiconductor Corporation **3** www.fairchildsemi.com FDMC7208S  Rev.C3 

## **Typical Characteristics (Q1 N-Channel)** TJ = 25°C unless otherwise noted 

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60 5<br>50 V GS VGS =  = 4.10 V5 V VGS = 3 V PULSE DURATION = 80DUTY CYCLE = 0.5% MAX  μ s<br>4<br>40 VGS = 3.5 V VGS = 3.5 V<br>VGS =  4 V 3<br>30<br>2 VGS =  4 V<br>20 V GS  = 3 V<br>1<br>10<br>PULSE DURATION = 80  μ s VGS = 4.5 V VGS =  10 V<br>DUTY CYCLE = 0.5% MAX<br>0 0<br>0 1 2 3 4 5 0 10 20 30 40 50 60<br>VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 1.  On Region Characteristics Figure 2.  Normalized On-Resistance<br>vs Drain Current and Gate Voltage<br>1.6 40<br>ID = 12 A PULSE DURATION = 80  μ s<br>VGS = 10 V ID = 12 A DUTY CYCLE = 0.5% MAX<br>1.4<br>30<br>1.2<br>20<br>1.0<br>TJ = 125  [o] C<br>10<br>0.8<br>TJ = 25  [o] C<br>0.6 0<br>-75 -50 -25 0 25 50 75 100 125 150 2 3 4 5 6 7 8 9 10<br>TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 3.  Normalized  On  Resistance                                         Figure 4.   On-Resistance vs  Gate to<br>vs Junction Temperature Source Voltage<br>60 100<br>PULSE DURATION = 80  μ s VGS = 0 V<br>DUTY CYCLE = 0.5% MAX<br>50<br>10<br>VDS = 5 V<br>40 TJ = 150  [o] C<br>TJ = 150  [o] C 1<br>30<br>TJ = 25  [o] C 0.1 T J  = 25 [ o] C<br>20<br>TJ = -55  [o] C 0.01 T J  = -55  [o] C<br>10<br>0 0.001<br>1.0 1.5 2.0 2.5 3.0 3.5 4.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2<br>VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)<br>Figure 5.  Transfer Characteristics Figure 6.    Source to Drain  Diode<br>Forward Voltage vs Source Current<br>NORMALIZED<br>, DRAIN CURRENT (A)<br>ID<br>DRAIN TO SOURCE ON-RESISTANCE<br>) Ω<br>(m<br>DRAIN TO<br>NORMALIZED rDS(on),<br>SOURCE ON-RESISTANCE<br> DRAIN TO SOURCE ON-RESISTANCE<br>, DRAIN CURRENT (A)<br>ID<br>, REVERSE DRAIN CURRENT (A)<br>IS<br>**----- End of picture text -----**<br>


©2012 Fairchild Semiconductor Corporation **4** www.fairchildsemi.com FDMC7208S  Rev.C3 

## **Typical Characteristics (Q1 N-Channel)** TJ = 25°C unless otherwise noted 

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10 2000<br>ID = 12 A Ciss<br>1000<br>8<br>VDD = 15 V<br>6 C oss<br>VDD = 10 V<br>100<br>4<br>VDD = 20 V<br>Crss<br>2 f = 1 MHz<br>V GS  = 0 V<br>0 10<br>0 5 10 15 0.1 1 10 30<br>Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 7.  Gate Charge Characteristics Figure 8.  Capacitance vs Drain<br>to Source Voltage<br>40 100<br>10<br>10<br>TJ = 25 [ o] C 1 THIS AREA IS  1 ms<br>LIMITED BY rDS(on) 10 ms<br>TJ = 100  [o] C SINGLE PULSE 100 ms<br>T J  = 125  [o] C 0.1 TJ = MAX RATED 1 s<br>R θ JA = 155 [ o] C/W DERIVED FROM 10 s<br>TA = 25  [o] C TEST DATA DC<br>1 0.01<br>0.01 0.1 1 10 100 0.01 0.1 1 10 100<br>tAV, TIME IN AVALANCHE (ms) VDS, DRAIN to SOURCE VOLTAGE (V)<br>Figure 9. Unclamped Inductive                                  Figure 10.  Forward Bias Safe<br>Switching Capability Operating Area<br>100<br>SINGLE PULSE<br>R θ JA  = 155  [o] C/W<br>TA = 25  [o] C<br>10<br>1<br>0.5<br>10-3 10-2 10-1 100 101 100 1000<br>t, PULSE WIDTH (sec)<br>Figure 11.  Single Pulse Maximum Power Dissipation<br>CAPACITANCE (pF)<br>, GATE TO SOURCE VOLTAGE (V)<br>GS<br>V<br>, DRAIN CURRENT (A)<br>ID<br>, AVALANCHE CURRENT (A)<br>IAS<br>, PEAK TRANSIENT POWER (W)<br>(PK)<br>P<br>**----- End of picture text -----**<br>


©2012 Fairchild Semiconductor Corporation **5** www.fairchildsemi.com FDMC7208S  Rev.C3 

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Typical Characteristics (Q1 N-Channel)  TJ = 25°C unless otherwise noted<br>2<br>DUTY CYCLE-DESCENDING ORDER<br>1<br>D = 0.5<br>      0.2<br>      0.1<br>      0.05       0.02 P DM<br>0.1       0.01<br>t 1<br>t 2<br>SINGLE PULSE NOTES:<br>0.01 R (N θ ote JA = 155   1b) [o] C/W DUTY FACTOR: D = t PEAK TJ = PDM x Z θJC 1 x R /t 2 θJc  + TC<br>0.005<br>10-3 10-2 10-1 100 101 100 1000<br>t, RECTANGULAR PULSE DURATION (sec)<br>Figure 12.  Junction-to-Ambient Transient Thermal Response Curve<br>Z JA θ<br>IMPEDANCE,<br>NORMALIZED THERMAL<br>**----- End of picture text -----**<br>


©2012 Fairchild Semiconductor Corporation **6** www.fairchildsemi.com FDMC7208S  Rev.C3 

## **Typical Characteristics (Q2 N-Channel)** TJ = 25 °C unless otherwise noted 

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80<br>VGS =  10 V<br>VGS =  4.5 V<br>60<br>VGS =  4 V<br>VGS = 3.5 V VGS = 3 V<br>40<br>20<br>PULSE DURATION = 80  μ s<br>DUTY CYCLE = 0.5% MAX<br>0<br>0.0 0.5 1.0 1.5 2.0 2.5 3.0<br>VDS, DRAIN TO SOURCE VOLTAGE (V)<br>, DRAIN CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


**Figure 14. On- Region Characteristics** 

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5<br>VGS = 3 V<br>4<br>PULSE DURATION = 80  μ s<br>DUTY CYCLE = 0.5% MAX<br>3<br>VGS = 3.5 V<br>2<br>1<br>VGS =  4 V VGS = 4.5 V VGS =  10 V<br>0<br>0 20 40 60 80<br>ID, DRAIN CURRENT (A)<br>NORMALIZED<br>DRAIN TO SOURCE ON-RESISTANCE<br>**----- End of picture text -----**<br>


**Figure 15. Normalized on-Resistance vs Drain Current and Gate  Voltage** 

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1.5 30<br>ID = 16 A PULSE DURATION = 80  μ s<br>1.4 V GS  = 10 V DUTY CYCLE = 0.5% MAX<br>24<br>1.3 ID = 16 A<br>1.2 18<br>1.1<br>12<br>1.0<br>0.9 TJ = 125  [o] C<br>6<br>0.8<br>TJ = 25  [o] C<br>0.7 0<br>-75 -50 -25 0 25 50 75 100 125 150 2 4 6 8 10<br>TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 16. Normalized On-Resistance  Figure 17. On-Resistance vs Gate to<br> vs Junction Temperature Source Voltage<br>80 100<br>PULSE DURATION = 80  μ s VGS = 0 V<br>DUTY CYCLE = 0.5% MAX<br>64 10<br>VDS = 5 V TJ = 125  [o] C<br>48 1<br>TJ = 125  [o] C TJ = 25 [ o] C<br>32 0.1<br>TJ = 25  [o] C TJ = -55  [o] C<br>16 0.01<br>TJ = -55  [o] C<br>0 0.001<br>1 2 3 4 0.0 0.2 0.4 0.6 0.8 1.0 1.2<br>VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)<br>) Ω<br>(m<br>DRAIN TO<br>NORMALIZED rDS(on),<br>SOURCE ON-RESISTANCE<br> DRAIN TO SOURCE ON-RESISTANCE<br>, DRAIN CURRENT (A)<br>ID<br>, REVERSE DRAIN CURRENT (A)<br>IS<br>**----- End of picture text -----**<br>


**Figure 18. Transfer Characteristics** 

**Figure 19. Source to Drain Diode Forward Voltage vs Source Current** 

©2012 Fairchild Semiconductor Corporation **7** www.fairchildsemi.com FDMC7208S  Rev.C3 

## **Typical Characteristics (Q2 N-Channel)** TJ = 25°C unless otherwise noted 

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10 3000<br>ID = 16 A<br>8 1000 Ciss<br>VDD = 15 V<br>6 C oss<br>VDD = 10 V<br>4 VDD = 20 V 100<br>2 f = 1 MHz C rss<br>VGS = 0 V<br>0 10<br>0 6 12 18 24 30 0.1 1 10 30<br>Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 20. Gate Charge Characteristics Figure 21. Capacitance vs Drain<br>to Source Voltage<br>40 100<br>10<br>10<br>TJ = 25 [ o] C 1 ms<br>1 THIS AREA IS<br>LIMITED BY r 10 ms<br>T J  = 125  [o] C TJ = 100  [o] C SINGLE PULSEDS(on) 100 ms<br>0.1 TJ = MAX RATED 1 s<br>R θ JA = 155 [ o] C/W DERIVED FROM 10 s<br>TEST DATA<br>TA = 25  [o] C DC<br>1 0.01<br>0.001 0.01 0.1 1 10 100 0.01 0.1 1 10 100<br>tAV, TIME IN AVALANCHE (ms) VDS, DRAIN to SOURCE VOLTAGE (V)<br>Figure 22. Unclamped Inductive  Figure 23. Forward Bias Safe<br>Switching Capability Operating Area<br>100<br>SINGLE PULSE<br>R θ JA  = 155  [o] C/W<br>TA = 25  [o] C<br>10<br>1<br>0.5<br>10-3 10-2 10-1 100 101 100 1000<br>t, PULSE WIDTH (sec)<br>Figure 24. Single Pulse Maximum Power Dissipation<br>CAPACITANCE (pF)<br>, GATE TO SOURCE VOLTAGE (V)<br>GS<br>V<br>, DRAIN CURRENT (A)<br>ID<br>, AVALANCHE CURRENT (A)<br>IAS<br>, PEAK TRANSIENT POWER (W)<br>(PK)<br>P<br>**----- End of picture text -----**<br>


©2012 Fairchild Semiconductor Corporation **8** www.fairchildsemi.com FDMC7208S  Rev.C3 

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Typical Characteristics (Q2 N-Channel)  TJ = 25 °C unless otherwise noted<br>2<br>DUTY CYCLE-DESCENDING ORDER<br>1<br>D = 0.5<br>      0.2<br>      0.1<br>      0.05 P DM<br>      0.02<br>0.1       0.01<br>t1<br>t 2<br>SINGLE PULSE NOTES:<br>0.01 ( R Note 1b θ JA = 155  ) [o] C/W DUTY FACTOR: D = t PEAK TJ = PDM x Z θJC 1 x R /t 2 θJC  + TC<br>0.005<br>10-3 10-2 10-1 100 101 100 1000<br>t, RECTANGULAR PULSE DURATION (sec)<br>Z JA θ<br>IMPEDANCE,<br>NORMALIZED THERMAL<br>**----- End of picture text -----**<br>


**Figure 26. Junction-to-Ambient Transient Thermal Response Curve** 

©2012 Fairchild Semiconductor Corporation **9** www.fairchildsemi.com FDMC7208S  Rev.C3 

## **Typical Characteristics** (continued) 

## **SyncFET[TM] Schottky body diode Characteristics** 

Fairchild’s SyncFET[TM] process embeds a Schottky diode in parallel with PowerTrench MOSFET. This diode exhibits similar characteristics to a discrete external Schottky diode in parallel with a MOSFET. Figure 27 shows the reverses recovery characteristic of the FDMC7208S. 

Schottky barrier diodes exhibit significant leakage at high temperature and high reverse voltage. This will increase the power in the device. 

**==> picture [463 x 178] intentionally omitted <==**

**----- Start of picture text -----**<br>
20 10-2<br>TJ = 125 [o] C<br>15 10-3<br>10 10-4 TJ = 100  [o] C<br>5 10-5<br>0 10-6 TJ = 25  [o] C<br>-5 10-7<br>0 5 10 15 20 25 30<br>0 40 80 120 160 200<br>TIME (ns) VDS, REVERSE VOLTAGE (V)<br>CURRENT (A)<br>, REVERSE LEAKAGE CURRENT (A)<br>IDSS<br>**----- End of picture text -----**<br>


**Figure 27. FDMC7208S SyncFET[TM] body diode reverse recovery characteristic** 

**Figure 28. SyncFET[TM ] body diode reverses leakage  versus drain-source voltage** 

©2012 Fairchild Semiconductor Corporation **10** www.fairchildsemi.com FDMC7208S  Rev.C3 

## **Dimensional Outline and Pad Layout** 

©2012 Fairchild Semiconductor Corporation **11** www.fairchildsemi.com FDMC7208S  Rev.C3 

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## **PRODUCT STATUS DEFINITIONS Definition of Terms** 

|**Datasheet Identification**|**Product Status**|**Definition**|
|---|---|---|
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Rev. I64 

©2012 Fairchild Semiconductor Corporation **12** www.fairchildsemi.com FDMC7208S  Rev.C3 

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