FDMA1029PZ

## **ON Semiconductor** 

## **Is Now** 

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## **FDMA1029PZ** 

## **Dual P-Channel PowerTrench MOSFET** 

## **General Description** 

This device is designed specifically as a single package solution for the battery charge switch in cellular handset and other ultra-portable applications. It features two independent P-Channel MOSFETs with low on-state resistance for minimum conduction losses.  When connected in the typical common source configuration, bi-directional current flow is possible. 

The MicroFET 2x2 package offers exceptional thermal performance for its physical size and is well suited to linear mode applications. 

**PIN 1 S1   G1    D2 D1       D2** meg **D1   G2   S2 MicroFET 2x2** 

## **Features** 

–3.1 A, –20V. RDS(ON)  = 95 m @ VGS = –4.5V RDS(ON)  = 141 m @ VGS = –2.5V Low profile – 0.8 mm maximum – in the new package MicroFET 2x2 mm 

HBM ESD protection level > 2.5kV (Note 3) RoHS Compliant Free from halogenated compounds and antimony oxides 

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S1 1 6 D1<br>G1 2 5 G2<br>©<br>D2 3 4 S2<br>**----- End of picture text -----**<br>


**Absolute Maximum Ratings** TA=25[o] C unless otherwise noted 

> **Symbol** ~~es~~ **Parameter Ratings Units** 

> VDS ~~a~~ Drain-Source Voltage –20 V 

> VGS ~~a~~ Gate-Source Voltage 12 V Drain Current – Continuous (Note 1a) –3.1 A ID – Pulsed –6 ~~ee eee~~ PD Power Dissipation for Single Operation (Note 1a) 1.4 W 

> (Note 1b) 0.7 ~~ee eee~~ 

> TJ, TSTG ~~a~~ Operating and Storage Junction Temperature Range –55 to +150 C **Thermal Characteristics** R JA Thermal Resistance, Junction-to-Ambient (Note 1a) 86 (Single Operation) R JA Thermal Resistance, Junction-to-Ambient (Note 1b) 173 (Single Operation) C/W R JA Thermal Resistance, Junction-to-Ambient (Note 1c) 69 (Dual Operation) R JA Thermal Resistance, Junction-to-Ambient (Note 1d) 151 (Dual Operation) **Package Marking and Ordering Information Device Marking Device Reel Size Tape width Quantity** 029 FDMA1029PZ 7’’ 8mm 3000 units ~~>~~ 

FDMA1029PZ  Rev.B4(W) 

2009 Fairchild Semiconductor Corporation 

||**Electrical Characteristics**|**Electrical Characteristics**|**Electrical Characteristics**|TA= 25°C unless otherwise noted|TA= 25°C unless otherwise noted||||||**Units**<br>V<br>mV/�C<br>�A<br>�A<br>V<br>mV/�C<br>m�<br>S<br>pF<br>pF<br>pF<br>ns<br>ns<br>ns<br>ns<br>nC<br>nC<br>nC<br>A<br>V<br>ns<br>nC|
|---|---|---|---|---|---|---|---|---|---|---|---|
||**Symbol**|**Parameter**||**Test Conditions**||**Min**||**Typ**||**Max**||
||**OffCharacteristics**|||||||||||
||BVDSS|Drain–Source Breakdown Voltage||VGS= 0 V,<br>ID= –250�A||–20||||||
||�BVDSS<br>�TJ|Breakdown Voltage Temperature<br>Coefficient||ID= –250�A, Referenced to 25�C||||–12||||
||IDSS|Zero Gate Voltage Drain Current||VDS= –16 V,<br>VGS= 0 V||||||–1||
||IGSS|Gate–BodyLeakage||VGS= ± 12 V, VDS= 0 V||||||±10||
||**On Characteristics**<br>**(Note 2)**|||||||||||
||VGS(th)|Gate Threshold Voltage||VDS= VGS,<br>ID= –250�A||–0.6||–1.0||–1.5||
||�VGS(th)<br>�TJ|Gate Threshold Voltage<br>Temperature Coefficient||ID= –250�A, Referenced to 25�C||||4||||
||RDS(on)|Static Drain–Source<br>On–Resistance||VGS= –4.5 V,  ID= –3.1 A<br>VGS= –2.5 V,  ID= –2.5 A<br>VGS= –4.5 V, ID= –3.1 A, TJ=125�C||||60<br>88<br>87||95<br>141<br>140||
||gFS|Forward Transconductance||VDS= –10 V,<br>ID= –3.1 A||||–11||||
||**Dynamic Characteristics**|||||||||||
||Ciss|Input Capacitance||VDS= –10 V,<br>VGS= 0 V,<br>f = 1.0 MHz||||540||||
||Coss|Output Capacitance||||||120||||
||Crss|Reverse Transfer Capacitance||||||100||||
||**Switching Characteristics (Note 2)**|||||||||||
||td(on)|Turn–On DelayTime||VDD= –10 V,<br>ID= –1 A,<br>VGS= –4.5 V, RGEN= 6�||||13||24||
||tr|Turn–On Rise Time||||||11||20||
||td(off)|Turn–Off DelayTime||||||37||59||
||tf|Turn–Off Fall Time||||||36||58||
||Qg|Total Gate Charge||VDS= –10 V,<br>ID= –3.1 A,<br>VGS= –4.5 V||||7.0||10||
||Qgs|Gate–Source Charge||||||1.1||||
||Qgd|Gate–Drain Charge||||||2.4||||
||**Drain–Source Diode Characteristics and Maximum Ratings**|||||||||||
||IS|Maximum Continuous Source–Drain Diode Forward Current||||||||-1.1||
||VSD|Source–Drain Diode Forward<br>Voltage|VGS= 0 V,  IS= –1.1 A(Note 2)||||–0.8|||–1.2||
||trr|Diode Reverse Recovery Time|IF= –3.1 A,<br>dIF/dt = 100 A/µs||||25|||||
||Qrr|Diode Reverse Recovery Charge|||||9|||||
|||||||||||||



FDMA1029PZ  Rev.B4(W) 

## **Notes:** 

1.  R 8 JA is determined with the device mounted on a 1 in[2] oz. copper pad on a 1.5 x 1.5 in. board of FR-4 material. R JC is guaranteed by design while R JA is determined by the user's board design. 

- (a) R JA = 86 °C/W when mounted on a 1 in[2] pad of 2 oz copper, 1.5 " x 1.5 " x 0.062 " thick PCB. For single operation. 

6 (b) R 8 JA = 173 °C/W when mounted on a minimum pad of 2 oz copper. For single operation. (c) R 8 JA = 69[o] C/W when mounted on a 1 in[2] pad of 2 oz copper, 1.5 ” x 1.5 ” x 0.062 ” thick PCB. For dual operation. (d) R 8 JA  = 151[o] C/W when mounted on a minimum pad of 2 oz copper. For dual operation. 

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a)86 mounted on a 1incopper. [2] pad of 2 oz  [o] C/W when  b)173 mounted minimum pad of 2 oz copper. [o] C/W when on  a  c)69 pad of 2 oz copper.mounted on a 1 in [o] C/W when  [2] d)151  mounted on a minimum pad of 2 oz copper. [o] C/W when<br>**----- End of picture text -----**<br>


2. Pulse Test : Pulse Width < 300 us, Duty Cycle < 2.0% 

3. The diode connected between the gate and source serves only as protection against ESD. No gate overvoltage rating is implied. 

FDMA1029PZ  Rev.B4(W) 

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Typical Characteristics<br>6 2.6<br>V4 5VGS =  2.5V VGS = -2.0V<br>5<br>2.0V 2.2<br>3.5V 3.0V<br>4<br>1.8<br>3<br>1.4 -2.5V<br>2 -3.0V<br>-3.5V -4.0V<br>1 1 -4.5V<br>1.5V<br>0 0.6<br>0 0.4 0.8 1.2 1.6 2 0 1 2 3 4 5 6<br>-VDS, DRAIN-SOURCE VOLTAGE (V) -ID, DRAIN CURRENT (A)<br>Figure 1. On-Region Characteristics.  Figure 2. On-Resistance Variation with<br>Drain Current and Gate Voltage.<br>1.5 0.2<br>1.4 VIGSD = -3.1A = -4.5V ID = -1.55A<br>1.3 0.16<br>1.2<br>1.1 0.12<br>TA = 125 [o] C<br>1<br>0.9 0.08<br>TA = 25 [o] C<br>0.8<br>0.7 0.04<br>-50 -25 0 25 50 75 100 125 150 0 2 4 6 8 10<br>TJ, JUNCTION TEMPERATURE ( [o] C) -VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 3. On-Resistance Variation with  Figure 4. On-Resistance Variation with<br>Temperature.  Gate-to-Source Voltage.<br>6 100<br>VDS = -5V VGS = 0V<br>5 10<br>4 1<br>3 0.1 T A  = 125 [o] C<br>2 0.01 25 [o] C<br>TA = 125 [o] C -55 [o] C -55 [o] C<br>1 0.001<br>25 [o] C<br>0 0.0001<br>0 0.5 1 1.5 2 2.5 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6<br>-VGS, GATE TO SOURCE VOLTAGE (V) -VSD, BODY DIODE FORWARD VOLTAGE (V)<br>Figure 5. Transfer Characteristics.  Figure 6. Body Diode Forward Voltage Variation<br>with Source Current and Temperature.<br>, NORMALIZED<br>, DRAIN CURRENT (A)-ID RDS(ON)<br>DRAIN-SOURCE ON-RESISTANCE<br>, NORMALIZED<br>DS(ON) , ON-RESISTANCE (OHM)<br>R DS(ON)<br>R<br> DRAIN-SOURCE ON-RESISTANCE<br>, DRAIN CURRENT (A)-ID<br>, REVERSE DRAIN CURRENT (A)-IS<br>**----- End of picture text -----**<br>


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FDMA1029PZ  Rev.B4(W)<br>**----- End of picture text -----**<br>


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Typical Characteristics<br>10 1000<br>f = 1MHz<br>ID = -3.1A VGS = 0 V<br>8 800<br>VDS = -5V -15V<br>6 600<br>-10V Ciss<br>4 400<br>Coss<br>2 200<br>Crss<br>0 0<br>0 2 4 6 8 10 12 14 0 4 8 12 16 20<br>Qg, GATE CHARGE (nC) -VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 7. Gate Charge Characteristics.  Figure 8. Capacitance Characteristics.<br>100<br>50<br>SINGLE PULSE<br>10 RDS(ON) LIMIT 100us 40 R�JA T  = 173°C/W A = 25 ° C<br>1ms<br>10ms<br>100ms<br>1 1s 30<br>10s<br>DC<br>0.1 SINGLE PULSE VGS = -4.5V 20<br>R�JA = 173 [o] C/W<br>TA = 25 [o] C 10<br>0.01<br>0.1 1 10 100<br>-VDS, DRAIN-SOURCE VOLTAGE (V) 0<br>0.0001 0.001 0.01 0.1 1 10 100 1000<br>Figure 9. Maximum Safe Operating Area.  Figure 10. Single Pulse Maximum Power<br>Dissipation.<br>1<br>D = 0.5 R �JA (t) = r(t) * R �JA<br>R �JA  =173 °C/W<br>0.2<br>0.1 P(pk)<br>0.1<br>0.05 t1<br>0.02 t2<br>0.01 TJ - TA = P * R�JA(t)<br>SINGLE PULSE Duty Cycle, D = t1 / t2<br>0.01<br>0.0001 0.001 0.01 0.1 1 10 100 1000<br>t1, TIME (sec)<br>Figure 11. Transient Thermal Response Curve.<br>                          Thermal characterization performed using the conditions described in Note 1b.<br>                           Transient thermal response will change depending on the circuit board design.<br>CAPACITANCE (pF)<br>, GATE-SOURCE VOLTAGE (V)<br>GS<br>-V<br>, DRAIN CURRENT (A)-ID<br>P(pk), PEAK TRANSIENT POWER (W)<br>THERMAL RESISTANCE<br>r(t), NORMALIZED EFFECTIVE TRANSIENT<br>**----- End of picture text -----**<br>


FDMA1029PZ  Rev.B4(W) 

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## **Dimensional Outline and Pad Layout** 

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_Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/package/packageDetails.html?id=PN_MLDEB-X06_ 

FDMA1029PZ  Rev.B4(W) 

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## **PRODUCT STATUS DEFINITIONS Definition of Terms** 

|**Definition of Terms**|||
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|**Datasheet Identification**|**Product Status**|**Definition**|
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Rev. I68 

FDMA1029PZ  Rev.B4(W)