FDG8842CZ

## **Is Now Part of** 

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## **FDG8842CZ** 

## **Complementary PowerTrench[®] MOSFET** 

**==> picture [61 x 37] intentionally omitted <==**

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April 2007<br>tm<br>**----- End of picture text -----**<br>


**Q1:30V,0.75A,0.4** Ω **;  Q2:–25V,–0.41A,1.1** Ω 

## **Features** 

Q1: N-Channel 

i[|] Max rDS(on) = 0.4Ω at VGS = 4.5V, ID = 0.75A i[|] Max rDS(on) = 0.5Ω at VGS = 2.7V, ID = 0.67A 

Q2: P-Channel 

i[|] Max rDS(on) = 1.1Ω at VGS = –4.5V, ID = –0.41A i[|] Max rDS(on) = 1.5Ω at VGS = –2.7V, ID = –0.25A i | Very  low  level   gate  drive  requirements   allowing  direct operation in 3V circuits(VGS(th) <1.5V) Very small package outline SC70-6 RoHS Compliant 

## **General Description** 

These N & P-Channel logic level enhancement mode field effect transistors  are  produced  using Fairchild’s proprietary, high cell density, DMOS  technology. This  very high density process is especially   tailored   to  minimize  on-state  resistance.   This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs. Since bias resistors are not required, this dual digital FET can replace several different digital transistors, with different bias resistor values. 

|**S1**<br>**S2**<br>**G2**<br>**D1**<br>**D2**<br>**G1**<br>**Pin 1**<br>**SC70-6**<br>/|**S1**<br>**S2**<br>**G2**<br>**D1**<br>**D2**<br>**G1**<br>**Pin 1**<br>**SC70-6**<br>/||**S1**<br>**G1**<br>**D2**|**Q1**<br>**Q2**<br>Le|<br>aEx a7<br>3}|**Q1**<br>**Q2**<br>Le|<br>aEx a7<br>3}|**Q1**<br>**Q2**<br>Le|<br>aEx a7<br>3}|**Q1**<br>**Q2**<br>Le|<br>aEx a7<br>3}|**Q1**<br>**Q2**<br>Le|<br>aEx a7<br>3}|**D1**<br>**G2**<br>**S2**|**D1**<br>**G2**<br>**S2**||
|---|---|---|---|---|---|---|---|---|---|---|---|
|**MOSFET Maximum Ratings  **TA= 25°C unless otherwise noted|= 25°C unless otherwise noted|||||||||||
|**Symbol**|**Parameter**|||||**Q1**|||**Q2**||**Units**|
|VDS<br>Drain to Source Voltage||||||30|||–25||V|
|VGS<br>Gate to Source Voltage||||||±12|||–8||V|
|Drain Current          -Continuous|Drain Current          -Continuous|||||0.75|||–0.41|||
|ID<br>-Pulsed||||||2.2|||–1.2||A|
|PD<br>Power Dissipation for Single Operation                                               (Note 1a)<br>(Note 1b)||Power Dissipation for Single Operation                                               (Note 1a)<br>(Note 1b)|Power Dissipation for Single Operation                                               (Note 1a)<br>(Note 1b)|Power Dissipation for Single Operation                                               (Note 1a)<br>(Note 1b)|||0.36<br>0.30||||W|
|TJ, TSTG<br>Operatingand Storage Junction Temperature Ran|e Junction Temperature Range|||||–55 to +150|–55 to +150||||°C|
|**Thermal Characteristics**||||||||||||
|RθJA<br>Thermal Resistance, Junction to Ambient Sin|Thermal Resistance, Junction to Ambient Sin|Thermal Resistance, Junction to Ambient Single operation||le operation(Note 1a)|||350||||°C/W|
|RθJA<br>Thermal Resistance, Junction to Ambient Sin|Thermal Resistance, Junction to Ambient Sin|Thermal Resistance, Junction to Ambient Single operation||le operation(Note 1b)|||415|||||
|**Package Marking and Ordering Information**||||||||||||
|**Device Marking**<br>**Device**|||**Reel Size**||**Tape Width**|||||**Quantity**||
|.42<br>FDG8842CZ|||7”|||8mm||||3000 units||



**1** 

©2007 Fairchild Semiconductor Corporation FDG8842CZ Rev.B 

www.fairchildsemi.com 

## **Electrical Characteristics** TJ = 25°C unless otherwise noted 

|**Electrica**|**l Characteristics**TJ= 25°|C unless otherwise noted||||||
|---|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test Conditions**|**Type**|**Min**|**Typ**|**Max**|**Units**|
|**Off Characteristics**||||||||
|BVDSS|Drain to Source Breakdown<br>Voltage|ID= 250μA, VGS= 0V<br>ID= –250μA, VGS= 0V|Q1<br>Q2|30<br>–25|||V|
|ΔBVDSS<br>ΔTJ|Breakdown Voltage Temperature<br>Coefficient|ID= 250μA, referenced to 25°C<br>ID= –250μA, referenced to 25°C|Q1<br>Q2||25<br>–21||mV/°C|
|IDSS|Zero Gate Voltage Drain Current|VDS= 24V,   VGS= 0V<br>VDS= –20V,   VGS= 0V|Q1<br>Q2|||1<br>–1|μA|
|IGSS|Gate to Source Leakage Current|VGS= ±12V, VDS= 0V<br>VGS= –8V, VDS= 0V|Q1<br>Q2|||±10<br>–100|μA<br>nA|
|**On Characteristics**||||||||
|VGS(th)|Gate to Source Threshold Voltage|VGS= VDS,  ID= 250μA<br>VGS= VDS,  ID= –250μA|Q1<br>Q2|0.65<br>–0.65|1.0<br>–0.8|1.5<br>–1.5|V|
|ΔVGS(th)<br>ΔTJ|Gate to Source Threshold Voltage<br>Temperature Coefficient|ID= 250μA, referenced to 25°C<br>ID= –250μA, referenced to 25°C|Q1<br>Q2||–3.0<br>1.8||mV/°C|
|rDS(on)|Static Drain to Source On<br>Resistance|VGS= 4.5V,  ID= 0.75A<br>VGS= 2.7V,  ID= 0.67A<br>VGS= 4.5V,  ID= 0.75A ,TJ= 125°C|Q1||0.25<br>0.29<br>0.36|0.4<br>0.5<br>0.6|Ω|
|||VGS= –4.5V,  ID= –0.41A<br>VGS= –2.7V,  ID= –0.25A<br>VGS= –4.5V,  ID= –0.41A ,TJ= 125°C|Q2||0.87<br>1.20<br>1.22|1.1<br>1.5<br>1.9||
|gFS|Forward Transconductance|VDS= 5V,  ID= 0.75A<br>VDS= –5V,  ID= –0.41A|Q1<br>Q2||3<br>8||S|
|**Dynamic Characteristics**||||||||
|Ciss|Input Capacitance|Q1<br>VDS= 10V, VGS= 0V, f= 1MHZ<br>Q2<br>VDS= –10V, VGS= 0V, f= 1MHZ|Q1<br>Q2||90<br>70|120<br>100|pF|
|Coss|Output Capacitance||Q1<br>Q2||20<br>30|30<br>40|pF|
|Crss|Reverse Transfer Capacitance||Q1<br>Q2||15<br>15|25<br>25|pF|
|**Switching Characteristics**<br>**(note 2)**||||||||
|td(on)|Turn-On Delay Time|Q1<br>VDD= 5V, ID= 0.5A,<br>VGS= 4.5V,RGEN= 6Ω<br>Q2<br>VDD= –5V, ID= –0.5A,<br>VGS= –4.5V,RGEN= 6Ω|Q1<br>Q2||4<br>6|10<br>12|ns|
|tr|Rise Time||Q1<br>Q2||1<br>16|10<br>29|ns|
|td(off)|Turn-Off Delay Time||Q1<br>Q2||9<br>35|18<br>56|ns|
|tf|Fall Time||Q1<br>Q2||1<br>40|10<br>64|ns|
|Qg|Total Gate Charge|Q1<br>VGS=4.5V, VDD= 5V, ID= 0.75A<br>Q2<br>VGS= –4.5V, VDD= –5V, ID= –0.41A|Q1<br>Q2||1.03<br>1.20|1.44<br>1.68|nC|
|Qgs|Gate to Source Charge||Q1<br>Q2||0.29<br>0.31||nC|
|Qgd|Gate to Drain “Miller” Charge||Q1<br>Q2||0.17<br>0.22||nC|



www.fairchildsemi.com 

©2007 Fairchild Semiconductor Corporation FDG8842CZ Rev.B 

**2** 

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Electrical Characteristics  TJ = 25°C unless otherwise noted<br>aDDD Symbol Parameter Test Conditions Type Min Typ Max Units<br>Drain-Source Diode Characteristics and Maximum Ratings<br>Q1 0.3<br>IS Maximum Continuous Drain-Source Diode Forward Current Q2 –0.3 A<br>Q1 0.76 1.2<br>VSD Source to Drain Diode  Forward Voltage [V] V [GS ] GS  [= 0V, I] = 0V, IS  [S ][= 0.3A         (Note 2)] = –0.3A       (Note 2)  Q2 –0.84 –1.2 V<br>**----- End of picture text -----**<br>


## **Notes:** 

1. RθJA  is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. 

RθJC is guaranteed by design while RθJA is determined by the user's board design. 

   - a. 350°C/W when mounted  on  a 1 in[2 ] pad of  2 oz  copper . b. 415°C/W when mounted on  a minimum pad of 2 oz copper. 

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Scale 1:1 on letter size paper.<br>**----- End of picture text -----**<br>


2. Pulse Test: Pulse Width < 300μs, Duty cycle < 2.0%. 

www.fairchildsemi.com 

©2007 Fairchild Semiconductor Corporation FDG8842CZ Rev.B 

**3** 

## **Typical Characteristics (Q1 N-Channel)** TJ = 25°C unless otherwise noted 

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2.20 2.6<br>VGS = 4.5V VGS =  2.7V VGS = 2.0V VGS = 1.8V<br>1.76 2.2<br>VGS = 2.0V<br>1.32 1.8<br>VGS =1.8V<br>0.88 1.4 VGS =  3.5V<br>PULSE DURATION = 80 μ s VGS = 2.7V<br>DUTY CYCLE = 0.5%MAX<br>0.44 VGS = 1.5V 1.0<br>PULSE DURATION = 80 μ s VGS = 4.5V<br>DUTY CYCLE = 0.5%MAX<br>0.00 0.6<br>0.0 0.5 1.0 1.5 2.0 0.00 0.44 0.88 1.32 1.76 2.20<br>VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT(A)<br>Figure 1.  On-Region Characteristics Figure 2.  Normalized On-Resistance<br>vs Drain Current and Gate Voltage<br>1.6 0.8<br> ID = 0.75A ID =0.38A PULSE DURATION = 80DUTY CYCLE = 0.5%MAX μ s<br>1.4 VGS = 4.5V<br>0.6<br>1.2<br>1.0 TJ = 125 [o] C<br>0.4<br>0.8<br>TJ = 25 [o] C<br>0.6 0.2<br>-50 -25 0 25 50 75 100 125 150 1 2 3 4 5<br>TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 3.  Normalized  On - Resistance                                         Figure 4.   On-Resistance vs  Gate to<br>vs Junction Temperature Source Voltage<br>2.20 2<br>PULSE DURATION = 80 μ s 1 VGS = 0V<br>DUTY CYCLE = 0.5%MAX<br>1.76<br>VDD = 5V<br>1.32 0.1 TJ = 150 [o] C<br>0.88 TJ = 150 [o] C TJ = 25 [o] C<br>0.01<br>0.44 TJ = 25 [o] C<br>TJ = -55 [o] C<br>TJ = -55 [o] C<br>0.00 0.001<br>0.0 0.5 1.0 1.5 2.0 2.5 0.2 0.4 0.6 0.8 1.0 1.2<br>VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)<br>Figure 5.  Transfer Characteristics Figure 6.    Source to Drain  Diode<br>Forward Voltage vs Source Current<br>NORMALIZED<br>DRAIN CURRENT (A)<br>,<br>ID<br>DRAIN TO SOURCE ON-RESISTANCE<br>)<br>Ω<br>(<br>, DRAIN TO<br>NORMALIZED rDS(on)<br>SOURCE ON-RESISTANCE<br> DRAIN TO SOURCE ON-RESISTANCE<br>, DRAIN CURRENT (A)<br>ID , REVERSE DRAIN CURRENT (A)IS<br>**----- End of picture text -----**<br>


www.fairchildsemi.com 

©2007 Fairchild Semiconductor Corporation FDG8842CZ Rev.B 

**4** 

## **Typical Characteristics (Q1 N-Channel)** TJ = 25°C unless otherwise noted 

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5 200<br>ID = 0.22A Ciss<br>100<br>4<br>Coss<br>3 VDD = 5V VDD = 10V<br>2 VDD = 15V 10 Crss<br>1 f = 1MHz<br>VGS = 0V<br>0 1<br>0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0.1 1 10 30<br>Qg, GATE CHARGE(nC) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 7.  Gate Charge Characteristics Figure 8.  Capacitance vs Drain<br>to Source Voltage<br>4 50<br>SINGLE PULSE<br>R θ JA= 415OC/W<br>1 100 μ s TA = 25OC<br>10<br>1ms<br>10ms<br>0.1<br>1<br>SINGLE PULSE<br>TJ = MAX RATED 100ms<br>R θ JA = 415OC/W 1s<br>0.01 TA = 25OC DC<br>0.005 0.1<br>0.1 1 10 100 0.0001 0.001 0.01 0.1 1 10 100 1000<br>VDS, DRAIN to SOURCE VOLTAGE (V) t, PULSE WIDTH (s)<br>Figure 9.  Forward Bias Safe                                              Figure 10.  Single  Pulse Maximum Power<br>Operating Area  Dissipation<br>1<br>DUTY CYCLE-DESCENDING ORDER<br>D = 0.5<br>      0.2<br>      0.1 PDM<br>      0.05<br>      0.02<br>0.1       0.01 t1<br>t2<br>NOTES:<br>DUTY FACTOR: D = t1/t2<br>PEAK TJ = PDM x Z θJA  x R θJA  + TA<br>SINGLE PULSE R θ JA = 415 [o] C/W<br>0.01<br>0.0001 0.001 0.01 0.1 1 10 100 1000<br>t, RECTANGULAR PULSE DURATION (s)<br>LIMITED<br>rDS(on)<br>CAPACITANCE (pF)<br>, GATE TO SOURCE VOLTAGE(V)<br>GS<br>V<br>, DRAIN CURRENT (A)<br>ID<br>, PEAK TRANSIENT POWER (W)<br>(PK)<br>P<br>IMPEDANCE, ZJA θ<br>NORMALIZED THERMAL<br>**----- End of picture text -----**<br>


**Figure 11.    Transient Thermal Response Curve** 

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©2007 Fairchild Semiconductor Corporation FDG8842CZ Rev.B 

**5** 

## **Typical Characteristics (Q2 P-Channel)** TJ = 25°C unless otherwise noted 

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1.2 5<br>VGS = -4.5V VGS = -3.5V VGS = -2.7V VGS = -1.5V PULSE DURATION = 80DUTY CYCLE = 0.5%MAX μ s<br>4<br>0.9<br>VGS = -2.5V VGS = -2.0V VGS = -2.5V<br>3<br>0.6 VGS = -2.0V VGS = -2.7V<br>2<br>0.3 PULSE DURATION = 80 μ s VGS = -3.5V<br>DUTY CYCLE = 0.5%MAX 1<br>VGS = -4.5V<br>VGS = -1.5V<br>0.0 0<br>0 1 2 3 4 0.0 0.3 0.6 0.9 1.2<br>-VDS, DRAIN TO SOURCE VOLTAGE (V) -ID, DRAIN CURRENT(A)<br>Figure 13. On Region Characteristics Figure 14. Normalized on-Resistance vs Drain<br>Current and Gate  Voltage<br>1.6 4<br> ID = -0.41A ID =-0.22A PULSE DURATION = 80 μ s<br>1.4 VGS = -4.5V DUTY CYCLE = 0.5%MAX<br>3<br>1.2<br>2<br>1.0 TJ = 125 [o] C<br>1<br>0.8<br>TJ = 25 [o] C<br>0.6 0<br>-50 -25 0 25 50 75 100 125 150 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0<br>TJ, JUNCTION TEMPERATURE ( [o] C) -VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 15. Normalized On Resistance  Figure 16. On-Resistance vs Gate to<br>vs Junction Temperature Source Voltage<br>0.6 3<br>PULSE DURATION = 80 μ s VGS = 0V<br>DUTY CYCLE = 0.5%MAX 1<br>VDS = -5V TJ = -55 [o] C<br>0.4 TJ = 150 [o] C<br>0.1 TJ = 150 [o] C<br>TJ = 25 [o] C<br>TJ = 25 [o] C<br>0.2<br>0.01<br>TJ = -55 [o] C<br>0.0 0.001<br>0.5 1.0 1.5 2.0 2.5 0.2 0.4 0.6 0.8 1.0 1.2<br>-VGS, GATE TO SOURCE VOLTAGE (V) -VSD, BODY DIODE FORWARD VOLTAGE (V)<br>NORMALIZED<br>, DRAIN CURRENT (A)<br>D<br>-I<br>DRAIN TO SOURCE ON-RESISTANCE<br>)<br>Ω<br>(<br>, DRAIN TO<br>NORMALIZED<br>rDS(on)<br>SOURCE ON-RESISTANCE<br> DRAIN TO SOURCE ON-RESISTANCE<br>, DRAIN CURRENT (A)<br>D<br>-I<br>, REVERSE DRAIN CURRENT (A)<br>S<br>-I<br>**----- End of picture text -----**<br>


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Figure 17. Transfer Characteristics<br>**----- End of picture text -----**<br>


**Figure 18. Source to Drain Diode Forward Voltage vs Source Current** 

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©2007 Fairchild Semiconductor Corporation FDG8842CZ Rev.B 

**6** 

## **Typical Characteristics(Q2 P-Channel)** TJ = 25°C unless otherwise noted 

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**----- Start of picture text -----**<br>
5 200<br>ID = -0.41A<br>100 Ciss<br>4<br>3 VDD = -5V VDD = -10V Coss<br>2 VDD = -15V 10<br>Crss<br>1 f = 1MHz<br>VGS = 0V<br>0 1<br>0.0 0.4 0.8 1.2 1.6 0.1 1 10 25<br>Qg, GATE CHARGE(nC) -VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 19. Gate Charge Characteristics Figure 20. Capacitance vs Drain<br>to Source Voltage<br>3 20<br>SINGLE PULSE<br>10 R θ JA= 415OC/W<br>1 1ms TA = 25OC<br>10ms<br>1<br>0.1 SINGLE PULSE<br>TJ = MAX RATED 100ms<br>R θ JA = 415 [o] C/W<br>TA = 25 [o] C 1s<br>DC<br>0.01 0.1<br>0.3 1 10 50 0.001 0.01 0.1 1 10 100 1000<br>-VDS, DRAIN to SOURCE VOLTAGE (V) t, PULSE WIDTH (s)<br>Figure 21. Forward Bias Safe                                             Figure 22. Single Pulse Maximum Power<br>Operating Area  Dissipation<br>1<br>DUTY CYCLE-DESCENDING ORDER<br>D = 0.5<br>      0.2<br>      0.1<br>      0.05 PDM<br>      0.02<br>      0.01<br>0.1 t1<br>t2<br>NOTES:<br>DUTY FACTOR: D = t1/t2<br>PEAK TJ = PDM x Z θJA  x R θJA  + TA<br>SINGLE PULSE R θ JA = 415oC/W<br>0.01<br>10-3 10-2 10-1 100 101 102 103<br>t, RECTANGULAR PULSE DURATION (s)<br>LIMITED<br>rDS(on)<br>CAPACITANCE (pF)<br>, GATE TO SOURCE VOLTAGE(V)<br>GS<br>-V<br>, DRAIN CURRENT (A)<br>D<br>-I<br>, PEAK TRANSIENT POWER (W)<br>(PK)<br>P<br>IMPEDANCE, ZJA θ<br>NORMALIZED THERMAL<br>**----- End of picture text -----**<br>


**Figure 23. Transient Thermal Response Curve** 

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©2007 Fairchild Semiconductor Corporation FDG8842CZ Rev.B 

**7** 

tm 

## **TRADEMARKS** 

|The following are registered and unregistered trademarks Fairchild<br>intended to be an exhaustive list of all such trademarks.<br>ACEx®<br>Across the board. Around the world™<br>ActiveArray™<br>Bottomless™<br>Build it Now™<br>CoolFET™<br>_CROSSVOLT_™<br>CTL™<br>Current Transfer Logic™<br>DOME™<br>E2CMOS™<br>EcoSPARK®<br>EnSigna™<br>FACT Quiet Series™<br>FACT®<br>FAST®<br>FASTr™<br>FPS™<br>FRFET®<br>GlobalOptoisolator**™**<br>GTO**™**<br>_i-Lo_™<br>ImpliedDisconnect™<br>IntelliMAX™<br>ISOPLANAR™<br>MICROCOUPLER™<br>MicroPak™<br>MICROWIRE™<br>Motion-SPM™<br>MSX™<br>MSXPro™<br>OCX™<br>OCXPro™<br>OPTOLOGIC®<br>OPTOPLANAR®<br>PACMAN™<br>PDP-SPM™<br>POP™<br>Power220®<br>Power247®<br>PowerEdge™<br>PowerSaver™|Semiconductor owns or is authorized<br>Power-SPM™<br>PowerTrench®<br>Programmable Active Droop™<br>QFET®<br>QS™<br>QT Optoelectronics™<br>Quiet Series™<br>RapidConfigure™<br>RapidConnect™<br>ScalarPump™<br>SMART START™<br>SPM®<br>STEALTH™<br>SuperFET™<br>SuperSOT™-3<br>SuperSOT™-6<br>SuperSOT™-8<br>SyncFET™<br>TCM™<br>The Power Franchise®<br> ™|to use and is not<br>TinyBoost™<br>TinyBuck™<br>TinyLogic®<br>TINYOPTO™<br>TinyPower™<br>TinyWire™<br>TruTranslation™<br>µSerDes™<br>UHC®<br>UniFET™<br>VCX™<br>Wire™|
|---|---|---|
|HiSeC**™**|tm||



## **DISCLAIMER** 

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. 

## **LIFE SUPPORT POLICY** 

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. 

As used herein: 

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 

2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 

## **PRODUCT STATUS DEFINITIONS Definition of Terms** 

|<br>**Definition of Terms**|||
|---|---|---|
|**Datasheet Identification**|**Product  Status**|**Definition**|
|Advance Information|Formative or In Design|This datasheet contains the design specifications for product<br>development. Specifications may change in any manner<br>without notice.|
|Preliminary|First Production|This datasheet contains preliminary data; supplementary data will<br>be published at a later date. Fairchild Semiconductor reserves the<br>right to make changes at any time without notice to improve<br>design.|
|No Identification Needed|Full Production|This datasheet contains final specifications. Fairchild<br>Semiconductor reserves the right to make changes at any time<br>without notice to improve design.|
|Obsolete|Not In Production|This datasheet contains specifications on a product that has been<br>discontinued by Fairchild Semiconductor.The datasheet is printed<br>for reference information only.|



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