FDG6332C

## **Is Now Part of** 

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## **FDG6332C** 

## **20V N & P-Channel PowerTrench[] MOSFETs** 

## **General Description** 

The N & P-Channel MOSFETs are produced using Fairchild Semiconductor’s advanced PowerTrench process that has been especially tailored to minimize on-state resistance and yet maintain superior switching performance. 

These devices have been designed to offer exceptional power dissipation in a very small footprint for applications where the bigger more expensive TSSOP-8 and SSOP-6 packages are impractical. 

## **Applications** 

- DC/DC converter 

- Load switch 

## **Features** 

   - **Q1** 0.7 A, 20V. RDS(ON) = 300 mΩ @ VGS = 4.5 V RDS(ON) = 400 mΩ @ VGS = 2.5 V 

   - **Q2** –0.6 A, –20V. RDS(ON) = 420 mΩ @ VGS = –4.5 V RDS(ON) = 630 mΩ @ VGS = –2.5 V 

   - Low gate charge 

   - High performance trench technology for extremely low RDS(ON) 

   - SC70-6 package: small footprint (51% smaller than SSOT-6); low profile (1mm thick) 

- LCD display inverter 

**==> picture [301 x 95] intentionally omitted <==**

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S<br>G<br>1 6<br>D<br>2 5<br>D<br>G<br>Pin 1 S 3 4<br>SC70-6<br>Complementary<br>**----- End of picture text -----**<br>


**Absolute Maximum Ratings** TA=25[o] C unless otherwise noted 

|**Symbol**|**Parameter**|||**Q1**||**Q2**||**Units**|
|---|---|---|---|---|---|---|---|---|
|VDSS|Drain-Source Voltage|||20||–20||V|
|VGSS|Gate-Source Voltage|||±12||±12||V|
|ID|Drain Current<br>– Continuous||(Note 1)|0.7||–0.6||A|
||– Pulsed|||2.1||–2|||
|PD|Power Dissipation for Single Operation||(Note 1)|0.3||||W|
|TJ, TSTG|Operatingand Storage Junction Temperature Range|||–55 to +150||||°C|
|**Thermal Characteristics**|||||||||
|RθJA|Thermal Resistance, Junction-to-Ambient||(Note 1)|415||||°C/W|
|**Package Marking and Ordering Information**|||||||||
|**Device Marking**<br>**Device**||**Reel Size**||**Tape width**|||**Quantity**||
|.32<br>FDG6332C|||7’’|8mm|8mm||3000 units||



FDG6332C  Rev C2 (W) 

2003 Fairchild Semiconductor Corporation 

|||**Electrical Characteristics**|**Electrical Characteristics**|**Electrical Characteristics**|TA= 25°C unless otherwise noted|TA= 25°C unless otherwise noted||||**Units**<br>V<br>mV/°C<br>µA<br>nA<br>nA<br>V<br>mV/°C<br>mΩ<br>S<br>A<br>pF<br>pF<br>pF<br>ns<br>ns<br>ns<br>ns<br>nC<br>nC<br>nC|
|---|---|---|---|---|---|---|---|---|---|---|
|||**Symbol**|**Parameter**||**Test Conditions**||**Min**|**Typ**|**Max**||
|||**Off Characteristics**|||||||||
|||BVDSS|Drain–Source Breakdown Voltage||VGS= 0 V,<br>ID= 250µA<br>VGS=0V,<br>ID= –250 µA|**Q1**<br>**Q2**|20<br>–20||||
|||∆BVDSS<br>∆TJ|Breakdown Voltage Temperature<br>Coefficient||ID= 250µA,Ref. to 25°C<br>ID= –250 µA,Ref.to25°C|**Q1**<br>**Q2**||14<br>–14|||
|||IDSS|Zero Gate Voltage Drain Current||VDS=   16 V,<br>VGS= 0 V<br>VDS= –16 V,<br>VGS= 0 V|**Q1**<br>**Q2**|||1<br>–1||
|||IGSSF/IGSSR|Gate–BodyLeakage,Forward||VGS=±12 V, VDS=0V||||±100||
|||IGSSF/IGSSR|Gate–BodyLeakage,Reverse||VGS=±12V, VDS=0V||||±100||
|||**On Characteristics**<br>**(Note 2)**|||||||||
|||VGS(th)|Gate Threshold Voltage|**Q1**|VDS= VGS, ID= 250µA||0.6|1.1|1.5||
|||||**Q2**|VDS= VGS, ID= –250µA||-0.6|–1.2|–1.5||
|||∆VGS(th)<br>∆TJ|Gate Threshold Voltage<br>Temperature Coefficient|**Q1**<br>**Q2**|ID= 250µA,Ref. To 25°C<br>ID= –250µA,Ref. to 25°C|||–2.8<br>3|||
|||RDS(on)|Static Drain–Source<br>On–Resistance|**Q1**|VGS= 4.5 V, ID=0.7 A<br>VGS= 2.5 V, ID=0.6 A<br>VGS= 4.5 V, ID=0.7A,TJ=125°C|||180<br>293<br>247|300<br>400<br>442||
|||||**Q2**|VGS= –4.5 V, ID= –0.6 A<br>VGS= –2.5 V, ID= –0.5 A<br>VGS=–4.5 V, ID=–0.6 A,TJ=125°C|||300<br>470<br>400|420<br>630<br>700||
|||gFS|Forward Transconductance|**Q1**|VDS= 5 V<br>ID= 0.7 A|||2.8|||
|||||**Q2**|VDS= –5 V<br>ID=  –0.6A|||1.8|||
|||ID(on)|On–State Drain Current|**Q1**|VGS= 4.5 V, VDS= 5 V||1||||
|||||**Q2**|VGS= –4.5 V, VDS= –5 V||–2||||
|||**Dynamic Characteristics**|||||||||
|||Ciss|Input Capacitance|**Q1**|VDS=10 V,VGS= 0 V,f=1.0MHz|||113|||
|||||**Q2**|VDS=–10 V, VGS= 0 V, f=1.0MHz|||114|||
|||Coss|Output Capacitance|**Q1**|VDS=10 V, VGS= 0 V, f=1.0MHz|||34|||
|||||**Q2**|VDS=–10 V, VGS= 0 V, f=1.0MHz|||24|||
|||Crss|Reverse Transfer Capacitance|**Q1**|VDS=10 V, VGS= 0 V, f=1.0MHz|||16|||
|||||**Q2**|VDS=–10 V, VGS= 0 V, f=1.0MHz|||9|||
|||**Switching Characteristics**<br>**(Note 2)**|||||||||
|||td(on)|Turn–On Delay Time|**Q1**|For**Q1**:<br>VDS=10 V,<br>ID= 1 A<br>VGS= 4.5 V,<br>RGEN= 6Ω<br>For**Q2**:<br>VDS=–10 V,<br>ID= –1 A<br>VGS= –4.5 V, RGEN= 6Ω|||5|10||
|||||**Q2**||||5.5|11||
|||tr|Turn–On Rise Time|**Q1**||||7|15||
|||||**Q2**||||14|25||
|||td(off)|Turn–Off Delay Time|**Q1**||||9|18||
|||||**Q2**||||6|12||
|||tf|Turn–Off Fall Time|**Q1**||||1.5|3||
|||||**Q2**||||1.7|3.4||
|||Qg|Total Gate Charge|**Q1**|For**Q1**:<br>VDS=10 V,<br>ID= 0.7 A<br>VGS= 4.5 V,<br>RGEN= 6Ω<br>For**Q2**:<br>VDS=–10 V,    ID= –0.6 A<br>VGS= –4.5 V,  RGEN= 6Ω|||1.1|1.5||
|||||**Q2**||||1.4|2||
|||Qgs|Gate–Source Charge|**Q1**||||0.24|||
|||||**Q2**||||0.3|||
|||Qgd|Gate–Drain Charge|**Q1**||||0.3|||
|||||**Q2**||||0.4|||
||||||||||||



FDG6332C Rev C2  (W) 

|**Electrical Characteristics**<br>TA= 25°C unless otherwise noted|**Electrical Characteristics**<br>TA= 25°C unless otherwise noted|**Electrical Characteristics**<br>TA= 25°C unless otherwise noted|**Electrical Characteristics**<br>TA= 25°C unless otherwise noted|**Electrical Characteristics**<br>TA= 25°C unless otherwise noted|||||
|---|---|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**||**Test Conditions**||**Min**|**Typ**|**Max**|**Units**|
|**Drain–Source Diode Characteristics and Maximum Ratings**|||||||||
|IS|Maximum Continuous Drain–Source Diode Forward Current|||**Q1**|||0.25|A|
|||||**Q2**|||–0.25||
|VSD|Drain–Source Diode Forward<br>Voltage|**Q1**|VGS= 0 V, IS= 0.25 A<br>(Note 2)|||0.74|1.2|V|
|||**Q2**|VGS= 0 V, IS= –0.25 A<br>(Note 2)|||–0.77|–1.2||



## **Notes:** 

**1.** RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.  RθJC is guaranteed by design while RθJA is determined by the user's board design.  RθJA  = 415°C/W when mounted on a minimum pad of FR-4 PCB in a still air environment. 

**2.** Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0% 

FDG6332C Rev C2  (W) 

## **Typical Characteristics: N-Channel** 

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4 1.8<br>VGS=4.5V 3.0V<br>3.5V 1.6<br>3 2.5V<br>VGS = 2.5V<br>1.4<br>2<br>3.0V<br>1.2<br>3.5V<br>2.0V 4.0V<br>1 4.5V<br>1<br>0 0.8<br>0 1 2 3 4 0 1 2 3 4<br>VDS, DRAIN-SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)<br>Figure 1. On-Region Characteristics. Figure 2. On-Resistance Variation with<br>Drain Current and Gate Voltage.<br>1.6 0.8<br>ID =0.7A<br>VGS = 4.5V ID =0.4A<br>1.4<br>0.6<br>1.2 TA = 125 [o] C<br>0.4<br>1 TA = 25 [o] C<br>0.2<br>0.8<br>0.6 0<br>-50 -25 0 25 50 75 100 125 150 1 2 3 4 5<br>TJ, JUNCTION TEMPERATURE ( [o] C) VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 3. On-Resistance Variation with Figure 4. On-Resistance Variation with<br>Temperature. Gate-to-Source Voltage.<br>2.5 10<br>VDS = 5V TA = -55 [o] C 25 [o] C VGS = 0V<br>2 1<br>125 [o] C TA = 125 [o] C<br>1.5 0.1 25 [o] C<br>-55 [o] C<br>1 0.01<br>0.5 0.001<br>0 0.0001<br>0.5 1 1.5 2 2.5 3 0 0.2 0.4 0.6 0.8 1 1.2<br>VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)<br>Figure 5. Transfer Characteristics. Figure 6. Body Diode Forward Voltage Variation<br>with Source Current and Temperature.<br>, NORMALIZED<br>, DRAIN CURRENT (A)ID RDS(ON)<br>DRAIN-SOURCE ON-RESISTANCE<br>, NORMALIZED<br>DS(ON) , ON-RESISTANCE (OHM)<br>R DS(ON)<br>R<br> DRAIN-SOURCE ON-RESISTANCE<br>, DRAIN CURRENT (A)ID<br>, REVERSE DRAIN CURRENT (A)IS<br>**----- End of picture text -----**<br>


FDG6332C Rev C2  (W) 

## **Typical Characteristics: N-Channel** 

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5 200<br>ID = 0.7A VDS = 5V 10V Vf = 1MHzGS = 0 V<br>4<br>15V 150<br>CISS<br>3<br>100<br>2<br>COSS<br>50<br>1<br>CRSS<br>0 0<br>0 0.4 0.8 1.2 1.6 0 5 10 15 20<br>Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)<br>CAPACITANCE (pF)<br>, GATE-SOURCE VOLTAGE (V)<br>GS<br>V<br>**----- End of picture text -----**<br>


**Figure 7. Gate Charge Characteristics.** 

**Figure 8. Capacitance Characteristics.** 

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10 10<br>SINGLE PULSE<br>R DS(ON)  LIMIT 1ms100µs 8 RθJA T  = 415°C/WA  = 25°C<br>1<br>10ms<br>6<br>100ms<br>1s<br>VGS = 4.5V DC 4<br>0.1 SINGLE PULSE<br>RθJA = 415 [o] C/W<br>TA = 25 [o] C 2<br>0.01 0<br>0.1 1 10 100 0.001 0.01 0.1 1 10 100<br>VDS, DRAIN-SOURCE VOLTAGE (V) t1, TIME (sec)<br>, DRAIN CURRENT (A)ID<br>P(pk), PEAK TRANSIENT POWER (W)<br>**----- End of picture text -----**<br>


**Figure 9. Maximum Safe Operating Area.** 

**Figure 10. Single Pulse Maximum Power Dissipation.** 

FDG6332C Rev C2  (W) 

## **Typical Characteristics: P-Channel** 

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2 1.8<br>VGS = -4.5V -3.0V<br>-3.5V VGS = -2.5V<br>1.6 -2.5V 1.6<br>1.2 1.4<br>-3.0V<br>0.8 1.2 -3.5V<br>-2.0V -4.0V<br>-4.5V<br>0.4 1<br>0 0.8<br>0 1 2 3 4 0 0.5 1 1.5 2<br>-VDS, DRAIN-SOURCE VOLTAGE (V) -ID, DRAIN CURRENT (A)<br>Figure 11. On-Region Characteristics. Figure 12. On-Resistance Variation with<br>Drain Current and Gate Voltage.<br>1.4 1.2<br>1.3 VIGSD = -0.6A = -4.5V 1 ID = -0.3 A<br>1.2<br>1.1 0.8<br>TA = 125 [o] C<br>1<br>0.6<br>0.9 TA = 25 [o] C<br>0.4<br>0.8<br>0.7 0.2<br>-50 -25 0 25 50 75 100 125 150 1 2 3 4 5<br>TJ, JUNCTION TEMPERATURE ( [o] C) -VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 13. On-Resistance Variation with Figure 14. On-Resistance Variation with<br>Temperature. Gate-to-Source Voltage.<br>2 10<br>VDS = -5V TA = -55 [o] C 25 [o] C VGS = 0V<br>125 [o] C 1<br>1.5<br>T A  = 125 [o] C<br>0.1<br>1 25 [o] C<br>0.01<br>-55 [o] C<br>0.5<br>0.001<br>0 0.0001<br>0.5 1 1.5 2 2.5 3 0 0.2 0.4 0.6 0.8 1 1.2<br>-VGS, GATE TO SOURCE VOLTAGE (V) -VSD, BODY DIODE FORWARD VOLTAGE (V)<br>Figure 15. Transfer Characteristics. Figure 16. Body Diode Forward Voltage Variation<br>with Source Current and Temperature.<br>, NORMALIZED<br>, DRAIN CURRENT (A)-ID RDS(ON)<br>DRAIN-SOURCE ON-RESISTANCE<br>, NORMALIZED<br>DS(ON) , ON-RESISTANCE (OHM)<br>R DS(ON)<br>R<br> DRAIN-SOURCE ON-RESISTANCE<br>, DRAIN CURRENT (A)-ID<br>, REVERSE DRAIN CURRENT (A)-IS<br>**----- End of picture text -----**<br>


FDG6332C Rev C2  (W) 

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Typical Characteristics: P-Channel<br>5 160<br>ID = -0.6A VDS = -5V -10V f = 1MHz<br>VGS = 0 V<br>4<br>120<br>-15V<br>CISS<br>3<br>80<br>2<br>COSS<br>40<br>1<br>CRSS<br>0 0<br>0 0.3 0.6 0.9 1.2 1.5 1.8 0 5 10 15 20<br>Qg, GATE CHARGE (nC) -VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 17. Gate Charge Characteristics. Figure 18. Capacitance Characteristics.<br>10 10<br>SINGLE PULSE<br>R DS(ON)  LIMIT 100µs 8 RθJAT = 415A = 25 o oCC/W<br>1ms<br>1<br>10ms 6<br>100ms<br>1s 4<br>0.1 V GS  = -4.5V DC<br>SINGLE PULSE<br>RθJA = 415 [o] C/W 2<br>T A  = 25 [o] C<br>0.01<br>0<br>0.1 1 10 100<br>0.001 0.01 0.1 1 10 100<br>-VDS, DRAIN-SOURCE VOLTAGE (V)<br>SINGLE PULSE TIME (SEC)<br>Figure 19. Maximum Safe Operating Area. Figure 20. Single Pulse Maximum<br>Power Dissipation.<br>1<br>D = 0.5 R θ JA(t) = r(t) * R θ JA<br>0.2 R θJA  = 415 °C/W<br>0.1<br>0.1 0.05 P(pk)<br>0.02 t1<br>0.01 t2<br>0.01 TJ - TA = P * RθJA(t)<br>SINGLE PULSE Duty Cycle, D = t1 / t2<br>0.001<br>0.0001 0.001 0.01 0.1 1 10 100<br>t1, TIME (sec)<br>Figure 21. Transient Thermal Response Curve.<br>Thermal characterization performed using the conditions described in Note 1.<br>Transient thermal response will change depending on the circuit board design.<br>FDG6332C<br>CAPACITANCE (pF)<br>, GATE-SOURCE VOLTAGE (V)<br>GS<br>-V<br>POWER (W)<br>, DRAIN CURRENT (A)-ID<br>THERMAL RESISTANCE<br>r(t), NORMALIZED EFFECTIVE TRANSIENT<br>**----- End of picture text -----**<br>


## **Typical Characteristics: P-Channel** 

FDG6332C Rev C2  (W) 

## ~~—~~ 

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Rev. I76 

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