FDG6318PZ

## **Is Now Part of** 

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January 2003<br>**----- End of picture text -----**<br>


## **FDG6318PZ** 

## **Dual P-Channel, Digital FET General  Description** 

## **Features** 

- These dual P-Channel logic level enhancement mode • -0.5A, -20V.        rDS(ON) = 780mΩ (Max)@ VGS = -4.5 V MOSFET are produced using Fairchild Semiconductor’s rDS(ON) = 1200mΩ  (Max) @ VGS = -2.5 V especially tailored to minimize on-state resistance. This device has been designed especially for bipolar digital • Very low level gate drive requirements allowing direct transistors and small signal MOSFETS operation in 3V circuits (VGS(TH) < 1.5V). 

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Applications • Gate-Source Zener for ESD ruggedness (>1.4kV Human<br>• Battery management Body Model).<br>• Compact industry standard SC-70-6 surface mount<br>package.<br>S<br>G<br>S 1 or 4 6 or 3 D<br>D<br>G 2 or 5 5 or 2 G<br>D<br>G<br>Pin 1 S D 3 or 6 4 or 1 S<br>- aE<br>SC70-6<br>The pinouts are symmetrical; pin1 and pin 4 are interchangeable.<br>MOSFET Maximum Ratings TA=25°C unless otherwise noted<br>Symbol Parameter Ratings Units<br>VDSS Drain to Source Voltage -20 V<br>VGS Gate to Source Voltage ±12 V<br>Drain Current<br>ID Continuous (TContinuous (TCC = 25 = 100 [o] C, V [o] C, VGSGS = - 4.5V)  = - 2.5V)  -0.5-0.3 AA<br>Pulsed Figure 4<br>PD Power dissipation 0.3 W<br>Derate above 25°C 2.4 mW/ [o] C<br>TJ, TSTG Operating and Storage Temperature -55 to 150 oC<br>Electrostatic Discharge Rating MIL-STD-883D<br>ESD 1.4 kV<br>Human Body Model ( 100pF / 1500Ω )<br>Thermal Characteristics<br>RθJA Thermal Resistance Junction to Ambient  (Note 1) 415 oC/W<br>Package Marking and Ordering Information<br>Device Marking Device Package Reel Size Tape Width Quantity<br>.68 FDG6318PZ SC70-6 7” 8 mm 3000<br>**----- End of picture text -----**<br>


©2003 Fairchild Semiconductor Corporation 

FDG6318PZ Rev. B 

|**Electrical Characteristics**TA= 25°C unless otherwise noted|**Electrical Characteristics**TA= 25°C unless otherwise noted|**Electrical Characteristics**TA= 25°C unless otherwise noted|**Electrical Characteristics**TA= 25°C unless otherwise noted|||||
|---|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test Conditions**||**Min**|**Typ**|**Max**|**Units**|
|**Off Characteristics**||||||||
|BVDSS|Drain to Source Breakdown Voltage|ID= -250µA, VGS= 0V||-20|-|-|V|
|IDSS|Zero Gate Voltage Drain Current|VGS =−16V ,    VGS =  0V||<br>-|-|-3|µA|
|IGSS|Gate to Source Leakage Current|VGS=±12V , VGS= 0V||-|-|±10|µA|
|**On Characteristics**||||||||
|VGS(TH)|Gate to Source Threshold Voltage|VGS= VDS, ID= -250µA||-0.65|-0.9|-1.5|V|
|rDS(ON)|Drain to Source On Resistance|ID = -0.5A, VGS= -4.5V||-|580|780|mΩ|
|||ID = -0.4A, VGS= -2.5V||-|910|1200||
|**Dynamic Characteristics**||||||||
|CISS|Input Capacitance|VDS= -10V, VGS= 0V,<br>f = 1MHz||-|85.4|-|pF|
|COSS|Output Capacitance|||-|24.9|-|pF|
|CRSS|Reverse Transfer Capacitance|||-|8.83|-|pF|
|Qg(TOT)|Total Gate Charge at -4.5V|VGS= 0V to -4.5V|VDD= -10V<br>ID= -0.5A<br>Ig= 1.0mA|-|1.08|1.62|nC|
|Qg(-2.5)|Total Gate Charge at -2.5V|VGS= 0V to  -2.5V||-|0.67|1.0|nC|
|Qgs|Gate to Source Gate Charge|||-|0.21|-|nC|
|Qgd|Gate to Drain “Miller” Charge|||-|0.33|-|nC|
|**Switching Characteristics**(VGS= -4.5V)||||||||
|tON|Turn-On Time|VDD= -10V, ID= -0.5A<br>VGS= -4.5V, RGS= 120Ω||-|-|35|ns|
|td(ON)|Turn-On DelayTime|||-|10|-|ns|
|tr|Rise Time|||-|13|-|ns|
|td(OFF)|Turn-Off DelayTime|||-|40|-|ns|
|tf|Fall Time|||-|24|-|ns|
|tOFF|Turn-Off Time|||-|-|96|ns|
|**Drain-Source Diode Characteristics**||||||||
|VSD|Source to Drain Diode Voltage|ISD= -0.5A||-|-0.9|-1.2|V|
|trr|Reverse RecoveryTime|ISD= -0.5A, dISD/dt = 100A/µs||-|-|22|ns|
|QRR|Reverse Recovered Charge|ISD= -0.5A, dISD/dt = 100A/µs||-|-|16|nC|
|**Notes:**<br>**1.**RθJA is the sum of the junction-to-case and case-to-ambient therm<br> the center drain pad.  RθJCis guaranteed by design while RθCAis||al resistance where the case thermal referen<br>determined by user’s board design. RθJA= 4||ce is defined as the solder mounting surface of<br>15oC/W when mounted on a 1inch2copper pad.||||



©2003 Fairchild Semiconductor Corporation 

FDG6318PZ Rev. B 

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Typical Characteristic  TA = 25°C unless otherwise noted<br>1.2 0.6<br>1.0<br>VGS = -4.5V<br>0.8 0.4<br>0.6<br>VGS = -2.5V<br>0.4 0.2<br>0.2<br>0 0<br>0 25 50 75 100 125 150 25 50 75 100 125 150<br>TA , AMBIENT TEMPERATURE ( [o] C) TA, CASE TEMPERATURE ( [o] C)<br>Figure 1.  Normalized Power Dissipation vs  Figure 2.  Maximum Continuous Drain Current vs<br>Ambient Temperature Case Temperature<br>2<br>1 DUTY CYCLE - DESCENDING ORDER<br>0.5<br>0.2<br>0.1<br>0.05<br>0.02<br>0.01<br>0.1 PDM<br>t 1<br>t 2<br>NOTES:<br>DUTY FACTOR: D = t1/t2<br>PEAK TJ = PDM x Z θ JA x R θ JA + TA<br>0.01<br>10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1] 10 [2] 10 [3]<br>t, RECTANGULAR PULSE DURATION (s)<br>Figure 3.  Normalized Maximum Transient Thermal Impedance<br>20<br>10 TRANSCONDUCTANCE TA = 25 [o] C<br>MAY LIMIT CURRENT FOR TEMPERATURES<br>IN THIS REGION ABOVE 25 [o] C DERATE PEAK<br>CURRENT AS FOLLOWS:<br>I = I25 150 - TA<br>125<br>1<br>V GS  = -4.5V<br>V GS  = -2.5V<br>0.4<br>10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 10 [0] 10 [1] 10 [2] 10 [3]<br>t, PULSE WIDTH (s)<br>Figure 4.  Peak Current Capability<br>, DRAIN CURRENT (A)<br>D<br>-I<br>POWER DISSIPATION MULTIPLIER<br>, NORMALIZED<br>ZJA θ<br>THERMAL IMPEDANCE<br>, PEAK CURRENT (A)<br>DM<br>-I<br>**----- End of picture text -----**<br>


©2003 Fairchild Semiconductor Corporation 

FDG6318PZ Rev. B 

## **Typical Characteristic** (Continued) TA = 25°C unless otherwise noted 

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10 3<br>PULSE DURATION = 80 µ s<br>DUTY CYCLE = 0.5% MAX<br>V DD = -10V<br>100 µ s<br>2  TJ = 150 [o] C<br>1  TJ = 25 [o] C<br>1ms<br>OPERATION IN THIS<br>AREA MAY BE 1  TJ = -55 [o] C<br>LIMITED BY rDS(ON) 10ms<br>SINGLE PULSE<br>0.1 TJ = MAX RATED<br>TA = 25 [o] C<br>0.05 0<br>1 10 30 0 1 2 3 4<br>VDS, DRAIN TO SOURCE VOLTAGE (V) -VGS , GATE TO SOURCE VOLTAGE (V)<br>Figure 5. Forward Bias Safe Operating Area Figure 6.  Transfer Characteristics<br>3 1.0<br>DUTY CYCLE = 0.5% MAXPULSE DURATION = 80 µ s VGS = -4.5V 0.9 ID = -0.5A PULSE DURATION = 80DUTY CYCLE = 0.5% MAX µ s<br> TA = 25 [o] C<br>2<br>0.8<br>VGS = -2.5V 0.7 I D  = -0.1A<br>1<br>VGS = -2V 0.6<br>0 0.5<br>0 0.5 1.0 1.5 2.0 2.5 3.0 2 3 4 5 6<br>-VDS, DRAIN TO SOURCE VOLTAGE (V) -VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 7.  Saturation Characteristics Figure 8.  Drain to Source On Resistance vs Gate<br>Voltage and Drain Current<br>1.50 1.2<br>PULSE DURATION = 80 µ s VGS = VDS, ID = 250 µ A<br>DUTY CYCLE = 0.5% MAX<br>1.25 1.0<br>1.00 0.8<br>VGS = -4.5V, ID = -0.5A<br>0.75 0.6<br>-80 -40 0 40 80 120 160 -80 -40 0 40 80 120 160<br>TJ, JUNCTION TEMPERATURE ( [o] C) TJ, JUNCTION TEMPERATURE ( [o] C)<br>Figure 9.  Normalized Drain to Source On  Figure 10.  Normalized Gate Threshold Voltage vs<br>Resistance vs Junction Temperature Junction Temperature<br>, DRAIN CURRENT (A) , DRAIN CURRENT (A)<br>-ID -ID<br>) Ω<br>, DRAIN TO SOURCE<br>, DRAIN CURRENT (A)D ON RESISTANCE (<br>-I rDS(ON)<br>ON RESISTANCE<br>NORMALIZED GATE THRESHOLD VOLTAGE<br>NORMALIZED DRAIN TO SOURCE<br>**----- End of picture text -----**<br>


©2003 Fairchild Semiconductor Corporation 

FDG6318PZ Rev. B 

## **Typical Characteristic** (Continued) TA = 25°C unless otherwise noted 

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1.10 200<br>ID = 250 µ A CISS = CGS + CGD<br>100<br>1.05 COSS ≅  CDS + CGD<br>CRSS = CGD<br>1.00<br>10<br>VGS = 0V, f = 1MHz<br>0.95 5<br>-80 -40 0 40 80 120 160 0.1 1 10 20<br>TJ, JUNCTION TEMPERATURE ( [o] C) -VDS , DRAIN TO SOURCE VOLTAGE (V)<br>Figure 11.  Normalized Drain to Source  Figure 12.  Capacitance vs Drain to Source<br>Breakdown Voltage vs Junction Temperature Voltage<br>10<br>VDD = -10V<br>8<br>6<br>4<br>WAVEFORMS IN<br>2 DESCENDING ORDER:<br>ID = -0.5A<br>ID = -0.1A<br>0<br>0 0.5 1.0 1.5 2.0<br>Qg, GATE CHARGE (nC)<br>BREAKDOWN VOLTAGE C, CAPACITANCE (pF)<br>NORMALIZED DRAIN TO SOURCE<br>, GATE TO SOURCE VOLTAGE (V)<br>GS<br>-V<br>**----- End of picture text -----**<br>


**Figure 13.  Gate Charge Waveforms for Constant Gate Currents** 

©2003 Fairchild Semiconductor Corporation 

FDG6318PZ Rev. B 

## _**PSPICE Electrical Model**_ 

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.SUBCKT FDG6318PZ  2 1 3 ; rev January 2003<br>CA  12  8 0.6e-10<br>CB  15  14 1.1e-10 ESG LDRAIN<br>CIN  6  8  0.75e-10 8 + 5 DRAIN<br>10 2<br>DBODY 5 7 DBODYMOD 6<br>DBREAK 7 11  DBREAKMOD RLDRAIN<br>DPLCAP 10 6 DPLCAPMOD RSLC1<br>EBREAK 5 11 17  18 -23.3EDS  14  8  5  8 1 RSLC2 515 +51ESLC EBREAK 1718+<br>EGS  13  8  6  8 1<br>50<br>ESG 5 10 8 6 1<br>EVTHRES 6 21 19 8  1 DPLCAP RDRAIN DBODY<br>EVTEMP 6 20 18 22 1 16 11<br>EVTHRES<br>IT  8  17  1 LGATE EVTEMP + 198 21 MWEAK<br>LDRAIN 2 5 1e-9LGATE 1  9 0.47e-9 GATE1 RGATE9 20 1822 + 6 MMED DBREAK<br>LSOURCE  3  7 0.47e-9 RLGATE MSTRO<br>LSOURCE<br>MMED 16 6 8 8 MMEDMOD CIN 8 RSOURCE SOURCE<br>MSTRO 16 6 8 8 MSTROMOD 7 3<br>MWEAK 16 21 8 8 MWEAKMOD RLSOURCE<br>RBREAK  17  18  RBREAKMOD  1 S1A S2A<br>RDRAIN 50 16 RDRAINMOD 280e-3 12 13 14 15 17 RBREAK 18<br>RGATE  9  20 12.4 8 13<br>RLDRAIN 2 5 10 S1B S2B RVTEMP<br>RLGATE 1 9 4.7 13<br>CB<br>RLSOURCE 3 7 4.7 CA 14 IT 19<br>RSLC1 5 51 RSLCMOD 1e-6 + +<br>RSLC2 5 50 1e3RSOURCE  8  7  RSOURCEMOD 190e-3 EGS 68 EDS 58 + VBAT<br>RVTHRES 22 8 RVTHRESMOD  1 8<br>RVTEMP 18 19 RVTEMPMOD 1 22<br>RVTHRES<br>**----- End of picture text -----**<br>


S1A  6  12  13  8  S1AMOD S1B  13  12  13  8  S1BMOD S2A  6  15  14  13  S2AMOD S2B  13  15  14  13  S2BMOD 

VBAT 22 19  DC  1 

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*20),2.5))} 

.MODEL DBODYMOD D (IS = 7.7e-11 N=1.277 RS = 1e-3 TRS1 = 2.8e-1 TRS2 = 3e-4  XTI=0  IKF=0.5 CJO = 3.9e-11 TT=33e-9   M = 0.50) 

.MODEL DBREAKMOD D (RS = 5.3e-1 TRS1 = 5.5e-3 TRS2 = -9e-5) .MODEL DPLCAPMOD D (CJO = 0.5e-10 IS = 1e-30 N = 10 M = 0.55) 

.MODEL MMEDMOD PMOS (VTO = -1.17  KP = 0.6  IS=1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 12.4) .MODEL MSTROMOD PMOS (VTO = -1.45  KP = 1.5  IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) 

.MODEL MWEAKMOD PMOS (VTO = -0.99  KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 124 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 5.5e-4 TC2 = -1e-7) .MODEL RDRAINMOD RES (TC1 = 2.8e-3 TC2 = 4.9e-6) .MODEL RSLCMOD RES (TC1 = 3.7e-3 TC2 = 7.8e-6) .MODEL RSOURCEMOD RES (TC1 = 3e-3 TC2 = 5.2e-6) .MODEL RVTHRESMOD RES (TC1 = 9e-4 TC2 = 3e-7) .MODEL RVTEMPMOD RES (TC1 = -5.5e-4 TC2 = -1e-9) 

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.5 VOFF= 0.2) .MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.2 VOFF= 0.5) .MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.4 VOFF= -0.1) .MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.1 VOFF= 0.4) 

.ENDS 

Note: For further discussion of the PSPICE model, consult **A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options** ; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley. 

©2003 Fairchild Semiconductor Corporation 

FDG6318PZ Rev. B 

## _**SABER Electrical Model**_ 

REV January 2003 template fdg6318pz n2,n1,n3 electrical n2,n1,n3 { var i iscl 

dp..model dbodymod =  (isl = 7.7e-11, nl=1.277, rs = 1e-3, trs1 = 2.8e-1, trs2 = 3e-4, xti=0, cjo = 3.9e-11, ikf=0.5, tt = 33e-9, m = 0.50) dp..model dbreakmod = (rs = 5.3e-1, trs1 = 5.5e-3, trs2 = -9.0e-5) 

dp..model dplcapmod =  (cjo = 0.5e-10, isl=10e-30, nl=10, m=0.55) 

m..model mmedmod = (type=_p, vto = -1.17, kp=0.6, is=1e-30, tox=1) m..model mstrongmod = (type=_p, vto = -1.45, kp = 1.5, is = 1e-30, tox = 1) m..model mweakmod = (type=_p, vto = -0.99, kp = 0.05, is = 1e-30, tox = 1, rs=0.1) sw_vcsp..model s1amod =  (ron = 1e-5, roff = 0.1, von = 0.5, voff = 0.2) sw_vcsp..model s1bmod =  (ron = 1e-5, roff = 0.1, von = 0.2, voff = 0.5) sw_vcsp..model s2amod =  (ron = 1e-5, roff = 0.1, von = 0.4, voff = -0.1) sw_vcsp..model s2bmod =  (ron = 1e-5, roff = 0.1, von = -0.1, voff = 0.4) 

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ESG LDRAIN<br>c.ca n12 n8 = 0.6e-10c.cb n15 n14 = 1.1e-10 10 68 + 5 DRAIN2<br>c.cin n6 n8 = 0.75e-10 RLDRAIN<br>RSLC1<br>dp.dbody n5 n7 = model=dbodymod RSLC2 51 +<br>dp.dbreak n7 n11 = model=dbreakmoddp.dplcap n10 n6 = model=dplcapmod 50ISCL EBREAK 1718<br>DPLCAP RDRAIN DBODY<br>i.it n8 n17 = 1 16<br>EVTHRES 11<br>l.ldrain n2 n5 = 1e-9 LGATE EVTEMP + 198 21 MWEAK<br>l.lgate n1 n9 = 0.47e-9l.lsource n3 n7 = 0.47e-9 GATE1 RGATE9 20 1822 + 6 MMED DBREAK<br>RLGATE MSTRO<br>m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u LSOURCE<br>m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u CIN 8 RSOURCE SOURCE3<br>m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u 7<br>RLSOURCE<br>res.rbreak n17 n18  = 1, tc1 = 5.5e-4, tc2 = -1e-7 S1A S2A<br>res.rdrain n50 n16  = 280e-3, tc1 = 2.8e-3, tc2 = 4.9e-6res.rgate n9 n20 = 12.4 12 138 1413 15 17 RBREAK 18<br>res.rldrain n2 n5 = 10 S1B 13 S2B RVTEMP<br>res.rlgate n1 n9 = 4.7res.rlsource n3 n7 = 4.7 CA + CB+ 14 IT 19<br>res.rslc1 n5 n51= 1e-6, tc1 = 3.7e-3, tc2 =7.8e-6res.rslc2 n5 n50 = 1e3 EGS 68 EDS 5 8 + VBAT<br>8<br>res.rsource n8 n7  = 190e-3, tc1 = 3e-3, tc2 =5.2e-6 22<br>res.rvtemp n18 n19  = 1, tc1 = -5.5e-4, tc2 = -1e-9 RVTHRES<br>res.rvthres n22 n8  = 1, tc1 = 9e-4, tc2 = 3e-7<br>**----- End of picture text -----**<br>


spe.ebreak n5 n11 n17 n18 = -23.3 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n5 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod 

v.vbat n22 n19 = dc=1 

equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/20))** 2.5)) } } 

©2003 Fairchild Semiconductor Corporation 

FDG6318PZ Rev. B 

_**SPICE Thermal Model**_ REV January 2003 **th JUNCTION** FDG6318PZ_JA Junction Ambient Copper Area= 1sq.in CTHERM1 Junction c2 0.17e-4 CTHERM2 c2 c3 2.7e-4 **RTHERM1 CTHERM1** CTHERM3 c3 c4 5.5e-4 CTHERM4 c4 c5 1.4e-3 CTHERM5 c5 c6 2.2e-3 **8** CTHERM6 c6 c7 2.6e-3 CTHERM7 c7 c8 6.6e-3 CTHERM8 c8 Ambient 0.29 **RTHERM2 CTHERM2** RTHERM1 Junction c2 11.2 RTHERM2 c2 c3 11.5 **7** RTHERM3 c3 c4 12.5 RTHERM4 c4 c5 27 **RTHERM3 CTHERM3** RTHERM5 c5 c6 81 RTHERM6 c6 c7 88 RTHERM7 c7 c8 92 **6** RTHERM8 c8 Ambient 93 **RTHERM4 CTHERM4** _**SABER Thermal Model**_ **5** SABER thermal model FDG6318PZ Copper Area= 1sq.in **RTHERM5 CTHERM5** template thermal_model th tl thermal_c th, tl { **4** ctherm.ctherm1 th c2 = 0.17e-4 ctherm.ctherm2 c2 c3 = 2.7e-4 ctherm.ctherm3 c3 c4 = 5.5e-4 **RTHERM6 CTHERM6** ctherm.ctherm4 c4 c5 = 1.4e-3 ctherm.ctherm5 c5 c6 = 2.2e-3 **3** ctherm.ctherm6 c6 c7 = 2.6e-3 ctherm.ctherm7 c7 c8 = 6.6e-3 ctherm.ctherm8 c8 tl = 0.29 **RTHERM7 CTHERM7** rtherm.rtherm1 th c2 = 11.2 rtherm.rtherm2 c2 c3 = 11.5 **2** rtherm.rtherm3 c3 c4 = 12.5 rtherm.rtherm4 c4 c5 = 27 rtherm.rtherm5 c5 c6 = 81 **RTHERM8 CTHERM8** rtherm.rtherm6 c6 c7 = 88 rtherm.rtherm7 c7 c8 = 92 rtherm.rtherm8 c8 tl = 93 } **tl AMBIENT** 

©2003 Fairchild Semiconductor Corporation 

FDG6318PZ Rev.B 

## **TRADEMARKS** 

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. 

|ACEx™|FACT™|ImpliedDisconnect™|PACMAN™|SPM™|
|---|---|---|---|---|
|ActiveArray™|FACT Quiet Series™|ISOPLANAR™|POP™|Stealth™|
|Bottomless™|FAST®|LittleFET™|Power247™|SuperSOT™-3|
|CoolFET™|FASTr™|MicroFET™|PowerTrench®|SuperSOT™-6|
|CROSSVOLT™|FRFET™|MicroPak™|QFET™|SuperSOT™-8|
|DOME™|GlobalOptoisolator™|MICROWIRE™|QS™|SyncFET™|
|EcoSPARK™|GTO™|MSX™|QT Optoelectronics™|TinyLogic®|
|E2CMOS™|HiSeC™|MSXPro™|Quiet Series™|TruTranslation™|
|EnSigna™|I2C™|OCX™|RapidConfigure™|UHC™|
|Across the board.|Around the world.™|OCXPro™|RapidConnect™|UltraFET®|
|The Power Franchise™||OPTOLOGIC®|SILENT SWITCHER®|VCX™|
|Programmable Active Droop™||OPTOPLANAR™|SMART START™||



## **DISCLAIMER** 

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 

## **LIFE SUPPORT POLICY** 

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. 

## As used herein: 

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 

2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 

## **PRODUCT STATUS DEFINITIONS Definition of Terms** 

|**Definition of Terms**|||
|---|---|---|
|**Datasheet Identification**|**Product Status**|**Definition**|
|Advance Information|Formative or In<br>Design|This datasheet contains the design specifications for<br>product development. Specifications may change in<br>any manner without notice.|
|Preliminary|First Production|This datasheet contains preliminary data, and<br>supplementary data will be published at a later date.<br>Fairchild Semiconductor reserves the right to make<br>changes at any time without notice in order to improve<br>design.|
|No Identification Needed|Full Production|This datasheet contains final specifications. Fairchild<br>Semiconductor reserves the right to make changes at<br>any time without notice in order to improve design.|
|Obsolete|Not In Production|This datasheet contains specifications on a product<br>that has been discontinued by Fairchild semiconductor.<br>The datasheet is printed for reference information only.|



Rev. I2 

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