FDG6303N

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September 2001 

## **FDG6303N Dual N-Channel, Digital FET** 

## **General Description** 

These dual N-Channel logic level enhancement mode field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance.  This  device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs. 

## **Features** 

- 25 V, 0.50 A  continuous, 1.5 A peak. 

- RDS(ON) = 0.45 Ω @ VGS= 4.5 V, RDS(ON) =0.60 Ω @ VGS= 2.7 V. 

- Very low level gate drive requirements allowing  direct operation in 3 V circuits (VGS(th) < 1.5 V). 

- Gate-Source Zener for ESD ruggedness (>6kV Human Body Model). 

- Compact industry standard SC70-6 surface mount package. 

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SC70-6 SOT-23 SuperSOTTM-6<br>**----- End of picture text -----**<br>


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SuperSOTTM-8 SO-8 SOT-223<br>**----- End of picture text -----**<br>


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1 or 4 * 6 or 3<br>) 2 or 5 | 5 or 2<br>3 or 6 4 or 1 *<br>**----- End of picture text -----**<br>


||**D1**<br>**S2**<br>**G2**<br>**.03**|||1 or 4 *****<br>2 or 5<br>~~)~~|~~)~~|~~)~~|~~)~~|~~)~~|~~)~~|~~)~~|~~)~~|~~)~~|~~)~~||6 or 3<br>5 or 2<br> ||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**SC70-6**<br>**G1**<br>**S1**|**D2**||3 or 6|||||||||||4 or 1 *****|||
|||||||||||||||||||
|*The pinouts are symmetrical; pin 1 and 4 are interchangeable.||||||||||||||||||
|Units inside the carrier can be of either orientation and will not affect the functionality of the device.||||||||||||||||||
|**Absolute Maximum Ratings**TA= 25°C unless otherwise noted||||||||||||||||||
|**Symbol**|**Parameter**|||**FDG6303N**|||||||||||||**Units**|
|VDSS|Drain-Source Voltage||||||25||||||||||V|
|VGSS|Gate-Source Voltage|||- 0.5 to +8|- 0.5 to +8||||||||||||V|
|ID|Drain/Output Current<br>- Continuous||||||0.5||||||||||A|
||- Pulsed||||||1.5|||||||||||
|PD|Maximum Power Dissipation|Maximum Power Dissipation(Note 1)|||||0.3||||||||||W|
|TJ,TSTG|Operating and Storage Temperature Range||||-55 to 150||||||||||||°C|
|ESD|Electrostatic Discharge  Rating MIL-STD-883D||||||6.0||6.0||||||||kV|
||Human Body  Model (100 pF / 1500Ω)|)||||||||||||||||
|**THERMAL CHARACTERISTICS**|**THERMAL CHARACTERISTICS**|||||||||||||||||
|RθJA<br>~~**a**~~|Thermal Resistance, Junction-to-Ambient||||||415||||||||||°C/W|



FDG6303N Rev.F 

|**Electrical Characteristics**(TA= 25OC|**Electrical Characteristics**(TA= 25OC|unless otherwise noted )|unless otherwise noted )|||||
|---|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Conditions**||**Min**|**Typ**|**Max**|**Units**|
|**OFF CHARACTERISTICS**||||||||
|BVDSS|Drain-Source Breakdown Voltage|VGS= 0 V,  ID= 250 µA||25|||V|
|∆BVDSS/∆TJ|Breakdown Voltage Temp. Coefficient|ID= 250 µA, Referenced|to  25oC||26||mV/oC|
|IDSS|Zero Gate Voltage  Drain Current|VDS= 20 V,  VGS= 0 V||||1|µA|
||||TJ= 55°C|||10|µA|
|IGSS|Gate - Body Leakage Current|VGS= 8 V,  VDS= 0 V||||100|nA|
|**ON CHARACTERISTICS**(Note 2)||||||||
|VGS(th)|Gate Threshold Voltage|VDS= VGS,  ID= 250 µA||0.65|0.8|1.5|V|
|∆VGS(th)/∆TJ|Gate Threshold Voltage Temp.Coefficient|ID= 250 µA, Referenced|to  25oC||-2.6||mV/oC|
|RDS(ON)|Static Drain-Source On-Resistance|VGS= 4.5 V,  ID= 0.5 A|||0.34|0.45|Ω|
||||T**J**=125°C||0.55|0.77||
|||VGS= 2.7 V,  ID= 0.2 A|||0.44|0.6||
|ID(ON)|On-State Drain Current|VGS= 2.7 V,  VDS= 5 V||0.5|||A|
|gFS|Forward Transconductance|VDS= 5 V,  ID=  0.5 A|||1.45||S|
|**DYNAMIC CHARACTERISTICS**||||||||
|Ciss|Input Capacitance|VDS= 10 V,  VGS= 0 V,<br>f  = 1.0 MHz|||50||pF|
|Coss|Output Capacitance||||28||pF|
|Crss|Reverse Transfer Capacitance||||9||pF|
|**SWITCHING CHARACTERISTICS**(Note 2)||||||||
|tD(on)|Turn - On Delay Time|VDD= 5 V,  ID= 0.5 A,<br>VGS= 4.5 V,  RGEN= 50Ω|||3|6|ns|
|tr|Turn - On Rise Time||||8.5|18|ns|
|tD(off)|Turn - Off Delay Time||||17|30|ns|
|tf|Turn - Off Fall Time||||13|25|ns|
|Qg|Total Gate Charge|VDS= 5 V,  ID= 0.5 A,<br>VGS= 4.5 V|||1.64|2.3|nC|
|Qgs|Gate-Source Charge||||0.38||nC|
|Qgd|Gate-Drain Charge||||0.45||nC|
|**DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS**||||||||
|IS|Maximum Continuous Source  Current|||||0.25|A|
|VSD|Drain-Source Diode Forward Voltage|VGS= 0 V,  IS= 0.25 A(Note 2)|||0.8|1.2|V|



Notes: 

1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design. RθJA = 415OC/W on minimum pad mounting on FR-4  board in still air. 

2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%. 

FDG6303N Rev.F 

## **Typical Electrical Characteristics** 

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1.5<br>V     = 4.5VGS    2.5V<br>3.0V<br>1.2 2.7V  2.0V<br>0.9<br>0.6<br> 1.5V<br>0.3<br>0<br>0 0.5 1 1.5 2 2.5 3<br>V     , DRAIN-SOURCE VOLTAGE (V)DS<br>I   , DRAIN-SOURCE CURRENT (A)D<br>**----- End of picture text -----**<br>


**Figure 1. On-Region Characteristics** . 

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1.6<br>I   = 0.5AD<br>1.4 V     = 4.5 V GS<br>1.2<br>1<br>0.8<br>0.6<br>-50 -25 0 25 50 75 100 125 150<br>T  , JUNCTION TEMPERATURE (°C)J<br>DS(ON)<br>R             , NORMALIZED<br>DRAIN-SOURCE ON-RESISTANCE<br>**----- End of picture text -----**<br>


## **Figure 3. On-Resistance Variation** 

**with Temperature** . 

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1<br>V     = 5.0VDS T  = -55°CJ<br>25°C<br>0.8<br>125°C<br>0.6<br>0.4<br>0.2<br>0<br>0 0.5 1 1.5 2 2.5<br>V     , GATE TO SOURCE VOLTAGE (V)GS<br>I   , DRAIN CURRENT (A)D<br>**----- End of picture text -----**<br>


**Figure  5. Transfer Characteristics.** 

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2<br>V    = 2.0VGS<br>1.5<br> 2.5V<br>2.7V<br> 3.0V<br>3.5V<br>1  4.5V<br>0.5<br>0 0.2 0.4 0.6 0.8 1 1.2<br>I    , DRAIN CURRENT (A)D<br>Figure 2. On-Resistance Variation with<br>                      Drain Current and Gate Voltage.<br>2<br> I   = 0.3AD<br>1.6<br>1.2<br> T  = 125°CA<br>0.8<br>0.4<br> T  = 25°CA<br>0<br>1 1.5 2 2.5 3 3.5 4 4.5 5<br>V      , GATE TO SOURCE VOLTAGE (V)GS<br>R              , NORMALIZED<br>DRAIN-SOURCE ON-RESISTANCE<br>DS(on)<br>R           , ON-RESISTANCE (OHM)<br>DS(ON)<br>**----- End of picture text -----**<br>


**Figure 4. On-Resistance Gate-to-Source Voltage.** 

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1<br>V     = 0VGS<br>0.1 T  = 125J ° C<br>25°C<br> -55°C<br>0.01<br>0.001<br>0.0001<br>0 0.2 0.4 0.6 0.8 1 1.2<br>V     , BODY DIODE FORWARD VOLTAGE (V)SD<br>I   , REVERSE DRAIN CURRENT (A)S<br>**----- End of picture text -----**<br>


## **Figure 6 . Body Diode Forward Voltage Variation with Source Current and Temperature.** 

FDG6303N Rev.F 

## **Typical Electrical Characteristics (continued)** 

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5 200<br>I   = 0.5AD V     = 5VDS<br>10V<br>4 15V 70<br>C  iss<br>3 30<br>C  oss<br>2<br>10<br>f = 1 MHz C  rss<br>1 V     = 0VGS<br>3<br>0 0.1 0.3 1 2 5 10 25<br>0 0.4 0.8 1.2 1.6 2<br>Q    , GATE CHARGE (nC)g V      , DRAIN TO SOURCE VOLTAGE (V)DS<br>Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics.<br>3 50<br>SINGLE PULSE<br>1 40 R     =415°C/W θ [JA]<br>0.5  T  = 25°CA<br>30<br>0.2<br>0.1 20<br>V     = 4.5VGS<br>0.05 SINGLE PULSE<br>10<br>R      = 415 °C/W       θ [JA]<br>0.02 T  = 25°CA<br>0.01 0<br>0.1 1 2 5 10 25 40 0.0001 0.001 0.01 0.1 1 10 200<br> V     , DRAI N-SOURCE VOLTAGE (V)DS SINGLE PULSE TIME (SEC)<br> 1ms<br> 10ms<br> 1s<br> DC<br>10s<br>100ms<br>RDS(ON) LIMIT<br>CAPACITANCE (pF)<br>GS<br>V      , GATE-SOURCE VOLTAGE (V)<br>POWER (W)<br>I   , DRAIN CURRENT (A)D<br>**----- End of picture text -----**<br>


**Figure 9. Maximum Safe Operating Area.** 

**Figure 10. Single Pulse Maximum Power** 

**Dissipation.** 

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1<br>0.5  D = 0.5<br>R        (t) = r(t)   θ [JA] *  R          θ [JA]<br>0.2   0.2      R        =415θ [JA]  °C/W<br>0.1  0.1<br> 0.05  P(pk)<br>0.05<br> 0.02   t  1<br>0.02  0.01   t    2<br>0.01  Single Pulse  T  - T    = P  * R       (t)J A θ [JA]<br>Duty Cycle, D = t 1/ t 2<br>0.005<br>0.002<br>0.0001 0.001 0.01 0.1 1 10 100 200<br>t  , TIME (sec)1<br>r(t), NORMALIZED EFFECTIVE<br>TRANSIENT THERMAL RESISTANCE<br>**----- End of picture text -----**<br>


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Figure 11. Transient Thermal Response Curve.<br>                           Thermal characterization performed using the conditions described in note 1.<br>                Transient thermal response will change depending on the circuit board design.<br>**----- End of picture text -----**<br>


FDG6303N Rev.F 

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TRADEMARKS<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is<br>not intended to be an exhaustive list of all such trademarks.<br>ACEx™ FACT™ ImpliedDisconnect™ PACMAN™ SPM™<br>ActiveArray™ FACT Quiet Series™ ISOPLANAR™ POP™ Stealth™<br>Bottomless™ FAST® LittlkeFET™ Power247™ SuperSOT™-3<br>CoolFET™ FASTr™ MicroFET™ PowerTrench® SuperSOT™-6<br>CROSSVOLT™ FRFET™ MicroPak™ QFET™ SuperSOT ™-8<br>DOME™ GlobalOptoisolator™ MICROWIRE™ qas™ SyncFET™<br>EcoSPARK™ GTOo™ MSX™ QT Optoelectronics™ TinyLogic®<br>E?CMOS™ HiSeC™ MSXPro™ Quiet Series™ TruTranslation™<br>EnSigna™ 2co™ OCX™ RapidConfigure™ UHC™<br>Across the board. Around the world.™ OCXPro™ RapidConnect™ UltraFET®<br>The Power Franchise™ OPTOLOGIC® SILENT SWITCHER® VCX™<br>Programmable Active Droop™ OPTOPLANAR™ SMART START™<br>DISCLAIMER<br>FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER<br>NOTICE TOANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD<br>DOES NOTASSUMEANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT<br>OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT<br>RIGHTS, NOR THE RIGHTS OF OTHERS.<br>LIFE SUPPORT POLICY<br>FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT<br>DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTENAPPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.<br>As used herein:<br>1. Life support devices or systems are devices or 2. A critical component is any component ofa life<br>systems which, (a) are intended for surgical implant into support device or system whose failure to perform can<br>the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life<br>failure to perform when properly used in accordance support device or system, or to affect its safety or<br>with instructions for use provided in the labeling, can be effectiveness.<br>reasonably expected to result in significant injury to the<br>user.<br>PRODUCT STATUS DEFINITIONS<br>Definition of Terms<br>Advance Information Formative or This datasheet contains the design specifications for<br>In Design product development. Specifications may change in<br>any manner without notice.<br>Preliminary First Production This datasheet contains preliminary data, and<br>supplementary data will be published at a later date.<br>Fairchild Semiconductor reserves the right to make<br>changes at any time without notice in order to improve<br>design.<br>No Identification Needed Full Production This datasheet contains final specifications. Fairchild<br>Semiconductor reserves the right to make changes at<br>any time without notice in order to improve design.<br>Obsolete Not In Production This datasheet contains specifications on a product<br>that has been discontinued by Fairchild semiconductor.<br>The datasheet is printed for reference information only.<br>**----- End of picture text -----**<br>


Rev. 12 

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