FDG6301N

## Digital FET, Dual N-Channel 

## FDG6301N 

## **General Description** 

These dual N−Channel logic level enhancement mode field effect transistors are produced using ON Semiconductor’s proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on−state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs. 

## **Features** 

- 25 V, 0.22 A Continuous, 0.65 A Peak 

   - ♦ RDS(ON) = 4  @ VGS = 4.5 V 

   - ♦ RDS(ON) = 5  @ VGS = 2.7 V 

- Very Low Level Gate Drive Requirements Allowing Direct Operation in 3 V Circuits (VGS(th) < 1.5 V) 

- Gate−Source Zener for ESD Ruggedness (>6 kV Human Body Model) 

- Compact Industry Standard SC70−6 Surface Mount Package 

- These Devices are Pb−Free and are RoHS Compliant 

**ABSOLUTE MAXIMUM RATINGS** (TA = 25 ° C unless otherwise noted) 

~~a~~ **Symbol** ~~es~~ **Parameter FDG6301N Units** VDSS Drain−Source Voltage 25 V ~~a ee~~ ~~**ee** ee~~ VGSS Gate−Source Voltage 8 V ID Drain/Output Current Continuous 0.22 A Pulsed 0.65 ~~a~~ PD Maximum Power Dissipation (Note 1) 0.3 W ~~aeees~~ TJ, TSTG Operating and Storage Temperature −55 to +150 ° C Range ~~Pf~~ ESD Electrostatic Discharge Rating 6.0 kV MIL−STD−883D Human Body Model (100 pF / 1500 ) ~~Pf~~ 

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

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www.onsemi.com<br>G2 [G2]<br>D1<br>D2<br>Fl G1<br>S1<br>SC−88/SC70−6/SOT−363<br>CASE 419B−02<br>**----- End of picture text -----**<br>


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MARKING DIAGRAM<br>**----- End of picture text -----**<br>


01M 01 = Specific Device Code M = Assembly Operation Month 

## **PIN CONNECTIONS** 

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**----- Start of picture text -----**<br>
1 or 4*<br>6 or 3<br>2 or 5 5 or 2<br>3 or 6 4 or 1*<br>**----- End of picture text -----**<br>


- *The pinouts are symmetrical; pin 1 and 4 are interchangeable. 

Units inside the carrier can be of either orientation and will not affect the functionality of the device. 

## **ORDERING INFORMATION** 

See detailed ordering and shipping information on page 5 of this data sheet. 

Publication Order Number: **FDG6301N/D** 

**1** 

© Semiconductor Components Industries, LLC, 1999 **May, 2021 − Rev. 7** 

**FDG6301N** 

## **THERMAL CHARACTERISTICS** 

|**THERMAL**|**CHARACTERISTICS**|||
|---|---|---|---|
|**Symbol**|**Parameter**|**Ratings**|**Unit**|
|R�JA|Thermal Resistance, Junction−to−Ambient (Note 1)|415|�C/W|



1. R � JA is the sum of the junction−to−case and case−to−ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R � JC is guaranteed by design while R � CA is determined by the user’s board design. R � JA = 415 ° C/W on minimum pad mounting on FR−4 board in still air. 

## **ELECTRICAL CHARACTERISTICS** (TA = 25 ° C unless otherwise noted) 

|**ELECTRICAL**|**CHARACTERISTICS**(TA= 25°C unle|ss otherwise noted)|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**|||||||
|BVDSS|Drain−Source Breakdown Voltage|VGS= 0 V, ID= 250�A|25|−|−|V|
|�BVDSS/�TJ|Breakdown Voltage Temperature<br>Coefficient|ID= 250�A, Referenced to 25�C|−|25|−|mV/�C|
|IDSS|Zero Gate Voltage Drain Current|VDS= 20 V, VGS= 0 V|−|−|1|�A|
|||VDS= 20 V, VGS= 0 V, TJ= 55�C|−|−|10|�A|
|IGSS|Gate−Body Leakage Current|VGS= 8 V, VDS= 0 V|−|−|100|nA|
|**ON CHARACTERISTICS**(Note 2)|||||||
|VGS(th)|Gate Threshold Voltage|VDS= VGS, ID= 250�A|0.65|0.85|1.5|V|
|�VGS(th)/�TJ|Gate Threshold Voltage<br>Temperature Coefficient|ID= 250�A, Referenced to 25�C|−|−2.1|−|mV/�C|
|RDS(on)|Static Drain−Source<br>On−Resistance|VGS= 4.5 V, ID= 0.22 A|−|2.6|4|�|
|||VGS= 4.5 V, ID= 0.22 A, TJ= 125�C|−|5.3|7||
|||VGS= 2.7 V, ID= 0.19 A|−|3.7|5||
|ID(on)|On−State Drain Current|VGS= 4.5 V, VDS= 5 V|0.22|−|−|A|
|gFS|Forward Transconductance|VDS= 5 V, ID= 0.22 A|−|0.2|−|S|
|**DYNAMIC CHARACTERISTICS**|||||||
|Ciss|Input Capacitance|VDS= 10 V, VGS= 0 V, f = 1.0 MHz|−|9.5|−|pF|
|Coss|Output Capacitance||−|6|−|pF|
|Crss|Reverse Transfer Capacitance||−|4.5|−|pF|
|**SWITCHING CHARACTERISTICS**(Note 2)|||||||
|tD(on)|Turn-On Delay Time|VDD= 5 V, ID= 0.5 A,<br>VGS= 4.5 V, RGEN= 50�|−|5|10|ns|
|tr|Turn-On Rise Time||−|4.5|10|ns|
|tD(off)|Turn-Off Delay Time||−|4|8|ns|
|tf|Turn-Off Fall Time||−|3.2|7|ns|
|Qg|Total Gate Charge|VDS= 5 V, ID= 0.22 A,<br>VGS= 4.5 V|−|0.29|0.4|nC|
|Qgs|Gate−Source Charge||−|0.12|−|nC|
|Qgd|Gate−Drain Charge||−|0.03|−|nC|
|**DRAIN−SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS**|||||||
|IS|Maximum Continuous Source Current||−|−|0.25|A|
|VSD|Drain−Source Diode Forward<br>Voltage|VGS= 0 V, IS= 0.25 A (Note 2)|−|0.8|1.2|V|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 2. Pulse Test: Pulse Width ≤ 300 � s, Duty Cycle ≤ 2.0% 

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**2** 

**FDG6301N** 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

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0.5<br> V    = 4.5 VGS<br> 3.5 V<br>0.4<br> 3.0 V<br>0.3 2.7 V<br>2.5 V<br>0.2<br>2.0 V<br>0.1<br>0<br>0 1 2 3 4 5<br>V DS, DRAIN−SOURCE VOLTAGE (V)<br>Figure 1. On−Region Characteristics<br>1.8<br>I   = 0.22 AD<br>1.6 V     = 4.5 V GS<br>1.4<br>1.2<br>1<br>0.8<br>0.6<br>−50 −25 0 25 50 75 100 125 150<br>TJ , JUNCTION TEMPERATURE ( ° C)<br>Figure 3. On−Resistance Variation with<br>Temperature<br>0.2<br>V DS = 5 V TJ = −55 ° C<br>25 ° C<br>0.15 125 ° C<br>0.1<br>0.05<br>0<br>0.5 1 1.5 2 2.5 3<br>VGS, GATE TO SOURCE VOLTAGE (V)<br>, DRAIN−SOURCE CURRENT (A)<br>ID<br>, NORMALIZED<br>DS(ON)<br>R<br>DRAIN−SOURCE ON−RESISTANCE<br>, DRAIN CURRENT (A)<br>ID<br>**----- End of picture text -----**<br>


**Figure 5. Transfer Characteristics** 

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5<br>4.5 V     = 2.5 VGS<br>4 2.7 V<br>3.0 V<br>3.5<br>3.5 V<br>3  4.0 V<br>4.5 V<br>5.0 V<br>2.5<br>2<br>0 0.1 0.2 0.3 0.4<br>ID, DRAIN CURRENT (A)<br>Figure 2. On−Resistance Variation with<br>Drain Current and Gate Voltage<br>20<br>ID = 0.10 A<br>16<br>12<br>8<br>TA = 125 ° C<br>4<br>25 ° C<br>0<br>1 2 3 4 5<br>VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 4. On−Resistance Variation with<br>Gate−to−Source Voltage<br>0.4<br>V    = 0 VGS<br>0.1<br>T  = 125 J °C<br>0.01<br>25°C<br>-55°C<br>0.001<br>0.0001<br>0 0.2 0.4 0.6 0.8 1 1.2<br>VSD, BODY DIODE FORWARD VOLTAGE (V)<br>, NORMALIZED<br>DS(ON)<br>R<br>DRAIN−SOURCE ON−RESISTANCE<br>�<br>, ON−RESISTANCE (   )<br>DS(ON)<br>R<br>, REVERSE DRAIN CURRENT (A)<br>IS<br>**----- End of picture text -----**<br>


**Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature** 

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**3** 

**FDG6301N** 

## **TYPICAL PERFORMANCE CHARACTERISTICS** (continued) 

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6 30<br>I   = 0.22 AD V    = 5 VDS<br>10 V<br>5<br>15<br>4<br>C iss<br>3 8<br>C oss<br>2 5<br>C rss<br>1 3 f = 1 MHz<br>VGS = 0 VGS = 0 V = 0 V<br>0 2<br>0 0.1 0.2 0.3 0.4 0.5 0.6 0.1 0.3 1 3 10 25<br>Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)DS, DRAIN TO SOURCE VOLTAGE (V), DRAIN TO SOURCE VOLTAGE (V)<br>Figure 7. Gate Charge Characteristics Figure 8. Capacitance Characteristics<br>1 50<br>SINGLE PULSE<br>10 ms R � JA = 415= 415 ° C/W<br>R DS(ON)  LIMIT 40 T A  = 25 ° C<br>0.3<br>100 ms<br>30<br>1 s<br>0.1<br>10 s 20<br>VGS = 4.5 V<br>0.03 SINGLE PULSER � JA = 415 ° C/W DC 10<br>TA = 25 ° C<br>0.01 0<br>0.4 0.8 2 5 10 25 40 0.0001 0.001 0.01 0.1 1 10 200<br>VDS, DRAIN−SOURCE VOLTAGE (V) SINGLE PULSE TIME (sec)<br>Figure 9. Maximum Safe Operating Area Figure 10. Single Pulse Maximum Power<br>Dissipation<br>1<br>0.5  D = 0.5<br>0.2   0.2 R � JA  (t) = r(t) * R � JA<br>0.1  0.1 R � JA = 415 ° C/W<br> 0.05<br>0.05 P(pk)<br> 0.02<br>0.02  0.01  t1<br>0.01  Single Pulse  t 2<br>TJ − TA = P * R � JA (t)<br>0.005 Duty Cycle, D = t1 / t2<br>0.002<br>0.0001 0.001 0.01 0.1 1 10 100 200<br>t  , TIME (sec)1<br>Thermal characterization performed using the conditions described in Note 1.<br>Transient thermal response will change depending on the circuit board design.<br>CAPACITANCE (pF)<br>, GATE−SOURCE VOLTAGE (V)<br>GS<br>V<br>POWER (W)<br>, DRAIN CURRENT (A)<br>ID<br>r(t), NORMALIZED EFFECTIVE<br>TRANSIENT THERMAL RESISTANCE<br>**----- End of picture text -----**<br>


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30<br>15<br>C iss<br>8<br>C oss<br>5<br>C rss<br>3 f = 1 MHz<br>VGS = 0 VGS = 0 V = 0 V<br>2<br>0.1 0.3 1 3 10 25<br>VDS, DRAIN TO SOURCE VOLTAGE (V)DS, DRAIN TO SOURCE VOLTAGE (V), DRAIN TO SOURCE VOLTAGE (V)<br>CAPACITANCE (pF)<br>**----- End of picture text -----**<br>


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50<br>SINGLE PULSE<br>R � JA = 415= 415 ° C/W<br>40 T A  = 25 ° C<br>30<br>20<br>10<br>0<br>0.0001 0.001 0.01 0.1 1 10 200<br>SINGLE PULSE TIME (sec)<br>POWER (W)<br>**----- End of picture text -----**<br>


**Figure 11. Transient Thermal Response Curve** 

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**4** 

**FDG6301N** 

## **ORDERING INFORMATION** 

|**ORDERING INFORMATION**||||
|---|---|---|---|
|**Device Order Number**|**Device Marking**|**Package Type**|**Shipping**†|
|FDG6301N|01|SC−88/SC70−6/SOT−363<br>(Pb−Free)|3000 / Tape & Reel|



- †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 

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**5** 

MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

**SC−88/SC70−6/SOT−363** CASE 419B−02 ISSUE Y 

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1<br>SCALE 2:1 2X DATE 11 DEC 2012<br>aaa H D<br>- D H NOTES:1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.<br>2. CONTROLLING DIMENSION: MILLIMETERS.<br>A 3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,<br>D GAGE PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-<br>PLANE SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.<br>4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF<br>6 5 4 THE PLASTIC BODY AND DATUM H.<br>L2 L 5. DATUMS A AND B ARE DETERMINED AT DATUM H.<br>E E1 DETAIL A 6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THELEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.<br>7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.<br>1 2 3<br>ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN<br>EXCESS OF DIMENSION b AT MAXIMUM  MATERIAL CONDI-<br>2X aaa C TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER<br>bbb H D 2X 3 TIPS RADIUS OF THE FOOT.<br>e MILLIMETERS INCHES<br>DIM MIN NOM MAX MIN NOM MAX<br>B l= 6X b : A −−− −−− 1.10 −−− −−− 0.043<br>ddd M C A-B D A1 0.00 −−− 0.10 0.000 −−− 0.004<br>TOP VIEW A2 0.70 0.90 1.00 0.027 0.035 0.039<br>b 0.15 0.20 0.25 0.006 0.008 0.010<br>C 0.08 0.15 0.22 0.003 0.006 0.009<br>A2 DETAIL A D 1.80 2.00 2.20 0.070 0.078 0.086<br>A E 2.00 2.10 2.20 0.078 0.082 0.086<br>E1 1.15 1.25 1.35 0.045 0.049 0.053<br>e 0.65 BSC 0.026 BSC<br>L 0.26 0.36 0.46 0.010 0.014 0.018<br>L2 0.15 BSC 0.006 BSC<br>aaa 0.15 0.006<br>bbb 0.30 0.012<br>6X ccc C ccc 0.10 0.004<br>(tll, A1 C  A SEATINGPLANE Ma c === ddd 0.10 0.004<br>SIDE VIEW END VIEW GENERIC<br>MARKING DIAGRAM*<br>RECOMMENDED 6<br>SOLDERING FOOTPRINT*<br>6X 6X XXXM<br>0.30 0.66<br>1<br>Ta os 2.50 XXX = Specific Device Code<br>M = Date Code*<br>= Pb−Free Package<br>0.65 yo (Note: Microdot may be in either location)<br>PITCH<br>**----- End of picture text -----**<br>


## DATE 11 DEC 2012 

1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 

   - *Date Code orientation and/or position may vary depending upon manufacturing location. 

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**----- Start of picture text -----**<br>
DIMENSIONS: MILLIMETERS<br>**----- End of picture text -----**<br>


- *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

- *This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ ”, may or may not be present. Some products may not follow the Generic Marking. 

## **STYLES ON PAGE 2** 

**DOCUMENT NUMBER: 98ASB42985B** 

**DESCRIPTION: SC−88/SC70−6/SOT−363** 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. 

**PAGE 1 OF 2** 

ON Semiconductor and          are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 

www.onsemi.com 

© Semiconductor Components Industries, LLC, 2019 

## **SC−88/SC70−6/SOT−363** CASE 419B−02 ISSUE Y 

## DATE 11 DEC 2012 

|STYLE 1:|STYLE 2:|STYLE 3:|STYLE 4:|STYLE 5:|STYLE 6:|
|---|---|---|---|---|---|
|PIN 1. EMITTER 2|CANCELLED|CANCELLED|PIN 1. CATHODE|PIN 1. ANODE|PIN 1. ANODE 2|
|2. BASE 2|||2. CATHODE|2. ANODE|2. N/C|
|3. COLLECTOR 1|||3. COLLECTOR|3. COLLECTOR|3. CATHODE 1|
|4. EMITTER 1|||4. EMITTER|4. EMITTER|4. ANODE 1|
|5. BASE 1|||5. BASE|5. BASE|5. N/C|
|6. COLLECTOR 2|||6. ANODE|6. CATHODE|6. CATHODE 2|
|STYLE 7:|STYLE 8:|STYLE 9:|STYLE 10:|STYLE 11:|STYLE 12:|
|PIN 1. SOURCE 2|CANCELLED|PIN 1. EMITTER 2|PIN 1. SOURCE 2|PIN 1. CATHODE 2|PIN 1. ANODE 2|
|2. DRAIN 2||2. EMITTER 1|2. SOURCE 1|2. CATHODE 2|2. ANODE 2|
|3. GATE 1||3. COLLECTOR 1|3. GATE 1|3. ANODE 1|3. CATHODE 1|
|4. SOURCE 1||4. BASE 1|4. DRAIN 1|4. CATHODE 1|4. ANODE 1|
|5. DRAIN 1||5. BASE 2|5. DRAIN 2|5. CATHODE 1|5. ANODE 1|
|6. GATE 2||6. COLLECTOR 2|6. GATE 2|6. ANODE 2|6. CATHODE 2|
|STYLE 13:|STYLE 14:|STYLE 15:|STYLE 16:|STYLE 17:|STYLE 18:|
|PIN 1. ANODE|PIN 1. VREF|PIN 1. ANODE 1|PIN 1. BASE 1|PIN 1. BASE 1|PIN 1. VIN1|
|2. N/C|2. GND|2. ANODE 2|2. EMITTER 2|2. EMITTER 1|2. VCC|
|3. COLLECTOR|3. GND|3. ANODE 3|3. COLLECTOR 2|3. COLLECTOR 2|3. VOUT2|
|4. EMITTER|4. IOUT|4. CATHODE 3|4. BASE 2|4. BASE 2|4. VIN2|
|5. BASE|5. VEN|5. CATHODE 2|5. EMITTER 1|5. EMITTER 2|5. GND|
|6. CATHODE|6. VCC|6. CATHODE 1|6. COLLECTOR 1|6. COLLECTOR 1|6. VOUT1|
|STYLE 19:|STYLE 20:|STYLE 21:|STYLE 22:|STYLE 23:|STYLE 24:|
|PIN 1. I OUT|PIN 1. COLLECTOR|PIN 1. ANODE 1|PIN 1. D1 (i)|PIN 1. Vn|PIN 1. CATHODE|
|2. GND|2. COLLECTOR|2. N/C|2. GND|2. CH1|2. ANODE|
|3. GND|3. BASE|3. ANODE 2|3. D2 (i)|3. Vp|3. CATHODE|
|4. V CC|4. EMITTER|4. CATHODE 2|4. D2 (c)|4. N/C|4. CATHODE|
|5. V EN|5. COLLECTOR|5. N/C|5. VBUS|5. CH2|5. CATHODE|
|6. V REF|6. COLLECTOR|6. CATHODE 1|6. D1 (c)|6. N/C|6. CATHODE|
|STYLE 25:|STYLE 26:|STYLE 27:|STYLE 28:|STYLE 29:|STYLE 30:|
|PIN 1. BASE 1|PIN 1. SOURCE 1|PIN 1. BASE 2|PIN 1. DRAIN|PIN 1. ANODE|PIN 1. SOURCE 1|
|2. CATHODE|2. GATE 1|2. BASE 1|2. DRAIN|2. ANODE|2. DRAIN 2|
|3. COLLECTOR 2|3. DRAIN 2|3. COLLECTOR 1|3. GATE|3. COLLECTOR|3. DRAIN 2|
|4. BASE 2|4. SOURCE 2|4. EMITTER 1|4. SOURCE|4. EMITTER|4. SOURCE 2|
|5. EMITTER|5. GATE 2|5. EMITTER 2|5. DRAIN|5. BASE/ANODE|5. GATE 1|
|6. COLLECTOR 1|6. DRAIN 1|6. COLLECTOR 2|6. DRAIN|6. CATHODE|6. DRAIN 1|



Note: Please refer to datasheet for style callout. If style type is not called out in the datasheet refer to the device datasheet pinout or pin assignment. 

|**DOCUMENT NUMBER:**|**98ASB42985B**|Electronic versions are uncontrolled except when accessed directly from the Document Repository.<br>Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red.|Electronic versions are uncontrolled except when accessed directly from the Document Repository.<br>Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red.|
|---|---|---|---|
|**DESCRIPTION:**|**SC−88/SC70−6/SOT−363**||**PAGE 2 OF 2**|



ON Semiconductor and          are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor the rights of others. 

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© Semiconductor Components Industries, LLC, 2019 

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