FDC6310P

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April 2001 

## **FDC6310P** 

## **Dual P-Channel 2.5V Specified PowerTrench[] MOSFET** 

## **General Description** 

These P-Channel 2.5V specified MOSFETs are produced using Fairchild Semiconductor's advanced PowerTrench process that has been especially tailored to minimize on-state resistance and yet maintain low gate charge for superior switching performance. 

These devices have been designed to offer exceptional power dissipation in a very small footprint for applications where the bigger more expensive SO-8 and TSSOP-8 packages are impractical. 

## **Applications** 

- Load switch 

## **Features** 

   - –2.2 A, –20 V. RDS(ON) = 125 mΩ @ V GS = –4.5 V RDS(ON) = 190 mΩ @ V GS = –2.5 V 

   - Low gate charge 

   - Fast switching speed 

   - High performance trench technology for extremely low RDS(ON) 

   - SuperSOT TM -6 package: small footprint 72% smaller than standard SO-8); low profile (1mm thick) 

- Battery protection 

- Power management 

**==> picture [134 x 80] intentionally omitted <==**

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D2<br>S1<br>D1<br>e at<br>Og G2<br>SuperSOT    -6TM G1 S2<br>**----- End of picture text -----**<br>


**==> picture [91 x 55] intentionally omitted <==**

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4 3<br>5 2<br>ST UHR<br>6 1<br>**----- End of picture text -----**<br>


**Absolute Maximum Ratings** TA=25oC unless otherwise noted 

|**Symbol **|**Parameter **|**Parameter **||**Ratings**|||**Units**|
|---|---|---|---|---|---|---|---|
|VDSS|Drain-Source Voltage|||–20|||V|
|VGSS|Gate-Source Voltage|||±12|||V|
|ID|Drain Current<br>– Continuous||(Note 1a)|–2.2|||A|
||– Pulsed|||–6||||
|PD|Power Dissipation for Single Operation||(Note 1a)|0.96|||W|
||||(Note 1b)|0.9||||
||||(Note 1c)|0.7||||
|TJ, TSTG|Operating and Storage Junction Temperature Range|||–55 to +150|||°C|
|**Thermal Characteristics**||||||||
|RθJA|Thermal Resistance, Junction-to-Ambient||Thermal Resistance, Junction-to-Ambient<br>(Note 1a)|130|||°C/W|
|RθJC|Thermal Resistance, Junction-to-Case||(Note 1)|60|||°C/W|
|**Package Marking and Ordering Information**||||**Information**||||
|**Device Marking**<br>**Device**<br>**Reel Size**<br>**Tape width**<br>.310<br>FDC6310P<br>7’’<br>8mm<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~ee~~||||||**Quantity**<br>3000 units||
|2001 Fairchild Semiconductor Corporation||||||FDC6310P  Rev C(W)||



FDC6310P  Rev C(W) 

|**Electrical Characteristics**<br>TA= 25°C unless otherwise noted|**Electrical Characteristics**<br>TA= 25°C unless otherwise noted|**Electrical Characteristics**<br>TA= 25°C unless otherwise noted|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test Conditions**|**Min**|**Typ**|**Max**|**Units**|
|**OffCharacteristics**|||||||
|BVDSS|Drain–Source Breakdown Voltag|e  VGS= 0 V, ID= –250µA|–20|||V|
|∆BVDSS<br>∆TJ|Breakdown Voltage Temperature<br>Coefficient|<br>ID= –250µA, Referenced to 25°C||–11||mV/°C|
|IDSS|Zero Gate Voltage Drain Current|<br>VDS= –16 V, VGS= 0 V|||–1|µA|
|IGSSF|Gate–Body Leakage, Forward|VGS= 12 V,<br>VDS= 0 V|||100|nA|
|IGSSR|Gate–Body Leakage, Reverse|VGS= –12 V, VDS= 0 V|||–100|nA|
|**On Characteristics**<br>**(Note 2)**|||||||
|VGS(th)|Gate Threshold Voltage|VDS= VGS, ID= –250µA|–0.6|–1.0|–1.5|V|
|∆VGS(th)<br> <br>∆TJ|Gate Threshold Voltage<br>Temperature Coefficient|ID= –250µA, Referenced to 25°C||3||mV/°C|
|RDS(on)|Static Drain–Source<br>On–Resistance|VGS= –4.5 V,  ID= –2.2 A<br>VGS= –2.5 V,  ID= –1.8 A<br>VGS=–4.5 V, ID=–2.2 A, TJ=125°C||100<br>145<br>137|125<br>190<br>184|mΩ|
|ID(on)|On–State Drain Current|VGS= –4.5 V,<br>VDS= –5 V|–6|||A|
|gFS|Forward Transconductance|VDS= –5 V,<br>ID= –3.5 A||6||S|
|**Dynamic Characteristics**|||||||
|Ciss|Input Capacitance|VDS= –10 V,<br>VGS= 0 V,<br>f = 1.0 MHz||337||pF|
|Coss|Output Capacitance|||88||pF|
|Crss|Reverse Transfer Capacitance|||51||pF|
|**Switching Characteristics**<br>**(Note 2)**|||||||
|td(on)|Turn–On Delay Time|VDD= –10 V,<br>ID= –1 A,<br>VGS= –4.5 V,<br>RGEN= 6Ω||9|18|ns|
|tr|Turn–On Rise Time|||12|22|ns|
|td(off)|Turn–Off Delay Time|||10|20|ns|
|tf|Turn–Off Fall Time|||5|10|ns|
|Qg|Total Gate Charge|VDS= –10 V,<br>ID= –2.2 A,<br>VGS= –4.5 V||3.7|5.2|nC|
|Qgs|Gate–Source Charge|||0.65||nC|
|Qgd|Gate–Drain Charge|||1.3||nC|
|**Drain–Source Diode Characteristics and Maximum Ratings**|||||||
|IS|Maximum Continuous Drain–Sour|ce Diode Forward Current|||–0.8|A|
|VSD|Drain–Source Diode Forward<br>Voltage|VGS= 0 V, IS= –0.8 A<br>(Note 2)||0.77|–1.2|V|



**Notes:** 

**1.** RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins.  RθJC is guaranteed by design while RθCA is determined by the user's board design. 

**==> picture [335 x 39] intentionally omitted <==**

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a) 130 mounted on a 0.125 in2 pad of 2 oz. °C/W when  b) 140°/W when mounted on a .004 incopper  2 pad of 2 oz  c) 180°/W when mounted on a minimum pad.<br>copper.<br>**----- End of picture text -----**<br>


Scale 1 : 1 on letter size paper 

**2.** Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0% 

FDC6310P Rev C(W) 

## **Typical Characteristics** 

**==> picture [418 x 131] intentionally omitted <==**

**----- Start of picture text -----**<br>
6 2.75<br>VGS =- 4.5V -3.0V 2.5<br>5 -3.5V -2.5V 2.25 VGS = -2.0V<br>4 2<br>3 1.75<br>-2.5V<br>-2.0V 1.5<br>2 -3.0V<br>- 1.8V 1.25 -3.5V<br>1 1 -4.5V<br>0 0.75<br>0 0.5 1 1.5 2 2.5 0 1 2 3 4 5 6<br>-VDS, DRAIN-SOURCE VOLTAGE (V) -ID, DRAIN CURRENT (A)<br>, NORMALIZED<br>DS(ON)<br>, DRAIN CURRENT (A) D R<br>-I<br>DRAIN-SOURCE ON-RESISTANCE<br>**----- End of picture text -----**<br>


**Figure 1. On-Region Characteristics.** 

**Figure 2. On-Resistance Variation with Drain Current and Gate Voltage.** 

**==> picture [420 x 318] intentionally omitted <==**

**----- Start of picture text -----**<br>
1.6 0.4<br>ID = -2.2A ID = -2.2 A<br>VGS = -4.5V 0.35<br>1.4<br>0.3<br>1.2 0.25<br>1 0.2<br>TA = 125 [o] C<br>0.15<br>0.8<br>0.1<br>0.6 T A = 25 [o] C<br>0.05<br>-50 -25 0 25 50 75 100 125 150 1 2 3 4 5<br>T J, JUNCTION TEMPERATURE ( [o] C) -VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 3. On-Resistance Variation with  Figure 4. On-Resistance Variation with<br>Temperature.  Gate-to-Source Voltage.<br>5 100<br>VDS = -5V TA = -55 [o] C 25 [o] C 10 VGS = 0V<br>4 125 [o] C T A = 125 [o] C<br>1<br>25 [o] C<br>3<br>0.1 -55 [o] C<br>2<br>0.01<br>1 0.001<br>0.0001<br>0<br>0 0.2 0.4 0.6 0.8 1 1.2 1.4<br>0.5 1 1.5 2 2.5 3<br>-VGS, GATE TO SOURCE VOLTAGE (V) -VSD, BODY DIODE FORWARD VOLTAGE (V)<br>, NORMALIZED<br>RDS(ON) , ON-RESISTANCE (OHM)DS(ON)<br> DRAIN-SOURCE ON-RESISTANCE R<br>, DRAIN CURRENT (A)-ID<br>, REVERSE DRAIN CURRENT (A)-IS<br>**----- End of picture text -----**<br>


**Figure 5. Transfer Characteristics.** 

**Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature.** 

FDC6310P Rev C(W) 

## **Typical Characteristics** 

**==> picture [426 x 532] intentionally omitted <==**

**----- Start of picture text -----**<br>
5 600<br>ID = -2.2A VDS =- 5V -10V 500 Vf = 1MHzGS = 0 V<br>4<br>-15V<br>400<br>3 C ISS<br>300<br>2<br>200<br>1 COSS<br>100<br>CRSS<br>0 0<br>0 1 2 3 4 5 0 5 10 15 20<br>Q g, GATE CHARGE (nC) -VDS, DRAIN TO SOURCE VOLTAGE (V)<br>Figure 7. Gate Charge Characteristics.  Figure 8. Capacitance Characteristics.<br>100 5<br>SINGLE PULSE<br>4 RθJA = 180°C/W<br>10 RDS(ON)  LIMIT 10ms T A = 25°C<br>100ms 3<br>1 1s<br>10s<br>DC 2<br>V GS  = -4.5V<br>0.1 SINGLE PULSE<br>RθJA = 180 [o] C/W 1<br>T A  = 25 [o] C<br>0.01 0<br>0.1 1 10 100 0.01 0.1 1 10 100 1000<br>-VDS, DRAIN-SOURCE VOLTAGE (V) t1, TIME (sec)<br>Figure 9. Maximum Safe Operating Area.  Figure 10. Single Pulse Maximum<br>Power Dissipation.<br>1<br>D = 0.5<br>RθJA(t) = r(t) + RθJA<br>0.2<br>R θJA  = 180°C/W<br>0.1 0.1<br>0.05<br>0.02 P(pk)<br>0.01 t 1<br>0.01 TJ - TA =t2 P * RθJA(t)<br>SINGLE PULSE Duty Cycle, D = t 1  / t 2<br>0.001<br>0.0001 0.001 0.01 0.1 1 10 100 1000<br>t1, TIME (sec)<br>Figure 11. Transient Thermal Response Curve.<br>Thermal characterization performed using the conditions described in Note 1c.<br>Transient themal response will change depending on the circuit board design.<br>CAPACITANCE (pF)<br>, GATE-SOURCE VOLTAGE (V)<br>GS<br>-V<br>, DRAIN CURRENT (A)-ID<br>P(pk), PEAK TRANSIENT POWER (W)<br>r(t), NORMALIZED EFFECTIVE<br>TRANSIENT THERMAL RESISTANCE<br>**----- End of picture text -----**<br>


FDC6310P Rev C(W) 

## **TRADEMARKS** 

The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. 

|ACEx™|FAST<br>|OPTOPLANAR™||SuperSOT™-3|
|---|---|---|---|---|
|Bottomless™|FASTr™|PACMAN™||SuperSOT™-6|
|CoolFET™|FRFET™|POP™||SuperSOT™-8|
|_CROSSVOLT_™|GlobalOptoisolator™|PowerTrench<br>||SyncFET™|
|DenseTrench™|GTO™|QFET™||TinyLogic™|
|DOME™|HiSeC™|QS™||UHC™|
|EcoSPARK™|ISOPLANAR™|QT Optoelectronics™||UltraFET<br>|
|E2CMOSTM|LittleFET™|Quiet Series™||VCX™|
|EnSignaTM|MicroFET™|SILENT SWITCHER|||
|FACT™|MICROWIRE™|SMART START™|||
|FACT Quiet Series™|OPTOLOGIC™|Stealth™|||



## **DISCLAIMER** 

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. 

## **LIFE SUPPORT POLICY** 

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 

1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant into support device or system whose failure to perform can the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life failure to perform when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. 

## **PRODUCT STATUS DEFINITIONS** 

## **Definition of Terms** 

|**Definition of Terms**|||
|---|---|---|
|**Datasheet Identification**|**Product Status**|**Definition**|
|Advance Information|Formative or<br>In Design|This datasheet contains the design specifications for<br>product development. Specifications may change in<br>any manner without notice.|
|Preliminary|First Production|This datasheet contains preliminary data, and<br>supplementary data will be published at a later date.<br>Fairchild Semiconductor reserves the right to make<br>changes at any time without notice in order to improve<br>design.|
|No Identification Needed|Full Production|This datasheet contains final specifications. Fairchild<br>Semiconductor reserves the right to make changes at<br>any time without notice in order to improve design.|
|Obsolete|Not In Production|This datasheet contains specifications on a product<br>that has been discontinued by Fairchild semiconductor.<br>The datasheet is printed for reference information only.|



Rev. H2 

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