FDC6305N

**DATA SHEET www.onsemi.com** 

## MOSFET – Dual, N-Channel, POWERTRENCH[�] 

## 2.5 V Specified FDC6305N 

## **General Description** 

These N−Channel low threshold 2.5 V specified MOSFETs are produced using **onsemi** ’s advanced POWERTRENCH process that has been especially tailored to minimize on−state resistance and yet maintain low gate charge for superior switching performance. 

## **Features** 

|**VDSS**|**RDS(ON) MAX**|**ID MAX**|
|---|---|---|
|20 V|0.08�@ 4.5 V|2.7 A|
||0.12�@ 2.5 V||



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D2<br>S1<br>D1<br>G2<br>G1 [S2]<br>TSOT23 6−Lead<br>SUPERSOT−6<br>CASE 419BL<br>**----- End of picture text -----**<br>


- N−Channel 2.7 A, 20 V 

   - RDS(ON) = 0.08 � @ VGS = 4.5 V RDS(ON) = 0.12 � @ VGS = 2.5 V 

- Fast Switching Speed 

- Low Gate Charge (3.5 nC Typical) 

- High Performance Trench Technology for Extremely Low RDS(ON) 

- SUPERSOT�−6 Package: Small Footprint (72% Smaller than Standard SO−8); Low Profile (1 mm Thick) 

- This is a Pb−Free Device 

## **Applications** 

## **MARKING DIAGRAM** 

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305 M �<br>�<br>1<br>305 = Specific Device Code<br>M = Assembly Operation Month<br>� = Pb−Free Package<br>**----- End of picture text -----**<br>


(Note: Microdot may be in either location) 

- DC/DC Converter 

- Load Switch 

- Motor Driving 

## **PINOUT** 

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## **ORDERING INFORMATION** 

|**Device**|**Packag**|**e**<br>**Shipping**†|
|---|---|---|
|FDC6305N|TSOT−2<br>(Pb−fre|3−6<br>e)<br>3000 /<br>Tape & Reel|



- †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. 

Publication Order Number: **FDC6305N/D** 

**1** 

© Semiconductor Components Industries, LLC, 1999 **February, 2022 − Rev. 3** 

**FDC6305N** 

**ABSOLUTE MAXIMUM RATINGS** (TA = 25 ° C unless otherwise noted) 

|**ABSOLU**|**TE MAXIMUM RATINGS** (TA= 25°C unless otherwise n|**TE MAXIMUM RATINGS** (TA= 25°C unless otherwise n|oted)||
|---|---|---|---|---|
|**Symbol**|**Parameter**||**Ratings**|**Unit**|
|VDSS|Drain−Source Voltage||20|V|
|VGSS|Gate−Source Voltage||±8|V|
|ID|Drain Current|− Continuous (Note 1a)|2.7|A|
|||− Pulsed|8|A|
|PD|Power Dissipation|(Note 1a)|0.96|W|
|||(Note 1b)|0.9|W|
|||(Note 1c)|0.7|W|
|TJ, TSTG|Operating and Storage Junction Temperature Range||−55 to +150|°C|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

## **THERMAL CHARACTERISTICS** 

|**Symbol**|**Parameter**|**Ratings**|**Unit**|
|---|---|---|---|
|R�JA|Thermal Resistance, Junction−to−Ambient (Note 1a)|130|°C/W|
|R�JC|Thermal Resistance, Junction−to−Case (Note 1)|60|°C/W|



**ELECTRICAL CHARACTERISTICS** (TA = 25 ° C unless otherwise noted) 

|**ELECTRI**|**CAL CHARACTERISTICS** (TA= 25°C un|less otherwise noted)|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|**OFF CHARACTERISTICS**|||||||
|BVDSS|Drain–Source Breakdown Voltage|VGS= 0 V, ID= 250�A|20|−|−|V|
|�BVDSS<br>�TJ|Breakdown Voltage Temperature<br>Coefficient|ID= 250�A,Referenced to 25°C|−|14|−|mV/°C|
|IDSS|Zero Gate Voltage Drain Current|VDS= 16 V, VGS= 0 V|−|−|1|�A|
|IGSSF|Gate–Body Leakage, Forward|VGS= 8 V, VDS= 0 V|−|−|100|nA|
|IGSSR|Gate–Body Leakage, Reverse|VGS= –8 V, VDS= 0 V|−|−|–100|nA|
|**ON CHARACTERISTICS**(Note 2)|||||||
|VGS(th)|Gate Threshold Voltage|VDS= VGS, ID= 250�A|0.4|0.9|1.5|V|
|�VGS(th)<br>�TJ|Gate Threshold Voltage<br>Temperature Coefficient|ID= 250�A, Referenced to 25°C|−|–2.7|−|mV/°C|
|RDS(on)|Static Drain–Source<br>On–Resistance|VGS= 4.5 V, ID= 2.7 A<br>VGS= 4.5 V, ID= 2.7 A, TJ= 125°C<br>VGS= 2.5 V, ID= 2.2 A|−<br>−<br>−|0.060<br>0.095<br>0.085|0.080<br>0.128<br>0.120|�|
|ID(on)|On−State Drain Current|VGS= 4.5 V, VDS= 5 V|6|−|−|A|
|gFS|Forward Transconductance|VDS= 5 V, ID= 2.7 A|−|8|−|S|
|**DYNAMIC CHARACTERISTICS**|||||||
|Ciss|Input Capacitance|VDS= 10 V, VGS= 0 V, f = 1.0 MHz|−|310|−|pF|
|Coss|Output Capacitance||−|80|−|pF|
|Crss|Reverse Transfer Capacitance||−|40|−|pF|
|**SWITCHING CHARACTERISTICS**(Note 2)|||||||
|td(on)|Turn–On Delay Time|VDD= 10 V, ID= 1 A,<br>VGS= 4.5 V, RGEN= 6�|−|5|15|ns|
|tr|Turn–On Rise Time||−|8.5|17|ns|
|td(off)|Turn–Off Delay Time||−|11|20|ns|
|tf|Turn–Off Fall Time||−|3|10|ns|
|Qg|Total Gate Charge|VDS= 10 V, ID= 2.7 A, VGS= 4.5 V|−|3.5|5|nC|
|Qgs|Gate–Source Charge||−|0.55|−|nC|
|Qgd|Gate–Drain Charge||−|0.95|−|nC|



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**2** 

**FDC6305N** 

## **ELECTRICAL CHARACTERISTICS** (TA = 25 ° C unless otherwise noted) (continued) 

|**ELECT**|**RICAL CHARACTERISTICS** (TA= 25°C unle|ss otherwise noted) (continued)|||||
|---|---|---|---|---|---|---|
|**Symbo**|**l**<br>**Parameter**|**Test Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|**DRAIN−SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS**|||||||
|IS|Maximum Continuous Drain–Source Diode Forward Current||−|−|0.8|A|
|VSD|Drain–Source Diode Forward Voltage<br>V|GS= 0 V, IS= 0.8 A (Note 2)|−|0.77|1.2|V|



Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 

1. R � JA is the sum of the junction−to−case and case−to−ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R � JC is guaranteed by design while R � CA is determined by the user’s board design. Both devices are assumed to be operating and sharing the dissipated heat energy equally. 

a. 130 ° C/W when mounted b. 140 ° C/W when mounted c. 180 ° C/W on a minimum on a 0.125 in[2] pad of 2 oz. on a 0.005 in[2] pad of 2 oz. mounting pad. copper. copper. 

Scale 1:1 on letter size paper 

2. Pulse Test: Pulse Width < 300 � s, Duty cycle < 2.0 %. 

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**3** 

**FDC6305N** 

## **TYPICAL CHARACTERISTICS** 

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10<br>VGS = 4.5 V<br>3.5 V 3.0 V<br>8 2.5 V<br>6<br>2.0 V<br>4<br>2<br>1.5 V<br>0<br>0 0.5 1 1.5 2 2.5 3<br>VDS, Drain to Source Voltage (V)<br>, Drain−Source Current (A)<br>ID<br>**----- End of picture text -----**<br>


**Figure 1. On−Region Characteristics** 

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1.6<br>ID = 2.7 A<br>VGS = 4.5 V<br>1.4<br>1.2<br>1<br>0.8<br>0.6<br>−50 −25 0 25 50 75 100 125 150<br>TJ, Junction Temperature ( ° C)<br>, Normalized<br>DS(ON)<br>R<br>Drain−Source On−Resistance<br>**----- End of picture text -----**<br>


**Figure 3. On−Resistance Variation with Temperature** 

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10<br>VDS = 5 V TA = −55 ° C 25 ° C<br>8<br>125 ° C<br>6<br>4<br>2<br>0<br>0 1 2 3 4<br>VGS, Gate to Source Voltage (V)<br>, Drain Current (A)<br>ID<br>**----- End of picture text -----**<br>


**Figure 5. Transfer Characteristics** 

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1.6<br>VGS = 2.5 V<br>1.4<br>3.0 V<br>1.2<br>3.5 V<br>4.0 V<br>4.5 V<br>1<br>0.8<br>0 2 4 6 8 10<br>ID, Drain Current (A)<br>Figure 2. On−Resistance Variation with<br>Drain Current and Gate Voltage<br>0.24<br>ID = 1.4 A<br>0.2<br>0.16<br>0.12 TA = 125 ° C<br>0.08<br>TA = 25 ° C<br>0.04<br>0<br>1 2 3 4 5<br>VGS, Gate to Source Voltage (V)<br>Figure 4. On−Resistance Variation with<br>Gate−to−Source Voltage<br>10<br>VGS = 0 V<br>1<br>TA = 125 ° C<br>0.1<br>25 ° C<br>0.01<br>−55 ° C<br>0.001<br>0.0001<br>0 0.2 0.4 0.6 0.8 1 1.2 1.4<br>VSD, Body Diode Forward Voltage (V)<br>, Normalized<br>DS(ON)<br>R<br>Drain−Source On−Resistance<br>) �<br>, On−Resistance (<br>DS(ON)<br>R<br>, Reverse Drain Current (A)<br>IS<br>**----- End of picture text -----**<br>


**Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature** 

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**4** 

**FDC6305N** 

## **TYPICAL CHARACTERISTICS** (continued) 

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5<br>ID = 2.7 A VDS = 5 V<br>4<br>10 V<br>3<br>15 V<br>2<br>1<br>0<br>0 0.5 1 1.5 2 2.5 3 3.5 4<br>Qg, Gate Charge (nC)<br>Figure 7. Gate Charge Characteristics<br>10<br>RDS(ON) LIMIT 100  � s<br>1 ms<br>1<br>10 ms<br>100 ms<br>0.1 VGS = 4.5 V 1 s<br>SINGLE PULSE DC<br>R � JA  = 180 ° C/W<br>TA = 25 ° C<br>0.01<br>0.1 1 10 100<br>VDS, Drain−Source Voltage (V)<br>, Gate−Source Voltage (V)<br>GS<br>V<br>, Drain Current (A)<br>ID<br>**----- End of picture text -----**<br>


**Figure 9. Maximum Safe Operating Area** 

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500<br>f = 1 MHz<br>VGS = 0 V<br>400<br>CISS<br>300<br>200<br>100<br>COSS<br>CRSS<br>0<br>0 4 8 12 16 20<br>VDS, Drain to Source Voltage (V)<br>Figure 8. Capacitance Characteristics<br>5<br>SINGLE PULSE<br>R � JA = 180 ° C/W<br>4 TA = 25 ° C<br>3<br>2<br>1<br>0<br>0.01 0.1 1 10 100 1000<br>Single Pulse Time (s)<br>Capacitance (pF)<br>Power (W)<br>**----- End of picture text -----**<br>


**Figure 10. Single Pulse Maximum Power Dissipation** 

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1<br>D = 0.5<br>R � JA(t) = r(t)  *  R � JA<br>0.2 R � JA  = 180 ° C/W<br>0.1<br>0.1 P(pk)<br>0.05<br>t1<br>0.02 t2<br>0.01<br>SINGLE PULSE TJ − TA = P * R � JA(t)<br>Duty Cycle, D = t1 / t2<br>0.01<br>0.0001 0.001 0.01 0.1 1 10 0 300<br>t1, Time (s)<br>Thermal Resistance<br>r(t), Normalized Effective Transient<br>**----- End of picture text -----**<br>


**Figure 11. Transient Thermal Response Curve** 

Thermal characterization performed using the conditions described in Note 1c. Transient themal response will change depending on the circuit board design. 

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**5** 

**FDC6305N** 

POWERTRENCH is registered trademark of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. 

SUPERSOT is a trademark of Semiconductor Components Industries, LLC dba “ **onsemi** ” or its affiliates and/or subsidiaries in the United States and/or other countries. 

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**6** 

## MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

## **TSOT23 6−Lead** CASE 419BL ISSUE A 

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1<br>**----- End of picture text -----**<br>


## DATE 31 AUG 2020 

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SCALE 2:1<br>**----- End of picture text -----**<br>


## **DOCUMENT NUMBER: 98AON83292G** 

## **TSOT23 6−Lead** 

## **DESCRIPTION:** 

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GENERIC<br>LAND PATTERN MARKING DIAGRAM*<br>RECOMMENDATION r ] ]<br>*FOR ADDITIONAL INFORMATION ON OUR<br>PB - FREE STRATEGY AND SOLDERING DETAILS, XXX M<br>PLEASE DOWNLOAD THE ON SEMICONDUCTOR<br>SOLDERING AND MOUNTING TECHNIQUES<br>REFERENCE MANUAL, SOLDERRMID. 1 | | | | i<br>XXX = Specific Device Code<br>M = Date Code<br>: = Pb−Free Package<br>(Note: Microdot may be in either location)<br>*This information is generic. Please refer to<br>device data sheet for actual part marking.<br>Pb−Free indicator, “G” or microdot “ ”, a<br>may or may not be present. Some products<br>may not follow the Generic Marking.<br>Electronic versions are uncontrolled except when accessed directly from the Document Repository.<br>Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red.<br>**----- End of picture text -----**<br>


## **PAGE 1 OF 1** 

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