FAM65CR51DZ2

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## Boost Converter Stage in APM16 Series for Multiphase and Semi-Bridgeless PFC FAM65CR51DZ1, FAM65CR51DZ2 

## **Features** 

- Integrated SIP or DIP Boost Converter Stage Power Module for On−board Charger (OBC) in EV or PHEV 

**APMCD−A16 12 LEAD CASE MODGG** 

- 5 kV/1 sec Electrically Isolated Substrate for Easy Assembly 

- Creepage and Clearance per IEC60664−1, IEC 60950−1 

- Compact Design for Low Total Module Resistance 

- Module Serialization for Full Traceability 

- Lead Free, RoHS and UL94V−0 Compliant 

- Automotive Qualified per AEC Q101 and AQG324 Guidelines 

## **Applications** 

**APMCD−B16 12 LEAD CASE MODGK** 

- PFC Stage of an On−board Charger in PHEV or EV 

## **Benefits** 

- Enable Design of Small, Efficient and Reliable System for Reduced Vehicle Fuel Consumption and CO2 Emission 

- Simplified Assembly, Optimized Layout, High Level of Integration, and Improved Thermal Performance 

## **MARKING DIAGRAM** 

**==> picture [60 x 27] intentionally omitted <==**

**----- Start of picture text -----**<br>
XXXXXXXXXXX<br>ZZZ ATYWW<br>NNNNNNN<br>**----- End of picture text -----**<br>


XXXX = Specific Device Code ZZZ = Lot ID AT = Assembly & Test Location Y = Year W = Work Week NNN = Serial Number 

## **ORDERING INFORMATION** 

See detailed ordering, marking and shipping information on page 2 of this data sheet. 

Publication Order Number: **FAM65CR51DZ1/D** 

**1** 

© Semiconductor Components Industries, LLC, 2018 **October, 2024 − Rev. 4** 

**FAM65CR51DZ1, FAM65CR51DZ2** 

## **ORDERING INFORMATION** 

|**Part Number**|**Package**|**Lead Forming**|**DBC Material**|**Pb−Free and**<br>**RoHS Compliant**|**Operating**<br>**Temperature (TA)**|**Packing**<br>**Method**|
|---|---|---|---|---|---|---|
|FAM65CR51DZ1|APM16−CDA|Y−Shape|Al2O3|Yes|−40°C ~ 125°C|Tube|
|FAM65CR51DZ2|APM16−CDB|L−Shape|Al2O3|Yes|−40°C ~ 125°C|Tube|



## **Pin Configuration and Description** 

**Figure 1. Pin Configuration** 

**Table 1. PIN DESCRIPTION** 

|**Pin Number**|**Pin Name**|**Pin Description**|
|---|---|---|
|1, 2|AC1|Phase 1 Leg of the PFC Bridge|
|3|NC|Not Connected|
|4|NC|Not Connected|
|5, 6|B+|Positive Battery Terminal|
|7, 8|Q1 Source|Source Terminal of Q1|
|9|Q1 Gate|Gate Terminal of Q1|
|10|Q2 Gate|Gate Terminal of Q2|
|11, 12|Q2 Source|Source Terminal of Q2|
|13|NC|Not Connected|
|14|NC|Not Connected|
|15, 16|AC2|Phase 2 Leg of the PFC Bridge|



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## **INTERNAL EQUIVALENT CIRCUIT** 

**Figure 2. Internal Block Diagram** 

**Table 2. ABSOLUTE MAXIMUM RATINGS OF MOSFET** (TJ = 25 ° C, Unless Otherwise Specified) 

|**Table 2. ABSOLUTE MAXIMUM RATINGS OF MOSFET**|**Table 2. ABSOLUTE MAXIMUM RATINGS OF MOSFET**(TJ = 25J = 25= 25°C, Unless Otherwise Specified)|C, Unless Otherwise Specified)||
|---|---|---|---|
|**Symbol**|**Parameter**|**Max**|**Unit**|
|VDS(Q1~Q2)|Drain−to−Source Voltage|650|V|
|VGS(Q1~Q2)|Gate−to−Source Voltage|±20|V|
|ID(Q1~Q2)|Drain Current Continuous (TC= 25°C, VGS= 10 V) (Note 1)|33|A|
||Drain Current Continuous (TC= 100°C, VGS= 10 V) (Note 1)|23|A|
|EAS(Q1~Q2)|Single Pulse Avalanche Energy (Note 2)|623|mJ|
|PD|Power Dissipation (Note 1)|160|W|
|TJ|Maximum Junction Temperature|−55 to +150|°C|
|TC|Maximum Case Temperature|−40 to +125|°C|
|TSTG|Storage Temperature|−40 to +125|°C|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

1. Maximum continuous current and power, without switching losses, to reach TJ = 150 ° C respectively at TC = 25 ° C and TC = 100 ° C; defined by design based on MOSFET RDS(ON) and R 8 JC and not subject to production test 

2. Starting TJ = 25 ° C, IAS = 6.5 A, RG = 25 

## **DBC Substrate** 

0.63 mm Al2O3 alumina with 0.3 mm copper on both sides. DBC substrate is NOT nickel plated. 

## **Lead Frame** 

OFC copper alloy, 0.50 mm thick. Plated with 8 um to 25.4 um thick Matte Tin 

## **Flammability Information** 

All materials present in the power module meet UL flammability rating class 94V−0. 

## **Compliance to RoHS Directives** 

The power module is 100% lead free and RoHS compliant 2000/53/C directive. 

## **Solder** 

Solder used is a lead free SnAgCu alloy. 

Solder presents high risk to melt at temperature beyond 210°C. Base of the leads, at the interface with the package body, should not be exposed to more than 200°C during mounting on the PCB or during welding to prevent the re−melting of the solder joints. 

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**Table 3. ELECTRICAL SPECIFICATIONS OF MOSFET** (TJ = 25 ° C, Unless Otherwise Specified) 

|**Symbol**<br>**Parameter**<br>**Conditions**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**<br>~~a GG~~|
|---|
|BVDSS<br>Drain−to−Source Breakdown Voltage<br>ID= 1 mA, VGS= 0 V<br>650<br>−<br>−<br>V<br>~~a GG~~|
|VGS(th)<br>Gate−to−Source Threshold Voltage<br>VGS= VDS, ID= 3.3 mA<br>3.0<br>−<br>5.0<br>V<br>RDS(ON)Q1<br>Q1 Low Side MOSFET<br>VGS= 10 V, ID= 20 A<br>−<br>44<br>51<br>m<br>RDS(ON)Q2<br>Q2 Low Side MOSFET<br>−<br>44<br>51<br>m<br>RDS(ON)Q1<br>Q1 Low Side MOSFET<br>VGS= 10 V, ID= 20 A, TJ= 125°C (Note 3)<br>−<br>79<br>−<br>m<br>RDS(ON)Q2<br>Q2 Low Side MOSFET<br>−<br>79<br>−<br>m<br>gFS<br>Forward Transconductance<br>VDS= 20 V, ID= 20 A (Note 3)<br>−<br>30<br>−<br>S<br>~~a Ge~~<br>~~SS~~<br>~~rs~~<br>~~ee~~<br>~~a~~<br>~~e~~~~**se**t~~<br>~~eee~~<br>~~r~~<br>~~ee~~<br>~~ee~~<br>~~a~~<br>~~G~~|
|IGSS<br>Gate−to−Source Leakage Current<br>VGS=±20 V, VDS= 0 V<br>−100<br>−<br>+100<br>nA<br>IDSS<br>Drain−to−Source Leakage Current<br>VDS= 650 V, VGS= 0 V<br>−<br>−<br>10<br>A<br>**DYNAMIC CHARACTERISTICS**(Note 3)<br>~~aGG~~<br>~~a~~<br>~~GG~~<br>~~OO~~|
|Ciss<br>Input Capacitance<br>VDS= 400 V<br>VGS= 0 V<br>f = 1 MHz<br>−<br>4864<br>−<br>pF<br>Coss<br>Output Capacitance<br>−<br>109<br>−<br>pF<br>Crss<br>Reverse Transfer Capacitance<br>−<br>16<br>−<br>pF<br>Coss(eff)<br>Effective Output Capacitance<br>VDS= 0 to 520 V<br>−<br>652<br>−<br>pF<br>~~rs~~<br>~~ee~~<br>~~eeee~~<br>~~rs~~<br>~~ee~~<br>~~ee~~<br>~~ee ee~~<br>~~rs~~<br>~~ee~~<br>~~a a~~|
|VGS= 0 V|
|Rg<br>Gate Resistance<br>f = 1 MHz<br>−<br>2<br>−<br>Qg(tot)<br>Total Gate Charge<br>VDS= 380 V<br>ID= 20 A<br>VGS= 0 to 10 V<br>−<br>123<br>−<br>nC<br>Qgs<br>Gate−to−Source Gate Charge<br>−<br>37.5<br>−<br>nC<br>Qgd<br>Gate−to−Drain “Miller” Charge<br>−<br>49<br>−<br>nC<br>**SWITCHING CHARACTERISTICS**(Note 3)<br>~~a~~<br>~~rs~~<br>~~ee~~<br>~~a ee~~<br>~~rs~~<br>~~ee~~<br>~~a ee~~<br>~~ee~~<br>~~ee~~<br>~~ee ee ee~~|
|ton<br>Turn−on Time<br>VDS= 400 V<br>−<br>87<br>−<br>ns|
|ID= 20 A<br>VGS= 10 V<br>td(on)<br>Turn−on Delay Time<br>−<br>47<br>−<br>ns|
|RG= 4.7 Ohm<br>tr<br>Turn−on Rise Time<br>−<br>43<br>−<br>ns|
|toff<br>Turn−off Time<br>−<br>148<br>−<br>ns|
|td(off)<br>Turn−off Delay Time<br>−<br>118<br>−<br>ns|
|tf<br>Turn−off Fall Time<br>−<br>29<br>−<br>ns|
|**BODY DIODE CHARACTERISTICS**|
|VSD<br>Source−to−Drain Diode Voltage<br>ISD= 20 A, VGS= 0 V<br>−<br>0.95<br>−<br>V<br>~~a GG~~|
|Trr<br>Reverse Recovery Time<br>VDS= 520 V, ID= 20 A,<br>dI/dt= 100 A/ s (Note 3)<br>−<br>133<br>−<br>ns<br>Qrr<br>Reverse Recovery Charge<br>−<br>669<br>−<br>nC<br>Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product<br>~~$s~~<br>~~f+} + —~~<br>~~ee~~<br>~~ee~~<br>~~ee ee ee~~|
|performance may not be indicated by the Electrical Characteristics if operated under different conditions.|
|3. Defined by design, not subject to production test|



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**Table 4. ABSOLUTE MAXIMUM RATINGS OF THE BOOST DIODE** (TJ = 25 ° C, Unless Otherwise Specified) 

|**Table 4. ABSOLUTE MAXIMUM RATINGS OF THE BOOST DIODE**|**Table 4. ABSOLUTE MAXIMUM RATINGS OF THE BOOST DIODE**(TJ = 25J = 25= 25°C, Unless Otherwise Specified)|C, Unless Otherwise Specified)||
|---|---|---|---|
|**Symbol**|**Parameter**|**Rating**|**Unit**|
|VRRM|Peak Repetitive Reverse Voltage (Note 4)|600|V|
|VRWM|Working Peak Reverse Voltage (Note 4)|600|V|
|VR|DC Blocking Voltage|600|V|
|IF(AV)|Average Rectified Forward Current TC= 25°C|15|A|
|IFSM|Non−Repetitive Peak Surge Current (Half Wave 1 Phase 60 Hz)|45|A|
|TJ|Maximum Junction Temperature|−55 to +175|°C|
|TC|Maximum Case Temperature|−40 to +125|°C|
|TSTG|Storage Temperature|−40 to +125|°C|
|EAVL|Avalanche Energy (2.85 A, 1 mH)|4|mJ|



4. VRRM  and IF(AV) value referenced to TO220−2L Auto Qualified Package Device ISL9R1560P_F085 

**Table 5. ELECTRICAL SPECIFICATIONS OF THE BOOST DIODE** (TJ = 25 ° C, Unless Otherwise Specified) 

|**Table 5. ELECTRICAL SPECIFICATIONS OF THE BOOST DIODE**|**Table 5. ELECTRICAL SPECIFICATIONS OF THE BOOST DIODE**(TJ = 25J = 25= 25°C, Unless Otherwise Specified)|**Table 5. ELECTRICAL SPECIFICATIONS OF THE BOOST DIODE**(TJ = 25J = 25= 25°C, Unless Otherwise Specified)|C, Unless Otherwise Specified)|C, Unless Otherwise Specified)|C, Unless Otherwise Specified)|C, Unless Otherwise Specified)|||
|---|---|---|---|---|---|---|---|---|
|**Symbol**<br>**Parameter**|**Test Conditions**|||**Min**|**Typ**<br>**Max**|||**Unit**|
|IR<br>Instantaneous Reverse Current|VR= 600 V|TC= 25°C||−|−<br>100|||A|
|||TC= 125°C||−|−<br>1|||mA|
|VFM<br>Instantaneous Forward Voltage (Note 5)|IF=15 A|TC= 25°C||−|1.65<br>2.2|||V|
|||TC= 125°C||−|1.24<br>1.7|||V|
|trr<br>Reverse Recovery Time|IF= 15 A|TC= 25°C||−|29<br>−|||ns|
|ta<br>Time to reach peak reverse current<br>tb<br>Time from peak IRRMto projected zero cross-<br>ing of IRRMbased on a straight line from peak<br>IRRMthrough 25% of IRRM<br>Qrr<br>Reverse Recovered Charge<br>5. Test pulse width = 300 s, Duty Cycle = 2%<br>~~eee~~|dIF/dt = 200 A/ s<br>VR=390 V<br>(Note 3)|TC= 25°C<br>−<br>16<br>−<br>ns<br>TC= 25°C<br>−<br>13<br>−<br>n<br>TC= 25°C<br>−<br>43<br>−<br>nC<br>~~eeeeee~~|||||||
|**Table 6. THERMAL RESISTANCE**|||||||||
|**Parameters**||**Min**||**Typ**||**Max**||**Unit**|
|RθJC(per MOSFET chip)<br>Q1,Q2 Thermal Resistance Junction−to−Case (Note 6)<br>−||||0.66||0.92||°C/W|
|RθJS(per MOSFET chip)<br>Q1,Q2 Thermal Resistance Junction−to−Sink (Note 7)||−||1.20||−||°C/W|
|RθJC(per DIODE chip)<br>D1,D2 Thermal Resistance Junction−to−Case (Note 6)||−||1.98||2.72||°C/W|
|RθJS(per DIODE chip)<br>D1,D2 Thermal Resistance Junction−to−Sink (Note 7)||−||2.97||−||°C/W|



6. Test method compliant with MIL STD 883−1012.1, from case temperature under the chip to case temperature measured below the package at the chip center, Cosmetic oxidation and discoloration on the DBC surface allowed 

7. Defined by thermal simulation assuming the module is mounted on a 5 mm Al−360 die casting material with 30 um of 1.8 W/mK thermal interface material 

**Table 7. ISOLATION** (Isolation resistance at tested voltage between the base plate and to control pins or power terminals.) 

|**Table 7. ISOLATION**(Isolation resistance at tested voltage between the base plate and to control pins or power terminals.)|(Isolation resistance at tested voltage between the base plate and to control pins or power terminals.)|(Isolation resistance at tested voltage between the base plate and to control pins or power terminals.)|(Isolation resistance at tested voltage between the base plate and to control pins or power terminals.)|
|---|---|---|---|
|**Test**|**Test Conditions**|**Isolation Resistance**|**Unit**|
|Leakage @ Isolation Voltage (Hi−Pot)|VAC= 5 kV, 60 Hz|100M <||



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## **PARAMETER DEFINITIONS** 

Reference to Table 3: Parameter of MOSFET Electrical Specifications 

BVDSS Q1, Q2 MOSFET Drain−to−Source Breakdown Voltage The maximum drain−to−source voltage the MOSFET can endure without the avalanche breakdown of the body− drain P−N junction in off state. The measurement conditions are to be found in Table 3. The typ. Temperature behavior is described in Figure 14 ~~pp~~ VGS(th) Q1, Q2 MOSFET Gate to Source Threshold Voltage The gate−to−source voltage measurement is triggered by a threshold ID current given in conditions at Table 4. The typ. Temperature behavior can be found in Figure 11 ~~ee~~ RDS(ON) Q1, Q2 MOSFET On Resistance RDS(on) is the total resistance between the source and the drain during the on state. The measurement conditions are to be found in Table 3 . The typ behavior can be found in Figure 12 and Figure 13 as well as Figure 18 ~~ee~~ gFS Q1, Q2 MOSFET Forward Transconductance Transconductance is the gain in the MOSFET, expressed in the Equation below. ~~a~~ It describes the change in drain current by the change in the gate−source bias voltage: gfs = [ IDS / VGS ]VDS IGSS Q1, Q2 MOSFET Gate−to−Source Leakage Current The current flowing from Gate to Source at the maximum allowed VGS The measurement conditions are described in the Table 3 . IDSS Q1, Q2 MOSFET Drain−to−Source Leakage Current ~~ee~~ - Drain – Source current is measured in off state while providing the maximum allowed drain−to source voltage and the gate is shorted to the source. IDSS has a positive temperature coefficient . ~~pp~~ 

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**Figure 3. Timing Measurement Variable Definition** 

**Table 8. PARAMETER OF SWITCHING CHARACTERISTICS** 

|Turn−On Delay (td(on))|This is the time needed to charge the input capacitance, Ciss, before the load current IDstarts flowing.<br>The measurement conditions are described in the Table 3.<br>For signal definition please check Figure 3 above.|
|---|---|
|Rise Time (tr)|The rise time is the time to discharge output capacitance, Coss.<br>After that time the MOSFET conducts the given load current ID.<br>The measurement conditions are described in the Table 3.<br>For signal definition please check Figure 3 above.|
|Turn−On Time (ton)|Is the sum of turn−on−delay and rise time|
|Turn−Off Delay (td(off))|td(off) is the time to discharge Ciss after the MOSFET is turned off.<br>During this time the load current IDis still flowing<br>The measurement conditions are described in the Table 3.<br>For signal definition please check Figure 3 above.|
|Fall Time (tf)|The fall time, tf, is the time to charge the output capacitance, Coss.<br>During this time the load current drops down and the voltage VDSrises accordingly.<br>The measurement conditions are described in the Table 3.<br>For signal definition please check Figure 3 above.|
|Turn−Off Time (toff)|Is the sum of turn−off−delay and fall time|



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**Figure 4. Dynamic Parameters of Silicon Diode (not in scale)** 

Reference to Table 5: Parameter of Diode Electrical Specifications 

|Instantaneous Reverse Current<br>(IR)|Current flowing in reverse after the reverse recovery time trr..<br>IRis shown in Figure 4 above<br>The behaviour over voltage can be seen in Figure 23.|
|---|---|
|Instantaneous Forward Voltage<br>VFM|Voltage drop over the diode in a dynamic condition given in Note 5.<br>The voltage is measured after the given test pulse width.<br>To avoid self heating effects a small duty cycle is used<br>The behaviour over voltage can be seen in Figure 22.|
|Reverse Recovery Time<br>trr|During this transition time,from conduction to blocking, the current is flowing in reverse direction<br>and diode generates switching losses. The time is characterized on the scope by using the ta and<br>tb approximation method<br>ta + tb = trr parameter result in Table 3<br>The parameter is dependent on temperature and initial dI/dt<br>Figure 25 shows the dependency on dI/dt|
|Time to reach peak reverse current<br>ta|ta is the transition time from the moment the current starts to flow in reverse direction until the<br>diode voltage drops (also the reverse current peak)|
|Time from peak IRRM to zero crossing<br>tb|tb is defined by using a linear approximation from the peak IRM to a projected zero crossing of IR<br>by crossing IR at 25% of IRRM|
|Reverse Recovered Charge<br>Qrr|The reverse recovery charge is defined as Qrr=∫trrIr(t) dt<br>This parameter is highly depend on temperature and dI/dt<br>See Figure 27.|



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## **TYPICAL CHARACTERISTICS − MOSFETs** 

**==> picture [491 x 591] intentionally omitted <==**

**----- Start of picture text -----**<br>
1.2 40<br>aee 35 eee VGS = 10 V<br>1.0<br>30<br>0.8 CSE SR E<br>25<br>0.6 20<br>CCAR 15 EERSEE<br>0.4<br>10 R JC = 0.92 ° C/W<br>0.2 R JC = 0.92 ° C/W<br>5<br>0 COPSIN 0 EL SE<br>0 25 50 75 100 125 150 25 50 75 100 125 150 175<br>TC, CASE TEMPERATURE ( ° C) TC, CASE TEMPERATURE ( ° C)<br>Figure 5. Normalized Power Dissipation vs. Figure 6. Maximum Continuous ID vs. Case<br>Case Temperature<br>60 V DS  = 20 V 100 VGS = 0 V<br>50<br>10<br>40<br>TJ = 25 ° C<br>30 i, A 1 TJ = 150 ° C TJ = 25 ° C<br>20<br>TJ = 150 ° C 0.1<br>6/7. ee<br>10 e e ee<br>TJ = −55 ° C<br>0 a es |) 0.01 ES<br>3 4 5 6 7 8 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4<br>VGS, GATE−TO−SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)<br>Figure 7. Transfer Characteristics Figure 8. Forward Diode<br>100<br>80<br>VGS = 15 V 10 V 90<br>PT AA P| tT | | te te et<br>70<br>8.0 V 80 VGS = 15 V<br>60 CAA 70 Ee<br>10 V<br>50 || 60 ee<br>7.0 V 8.0 V<br>40 a If]4eeepee 50 eeePTeee<br>7.0 V<br>40<br>30<br>6.0 V<br>S)/46>=.88see 30 Loeee 6.0 V<br>20 pate TF<br>5.5 V 20 5.5 V<br>10 4>_ eee 5.0 V 10 ae ee 5.0 V<br>0 Za eee 0 AZASSSTLE$ E LE$LE<br>0 1 2 3 4 5 6 7 8 9 10 0 10 20 30 40 50 60 70 80 90 100<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V) VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>, DRAIN CURRENT (A)<br>ID<br>POWER DISSIPATION MULTIPLIER<br>, DRAIN CURRENT (A)<br>ID<br>, REVERSE DRAIN CURRENT (A)<br>IS<br>, DRAIN CURRENT (A) , DRAIN CURRENT (A)<br>ID ID<br>**----- End of picture text -----**<br>


**Figure 9. On Region Characteristics (25 C)** 

**Figure 10. On Region Characteristics (150 C)** 

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## **TYPICAL CHARACTERISTICS − MOSFETs** 

**==> picture [491 x 591] intentionally omitted <==**

**----- Start of picture text -----**<br>
200 2.5<br>ID = 20 A ID = 20 A<br>VGS = 10 V<br>2.0 ot<br>150<br>1.5<br>100 T J  = 150 ° C<br>1.0<br>50 or T J  = 25 ° C - Lier<br>KS ee ee<br>0.5<br>0 ee 0<br>eenee<br>5.5 6.5 7.5 8.5 9.5 −75 −50 −25 0 25 50 75 100 125 150 175<br>VGS, GATE−TO−SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE ( ° C)<br>Figure 11. On−Resistance vs. Gate−to−Source Figure 12. RDS(norm) vs. Junction Temperature<br>Voltage<br>1.2 1.2<br>ID = 3.3 mA ID = 10 A<br>1.1<br>1.0<br>a) GE<br>1.0<br>TPS poet<br>0.8<br>PN 0.9 Lhe EL<br>0.6 0.8<br>ALLELLED|) $= GECee ee<br>−75 −50 −25 0 25 50 75 100 125 150 175 −75 −50 −25 0 25 50 75 100 125 150 175<br>TA, AMBIENT TEMPERATURE ( ° C) TA, AMBIENT TEMPERATURE ( ° C)<br>Figure 13. Normalized Gate Threshold Voltage Figure 14. Normalized Breakdown Voltage vs.<br>vs. Temperature Temperature<br>30 100K<br>25<br>10K CISS<br>20<br>1K<br>15<br>COSS<br>100<br>10<br>CRSS<br>10 V GS = 0 V<br>5 f = 1 MHz<br>0 1<br>0 100 200 300 400 500 600 700 0.1 1 10 100 1000<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V) VDS, DRAIN−TO−SOURCE VOLTAGE (V)<br>)<br>, ON−RESISTANCE (m<br>, NORMALIZED DRAIN−TO−<br>DS(ON) SOURCE ON−RESISTANCE<br>R DS(ON)<br>R<br>BREAKDOWN VOLTAGE<br>NORMALIZED DRAIN−TO−SOURCE<br>NORMALIZED GATE THRESHOLD VOLTAGE<br>J)<br>Eoss (<br>CAPACITANCE (pF)<br>**----- End of picture text -----**<br>


**Figure 15. Eoss vs. Drain−to−Source Voltage** 

**Figure 16. Capacitance Variation** 

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## **TYPICAL CHARACTERISTICS − MOSFETs** 

**==> picture [490 x 601] intentionally omitted <==**

**----- Start of picture text -----**<br>
10 0.060<br>VDD = 130 V TC = 25 ° C<br>8<br>0.055<br>VDD = 400 V<br>fe VGS = 10 V 7 y<br>6<br>] “|<br>0.050<br>4 VGS = 20 V<br>0.045<br>Pf peel aan<br>2<br>0 0.040<br>0 40 80 120 160 0 20 40 60 80<br>QG, GATE CHARGE (nC) ID, DRAIN CURRENT (A)<br>Figure 17. Gate Charge Characteristics Figure 18. ON−Resistance Variation with Drain<br>Current and Gage Voltage<br>aee ee eee 10,000 -—-—- VGS ee = 10 V oc For temperatures above 25 ° C a<br>PH ein derate peak current as follows: i<br>100 Pt TT er NNT LT a |<br>———aSSS =6 eeas ee 100 s HH 1000 NOTHaSS eeeELTA 1 I = I25 x ,/——— 50 125 = TC ||!<br>10<br>SS TC = 25 ° C SESSa  SSE 1 ms HH SS| T ee C  = 25 ° C HII<br>1 Single Pulse R JC = 0.92 ° C/W Thermal LimitRDS(on) Limit ASSNLUT.a tdSSSe 100 ms ~ 10 ms all Innalll 100 ;riETet Limited I Tra DM ot  206 A eeeit |welllNN! NOTES:R 6 JC = 0.92 ~—~__ ° C/W  HfLTsen<br>Duty Cycle, D = t1/t2<br>0.1 Package Limit 0hy PS 1 s 10 eS Single Pulse Peak TJ = PDM x Z JC(t) + TC iii<br>re it " Hill<br>1 10 100 1000 0.000001 0.00001 0.0001 0.001 0.01 0.1 1<br>VDS, DRAIN−TO−SOURCE VOLTAGE (V) t, PULSE WIDTH (sec)<br>Figure 19. Safe Operating Area Figure 20. Peak Current Capability<br>10<br>a OOGe OO GQ GO OOO GGG OO<br>ea<br>1 8 1 A<br>Ae Duty Cycle = 0.5 ee ee ee ee ee eee ee<br>pa<br>0.2<br>ee —_———- ——<br>0.1<br>0.1 a =n a|<br>SS 0.05 aeet<br>i 0.02 ae<br>cae<br>0.01 0.01<br>soe 20 |<br>a Single Pulse OO 0 OO GQ NOG QO OD OG GY ONG OO GOGO<br>0.001 Fo EE=e TE ET TET<br>0.00001 0.0001 0.001 0.01 0.1 1 10 100<br>t, RECTANGULAR PULSE DURATION (sec)<br>co<br>)<br>RESISTANCE (<br>, DRAIN−TO−SOURCE ON<br>, GATE−TO−SOURCE VOLTAGE (V) DS(on)<br>GS R<br>V<br>, DRAIN CURRENT (A) , PEAK CURRENT (A)<br>ID IDM<br>C/W)<br>°<br>, NORMALIZED THERMAL IMPEDANCE (<br>JA<br>Z<br>**----- End of picture text -----**<br>


**Figure 21. Transient Thermal Impedance** 

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**FAM65CR51DZ1, FAM65CR51DZ2** 

## **TYPICAL CHARACTERISTICS − DIODES** 

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**----- Start of picture text -----**<br>
100 1000<br>—— TA = 100 ° C 100 _—_—_ |<br>ee ee 7 ee 10 a 125 ° C<br>T A  = 125 ° C<br>TA = 25 ° C 1<br>10 |SOVise 0.1 eea,eee<br>25 ° C<br>0.01<br>ey /A eS — — — — — —<br>0.001<br>1 [ 0.0001<br>0.2 0.7 1.2 1.7 2.2 2.7 3.2 100 200 300 400 500 600<br>VF, FORWARD VOLTAGE (V) VR, REVERSE VOLTAGE (V)<br>Figure 22. Typical Forward Voltage Drop vs. Figure 23. Typical Reverse Current vs.<br>Forward Current Reverse Voltage<br>500 TT 150 r ] | | ] f fq 4]<br>400 PAT ET<br>0)| 100 125 ° C FT<br>300 PT ft ft fy<br>TUNE ETT ah PTT yy<br>PTA ETT ETT P|<br>200<br>DN | || Pf] fa<br>PTT NET 50<br>25 ° C<br>100 I INI Tm<br>0 eell 0 ry FP] fT dd<br>0.1 1 10 100 100 200 300 400 500<br>VR, REVERSE VOLTAGE (V) di/dt (A/ u s)<br>Figure 24. Capacitance Figure 25. Reverse Recovery Time vs. di/dt<br>15 500<br>125 ° C 400 125 ° C<br>PP = pe<br>10 er Teer<br>300<br>25 ° C<br>B= ape 200 ><br>5<br>aCert aeeer] PFFREE| | | | |<br>Chee| | || 100 CUE 25 ° C ee<br>0 PPE 0<br>ET TP) F+TeetT | Tl hv|l ht ht CT<br>100 200 300 400 500 100 200 300 400 500<br>di/dt (A/ u s) di/dt (A/ u s)<br>, FORWARD CURRENT (A) , REVERSE CURRENT (A)<br>IF IR<br>C, CAPACITANCE (pF)<br>, REVERSE RECOVERY TIME (ns)<br>trr<br>, REVERSE RECOVERY CURRENT (A)Irr , REVERSE RECOVERY CHARGE (nC)Qrr<br>**----- End of picture text -----**<br>


**Figure 26. Reverse Recovery Current vs. di/dt** 

**Figure 27. Reverse Recovery Charge vs. di/dt** 

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**FAM65CR51DZ1, FAM65CR51DZ2** 

## **TYPICAL CHARACTERISTICS − DIODES** 

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**----- Start of picture text -----**<br>
1<br>P|SR Duty Cycle = 0.5 aeeHsSS aSSSeeea a a tHeee<br>PE 0.2 oe er0 |Oe<br>0.1 pet 0.1<br>SS 0.05 _ eeoeoeSee TE eerSe a a a<br>0.02<br>aSeA<br>0.01<br>0.01<br>Single Pulse SS AS OE CO GN DS SO 6SD GN NG 6 CG EN OS OO<br>Sent<br>0.001<br>0.00001 0.001 0.1 10 1000<br>t, RECTANGULAR PULSE DURATION (sec)<br><>)<br>C/W)<br>°<br>, NORMALIZED THERMAL IMPEDANCE (<br>JC<br>Z<br>**----- End of picture text -----**<br>


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**----- Start of picture text -----**<br>
Figure 28. Transient Thermal Impedance<br>**----- End of picture text -----**<br>


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MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

## **APMCD−A16 / 12LD, AUTOMOTIVE MODULE** CASE MODGG ISSUE C 

DATE 03 NOV 2021 

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**GENERIC MARKING DIAGRAM*** XXXX = Specific Device Code ZZZ = Lot ID XXXXXXXXXXXXXXXX AT = Assembly & Test Location ZZZ ATYWW Y = Year NNNNNNN WW = Work Week NNN = Serial Number 

*This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ � ”, may or may not be present. Some products may not follow the Generic Marking. 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98AON94738G** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: APMCD−A16 / 12LD, AUTOMOTIVE MODULE PAGE 1 OF 1** 

**onsemi** and                     are trademarks of Semiconductor Components Industries, LLC dba **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. 

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MECHANICAL CASE OUTLINE **PACKAGE DIMENSIONS** 

## **APMCD−B16 / 12LD, AUTOMOTIVE MODULE** CASE MODGK ISSUE D 

DATE 04 NOV 2021 

**==> picture [75 x 39] intentionally omitted <==**

**GENERIC MARKING DIAGRAM*** XXXX = Specific Device Code ZZZ = Lot ID XXXXXXXXXXXXXXXX AT = Assembly & Test Location ZZZ ATYWW Y = Year NNNNNNN W = Work Week NNN = Serial Number 

*This information is generic. Please refer to device data sheet for actual part marking. Pb−Free indicator, “G” or microdot “ � ”, may or may not be present. Some products may not follow the Generic Marking. 

Electronic versions are uncontrolled except when accessed directly from the Document Repository. **DOCUMENT NUMBER: 98AON97134G** Printed  versions are uncontrolled  except when stamped  “CONTROLLED COPY” in red. **DESCRIPTION: APMCD−B16 / 12LD, AUTOMOTIVE MODULE PAGE 1 OF 1** 

**onsemi** and                     are trademarks of Semiconductor Components Industries, LLC dba **onsemi** or its subsidiaries in the United States and/or other countries. **onsemi** reserves the right to make changes without further notice to any products herein. **onsemi** makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does **onsemi** assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. **onsemi** does not convey any license under its patent rights nor the rights of others. 

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