EPF8282ATC100-4N

**January 2003, ver. 11.1** 

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## **FLEX 8000** 

## **Programmable Logic Device Family** 

## **Data Sheet** 

## 1 **Features...** 

- Low-cost, high-density, register-rich CMOS programmable logic device (PLD) family (see Table 1) 

   - 2,500 to 16,000 usable gates 

   - 282 to 1,500 registers 

- System-level features 

   - In-circuit reconfigurability (ICR) via external configuration devices or intelligent controller 

   - Fully compliant with the peripheral component interconnect Special Interest Group (PCI SIG) _**PCI Local Bus Specification, Revision 2.2**_ for 5.0-V operation 

   - Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990 on selected devices 

   - – MultiVolt[TM] I/O interface enabling device core to run at 5.0 V, while I/O pins are compatible with 5.0-V and 3.3-V logic levels 

   - Low power consumption (typical specification is 0.5 mA or less in standby mode) 

- Flexible interconnect 

   - FastTrack[®] Interconnect continuous routing structure for fast, predictable interconnect delays 

   - Dedicated carry chain that implements arithmetic functions such as fast adders, counters, and comparators (automatically used by software tools and megafunctions) 

   - Dedicated cascade chain that implements high-speed, high-fan-in logic functions (automatically used by software tools and megafunctions) 

   - Tri-state emulation that implements internal tri-state nets 

- Powerful I/O pins 

- Programmable output slew-rate control reduces switching noise 

_**Table 1. FLEX 8000 Device Features**_ 

|**_Table 1. FLEX 8000 Device Features_**|**_Table 1. FLEX 8000 Device Features_**|**_Table 1. FLEX 8000 Device Features_**|**_Table 1. FLEX 8000 Device Features_**|**_Table 1. FLEX 8000 Device Features_**|**_Table 1. FLEX 8000 Device Features_**|**_Table 1. FLEX 8000 Device Features_**|
|---|---|---|---|---|---|---|
|**Feature**|**EPF8282A**<br>**EPF8282AV**|**EPF8452A**|**EPF8636A**|**EPF8820A**|**EPF81188A**|**EPF81500A**|
|Usable gates|2,500|4,000|6,000|8,000|12,000|16,000|
|Flipflops|282|452|636|820|1,188|1,500|
|Logic array blocks (LABs)|26|42|63|84|126|162|
|Logic elements (LEs)|208|336|504|672|1,008|1,296|
|Maximum user I/O pins|78|120|136|152|184|208|



**Altera Corporation** 

**1** 

DS-F8000-11.1 

## **FLEX 8000 Programmable Logic Device Family Data Sheet** 

|JTAG BST circuitry|Yes|No|Yes|Yes|No|Yes|
|---|---|---|---|---|---|---|
|**...and More**<br>**Features**<br>■<br>Peripheral register for fast setup and clock-to-output delay<br>■<br>Fabricated on an advanced SRAM process<br>■<br>Available in a variety of packages with 84 to 304 pins (seeTable 2)<br>■<br>Software design support and automatic place-and-route provided by<br>the Altera®MAX+PLUS®II development system for Windows-based<br>PCs, as well as Sun SPARCstation, HP 9000 Series 700/800, and IBM<br>RISC System/6000 workstations<br>■<br>Additional design entry and simulation support provided by EDIF<br>2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),<br>Verilog HDL, VHDL, and other interfaces to popular EDA tools from<br>manufacturers such as Cadence, Exemplar Logic, Mentor Graphics,<br>OrCAD, Synopsys, Synplicity, and Veribest|||||||



_**Table 2. FLEX 8000 Package Options & I/O Pin Count** Note (1)_ 

|**_Table 2. FLEX 8000 Package Options & I/O Pin Count_**<br>_Note (1)_|**_Table 2. FLEX 8000 Package Options & I/O Pin Count_**<br>_Note (1)_|**_Table 2. FLEX 8000 Package Options & I/O Pin Count_**<br>_Note (1)_|**_Table 2. FLEX 8000 Package Options & I/O Pin Count_**<br>_Note (1)_|**_Table 2. FLEX 8000 Package Options & I/O Pin Count_**<br>_Note (1)_|**_Table 2. FLEX 8000 Package Options & I/O Pin Count_**<br>_Note (1)_|**_Table 2. FLEX 8000 Package Options & I/O Pin Count_**<br>_Note (1)_|**_Table 2. FLEX 8000 Package Options & I/O Pin Count_**<br>_Note (1)_|**_Table 2. FLEX 8000 Package Options & I/O Pin Count_**<br>_Note (1)_|**_Table 2. FLEX 8000 Package Options & I/O Pin Count_**<br>_Note (1)_|**_Table 2. FLEX 8000 Package Options & I/O Pin Count_**<br>_Note (1)_|**_Table 2. FLEX 8000 Package Options & I/O Pin Count_**<br>_Note (1)_|**_Table 2. FLEX 8000 Package Options & I/O Pin Count_**<br>_Note (1)_|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Device**|**84-**<br>**Pin**<br>**PLCC**|**100-**<br>**Pin**<br>**TQFP**|**144-**<br>**Pin**<br>**TQFP**|**160-**<br>**Pin**<br>**PQFP**|**160-**<br>**Pin**<br>**PGA**|**192-**<br>**Pin**<br>**PGA**|**208-**<br>**Pin**<br>**PQFP**|**225-**<br>**Pin**<br>**BGA**|**232-**<br>**Pin**<br>**PGA**|**240-**<br>**Pin**<br>**PQFP**|**280-**<br>**Pin**<br>**PGA**|**304-**<br>**Pin**<br>**RQFP**|
|EPF8282A|68|78|||||||||||
|EPF8282AV||78|||||||||||
|EPF8452A|68|68||120|120||||||||
|EPF8636A|68|||118||136|136||||||
|EPF8820A|||112|120||152|152|152|||||
|EPF81188A|||||||148||184|184|||
|EPF81500A||||||||||181|208|208|



## _**Note:**_ 

(1) FLEX 8000 device package types include plastic J-lead chip carrier (PLCC), thin quad flat pack (TQFP), plastic quad flat pack (PQFP), power quad flat pack (RQFP), ball-grid array (BGA), and pin-grid array (PGA) packages. 

## **General Description** 

Altera’s Flexible Logic Element MatriX (FLEX[®] ) family combines the benefits of both erasable programmable logic devices (EPLDs) and fieldprogrammable gate arrays (FPGAs). The FLEX 8000 device family is ideal for a variety of applications because it combines the fine-grained architecture and high register count characteristics of FPGAs with the high speed and predictable interconnect delays of EPLDs. Logic is implemented in LEs that include compact 4-input look-up tables (LUTs) and programmable registers. High performance is provided by a fast, continuous network of routing resources. 

**Altera Corporation** 

**2** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

FLEX 8000 devices provide a large number of storage elements for applications such as digital signal processing (DSP), wide-data-path manipulation, and data transformation. These devices are an excellent choice for bus interfaces, TTL integration, coprocessor functions, and high-speed controllers. The high-pin-count packages can integrate multiple 32-bit buses into a single device. Table 3 shows FLEX 8000 performance and LE requirements for typical applications. 

## _**Table 3. FLEX 8000 Performance**_ 

|**_Table 3. FLEX 8000 Performance_**|**_Table 3. FLEX 8000 Performance_**|**_Table 3. FLEX 8000 Performance_**|**_Table 3. FLEX 8000 Performance_**|**_Table 3. FLEX 8000 Performance_**|**_Table 3. FLEX 8000 Performance_**|
|---|---|---|---|---|---|
|**Application**|**LEs Used**|**Speed Grade**|||**Units**|
|||**A-2**|**A-3**|**A-4**||
|16-bit loadable counter|16|125|95|83|MHz|
|16-bit up/down counter|16|125|95|83|MHz|
|24-bit accumulator|24|87|67|58|MHz|
|16-bit address decode|4|4.2|4.9|6.3|ns|
|16-to-1 multiplexer|10|6.6|7.9|9.5|ns|



All FLEX 8000 device packages provide four dedicated inputs for synchronous control signals with large fan-outs. Each I/O pin has an associated register on the periphery of the device. As outputs, these registers provide fast clock-to-output times; as inputs, they offer quick setup times. 

The logic and interconnections in the FLEX 8000 architecture are configured with CMOS SRAM elements. FLEX 8000 devices are configured at system power-up with data stored in an industry-standard parallel EPROM or an Altera serial configuration devices, or with data provided by a system controller. Altera offers the EPC1, EPC1213, EPC1064, and EPC1441 configuration devices, which configure FLEX 8000 devices via a serial data stream. Configuration data can also be stored in an industry-standard 32 K × 8 bit or larger configuration device, or downloaded from system RAM. After a FLEX 8000 device has been configured, it can be reconfigured in-circuit by resetting the device and loading new data. Because reconfiguration requires less than 100 ms, realtime changes can be made during system operation. For information on how to configure FLEX 8000 devices, go to the following documents: 

- _Configuration Devices for APEX & FLEX Devices Data Sheet_ 

- _BitBlaster Serial Download Cable Data Sheet_ 

- _ByteBlasterMV Parallel Port Download Cable Data Sheet_ 

- _Application Note 33 (Configuring FLEX 8000 Devices)_ 

- _Application Note 38 (Configuring Multiple FLEX 8000 Devices)_ 

**Altera Corporation** 

**3** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

FLEX 8000 devices contain an optimized microprocessor interface that permits the microprocessor to configure FLEX 8000 devices serially, in parallel, synchronously, or asynchronously. The interface also enables the microprocessor to treat a FLEX 8000 device as memory and configure the device by writing to a virtual memory location, making it very easy for the designer to create configuration software. 

The FLEX 8000 family is supported by Altera’s MAX+PLUS II development system, a single, integrated package that offers schematic, text—including the Altera Hardware Description Language (AHDL), VHDL, and Verilog HDL—and waveform design entry, compilation and logic synthesis, simulation and timing analysis, and device programming. The MAX+PLUS II software provides EDIF 2 0 0 and 3 0 0, library of parameterized modules (LPM), VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industrystandard PC- and UNIX workstation-based EDA tools. The MAX+PLUS II software runs on Windows-based PCs and Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000 workstations. 

The MAX+PLUS II software interfaces easily with common gate array EDA tools for synthesis and simulation. For example, the MAX+PLUS II software can generate Verilog HDL files for simulation with tools such as Cadence Verilog-XL. Additionally, the MAX+PLUS II software contains EDA libraries that use device-specific features such as carry chains, which are used for fast counter and arithmetic functions. For instance, the Synopsys Design Compiler library supplied with the MAX+PLUS II development system includes DesignWare functions that are optimized for the FLEX 8000 architecture. 

f 

**Functional Description** 

For more information on the MAX+PLUS II software, go to the _MAX+PLUS II Programmable Logic Development System & Software Data Sheet_ . 

The FLEX 8000 architecture incorporates a large matrix of compact building blocks called logic elements (LEs). Each LE contains a 4-input LUT that provides combinatorial logic capability and a programmable register that offers sequential logic capability. The fine-grained structure of the LE provides highly efficient logic implementation. 

Eight LEs are grouped together to form a logic array block (LAB). Each FLEX 8000 LAB is an independent structure with common inputs, interconnections, and control signals. The LAB architecture provides a coarse-grained structure for high device performance and easy routing. 

**Altera Corporation** 

**4** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

Figure 1 shows a block diagram of the FLEX 8000 architecture. Each group of eight LEs is combined into an LAB; LABs are arranged into rows and columns. The I/O pins are supported by I/O elements (IOEs) located at the ends of rows and columns. Each IOE contains a bidirectional I/O buffer and a flipflop that can be used as either an input or output register. 

## _**Figure 1. FLEX 8000 Device Block Diagram**_ 

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I/O Element IOE IOE IOE IOE<br>(IOE)<br>IOE IOE<br>IOE IOE<br>FastTrack<br>Interconnect<br>Logic Array<br>Block (LAB)<br>IOE IOE<br>IOE IOE<br>Logic<br>Element (LE)<br>IOE IOE IOE IOE<br>**----- End of picture text -----**<br>


Signal interconnections within FLEX 8000 devices and between device pins are provided by the FastTrack Interconnect, a series of fast, continuous channels that run the entire length and width of the device. IOEs are located at the end of each row (horizontal) and column (vertical) FastTrack Interconnect path. 

**Altera Corporation** 

**5** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

## **Logic Array Block** 

A logic array block (LAB) consists of eight LEs, their associated carry and cascade chains, LAB control signals, and the LAB local interconnect. The LAB provides the coarse-grained structure of the FLEX 8000 architecture. This structure enables FLEX 8000 devices to provide efficient routing, high device utilization, and high performance. Figure 2 shows a block diagram of the FLEX 8000 LAB. 

## _**Figure 2. FLEX 8000 Logic Array Block**_ 

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Dedicated<br>Inputs Row Interconnect<br>24 4<br>8<br>LAB Local<br>Interconnect 4 See Figure 8<br>(32 channels) Carry-In andCascade-In for details.<br>from LAB 8 16<br>on Left<br>LAB Control 4 2<br>Signals<br>Column-to-Row<br>4 LE1 Interconnect<br>Column<br>4 LE2 Interconnect<br>4 LE3<br>4 LE4<br>4 LE5<br>4 LE6<br>4 LE7<br>4 LE8<br>8 2<br>Carry-Out and<br>Cascade-Out<br>to LAB on Right<br>**----- End of picture text -----**<br>


**Altera Corporation** 

**6** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

Each LAB provides four control signals that can be used in all eight LEs. Two of these signals can be used as clocks, and the other two for clear/preset control. The LAB control signals can be driven directly from a dedicated input pin, an I/O pin, or any internal signal via the LAB local interconnect. The dedicated inputs are typically used for global clock, clear, or preset signals because they provide synchronous control with very low skew across the device. FLEX 8000 devices support up to four individual global clock, clear, or preset control signals. If logic is required on a control signal, it can be generated in one or more LEs in any LAB and driven into the local interconnect of the target LAB. 

## **Logic Element** 

The logic element (LE) is the smallest unit of logic in the FLEX 8000 architecture, with a compact size that provides efficient logic utilization. Each LE contains a 4-input LUT, a programmable flipflop, a carry chain, and cascade chain. Figure 3 shows a block diagram of an LE. 

## _**Figure 3. FLEX 8000 LE**_ 

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Carry-In Cascade-In<br>DFF<br>DATA1<br>DATA2DATA3 Look-Up(LUT)Table ChainCarry CascadeChain D PRNQ LE-Out<br>DATA4<br>CLRN<br>Clear/<br>LABCTRL1 Preset<br>LABCTRL2 Logic<br>Clock<br>Select<br>LABCTRL3<br>LABCTRL4<br>Carry-Out Cascade-Out<br>**----- End of picture text -----**<br>


The LUT is a function generator that can quickly compute any function of four variables. The programmable flipflop in the LE can be configured for D, T, JK, or SR operation. The clock, clear, and preset control signals on the flipflop can be driven by dedicated input pins, general-purpose I/O pins, or any internal logic. For purely combinatorial functions, the flipflop is bypassed and the output of the LUT goes directly to the output of the LE. 

**Altera Corporation** 

**7** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

The FLEX 8000 architecture provides two dedicated high-speed data paths—carry chains and cascade chains—that connect adjacent LEs without using local interconnect paths. The carry chain supports highspeed counters and adders; the cascade chain implements wide-input functions with minimum delay. Carry and cascade chains connect all LEs in an LAB and all LABs in the same row. Heavy use of carry and cascade chains can reduce routing flexibility. Therefore, the use of carry and cascade chains should be limited to speed-critical portions of a design. 

## _Carry Chain_ 

The carry chain provides a very fast (less than 1 ns) carry-forward function between LEs. The carry-in signal from a lower-order bit moves forward into the higher-order bit via the carry chain, and feeds into both the LUT and the next portion of the carry chain. This feature allows the FLEX 8000 architecture to implement high-speed counters and adders of arbitrary width. The MAX+PLUS II Compiler can create carry chains automatically during design processing; designers can also insert carry chain logic manually during design entry. 

Figure 4 shows how an _n_ -bit full adder can be implemented in _n_ + 1 LEs with the carry chain. One portion of the LUT generates the sum of two bits using the input signals and the carry-in signal; the sum is routed to the output of the LE. The register is typically bypassed for simple adders, but can be used for an accumulator function. Another portion of the LUT and the carry chain logic generate the carry-out signal, which is routed directly to the carry-in signal of the next-higher-order bit. The final carry-out signal is routed to another LE, where it can be used as a general-purpose signal. In addition to mathematical functions, carry chain logic supports very fast counters and comparators. 

**Altera Corporation** 

**8** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

_**Figure 4. FLEX 8000 Carry Chain Operation**_ 

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Carry-In<br>a1 LU Register s1<br>b1<br>Carry<br>LE1<br>a2 LUT Register s2<br>b2<br>Carry Chain<br>LE2<br>an LUT Register sn<br>bn<br>Carry Chain<br>LEn<br>LUT Register Carry-Out<br>Carry Chain<br>LEn + 1<br>**----- End of picture text -----**<br>


## _Cascade Chain_ 

With the cascade chain, the FLEX 8000 architecture can implement functions that have a very wide fan-in. Adjacent LUTs can be used to compute portions of the function in parallel; the cascade chain serially connects the intermediate values. The cascade chain can use a logical `AND` or logical `OR` (via De Morgan’s inversion) to connect the outputs of adjacent LEs. Each additional LE provides four more inputs to the effective width of a function, with a delay as low as 0.6 ns per LE. 

**Altera Corporation** 

**9** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

The MAX+PLUS II Compiler can create cascade chains automatically during design processing; designers can also insert cascade chain logic manually during design entry. Cascade chains longer than eight LEs are automatically implemented by linking LABs together. The last LE of an LAB cascades to the first LE of the next LAB. 

Figure 5 shows how the cascade function can connect adjacent LEs to form functions with a wide fan-in. These examples show functions of 4 _n_ variables implemented with _n_ LEs. For a device with an A-2 speed grade, the LE delay is 2.4 ns; the cascade chain delay is 0.6 ns. With the cascade chain, 4.2 ns is needed to decode a 16-bit address. 

## _**Figure 5. FLEX 8000 Cascade Chain Operation**_ 

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AND Cascade Chain OR Cascade Chain<br>LE1 LE1<br>d[3..0] LUT d[3..0] LUT<br>LE2 LE2<br>d[7..4] LUT d[7..4] LUT<br>LEn LEn<br>d[(4n-1)..4(n-1)] LUT d[(4n-1)..4(n-1)] LUT<br>**----- End of picture text -----**<br>


## _LE Operating Modes_ 

The FLEX 8000 LE can operate in one of four modes, each of which uses LE resources differently. See Figure 6. In each mode, seven of the ten available inputs to the LE—the four data inputs from the LAB local interconnect, the feedback from the programmable register, and the carry-in and cascade-in from the previous LE—are directed to different destinations to implement the desired logic function. The three remaining inputs to the LE provide clock, clear, and preset control for the register. The MAX+PLUS II software automatically chooses the appropriate mode for each application. Design performance can also be enhanced by designing for the operating mode that supports the desired application. 

**Altera Corporation** 

**10** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

## _**Figure 6. FLEX 8000 LE Operating Modes**_ 

## **Normal Mode** 

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Carry-In Cascade-In LE-Out<br>data1 PRN<br>data2 D Q<br>4-Input<br>LUT<br>data3 CLRN<br>Cascade-Out<br>data4<br>**----- End of picture text -----**<br>


## **Arithmetic Mode** 

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Carry-In Cascade-In LE-Out<br>PRN<br>D Q<br>data1<br>data2 3-Input<br>LUT<br>CLRN<br>Cascade-Out<br>3-Input<br>LUT<br>Carry-Out<br>**----- End of picture text -----**<br>


## **Up/Down Counter Mode** 

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Carry-In Cascade-In<br>data1 (ena) PRN<br>data2 (nclr) 3-Input 1 D Q LE-Out<br>LUT<br>0<br>data3 (data)<br>CLRN<br>3-Input<br>LUT<br>data4 (nload) Carry-Out Cascade-Out<br>**----- End of picture text -----**<br>


## **Clearable Counter Mode** 

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Carry-In<br>data1(ena) PRN<br>data2 (nclr) 3-Input 1 D Q LE-Out<br>LUT<br>0<br>data3 (data)<br>CLRN<br>3-Input<br>LUT<br>data4 (nload) Carry-Out Cascade-Out<br>**----- End of picture text -----**<br>


**Altera Corporation** 

**11** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

## **Normal Mode** 

The normal mode is suitable for general logic applications and wide decoding functions that can take advantage of a cascade chain. In normal mode, four data inputs from the LAB local interconnect and the carry-in signal are the inputs to a 4-input LUT. Using a configurable SRAM bit, the MAX+PLUS II Compiler automatically selects the carry-in or the `DATA3` signal as an input. The LUT output can be combined with the cascade-in signal to form a cascade chain through the cascade-out signal. The `LE-Out` signal—the data output of the LE—is either the combinatorial output of the LUT and cascade chain, or the data output ( `Q)` of the programmable register. 

## **Arithmetic Mode** 

The arithmetic mode offers two 3-input LUTs that are ideal for implementing adders, accumulators, and comparators. One LUT provides a 3-bit function; the other generates a carry bit. As shown in Figure 6, the first LUT uses the carry-in signal and two data inputs from the LAB local interconnect to generate a combinatorial or registered output. For example, in an adder, this output is the sum of three bits: `a` , `b` , and the carry-in. The second LUT uses the same three signals to generate a carry-out signal, thereby creating a carry chain. The arithmetic mode also supports a cascade chain. 

## **Up/Down Counter Mode** 

The up/down counter mode offers counter enable, synchronous up/down control, and data loading options. These control signals are generated by the data inputs from the LAB local interconnect, the carry-in signal, and output feedback from the programmable register. Two 3-input LUTs are used: one generates the counter data, and the other generates the fast carry bit. A 2-to-1 multiplexer provides synchronous loading. Data can also be loaded asynchronously with the clear and preset register control signals, without using the LUT resources. 

## **Clearable Counter Mode** 

The clearable counter mode is similar to the up/down counter mode, but supports a synchronous clear instead of the up/down control; the clear function is substituted for the cascade-in signal in the up/down counter mode. Two 3-input LUTs are used: one generates the counter data, and the other generates the fast carry bit. Synchronous loading is provided by a 2-to-1 multiplexer, and the output of this multiplexer is `AND` ed with a synchronous clear. 

**Altera Corporation** 

**12** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

## _Internal Tri-State Emulation_ 

Internal tri-state emulation provides internal tri-stating without the limitations of a physical tri-state bus. In a physical tri-state bus, the tri-state buffers’ output enable signals select the signal that drives the bus. However, if multiple output enable signals are active, contending signals can be driven onto the bus. Conversely, if no output enable signals are active, the bus will float. Internal tri-state emulation resolves contending tri-state buffers to a low value and floating buses to a high value, thereby eliminating these problems. The MAX+PLUS II software automatically implements tri-state bus functionality with a multiplexer. 

## _Clear & Preset Logic Control_ 

Logic for the programmable register’s clear and preset functions is controlled by the `DATA3` , `LABCTRL1` , and `LABCTRL2` inputs to the LE. The clear and preset control structure of the LE is used to asynchronously load signals into a register. The register can be set up so that `LABCTRL1` implements an asynchronous load. The data to be loaded is driven to `DATA3` ; when `LABCTRL1` is asserted, `DATA3` is loaded into the register. 

During compilation, the MAX+PLUS II Compiler automatically selects the best control signal implementation. Because the clear and preset functions are active-low, the Compiler automatically assigns a logic high to an unused clear or preset. 

The clear and preset logic is implemented in one of the following six asynchronous modes, which are chosen during design entry. LPM functions that use registers will automatically use the correct asynchronous mode. See Figure 7. 

- Clear only 

- Preset only 

- Clear and preset 

- Load with clear 

- Load with preset 

- Load without clear or preset 

**Altera Corporation** 

**13** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

## _**Figure 7. FLEX 8000 LE Asynchronous Clear & Preset Modes**_ 

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**----- Start of picture text -----**<br>
Asynchronous Clear Asynchronous Preset Asynchronous Clear & Preset<br>VCC  LABCTRL1 or LABCTRL1<br>LABCTRL2<br>PRN<br>PRN PRN<br>D Q<br>D Q D Q<br>CLRN<br>CLRN CLRN<br>LABCTRL1 or LABCTRL2<br>LABCTRL2<br>Asynchronous Load with Clear<br>LABCTRL1 NOT<br>(Asynchronous<br> Load)<br>DATA3 PRN<br>(Data) D Q<br>NOT<br>CLRN<br>LABCTRL2<br>(Clear)<br>Asynchronous Load with Preset<br>LABCTRL1 NOT<br>(Asynchronous<br> Load)<br>LABCTRL2<br>(Preset)<br>PRN<br>D Q<br>DATA3<br>(Data)<br>CLRN<br>NOT<br>Asynchronous Load without Clear or Preset<br>NOT<br>LABCTRL1<br>(Asynchronous<br> Load)<br>PRN<br>DATA3<br>D Q<br>(Data)<br>CLRN<br>NOT<br>**----- End of picture text -----**<br>


**Altera Corporation** 

**14** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

## **Asynchronous Clear** 

A register is cleared by one of the two `LABCTRL` signals. When the `CLRn` port receives a low signal, the register is set to zero. 

## **Asynchronous Preset** 

An asynchronous preset is implemented as either an asynchronous load or an asynchronous clear. If `DATA3` is tied to `VCC` , asserting `LABCTRLl` asynchronously loads a `1` into the register. Alternatively, the MAX+PLUS II software can provide preset control by using the clear and inverting the input and output of the register. Inversion control is available for the inputs to both LEs and IOEs. Therefore, if a register is preset by only one of the two `LABCTRL` signals, the `DATA3` input is not needed and can be used for one of the LE operating modes. 

## **Asynchronous Clear & Preset** 

When implementing asynchronous clear and preset, `LABCTRL1` controls the preset and `LABCTRL2` controls the clear. The `DATA3` input is tied to `VCC` ; therefore, asserting `LABCTRL1` asynchronously loads a `1` into the register, effectively presetting the register. Asserting `LABCTRL2` clears the register. 

## **Asynchronous Load with Clear** 

When implementing an asynchronous load with the clear, `LABCTRL1` implements the asynchronous load of `DATA3` by controlling the register preset and clear. `LABCTRL2` implements the clear by controlling the register clear. 

## **Asynchronous Load with Preset** 

When implementing an asynchronous load in conjunction with a preset, the MAX+PLUS II software provides preset control by using the clear and inverting the input and output of the register. Asserting `LABCTRL2` clears the register, while asserting `LABCTRL1` loads the register. The MAX+PLUS II software inverts the signal that drives the `DATA3` signal to account for the inversion of the register’s output. 

## **Asynchronous Load without Clear or Preset** 

When implementing an asynchronous load without the clear or preset, `LABCTRL1` implements the asynchronous load of `DATA3` by controlling the register preset and clear. 

**Altera Corporation** 

**15** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

## **FastTrack Interconnect** 

In the FLEX 8000 architecture, connections between LEs and device I/O pins are provided by the FastTrack Interconnect, a series of continuous horizontal (row) and vertical (column) routing channels that traverse the entire FLEX 8000 device. This device-wide routing structure provides predictable performance even in complex designs. In contrast, the segmented routing structure in FPGAs requires switch matrices to connect a variable number of routing paths, which increases the delays between logic resources and reduces performance. 

The LABs within FLEX 8000 devices are arranged into a matrix of columns and rows. Each row of LABs has a dedicated row interconnect that routes signals both into and out of the LABs in the row. The row interconnect can then drive I/O pins or feed other LABs in the device. Figure 8 shows how an LE drives the row and column interconnect. 

_**Figure 8. FLEX 8000 LAB Connections to Row & Column Interconnect**_ 

**==> picture [285 x 275] intentionally omitted <==**

**----- Start of picture text -----**<br>
16 Column<br>Channels<br>Row Channels<br>(1)<br>Each LE drives one<br>row channel.<br>LE1<br>LE2<br>to Local to Local Each LE drives up to<br>Feedback Feedback two column channels.<br>**----- End of picture text -----**<br>


_**Note:**_ 

- (1) See Table 4 for the number of row channels. 

**Altera Corporation** 

**16** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

Each LE in an LAB can drive up to two separate column interconnect channels. Therefore, all 16 available column channels can be driven by the LAB. The column channels run vertically across the entire device, and share access to LABs in the same column but in different rows. The MAX+PLUS II Compiler chooses which LEs must be connected to a column channel. A row interconnect channel can be fed by the output of the LE or by two column channels. These three signals feed a multiplexer that connects to a specific row channel. Each LE is connected to one 3-to-1 multiplexer. In an LAB, the multiplexers provide all 16 column channels with access to 8 row channels. 

Each column of LABs has a dedicated column interconnect that routes signals out of the LABs into the column. The column interconnect can then drive I/O pins or feed into the row interconnect to route the signals to other LABs in the device. A signal from the column interconnect, which can be either the output of an LE or an input from an I/O pin, must transfer to the row interconnect before it can enter an LAB. Table 4 summarizes the FastTrack Interconnect resources available in each FLEX 8000 device. 

_**Table 4. FLEX 8000 FastTrack Interconnect Resources**_ 

|**_Table 4. FLEX 8000 FastTrack Interconnect Resources_**|**_Table 4. FLEX 8000 FastTrack Interconnect Resources_**|**_Table 4. FLEX 8000 FastTrack Interconnect Resources_**|**_Table 4. FLEX 8000 FastTrack Interconnect Resources_**|**_Table 4. FLEX 8000 FastTrack Interconnect Resources_**|
|---|---|---|---|---|
|**Device**|**Rows**|**Channels per Row**|**Columns**|**Channels per Column**|
|EPF8282A<br>EPF8282AV|2|168|13|16|
|EPF8452A|2|168|21|16|
|EPF8636A|3|168|21|16|
|EPF8820A|4|168|21|16|
|EPF81188A|6|168|21|16|
|EPF81500A|6|216|27|16|



Figure 9 shows the interconnection of four adjacent LABs, with row, column, and local interconnects, as well as the associated cascade and carry chains. 

**Altera Corporation** 

**17** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

## _**Figure 9. FLEX 8000 Device Interconnect Resources**_ 

_Each LAB is named according to its physical row (A, B, C, etc.) and column (1, 2, 3, etc.) position within the device._ 

**==> picture [387 x 295] intentionally omitted <==**

**----- Start of picture text -----**<br>
See Figure 12<br>for details.<br>IOE IOE IOE IOE<br>Column See Figure 11<br>Interconnect Row for details.<br>Interconnect<br>1 IOE IOE 1<br>8 IOE IOE 8<br>LAB LAB<br>A1 A2<br>1 IOE IOE 1<br>8 IOE IOE 8<br>LAB LAB<br>B1 B2<br>LAB Local<br>Interconnect<br>Cascade &<br>Carry Chain<br>IOE IOE IOE IOE<br>**----- End of picture text -----**<br>


## **I/O Element** 

An IOE contains a bidirectional I/O buffer and a register that can be used either as an input register for external data that requires a fast setup time, or as an output register for data that requires fast clock-to-output performance. IOEs can be used as input, output, or bidirectional pins. The MAX+PLUS II Compiler uses the programmable inversion option to automatically invert signals from the row and column interconnect where appropriate. Figure 10 shows the IOE block diagram. 

**Altera Corporation** 

**18** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

## _**Figure 10. FLEX 8000 IOE**_ 

_Numbers in parentheses are for EPF81500A devices only._ 

**==> picture [351 x 272] intentionally omitted <==**

**----- Start of picture text -----**<br>
I/O Controls<br>To Row or Column 6<br>Interconnect<br>(6) Programmable<br>Inversion<br>VCC<br>From Row or Column<br>Interconnect D Q<br>CLRN Slew-Rate<br>Control<br>VCC<br>CLR0 CLR1/OE0 CLK0 CLK1/OE1 OE2 OE3 (OE [4..9])<br>**----- End of picture text -----**<br>


## _Row-to-IOE Connections_ 

Figure 11 illustrates the connection between row interconnect channels and IOEs. An input signal from an IOE can drive two separate row channels. When an IOE is used as an output, the signal is driven by an _n_ -to-1 multiplexer that selects the row channels. The size of the multiplexer varies with the number of columns in a device. EPF81500A devices use a 27-to-1 multiplexer; EPF81188A, EPF8820A, EPF8636A, and EPF8452A devices use a 21-to-1 multiplexer; and EPF8282A and EPF8282AV devices use a 13-to-1 multiplexer. Eight IOEs are connected to each side of the row channels. 

**Altera Corporation** 

**19** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

## _**Figure 11. FLEX 8000 Row-to-IOE Connections**_ 

_Numbers in parentheses are for EPF81500A devices. See Note (1)._ 

**==> picture [360 x 347] intentionally omitted <==**

**----- Start of picture text -----**<br>
2<br>2<br>2<br>2<br>Each IOE can drive n IOE 1<br>up to two row<br>channels.<br>n IOE 2<br>2 2 2 2 n IOE 3<br>n IOE 4<br>Row Interconnect<br>168<br>(216) n IOE 5<br>168<br>(216)<br>Each IOE is 2 2 2 2 n IOE 6<br>driven by an<br>n-to-1multiplexer. n IOE 7<br>n IOE 8<br>2<br>2<br>2<br>2<br>**----- End of picture text -----**<br>


_**Note:**_ 

- (1) _n_ = 13 for EPF8282A and EPF8282AV devices. _n_ = 21 for EPF8452A, EPF8636A, EPF8820A, and EPF81188A devices. _n_ = 27 for EPF81500A devices. 

## _Column-to-IOE Connections_ 

Two IOEs are located at the top and bottom of the column channels (see Figure 12). When an IOE is used as an input, it can drive up to two separate column channels. The output signal to an IOE can choose from 8 of the 16 column channels through an 8-to-1 multiplexer. 

**Altera Corporation** 

**20** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

_**Figure 12. FLEX 8000 Column-to-IOE Connections**_ 

**==> picture [283 x 177] intentionally omitted <==**

**----- Start of picture text -----**<br>
Each IOE is Each IOE can drive<br>driven by an IOE IOE up to two column<br>8-to-1 signals.<br>multiplexer.<br>8 8<br>16<br>Column Interconnect<br>**----- End of picture text -----**<br>


In addition to general-purpose I/O pins, FLEX 8000 devices have four dedicated input pins. These dedicated inputs provide low-skew, devicewide signal distribution, and are typically used for global clock, clear, and preset control signals. The signals from the dedicated inputs are available as control signals for all LABs and I/O elements in the device. The dedicated inputs can also be used as general-purpose data inputs because they can feed the local interconnect of each LAB in the device. 

Signals enter the FLEX 8000 device either from the I/O pins that provide general-purpose input capability or from the four dedicated inputs. The IOEs are located at the ends of the row and column interconnect channels. 

I/O pins can be used as input, output, or bidirectional pins. Each I/O pin has a register that can be used either as an input register for external data that requires fast setup times, or as an output register for data that requires fast clock-to-output performance. The MAX+PLUS II Compiler uses the programmable inversion option to invert signals automatically from the row and column interconnect when appropriate. 

The clock, clear, and output enable controls for the IOEs are provided by a network of I/O control signals. These signals can be supplied by either the dedicated input pins or by internal logic. The IOE control-signal paths are designed to minimize the skew across the device. All control-signal sources are buffered onto high-speed drivers that drive the signals around the periphery of the device. This “peripheral bus” can be configured to provide up to four output enable signals (10 in EPF81500A devices), and up to two clock or clear signals. Figure 13 on page 22 shows how two output enable signals are shared with one clock and one clear signal. 

**Altera Corporation** 

**21** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

The signals for the peripheral bus can be generated by any of the four dedicated inputs or signals on the row interconnect channels, as shown in Figure 13. The number of row channels in a row that can drive the peripheral bus correlates to the number of columns in the FLEX 8000 device. EPF8282A and EPF8282AV devices use 13 channels; EPF8452A, EPF8636A, EPF8820A, and EPF81188A devices use 21 channels; and EPF81500A devices use 27 channels. The first LE in each LAB is the source of the row channel signal. The six peripheral control signals (12 in EPF81500A devices) can be accessed by each IOE. 

## _**Figure 13. FLEX 8000 Peripheral Bus**_ 

**==> picture [274 x 176] intentionally omitted <==**

**----- Start of picture text -----**<br>
Numbers in parentheses are for EPF81500A devices.<br>Peripheral Control<br>Signals<br>Programmable<br>Inversion<br>Dedicated 4<br>Inputs<br>1<br>2<br>Row Channels<br>n (1)<br>CLR0 CLR1/OE0 CLK0 CLK1/OE1 OE2 OE3 (OE[4..9])<br>**----- End of picture text -----**<br>


## _**Note:**_ 

- (1) _n_ = 13 for EPF8282A and EPF8282AV devices. _n_ = 21 for EPF8452A, EPF8636A, EPF8820A, and EPF81188A devices. _n_ = 27 for EPF81500A devices. 

**Altera Corporation** 

**22** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

Table 5 lists the source of the peripheral control signal for each FLEX 8000 device by row. 

_**Table 5. Row Sources of FLEX 8000 Peripheral Control Signals**_ 

|**_Table 5. Row Sources of FLEX 8000 Peripheral Control Signals_**|**_Table 5. Row Sources of FLEX 8000 Peripheral Control Signals_**|**_Table 5. Row Sources of FLEX 8000 Peripheral Control Signals_**|**_Table 5. Row Sources of FLEX 8000 Peripheral Control Signals_**|**_Table 5. Row Sources of FLEX 8000 Peripheral Control Signals_**|**_Table 5. Row Sources of FLEX 8000 Peripheral Control Signals_**|**_Table 5. Row Sources of FLEX 8000 Peripheral Control Signals_**|
|---|---|---|---|---|---|---|
|**Peripheral**<br>**Control Signal**|**EPF8282A**<br>**EPF8282AV**|**EPF8452A**|**EPF8636A**|**EPF8820A**|**EPF81188A**|**EPF81500A**|
|`CLK0`|Row A|Row A|Row A|Row A|Row E|Row E|
|`CLK1/OE1`|Row B|Row B|Row C|Row C|Row B|Row B|
|`CLR0`|Row A|Row A|Row B|Row B|Row F|Row F|
|`CLR1/OE0`|Row B|Row B|Row C|Row D|Row C|Row C|
|`OE2`|Row A|Row A|Row A|Row A|Row D|Row A|
|`OE3`|Row B|Row B|Row B|Row B|Row A|Row A|
|`OE4`|–|–|–|–|–|Row B|
|`OE5`|–|–|–|–|–|Row C|
|`OE6`|–|–|–|–|–|Row D|
|`OE7`|–|–|–|–|–|Row D|
|`OE8`|–|–|–|–|–|Row E|
|`OE9`|–|–|–|–|–|Row F|



## **Output Configuration** 

This section discusses slew-rate control and MultiVolt I/O interface operation for FLEX 8000 devices. 

## **Slew-Rate Control** 

The output buffer in each IOE has an adjustable output slew rate that can be configured for low-noise or high-speed performance. A slow slew rate reduces system noise by slowing signal transitions, adding a maximum delay of 3.5 ns. The slow slew-rate setting affects only the falling edge of a signal. The fast slew rate should be used for speed-critical outputs in systems that are adequately protected against noise. Designers can specify the slew rate on a pin-by-pin basis during design entry or assign a default slew rate to all pins on a global basis. 

f 

For more information on high-speed system design, go to _Application Note 75 (High-Speed Board Designs)_ . 

**Altera Corporation** 

**23** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

## **MultiVolt I/O Interface** 

The FLEX 8000 device architecture supports the MultiVolt I/O interface feature, which allows EPF81500A, EPF81188A, EPF8820A, and EPF8636A devices to interface with systems with differing supply voltages. These devices in all packages—except for EPF8636A devices in 84-pin PLCC packages—can be set for 3.3-V or 5.0-V I/O pin operation. These devices have one set of VCC pins for internal operation and input buffers ( `VCCINT` ), and another set for I/O output drivers ( `VCCIO` ). 

The `VCCINT` pins must always be connected to a 5.0-V power supply. With a 5.0-V VCCINT level, input voltages are at TTL levels and are therefore compatible with 3.3-V and 5.0-V inputs. 

The `VCCIO` pins can be connected to either a 3.3-V or 5.0-V power supply, depending on the output requirements. When the `VCCIO` pins are connected to a 5.0-V power supply, the output levels are compatible with 5.0-V systems. When the `VCCIO` pins are connected to a 3.3-V power supply, the output high is at 3.3 V and is therefore compatible with 3.3-V or 5.0-V systems. Devices operating with VCCIO levels lower than 4.75 V incur a nominally greater timing delay of _tOD2_ instead of _tOD1_ . See Table 8 on page 26. 

## **IEEE Std. 1149.1 (JTAG) Boundary-Scan Support** 

The EPF8282A, EPF8282AV, EPF8636A, EPF8820A, and EPF81500A devices provide JTAG BST circuitry. FLEX 8000 devices with JTAG circuitry support the JTAG instructions shown in Table 6. 

_**Table 6. EPF8282A, EPF8282AV, EPF8636A, EPF8820A & EPF81500A JTAG Instructions**_ 

|**_Table 6. EPF8282A, EPF8282AV, EPF8636A, EPF8820A & EPF81500A JTAG Instructions_**|**_Table 6. EPF8282A, EPF8282AV, EPF8636A, EPF8820A & EPF81500A JTAG Instructions_**|
|---|---|
|**JTAG Instruction**|**Description**|
|SAMPLE/PRELOAD|Allows a snapshot of the signals at the device pins to be captured and examined during<br>normal device operation, and permits an initial data pattern to be output at the device pins.|
|EXTEST|Allows the external circuitry and board-level interconnections to be tested by forcing a test<br>pattern at the output pins and capturing test results at the input pins.|
|BYPASS|Places the 1-bit bypass register between the`TDI`and`TDO`pins, which allows the BST<br>data to pass synchronously through the selected device to adjacent devices during<br>normal device operation.|



**Altera Corporation** 

**24** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

The instruction register length for FLEX 8000 devices is three bits. Table 7 shows the boundary-scan register length for FLEX 8000 devices. 

_**Table 7. FLEX 8000 Boundary-Scan Register Length**_ 

|**_Table 7. FLEX 8000 Boundary-Scan Register Length_**|**_Table 7. FLEX 8000 Boundary-Scan Register Length_**|
|---|---|
|**Device**|**Boundary-Scan Register Length**|
|EPF8282A, EPF8282AV|273|
|EPF8636A|417|
|EPF8820A|465|
|EPF81500A|645|



FLEX 8000 devices that support JTAG include weak pull-ups on the JTAG pins. Figure 14 shows the timing requirements for the JTAG signals. 

_**Figure 14. EPF8282A, EPF8282AV, EPF8636A, EPF8820A & EPF81500A JTAG Waveforms**_ 

**==> picture [291 x 189] intentionally omitted <==**

**----- Start of picture text -----**<br>
TMS<br>TDI<br> t JCP<br> tJCH  tJCL  t JPSU tJPH<br>TCK<br>tJPZX tJPCO tJPXZ<br>TDO<br>tJSSU tJSH<br>Signal<br>to Be<br>Captured<br>tJSZX tJSCO tJSXZ<br>Signal<br>to Be<br>Driven<br>**----- End of picture text -----**<br>


Table 8 shows the timing parameters and values for EPF8282A, EPF8282AV, EPF8636A, EPF8820A, and EPF81500A devices. 

**Altera Corporation** 

**25** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

_**Table 8.  JTAG Timing Parameters & Values**_ 

|**_Table 8.  JTAG Timing Parameters & Values_**|**_Table 8.  JTAG Timing Parameters & Values_**|**_Table 8.  JTAG Timing Parameters & Values_**|**_Table 8.  JTAG Timing Parameters & Values_**|**_Table 8.  JTAG Timing Parameters & Values_**|
|---|---|---|---|---|
|**Symbol**|**Parameter**|**EPF8282A**<br>**EPF8282AV**<br>**EPF8636A**<br>**EPF8820A**<br>**EPF81500A**||**Unit**|
|||**Min**|**Max**||
|**tJCP**|`TCK`clock period|100||ns|
|**tJCH**|`TCK`clock high time|50||ns|
|**tJCL**|`TCK`clock low time|50||ns|
|**tJPSU**|JTAG port setup time|20||ns|
|**tJPH**|JTAG port hold time|45||ns|
|**tJPCO**|JTAGport clock to output||25|ns|
|**tJPZX**|JTAG port high-impedance to valid output||25|ns|
|**tJPXZ**|JTAG port valid output to high-impedance||25|ns|
|**tJSSU**|Capture register setup time|20||ns|
|**tJSH**|Capture register hold time|45||ns|
|**tJSCO**|Update register clock to output||35|ns|
|**tJSZX**|Update register high-impedance to valid output||35|ns|
|**tJSXZ**|Update register valid output to high-impedance||35|ns|



f 

## **Generic Testing** 

For detailed information on JTAG operation in FLEX 8000 devices, refer to _Application Note 39 (IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera Devices)_ . 

Each FLEX 8000 device is functionally tested and specified by Altera. Complete testing of each configurable SRAM bit and all logic functionality ensures 100% configuration yield. AC test measurements for FLEX 8000 devices are made under conditions equivalent to those shown in Figure 15. Designers can use multiple test patterns to configure devices during all stages of the production flow. 

**Altera Corporation** 

**26** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

## _**Figure 15. FLEX 8000 AC Test Conditions**_ 

**==> picture [291 x 164] intentionally omitted <==**

**----- Start of picture text -----**<br>
Power supply transients can affect AC<br>measurements. Simultaneous transitions<br>of multiple outputs should be avoided for  VCC<br>accurate measurement. Threshold tests<br>464 Ω<br>must not be performed under AC  (703 Ω)<br>conditions. Large-amplitude, fast-ground-<br>Device To Test<br>current transients normally occur as the<br>Output System<br>device outputs discharge the load<br>capacitances. When these transients flow<br>through the parasitic inductance between  250 Ω<br>the device ground pin and the test system  (8.06 KΩ) C1 (includes<br>ground, significant reductions in  JIG capacitance)<br>observable noise immunity can result.  Device input<br>Numbers in parentheses are for 3.3-V  rise and fall<br>devices or outputs. Numbers without  times < 3 ns<br>parentheses are for 5.0-V devices or<br>outputs.<br>**----- End of picture text -----**<br>


## **Operating Conditions** 

Tables 9 through 12 provide information on absolute maximum ratings, recommended operating conditions, operating conditions, and capacitance for 5.0-V FLEX 8000 devices. 

_**Table 9. FLEX 8000 5.0-V Device Absolute Maximum Ratings** Note (1)_ 

|**_Table 9. FLEX 8000 5.0-V Device Absolute Maximum Ratings_**<br>_Note (1)_|**_Table 9. FLEX 8000 5.0-V Device Absolute Maximum Ratings_**<br>_Note (1)_|**_Table 9. FLEX 8000 5.0-V Device Absolute Maximum Ratings_**<br>_Note (1)_|**_Table 9. FLEX 8000 5.0-V Device Absolute Maximum Ratings_**<br>_Note (1)_|**_Table 9. FLEX 8000 5.0-V Device Absolute Maximum Ratings_**<br>_Note (1)_|**_Table 9. FLEX 8000 5.0-V Device Absolute Maximum Ratings_**<br>_Note (1)_|
|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Conditions**|**Min**|**Max**|**Unit**|
|VCC|Supply voltage|With respect to ground_(2)_|–2.0|7.0|V|
|VI|DC input voltage||–2.0|7.0|V|
|IOUT|DC output current, per pin||–25|25|mA|
|TSTG|Storage temperature|No bias|–65|150|° C|
|TAMB|Ambient temperature|Under bias|–65|135|° C|
|TJ|Junction temperature|Ceramic packages, under bias||150|° C|
|||PQFP and RQFP, under bias||135|° C|



**Altera Corporation** 

**27** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

_**Table 10. FLEX 8000 5.0-V Device Recommended Operating Conditions**_ 

|**_Table 10. FLEX 8000 5.0-V Device Recommended Operating Conditions_**|**_Table 10. FLEX 8000 5.0-V Device Recommended Operating Conditions_**|**_Table 10. FLEX 8000 5.0-V Device Recommended Operating Conditions_**|**_Table 10. FLEX 8000 5.0-V Device Recommended Operating Conditions_**|**_Table 10. FLEX 8000 5.0-V Device Recommended Operating Conditions_**|**_Table 10. FLEX 8000 5.0-V Device Recommended Operating Conditions_**|
|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Conditions**|**Min**|**Max**|**Unit**|
|VCCINT|Supply voltage for internal logic<br>and input buffers|_(3)_,_(4)_|4.75 (4.50)|5.25 (5.50)|V|
|VCCIO|Supply voltage for output<br>buffers, 5.0-V operation|_(3)_,_(4)_|4.75 (4.50)|5.25 (5.50)|V|
||Supply voltage for output<br>buffers, 3.3-V operation|_(3)_,_(4)_|3.00 (3.00)|3.60 (3.60)|V|
|VI|Input voltage||–0.5|VCCINT+ 0.5|V|
|VO|Output voltage||0|VCCIO|V|
|TA|Operating temperature|For commercial use|0|70|° C|
|||For industrial use|–40|85|° C|
|tR|Input rise time|||40|ns|
|tF|Input fall time|||40|ns|



_**Table 11. FLEX 8000 5.0-V Device DC Operating Conditions** Notes (5), (6)_ 

|**_Table 11. FLEX 8000 5.0-V Device DC Operating Conditions_**<br>_Notes (5), (6)_|**_Table 11. FLEX 8000 5.0-V Device DC Operating Conditions_**<br>_Notes (5), (6)_|**_Table 11. FLEX 8000 5.0-V Device DC Operating Conditions_**<br>_Notes (5), (6)_|**_Table 11. FLEX 8000 5.0-V Device DC Operating Conditions_**<br>_Notes (5), (6)_|**_Table 11. FLEX 8000 5.0-V Device DC Operating Conditions_**<br>_Notes (5), (6)_|**_Table 11. FLEX 8000 5.0-V Device DC Operating Conditions_**<br>_Notes (5), (6)_|**_Table 11. FLEX 8000 5.0-V Device DC Operating Conditions_**<br>_Notes (5), (6)_|
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|VIH|High-level input voltage||2.0||VCCINT+ 0.5|V|
|VIL|Low-level input voltage||–0.5||0.8|V|
|VOH|5.0-V high-level TTL output<br>voltage|IOH= –4 mA DC_(7)_<br>VCCIO= 4.75 V|2.4|||V|
||3.3-V high-level TTL output<br>voltage|IOH= –4 mA DC_(7)_<br>VCCIO= 3.00 V|2.4|||V|
||3.3-V high-level CMOS output<br>voltage|IOH= –0.1 mA DC_(7)_<br>VCCIO= 3.00 V|VCCIO– 0.2|||V|
|VOL|5.0-V low-level TTL output<br>voltage|IOL= 12 mA DC_(7)_<br>VCCIO= 4.75 V|||0.45|V|
||3.3-V low-level TTL output<br>voltage|IOL= 12 mA DC_(7)_<br>VCCIO= 3.00 V|||0.45|V|
||3.3-V low-level CMOS output<br>voltage|IOL= 0.1 mA DC_(7)_<br>VCCIO= 3.00 V|||0.2|V|
|II|Input leakage current|VI= VCCor ground|–10||10|µA|
|IOZ|Tri-state output off-state<br>current|VO= VCCor ground|–40||40|µA|
|ICC0|VCCsupply current (standby)|VI= ground, no load||0.5|10|mA|



**Altera Corporation** 

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**FLEX 8000 Programmable Logic Device Family Data Sheet** 

|||||||
|---|---|---|---|---|---|
|**_Table 12. FLEX 8000 5.0-V Device Capacitance_**<br>_Note (8)_||||||
|**Symbol**|**Parameter**|**Conditions**|**Min**|**Max**|**Unit**|
|CIN|Input capacitance|VIN= 0 V, f = 1.0 MHz||10|pF|
|COUT|Output capacitance|VOUT= 0 V, f = 1.0 MHz||10|pF|



## _**Notes to tables:**_ 

(1) See the _Operating Requirements for Altera Devices Data Sheet_ . 

- (2) Minimum DC input is –0.5 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 7.0 V for input currents less than 100 mA and periods shorter than 20 ns. 

- (3) The maximum V CC rise time is 100 ms. 

- (4) Numbers in parentheses are for industrial-temperature-range devices. 

- (5) Typical values are for T A = 25 ° C and V CC = 5.0 V. 

(6) These values are specified in Table 10 on page 28. 

(7) The IOH parameter refers to high-level TTL or CMOS output current; the IOL parameter refers to low-level TTL or CMOS output current. 

- (8) Capacitance is sample-tested only. 

Tables 13 through 16 provide information on absolute maximum ratings, recommended operating conditions, operating conditions, and capacitance for 3.3-V FLEX 8000 devices. 

_**Table 13. FLEX 8000 3.3-V Device Absolute Maximum Ratings** Note (1)_ 

|**_Table 13. FLEX 8000 3.3-V Device Absolute Maximum Ratings_**<br>_Note (1)_|**_Table 13. FLEX 8000 3.3-V Device Absolute Maximum Ratings_**<br>_Note (1)_|**_Table 13. FLEX 8000 3.3-V Device Absolute Maximum Ratings_**<br>_Note (1)_|**_Table 13. FLEX 8000 3.3-V Device Absolute Maximum Ratings_**<br>_Note (1)_|**_Table 13. FLEX 8000 3.3-V Device Absolute Maximum Ratings_**<br>_Note (1)_|**_Table 13. FLEX 8000 3.3-V Device Absolute Maximum Ratings_**<br>_Note (1)_|
|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Conditions**|**Min**|**Max**|**Unit**|
|VCC|Supply voltage|With respect to ground_(2)_|–2.0|5.3|V|
|VI|DC input voltage||–2.0|5.3|V|
|IOUT|DC output current, per pin||–25|25|mA|
|TSTG|Storage temperature|No bias|–65|150|° C|
|TAMB|Ambient temperature|Under bias|–65|135|° C|
|TJ|Junction temperature|Plastic packages, under bias||135|° C|



_**Table 14. FLEX 8000 3.3-V Device Recommended Operating Conditions**_ 

|**_Table 14. FLEX 8000 3.3-V Device Recommended Operating Conditions_**|**_Table 14. FLEX 8000 3.3-V Device Recommended Operating Conditions_**|**_Table 14. FLEX 8000 3.3-V Device Recommended Operating Conditions_**|**_Table 14. FLEX 8000 3.3-V Device Recommended Operating Conditions_**|**_Table 14. FLEX 8000 3.3-V Device Recommended Operating Conditions_**|**_Table 14. FLEX 8000 3.3-V Device Recommended Operating Conditions_**|
|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Conditions**|**Min**|**Max**|**Unit**|
|VCC|Supply voltage|_(3)_|3.0|3.6|V|
|VI|Input voltage||–0.3|VCC+ 0.3|V|
|VO|Output voltage||0|VCC|V|
|TA|Operatingtemperature|For commercial use|0|70|° C|
|tR|Input rise time|||40|ns|
|tF|Input fall time|||40|ns|



**Altera Corporation** 

**29** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

_**Table 15. FLEX 8000 3.3-V Device DC Operating Conditions** Note (4)_ 

|**_Table 15. FLEX 8000 3.3-V Device DC Operating Conditions_**<br>_Note (4)_|**_Table 15. FLEX 8000 3.3-V Device DC Operating Conditions_**<br>_Note (4)_|**_Table 15. FLEX 8000 3.3-V Device DC Operating Conditions_**<br>_Note (4)_|**_Table 15. FLEX 8000 3.3-V Device DC Operating Conditions_**<br>_Note (4)_|**_Table 15. FLEX 8000 3.3-V Device DC Operating Conditions_**<br>_Note (4)_|**_Table 15. FLEX 8000 3.3-V Device DC Operating Conditions_**<br>_Note (4)_|**_Table 15. FLEX 8000 3.3-V Device DC Operating Conditions_**<br>_Note (4)_|
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|VIH|High-level input voltage||2.0||VCC+ 0.3|V|
|VIL|Low-level input voltage||–0.3||0.8|V|
|VOH|High-level output voltage|IOH= –0.1 mA DC_(5)_|VCC– 0.2|||V|
|VOL|Low-level output voltage|IOL= 4 mA DC_(5)_|||0.45|V|
|II|Input leakage current|VI= VCCorground|–10||10|µA|
|IOZ|Tri-state output off-state current|VO= VCCor ground|–40||40|µA|
|ICC0|VCCsupply current (standby)|VI= ground, no load_(6)_||0.3|10|mA|



_**Table 16. FLEX 8000 3.3-V Device Capacitance** Note (7)_ 

|**_Table 16. FLEX 8000 3.3-V Device Capacitance_**<br>_Note (7)_|**_Table 16. FLEX 8000 3.3-V Device Capacitance_**<br>_Note (7)_|**_Table 16. FLEX 8000 3.3-V Device Capacitance_**<br>_Note (7)_|**_Table 16. FLEX 8000 3.3-V Device Capacitance_**<br>_Note (7)_|**_Table 16. FLEX 8000 3.3-V Device Capacitance_**<br>_Note (7)_|**_Table 16. FLEX 8000 3.3-V Device Capacitance_**<br>_Note (7)_|
|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Conditions**|**Min**|**Max**|**Unit**|
|CIN|Input capacitance|VIN= 0 V, f = 1.0 MHz||10|pF|
|COUT|Output capacitance|VOUT= 0 V, f = 1.0 MHz||10|pF|



## _**Notes to tables:**_ 

(1) See the _Operating Requirements for Altera Devices Data Sheet_ . 

(2) Minimum DC input voltage is –0.3 V. During transitions, the inputs may undershoot to –2.0 V or overshoot to 5.3 V for input currents less than 100 mA and periods shorter than 20 ns. 

(3) The maximum VCC rise time is 100 ms. VCC must rise monotonically. 

(4) These values are specified in Table 14 on page 29. 

(5) The IOH parameter refers to high-level TTL output current; the IOL parameter refers to low-level TTL output current. 

(6) Typical values are for TA = 25° C and VCC = 3.3 V. 

(7) Capacitance is sample-tested only. 

Figure 16 shows the typical output drive characteristics of 5.0-V FLEX 8000 devices. The output driver is compliant with _**PCI Local Bus Specification, Revision 2.2**_ . 

**Altera Corporation** 

**30** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

_**Figure 16. Output Drive Characteristics of 5.0-V FLEX 8000 Devices (Except EPF8282A)**_ 

**==> picture [391 x 147] intentionally omitted <==**

**----- Start of picture text -----**<br>
200 200<br>150 IOL 150 IOL<br>Typical IOutput O Typical IO<br>Output<br>Current (mA)<br>100 VCCINT = 5.0 V Current (mA)100 VCCINT = 5.0 V<br>VCCIO = 5.0 V VCCIO = 3.3 V<br>Room Temperature Room Temperature<br>50 IOH 50 IOH<br>1 2 3 4 5 1 2 3 4<br>Output Voltage (V) Output Voltage (V)<br>**----- End of picture text -----**<br>


Figure 17 shows the typical output drive characteristics of 5.0-V EPF8282A devices. The output driver is compliant with _**PCI Local Bus Specification, Revision 2.2**_ . 

_**Figure 17. Output Drive Characteristics of EPF8282A Devices with 5.0-V V CCIO**_ 

**==> picture [214 x 163] intentionally omitted <==**

**----- Start of picture text -----**<br>
150 IOL<br>120<br>VCC = 5.0 V<br>Typical IO Room Temperature<br>Output 90<br>Current (mA)<br>IOH<br>60<br>30<br>1 2 3 4 5<br>Output Voltage (V)<br>**----- End of picture text -----**<br>


Figure 18 shows the typical output drive characteristics of EPF8282AV devices. 

**Altera Corporation** 

**31** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

_**Figure 18. Output Drive Characteristics of EPF8282AV Devices**_ 

**==> picture [207 x 163] intentionally omitted <==**

**----- Start of picture text -----**<br>
100<br>75 IOL<br>Typical IO<br>Output 50 VCC = 3.3 V<br>Current (mA) Room Temperature<br>IOH<br>25<br>1 2 3 4<br>Output Voltage (V)<br>**----- End of picture text -----**<br>


## **Timing Model** 

The continuous, high-performance FastTrack Interconnect routing structure ensures predictable performance and accurate simulation and timing analysis. This predictable performance contrasts with that of FPGAs, which use a segmented connection scheme and hence have unpredictable performance. Timing simulation and delay prediction are available with the MAX+PLUS II Simulator and Timing Analyzer, or with industry-standard EDA tools. The Simulator offers both pre-synthesis functional simulation to evaluate logic design accuracy and postsynthesis timing simulation with 0.1-ns resolution. The Timing Analyzer provides point-to-point timing delay information, setup and hold time prediction, and device-wide performance analysis. 

Tables 17 through 20 describe the FLEX 8000 timing parameters and their symbols. 

**Altera Corporation** 

**32** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

|||
|---|---|
|**_Table 17. FLEX 8000 Internal Timing Parameters_**<br>_Note (1)_||
|**Symbol**|**Parameter**|
|_tIOD_|IOE register data delay|
|_tIOC_|IOE register control signal delay|
|_tIOE_|Output enable delay|
|_tIOCO_|IOE register clock-to-output delay|
|_tIOCOMB_|IOE combinatorial delay|
|_tIOSU_|IOE register setup time before clock; IOE register recovery time after asynchronous clear|
|_tIOH_|IOE register hold time after clock|
|_tIOCLR_|IOE register clear delay|
|_tIN_|Input pad and buffer delay|
|_tOD1_|Output buffer andpad delay, slow slew rate = off, VCCIO= 5.0 V C1 = 35pF_(2)_|
|_tOD2_|Output buffer and pad delay, slow slew rate = off, VCCIO= 3.3 V C1 = 35 pF_(2)_|
|_tOD3_|Output buffer and pad delay, slow slew rate = on, C1 = 35 pF_(3)_|
|_tXZ_|Output buffer disable delay, C1 = 5 pF|
|_tZX1_|Output buffer enable delay, slow slew rate = off, VCCIO= 5.0 V, C1 = 35 pF_(2)_|
|_tZX2_|Output buffer enable delay, slow slew rate = off, VCCIO= 3.3 V, C1 = 35 pF_(2)_|
|_tZX3_|Output buffer enable delay, slow slew rate = on, C1 = 35 pF_(3)_|



_**Table 18. FLEX 8000 LE Timing Parameters** Note (1)_ 

|**_Table 18. FLEX 8000 LE Timing Parameters_**<br>_Note (1)_|**_Table 18. FLEX 8000 LE Timing Parameters_**<br>_Note (1)_|
|---|---|
|**Symbol**|**Parameter**|
|_tLUT_|LUT delay for data-in|
|_tCLUT_|LUT delayfor carry-in|
|_tRLUT_|LUT delay for LE register feedback|
|_tGATE_|Cascade gate delay|
|_tCASC_|Cascade chain routing delay|
|_tCICO_|Carry-in to carry-out delay|
|_tCGEN_|Data-in to carry-out delay|
|_tCGENR_|LE register feedback to carry-out delay|
|_tC_|LE register control signal delay|
|_tCH_|LE register clock high time|
|_tCL_|LE register clock low time|
|_tCO_|LE register clock-to-output delay|
|_tCOMB_|Combinatorial delay|
|_tSU_|LE register setup time before clock; LE register recovery time after asynchronous preset, clear, or<br>load|
|_tH_|LE register hold time after clock|
|_tPRE_|LE register preset delay|
|_tCLR_|LE register clear delay|



**Altera Corporation** 

**33** 

## **FLEX 8000 Programmable Logic Device Family Data Sheet** 

|||
|---|---|
|**_Table 19. FLEX 8000 Interconnect Timing Parameters_**<br>_Note (1)_||
|**Symbol**|**Parameter**|
|_tLABCASC_|Cascade delay between LEs in different LABs|
|_tLABCARRY_|Carry delay between LEs in different LABs|
|_tLOCAL_|LAB local interconnect delay|
|_tROW_|Row interconnect routing delay_(4)_|
|_tCOL_|Column interconnect routing delay|
|_tDIN_C_|Dedicated input to LE control delay|
|_tDIN_D_|Dedicated input to LE data delay _(4)_|
|_tDIN_IO_|Dedicated input to IOE control delay|



_**Table 20. FLEX 8000 External Reference Timing Characteristics** Note (5)_ 

|**_Table 20. FLEX 8000 External Reference Timing Characteristics_**<br>_Note (5)_|**_Table 20. FLEX 8000 External Reference Timing Characteristics_**<br>_Note (5)_|
|---|---|
|**Symbol**|**Parameter**|
|**tDRR**|Register-to-register delay via 4 LEs, 3 row interconnects, and 4 local interconnects_(6)_|
|**tODH**|Output data hold time after clock_(7)_|



## _**Notes to tables:**_ 

- (1) Internal timing parameters cannot be measured explicitly. They are worst-case delays based on testable and external parameters specified by Altera. Internal timing parameters should be used for estimating device performance. Post-compilation timing simulation or timing analysis is required to determine actual worst-case performance. 

- (2) These values are specified in Table 10 on page 28 or Table 14 on page 29. 

- (3) For the _tOD3_ and _tZX3_ parameters, VCCIO = 3.3 V or 5.0 V. 

- (4) The _tROW_ and _t DIN_D_ delays are worst-case values for typical applications. Post-compilation timing simulation or timing analysis is required to determine actual worst-case performance. 

- (5) External reference timing characteristics are factory-tested, worst-case values specified by Altera. A representative subset of signal paths is tested to approximate typical device applications. 

- (6) For more information on test conditions, see _Application Note 76_ ( _Understanding FLEX 8000 Timing_ ). 

- (7) This parameter is a guideline that is sample-tested only and is based on extensive device characterization. This parameter applies to global and non-global clocking, and for LE and I/O element registers. 

The FLEX 8000 timing model shows the delays for various paths and functions in the circuit. See Figure 19. This model contains three distinct parts: the LE; the IOE; and the interconnect, including the row and column FastTrack Interconnect, LAB local interconnect, and carry and cascade interconnect paths. Each parameter shown in Figure 19 is expressed as a worst-case value in Tables 22 through 49. Hand-calculations that use the FLEX 8000 timing model and these timing parameters can be used to estimate FLEX 8000 device performance. Timing simulation or timing analysis after compilation is required to determine the final worst-case performance. Table 21 summarizes the interconnect paths shown in Figure 19. 

f 

For more information on timing parameters, go to _Application Note 76 (Understanding FLEX 8000 Timing)_ . 

**Altera Corporation** 

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**==> picture [8 x 397] intentionally omitted <==**

**----- Start of picture text -----**<br>
Altera Corporation<br> 35<br>**----- End of picture text -----**<br>


**==> picture [504 x 366] intentionally omitted <==**

**----- Start of picture text -----**<br>
tROW<br>Carry-In from Cascade-In from<br>Previous LE Previous LE<br>LE IOE<br>Cascade Register Output Data I/O Register Output<br>LUT Delay Gate Delay Delays Delay Delays Delays<br>tLUT<br>tLOCAL Carry ChaintttCLUTRLUTCGENDelay tGATE ttttttCOCOMBSUCLRHPRE LE-Out tCOL I/O RegisterControltIODtIOC tttttIOCOIOCOMBIOSUIOHIOCLR tttttttOD1OD2OD3XZZX1ZX2ZX3 I/O Pin<br>tCGENR<br>tCICO tIOE<br>Input<br>Register Delay<br>Control<br>tIN<br>tC<br>tCASC CascadeRouting Delay<br>Data-In<br>Dedicated<br>Input Delays<br>tDIN_D tLABCARRY tLABCASC<br>tDIN_C<br>tDIN_IO<br>Carry-Out Carry-Out Cascade-Out Cascade-Out<br>to Next LE to Next LE to Next LE in to Next LE in<br>in Same in Next Next LAB Same LAB<br>LAB LAB<br>Figure 19. FLEX 8000 Timing Model<br>**----- End of picture text -----**<br>


**FLEX 8000 Programmable Logic Device Family Data Sheet** 

_**Table 21. FLEX 8000 Timing Model Interconnect Paths**_ 

|**_Table 21. FLEX 8000 Timing Model Interconnect Paths_**|**_Table 21. FLEX 8000 Timing Model Interconnect Paths_**|**_Table 21. FLEX 8000 Timing Model Interconnect Paths_**|
|---|---|---|
|**Source**|**Destination**|**Total Delay**|
|LE-Out|LE in same LAB|_tLOCAL_|
|LE-Out|LE in same row, different LAB|_tROW + tLOCAL_|
|LE-Out|LE in different row|_tCOL + tROW + tLOCAL_|
|LE-Out|IOE on column|_tCOL_|
|LE-Out|IOE on row|_tROW_|
|IOE on row|LE in same row|_tROW + tLOCAL_|
|IOE on column|Any LE|_tCOL + tROW + tLOCAL_|



Tables 22 through 49 show the FLEX 8000 internal and external timing parameters. 

_**Table 22. EPF8282A Internal I/O Element Timing Parameters**_ 

|**_Table 22. EPF8282A Internal I/O Element Timing Parameters_**|**_Table 22. EPF8282A Internal I/O Element Timing Parameters_**|**_Table 22. EPF8282A Internal I/O Element Timing Parameters_**|**_Table 22. EPF8282A Internal I/O Element Timing Parameters_**|**_Table 22. EPF8282A Internal I/O Element Timing Parameters_**|**_Table 22. EPF8282A Internal I/O Element Timing Parameters_**|**_Table 22. EPF8282A Internal I/O Element Timing Parameters_**|**_Table 22. EPF8282A Internal I/O Element Timing Parameters_**|
|---|---|---|---|---|---|---|---|
|**Symbol**|**Speed Grade**||||||**Unit**|
||**A-2**||**A-3**||**A-4**|||
||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|_tIOD_||0.7||0.8||0.9|ns|
|_tIOC_||1.7||1.8||1.9|ns|
|_tIOE_||1.7||1.8||1.9|ns|
|_tIOCO_||1.0||1.0||1.0|ns|
|_tIOCOMB_||0.3||0.2||0.1|ns|
|_tIOSU_|1.4||1.6||1.8||ns|
|_tIOH_|0.0||0.0||0.0||ns|
|_tIOCLR_||1.2||1.2||1.2|ns|
|_tIN_||1.5||1.6||1.7|ns|
|_tOD1_||1.1||1.4||1.7|ns|
|_tOD2_||–||–||–|ns|
|_tOD3_||4.6||4.9||5.2|ns|
|_tXZ_||1.4||1.6||1.8|ns|
|_tZX1_||1.4||1.6||1.8|ns|
|_tZX2_||–||–||–|ns|
|_tZX3_||4.9||5.1||5.3|ns|



**Altera Corporation** 

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**FLEX 8000 Programmable Logic Device Family Data Sheet** 

_**Table 23. EPF8282A Interconnect Timing Parameters**_ 

|**_Table 23. EPF8282A Interconnect Timing Parameters_**|**_Table 23. EPF8282A Interconnect Timing Parameters_**|**_Table 23. EPF8282A Interconnect Timing Parameters_**|**_Table 23. EPF8282A Interconnect Timing Parameters_**|**_Table 23. EPF8282A Interconnect Timing Parameters_**|**_Table 23. EPF8282A Interconnect Timing Parameters_**|**_Table 23. EPF8282A Interconnect Timing Parameters_**|**_Table 23. EPF8282A Interconnect Timing Parameters_**|
|---|---|---|---|---|---|---|---|
|**Symbol**|**Speed Grade**||||||**Unit**|
||**A-2**||**A-3**||**A-4**|||
||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|_tLABCASC_||0.3||0.3||0.4|ns|
|_tLABCARRY_||0.3||0.3||0.4|ns|
|_tLOCAL_||0.5||0.6||0.8|ns|
|_tROW_||4.2||4.2||4.2|ns|
|_tCOL_||2.5||2.5||2.5|ns|
|_tDIN_C_||5.0||5.0||5.5|ns|
|_tDIN_D_||7.2||7.2||7.2|ns|
|_tDIN_IO_||5.0||5.0||5.5|ns|



**Altera Corporation** 

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**FLEX 8000 Programmable Logic Device Family Data Sheet** 

_**Table 24. EPF8282A LE Timing Parameters**_ 

|**_Table 24. EPF8282A LE Timing Parameters_**|**_Table 24. EPF8282A LE Timing Parameters_**|**_Table 24. EPF8282A LE Timing Parameters_**|**_Table 24. EPF8282A LE Timing Parameters_**|**_Table 24. EPF8282A LE Timing Parameters_**|**_Table 24. EPF8282A LE Timing Parameters_**|**_Table 24. EPF8282A LE Timing Parameters_**|**_Table 24. EPF8282A LE Timing Parameters_**|
|---|---|---|---|---|---|---|---|
|**Symbol**|**Speed Grade**||||||**Unit**|
||**A-2**||**A-3**||**A-4**|||
||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|_tLUT_||2.0||2.5||3.2|ns|
|_tCLUT_||0.0||0.0||0.0|ns|
|_tRLUT_||0.9||1.1||1.5|ns|
|_tGATE_||0.0||0.0||0.0|ns|
|_tCASC_||0.6||0.7||0.9|ns|
|_tCICO_||0.4||0.5||0.6|ns|
|_tCGEN_||0.4||0.5||0.7|ns|
|_tCGENR_||0.9||1.1||1.5|ns|
|_tC_||1.6||2.0||2.5|ns|
|_tCH_|4.0||4.0||4.0||ns|
|_tCL_|4.0||4.0||4.0||ns|
|_tCO_||0.4||0.5||0.6|ns|
|_tCOMB_||0.4||0.5||0.6|ns|
|_tSU_|0.8||1.1||1.2||ns|
|_tH_|0.9||1.1||1.5||ns|
|_tPRE_||0.6||0.7||0.8|ns|
|_tCLR_||0.6||0.7||0.8|ns|



_**Table 25. EPF8282A External Timing Parameters**_ 

|**_Table 25. EPF8282A External Timing Parameters_**|**_Table 25. EPF8282A External Timing Parameters_**|**_Table 25. EPF8282A External Timing Parameters_**|**_Table 25. EPF8282A External Timing Parameters_**|**_Table 25. EPF8282A External Timing Parameters_**|**_Table 25. EPF8282A External Timing Parameters_**|**_Table 25. EPF8282A External Timing Parameters_**|**_Table 25. EPF8282A External Timing Parameters_**|
|---|---|---|---|---|---|---|---|
|**Symbol**|**Speed Grade**||||||**Unit**|
||**A-2**||**A-3**||**A-4**|||
||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|**tDRR**||15.8||19.8||24.8|ns|
|**tODH**|1.0||1.0||1.0||ns|



**Altera Corporation** 

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**FLEX 8000 Programmable Logic Device Family Data Sheet** 

_**Table 26. EPF8282AV I/O Element Timing Parameters**_ 

|**_Table 26. EPF8282AV I/O Element Timing Parameters_**|**_Table 26. EPF8282AV I/O Element Timing Parameters_**|**_Table 26. EPF8282AV I/O Element Timing Parameters_**|**_Table 26. EPF8282AV I/O Element Timing Parameters_**|**_Table 26. EPF8282AV I/O Element Timing Parameters_**|**_Table 26. EPF8282AV I/O Element Timing Parameters_**|
|---|---|---|---|---|---|
|**Symbol**|**Speed Grade**||||**Unit**|
||**A-3**||**A-4**|||
||**Min**|**Max**|**Min**|**Max**||
|_tIOD_||0.9||2.2|ns|
|_tIOC_||1.9||2.0|ns|
|_tIOE_||1.9||2.0|ns|
|_tIOCO_||1.0||2.0|ns|
|_tIOCOMB_||0.1||0.0|ns|
|_tIOSU_|1.8||2.8||ns|
|_tIOH_|0.0||0.2||ns|
|_tIOCLR_||1.2||2.3|ns|
|_tIN_||1.7||3.4|ns|
|_tOD1_||1.7||4.1|ns|
|_tOD2_||–||–|ns|
|_tOD3_||5.2||7.1|ns|
|_tXZ_||1.8||4.3|ns|
|_tZX1_||1.8||4.3|ns|
|_tZX2_||–||–|ns|
|_tZX3_||5.3||8.3|ns|



_**Table 27. EPF8282AV Interconnect Timing Parameters**_ 

|**_Table 27. EPF8282AV Interconnect Timing Parameters_**|**_Table 27. EPF8282AV Interconnect Timing Parameters_**|**_Table 27. EPF8282AV Interconnect Timing Parameters_**|**_Table 27. EPF8282AV Interconnect Timing Parameters_**|**_Table 27. EPF8282AV Interconnect Timing Parameters_**|**_Table 27. EPF8282AV Interconnect Timing Parameters_**|
|---|---|---|---|---|---|
|**Symbol**|**Speed Grade**||||**Unit**|
||**A-3**||**A-4**|||
||**Min**|**Max**|**Min**|**Max**||
|_tLABCASC_||0.4||1.3|ns|
|_tLABCARRY_||0.4||0.8|ns|
|_tLOCAL_||0.8||1.5|ns|
|_tROW_||4.2||6.3|ns|
|_tCOL_||2.5||3.8|ns|
|_tDIN_C_||5.5||8.0|ns|
|_tDIN_D_||7.2||10.8|ns|
|_tDIN_IO_||5.5||9.0|ns|



**Altera Corporation** 

**39** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

_**Table 28. EPF8282AV Logic Element Timing Parameters**_ 

|**_Table 28. EPF8282AV Logic Element Timing Parameters_**|**_Table 28. EPF8282AV Logic Element Timing Parameters_**|**_Table 28. EPF8282AV Logic Element Timing Parameters_**|**_Table 28. EPF8282AV Logic Element Timing Parameters_**|**_Table 28. EPF8282AV Logic Element Timing Parameters_**|**_Table 28. EPF8282AV Logic Element Timing Parameters_**|
|---|---|---|---|---|---|
|**Symbol**|**Speed Grade**||||**Unit**|
||**A-3**||**A-4**|||
||**Min**|**Max**|**Min**|**Max**||
|_tLUT_||3.2||7.3|ns|
|_tCLUT_||0.0||1.4|ns|
|_tRLUT_||1.5||5.1|ns|
|_tGATE_||0.0||0.0|ns|
|_tCASC_||0.9||2.8|ns|
|_tCICO_||0.6||1.5|ns|
|_tCGEN_||0.7||2.2|ns|
|_tCGENR_||1.5||3.7|ns|
|_tC_||2.5||4.7|ns|
|_tCH_|4.0||6.0||ns|
|_tCL_|4.0||6.0||ns|
|_tCO_||0.6||0.9|ns|
|_tCOMB_||0.6||0.9|ns|
|_tSU_|1.2||2.4||ns|
|_tH_|1.5||4.6||ns|
|_tPRE_||0.8||1.3|ns|
|_tCLR_||0.8||1.3|ns|



_**Table 29. EPF8282AV External Timing Parameters**_ 

|**_Table 29. EPF8282AV External Timing Parameters_**|**_Table 29. EPF8282AV External Timing Parameters_**|**_Table 29. EPF8282AV External Timing Parameters_**|**_Table 29. EPF8282AV External Timing Parameters_**|**_Table 29. EPF8282AV External Timing Parameters_**|**_Table 29. EPF8282AV External Timing Parameters_**|
|---|---|---|---|---|---|
|**Symbol**|**Speed Grade**||||**Unit**|
||**A-3**||**A-4**|||
||**Min**|**Max**|**Min**|**Max**||
|**tDRR**||24.8||50.1|ns|
|**tODH**|1.0||1.0||ns|



**Altera Corporation** 

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**FLEX 8000 Programmable Logic Device Family Data Sheet** 

## _**Table 30. EPF8452A I/O Element Timing Parameters**_ 

|**_Table 30. EPF8452A I/O Element Timing Parameters_**|**_Table 30. EPF8452A I/O Element Timing Parameters_**|**_Table 30. EPF8452A I/O Element Timing Parameters_**|**_Table 30. EPF8452A I/O Element Timing Parameters_**|**_Table 30. EPF8452A I/O Element Timing Parameters_**|**_Table 30. EPF8452A I/O Element Timing Parameters_**|**_Table 30. EPF8452A I/O Element Timing Parameters_**|**_Table 30. EPF8452A I/O Element Timing Parameters_**|
|---|---|---|---|---|---|---|---|
|**Symbol**|**Speed Grade**||||||**Unit**|
||**A-2**||**A-3**||**A-4**|||
||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|_tIOD_||0.7||0.8||0.9|ns|
|_tIOC_||1.7||1.8||1.9|ns|
|_tIOE_||1.7||1.8||1.9|ns|
|_tIOCO_||1.0||1.0||1.0|ns|
|_tIOCOMB_||0.3||0.2||0.1|ns|
|_tIOSU_|1.4||1.6||1.8||ns|
|_tIOH_|0.0||0.0||0.0||ns|
|_tIOCLR_||1.2||1.2||1.2|ns|
|_tIN_||1.5||1.6||1.7|ns|
|_tOD1_||1.1||1.4||1.7|ns|
|_tOD2_||–||–||–|ns|
|_tOD3_||4.6||4.9||5.2|ns|
|_tXZ_||1.4||1.6||1.8|ns|
|_tZX1_||1.4||1.6||1.8|ns|
|_tZX2_||–||–||–|ns|
|_tZX3_||4.9||5.1||5.3|ns|



_**Table 31. EPF8452A Interconnect Timing Parameters**_ 

|**_Table 31. EPF8452A Interconnect Timing Parameters_**|**_Table 31. EPF8452A Interconnect Timing Parameters_**|**_Table 31. EPF8452A Interconnect Timing Parameters_**|**_Table 31. EPF8452A Interconnect Timing Parameters_**|**_Table 31. EPF8452A Interconnect Timing Parameters_**|**_Table 31. EPF8452A Interconnect Timing Parameters_**|**_Table 31. EPF8452A Interconnect Timing Parameters_**|**_Table 31. EPF8452A Interconnect Timing Parameters_**|
|---|---|---|---|---|---|---|---|
|**Symbol**|**Speed Grade**||||||**Unit**|
||**A-2**||**A-3**||**A-4**|||
||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|_tLABCASC_||0.3||0.4||0.4|ns|
|_tLABCARRY_||0.3||0.4||0.4|ns|
|_tLOCAL_||0.5||0.5||0.7|ns|
|_tROW_||5.0||5.0||5.0|ns|
|_tCOL_||3.0||3.0||3.0|ns|
|_tDIN_C_||5.0||5.0||5.5|ns|
|_tDIN_D_||7.0||7.0||7.5|ns|
|_tDIN_IO_||5.0||5.0||5.5|ns|



**Altera Corporation** 

**41** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

_**Table 32. EPF8452A LE Timing Parameters**_ 

|**_Table 32. EPF8452A LE Timing Parameters_**|**_Table 32. EPF8452A LE Timing Parameters_**|**_Table 32. EPF8452A LE Timing Parameters_**|**_Table 32. EPF8452A LE Timing Parameters_**|**_Table 32. EPF8452A LE Timing Parameters_**|**_Table 32. EPF8452A LE Timing Parameters_**|**_Table 32. EPF8452A LE Timing Parameters_**|**_Table 32. EPF8452A LE Timing Parameters_**|
|---|---|---|---|---|---|---|---|
|**Symbol**|**Speed Grade**||||||**Unit**|
||**A-2**||**A-3**||**A-4**|||
||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|_tLUT_||2.0||2.3||3.0|ns|
|_tCLUT_||0.0||0.2||0.1|ns|
|_tRLUT_||0.9||1.6||1.6|ns|
|_tGATE_||0.0||0.0||0.0|ns|
|_tCASC_||0.6||0.7||0.9|ns|
|_tCICO_||0.4||0.5||0.6|ns|
|_tCGEN_||0.4||0.9||0.8|ns|
|_tCGENR_||0.9||1.4||1.5|ns|
|_tC_||1.6||1.8||2.4|ns|
|_tCH_|4.0||4.0||4.0||ns|
|_tCL_|4.0||4.0||4.0||ns|
|_tCO_||0.4||0.5||0.6|ns|
|_tCOMB_||0.4||0.5||0.6|ns|
|_tSU_|0.8||1.0||1.1||ns|
|_tH_|0.9||1.1||1.4||ns|
|_tPRE_||0.6||0.7||0.8|ns|
|_tCLR_||0.6||0.7||0.8|ns|



## _**Table 33. EPF8452A External Timing Parameters**_ 

|**_Table 33. EPF8452A External Timing Parameters_**|**_Table 33. EPF8452A External Timing Parameters_**|**_Table 33. EPF8452A External Timing Parameters_**|**_Table 33. EPF8452A External Timing Parameters_**|**_Table 33. EPF8452A External Timing Parameters_**|**_Table 33. EPF8452A External Timing Parameters_**|**_Table 33. EPF8452A External Timing Parameters_**|**_Table 33. EPF8452A External Timing Parameters_**|
|---|---|---|---|---|---|---|---|
|**Symbol**|**Speed Grade**||||||**Unit**|
||**A-2**||**A-3**||**A-4**|||
||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|**tDRR**||16.0||20.0||25.0|ns|
|**tODH**|1.0||1.0||1.0||ns|



**Altera Corporation** 

**42** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

## _**Table 34. EPF8636A I/O Element Timing Parameters**_ 

|**_Table 34. EPF8636A I/O Element Timing Parameters_**|**_Table 34. EPF8636A I/O Element Timing Parameters_**|**_Table 34. EPF8636A I/O Element Timing Parameters_**|**_Table 34. EPF8636A I/O Element Timing Parameters_**|**_Table 34. EPF8636A I/O Element Timing Parameters_**|**_Table 34. EPF8636A I/O Element Timing Parameters_**|**_Table 34. EPF8636A I/O Element Timing Parameters_**|**_Table 34. EPF8636A I/O Element Timing Parameters_**|
|---|---|---|---|---|---|---|---|
|**Symbol**|**Speed Grade**||||||**Unit**|
||**A-2**||**A-3**||**A-4**|||
||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|_tIOD_||0.7||0.8||0.9|ns|
|_tIOC_||1.7||1.8||1.9|ns|
|_tIOE_||1.7||1.8||1.9|ns|
|_tIOCO_||1.0||1.0||1.0|ns|
|_tIOCOMB_||0.3||0.2||0.1|ns|
|_tIOSU_|1.4||1.6||1.8||ns|
|_tIOH_|0.0||0.0||0.0||ns|
|_tIOCLR_||1.2||1.2||1.2|ns|
|_tIN_||1.5||1.6||1.7|ns|
|_tOD1_||1.1||1.4||1.7|ns|
|_tOD2_||1.6||1.9||2.2|ns|
|_tOD3_||4.6||4.9||5.2|ns|
|_tXZ_||1.4||1.6||1.8|ns|
|_tZX1_||1.4||1.6||1.8|ns|
|_tZX2_||1.9||2.1||2.3|ns|
|_tZX3_||4.9||5.1||5.3|ns|



## _**Table 35. EPF8636A Interconnect Timing Parameters**_ 

|**_Table 35. EPF8636A Interconnect Timing Parameters_**|**_Table 35. EPF8636A Interconnect Timing Parameters_**|**_Table 35. EPF8636A Interconnect Timing Parameters_**|**_Table 35. EPF8636A Interconnect Timing Parameters_**|**_Table 35. EPF8636A Interconnect Timing Parameters_**|**_Table 35. EPF8636A Interconnect Timing Parameters_**|**_Table 35. EPF8636A Interconnect Timing Parameters_**|**_Table 35. EPF8636A Interconnect Timing Parameters_**|
|---|---|---|---|---|---|---|---|
|**Symbol**|**Speed Grade**||||||**Unit**|
||**A-2**||**A-3**||**A-4**|||
||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|_tLABCASC_||0.3||0.4||0.4|ns|
|_tLABCARRY_||0.3||0.4||0.4|ns|
|_tLOCAL_||0.5||0.5||0.7|ns|
|_tROW_||5.0||5.0||5.0|ns|
|_tCOL_||3.0||3.0||3.0|ns|
|_tDIN_C_||5.0||5.0||5.5|ns|
|_tDIN_D_||7.0||7.0||7.5|ns|
|_tDIN_IO_||5.0||5.0||5.5|ns|



**Altera Corporation** 

**43** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

## _**Table 36. EPF8636A LE Timing Parameters**_ 

|**_Table 36. EPF8636A LE Timing Parameters_**|**_Table 36. EPF8636A LE Timing Parameters_**|**_Table 36. EPF8636A LE Timing Parameters_**|**_Table 36. EPF8636A LE Timing Parameters_**|**_Table 36. EPF8636A LE Timing Parameters_**|**_Table 36. EPF8636A LE Timing Parameters_**|**_Table 36. EPF8636A LE Timing Parameters_**|**_Table 36. EPF8636A LE Timing Parameters_**|
|---|---|---|---|---|---|---|---|
|**Symbol**|**Speed Grade**||||||**Unit**|
||**A-2**||**A-3**||**A-4**|||
||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|_tLUT_||2.0||2.3||3.0|ns|
|_tCLUT_||0.0||0.2||0.1|ns|
|_tRLUT_||0.9||1.6||1.6|ns|
|_tGATE_||0.0||0.0||0.0|ns|
|_tCASC_||0.6||0.7||0.9|ns|
|_tCICO_||0.4||0.5||0.6|ns|
|_tCGEN_||0.4||0.9||0.8|ns|
|_tCGENR_||0.9||1.4||1.5|ns|
|_tC_||1.6||1.8||2.4|ns|
|_tCH_|4.0||4.0||4.0||ns|
|_tCL_|4.0||4.0||4.0||ns|
|_tCO_||0.4||0.5||0.6|ns|
|_tCOMB_||0.4||0.5||0.6|ns|
|_tSU_|0.8||1.0||1.1||ns|
|_tH_|0.9||1.1||1.4||ns|
|_tPRE_||0.6||0.7||0.8|ns|
|_tCLR_||0.6||0.7||0.8|ns|



## _**Table 37. EPF8636A External Timing Parameters**_ 

|**_Table 37. EPF8636A External Timing Parameters_**|**_Table 37. EPF8636A External Timing Parameters_**|**_Table 37. EPF8636A External Timing Parameters_**|**_Table 37. EPF8636A External Timing Parameters_**|**_Table 37. EPF8636A External Timing Parameters_**|**_Table 37. EPF8636A External Timing Parameters_**|**_Table 37. EPF8636A External Timing Parameters_**|**_Table 37. EPF8636A External Timing Parameters_**|
|---|---|---|---|---|---|---|---|
|**Symbol**|**Speed Grade**||||||**Unit**|
||**A-2**||**A-3**||**A-4**|||
||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|**tDRR**||16.0||20.0||25.0|ns|
|**tODH**|1.0||1.0||1.0||ns|



**Altera Corporation** 

**44** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

## _**Table 38. EPF8820A I/O Element Timing Parameters**_ 

|**_Table 38. EPF8820A I/O Element Timing Parameters_**|**_Table 38. EPF8820A I/O Element Timing Parameters_**|**_Table 38. EPF8820A I/O Element Timing Parameters_**|**_Table 38. EPF8820A I/O Element Timing Parameters_**|**_Table 38. EPF8820A I/O Element Timing Parameters_**|**_Table 38. EPF8820A I/O Element Timing Parameters_**|**_Table 38. EPF8820A I/O Element Timing Parameters_**|**_Table 38. EPF8820A I/O Element Timing Parameters_**|
|---|---|---|---|---|---|---|---|
|**Symbol**|**Speed Grade**||||||**Unit**|
||**A-2**||**A-3**||**A-4**|||
||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|_tIOD_||0.7||0.8||0.9|ns|
|_tIOC_||1.7||1.8||1.9|ns|
|_tIOE_||1.7||1.8||1.9|ns|
|_tIOCO_||1.0||1.0||1.0|ns|
|_tIOCOMB_||0.3||0.2||0.1|ns|
|_tIOSU_|1.4||1.6||1.8||ns|
|_tIOH_|0.0||0.0||0.0||ns|
|_tIOCLR_||1.2||1.2||1.2|ns|
|_tIN_||1.5||1.6||1.7|ns|
|_tOD1_||1.1||1.4||1.7|ns|
|_tOD2_||1.6||1.9||2.2|ns|
|_tOD3_||4.6||4.9||5.2|ns|
|_tXZ_||1.4||1.6||1.8|ns|
|_tZX1_||1.4||1.6||1.8|ns|
|_tZX2_||1.9||2.1||2.3|ns|
|_tZX3_||4.9||5.1||5.3|ns|



## _**Table 39. EPF8820A Interconnect Timing Parameters**_ 

|**_Table 39. EPF8820A Interconnect Timing Parameters_**|**_Table 39. EPF8820A Interconnect Timing Parameters_**|**_Table 39. EPF8820A Interconnect Timing Parameters_**|**_Table 39. EPF8820A Interconnect Timing Parameters_**|**_Table 39. EPF8820A Interconnect Timing Parameters_**|**_Table 39. EPF8820A Interconnect Timing Parameters_**|**_Table 39. EPF8820A Interconnect Timing Parameters_**|**_Table 39. EPF8820A Interconnect Timing Parameters_**|
|---|---|---|---|---|---|---|---|
|**Symbol**|**Speed Grade**||||||**Unit**|
||**A-2**||**A-3**||**A-4**|||
||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|_tLABCASC_||0.3||0.3||0.4|ns|
|_tLABCARRY_||0.3||0.3||0.4|ns|
|_tLOCAL_||0.5||0.6||0.8|ns|
|_tROW_||5.0||5.0||5.0|ns|
|_tCOL_||3.0||3.0||3.0|ns|
|_tDIN_C_||5.0||5.0||5.5|ns|
|_tDIN_D_||7.0||7.0||7.5|ns|
|_tDIN_IO_||5.0||5.0||5.5|ns|



**Altera Corporation** 

**45** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

_**Table 40. EPF8820A LE Timing Parameters**_ 

|**_Table 40. EPF8820A LE Timing Parameters_**|**_Table 40. EPF8820A LE Timing Parameters_**|**_Table 40. EPF8820A LE Timing Parameters_**|**_Table 40. EPF8820A LE Timing Parameters_**|**_Table 40. EPF8820A LE Timing Parameters_**|**_Table 40. EPF8820A LE Timing Parameters_**|**_Table 40. EPF8820A LE Timing Parameters_**|**_Table 40. EPF8820A LE Timing Parameters_**|
|---|---|---|---|---|---|---|---|
|**Symbol**|**Speed Grade**||||||**Unit**|
||**A-2**||**A-3**||**A-4**|||
||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|_tLUT_||2.0||2.5||3.2|ns|
|_tCLUT_||0.0||0.0||0.0|ns|
|_tRLUT_||0.9||1.1||1.5|ns|
|_tGATE_||0.0||0.0||0.0|ns|
|_tCASC_||0.6||0.7||0.9|ns|
|_tCICO_||0.4||0.5||0.6|ns|
|_tCGEN_||0.4||0.5||0.7|ns|
|_tCGENR_||0.9||1.1||1.5|ns|
|_tC_||1.6||2.0||2.5|ns|
|_tCH_|4.0||4.0||4.0||ns|
|_tCL_|4.0||4.0||4.0||ns|
|_tCO_||0.4||0.5||0.6|ns|
|_tCOMB_||0.4||0.5||0.6|ns|
|_tSU_|0.8||1.1||1.2||ns|
|_tH_|0.9||1.1||1.5||ns|
|_tPRE_||0.6||0.7||0.8|ns|
|_tCLR_||0.6||0.7||0.8|ns|



## _**Table 41. EPF8820A External Timing Parameters**_ 

|**_Table 41. EPF8820A External Timing Parameters_**|**_Table 41. EPF8820A External Timing Parameters_**|**_Table 41. EPF8820A External Timing Parameters_**|**_Table 41. EPF8820A External Timing Parameters_**|**_Table 41. EPF8820A External Timing Parameters_**|**_Table 41. EPF8820A External Timing Parameters_**|**_Table 41. EPF8820A External Timing Parameters_**|**_Table 41. EPF8820A External Timing Parameters_**|
|---|---|---|---|---|---|---|---|
|**Symbol**|**Speed Grade**||||||**Unit**|
||**A-2**||**A-3**||**A-4**|||
||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|**tDRR**||16.0||20.0||25.0|ns|
|**tODH**|1.0||1.0||1.0||ns|



**Altera Corporation** 

**46** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

## _**Table 42. EPF81188A I/O Element Timing Parameters**_ 

|**_Table 42. EPF81188A I/O Element Timing Parameters_**|**_Table 42. EPF81188A I/O Element Timing Parameters_**|**_Table 42. EPF81188A I/O Element Timing Parameters_**|**_Table 42. EPF81188A I/O Element Timing Parameters_**|**_Table 42. EPF81188A I/O Element Timing Parameters_**|**_Table 42. EPF81188A I/O Element Timing Parameters_**|**_Table 42. EPF81188A I/O Element Timing Parameters_**|**_Table 42. EPF81188A I/O Element Timing Parameters_**|
|---|---|---|---|---|---|---|---|
|**Symbol**|**Speed Grade**||||||**Unit**|
||**A-2**||**A-3**||**A-4**|||
||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|_tIOD_||0.7||0.8||0.9|ns|
|_tIOC_||1.7||1.8||1.9|ns|
|_tIOE_||1.7||1.8||1.9|ns|
|_tIOCO_||1.0||1.0||1.0|ns|
|_tIOCOMB_||0.3||0.2||0.1|ns|
|_tIOSU_|1.4||1.6||1.8||ns|
|_tIOH_|0.0||0.0||0.0||ns|
|_tIOCLR_||1.2||1.2||1.2|ns|
|_tIN_||1.5||1.6||1.7|ns|
|_tOD1_||1.1||1.4||1.7|ns|
|_tOD2_||1.6||1.9||2.2|ns|
|_tOD3_||4.6||4.9||5.2|ns|
|_tXZ_||1.4||1.6||1.8|ns|
|_tZX1_||1.4||1.6||1.8|ns|
|_tZX2_||1.9||2.1||2.3|ns|
|_tZX3_||4.9||5.1||5.3|ns|



## _**Table 43. EPF81188A Interconnect Timing Parameters**_ 

|**_Table 43. EPF81188A Interconnect Timing Parameters_**|**_Table 43. EPF81188A Interconnect Timing Parameters_**|**_Table 43. EPF81188A Interconnect Timing Parameters_**|**_Table 43. EPF81188A Interconnect Timing Parameters_**|**_Table 43. EPF81188A Interconnect Timing Parameters_**|**_Table 43. EPF81188A Interconnect Timing Parameters_**|**_Table 43. EPF81188A Interconnect Timing Parameters_**|**_Table 43. EPF81188A Interconnect Timing Parameters_**|
|---|---|---|---|---|---|---|---|
|**Symbol**|**Speed Grade**||||||**Unit**|
||**A-2**||**A-3**||**A-4**|||
||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|_tLABCASC_||0.3||0.3||0.4|ns|
|_tLABCARRY_||0.3||0.3||0.4|ns|
|_tLOCAL_||0.5||0.6||0.8|ns|
|_tROW_||5.0||5.0||5.0|ns|
|_tCOL_||3.0||3.0||3.0|ns|
|_tDIN_C_||5.0||5.0||5.5|ns|
|_tDIN_D_||7.0||7.0||7.5|ns|
|_tDIN_IO_||5.0||5.0||5.5|ns|



**Altera Corporation** 

**47** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

## _**Table 44. EPF81188A LE Timing Parameters**_ 

|**_Table 44. EPF81188A LE Timing Parameters_**|**_Table 44. EPF81188A LE Timing Parameters_**|**_Table 44. EPF81188A LE Timing Parameters_**|**_Table 44. EPF81188A LE Timing Parameters_**|**_Table 44. EPF81188A LE Timing Parameters_**|**_Table 44. EPF81188A LE Timing Parameters_**|**_Table 44. EPF81188A LE Timing Parameters_**|**_Table 44. EPF81188A LE Timing Parameters_**|
|---|---|---|---|---|---|---|---|
|**Symbol**|**Speed Grade**||||||**Unit**|
||**A-2**||**A-3**||**A-4**|||
||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|_tLUT_||2.0||2.5||3.2|ns|
|_tCLUT_||0.0||0.0||0.0|ns|
|_tRLUT_||0.9||1.1||1.5|ns|
|_tGATE_||0.0||0.0||0.0|ns|
|_tCASC_||0.6||0.7||0.9|ns|
|_tCICO_||0.4||0.5||0.6|ns|
|_tCGEN_||0.4||0.5||0.7|ns|
|_tCGENR_||0.9||1.1||1.5|ns|
|_tC_||1.6||2.0||2.5|ns|
|_tCH_|4.0||4.0||4.0||ns|
|_tCL_|4.0||4.0||4.0||ns|
|_tCO_||0.4||0.5||0.6|ns|
|_tCOMB_||0.4||0.5||0.6|ns|
|_tSU_|0.8||1.1||1.2||ns|
|_tH_|0.9||1.1||1.5||ns|
|_tPRE_||0.6||0.7||0.8|ns|
|_tCLR_||0.6||0.7||0.8|ns|



## _**Table 45. EPF81188A External Timing Parameters**_ 

|**_Table 45. EPF81188A External Timing Parameters_**|**_Table 45. EPF81188A External Timing Parameters_**|**_Table 45. EPF81188A External Timing Parameters_**|**_Table 45. EPF81188A External Timing Parameters_**|**_Table 45. EPF81188A External Timing Parameters_**|**_Table 45. EPF81188A External Timing Parameters_**|**_Table 45. EPF81188A External Timing Parameters_**|**_Table 45. EPF81188A External Timing Parameters_**|
|---|---|---|---|---|---|---|---|
|**Symbol**|**Speed Grade**||||||**Unit**|
||**A-2**||**A-3**||**A-4**|||
||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|**tDRR**||16.0||20.0||25.0|ns|
|**tODH**|1.0||1.0||1.0||ns|



**Altera Corporation** 

**48** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

## _**Table 46. EPF81500A I/O Element Timing Parameters**_ 

|**_Table 46. EPF81500A I/O Element Timing Parameters_**|**_Table 46. EPF81500A I/O Element Timing Parameters_**|**_Table 46. EPF81500A I/O Element Timing Parameters_**|**_Table 46. EPF81500A I/O Element Timing Parameters_**|**_Table 46. EPF81500A I/O Element Timing Parameters_**|**_Table 46. EPF81500A I/O Element Timing Parameters_**|**_Table 46. EPF81500A I/O Element Timing Parameters_**|**_Table 46. EPF81500A I/O Element Timing Parameters_**|
|---|---|---|---|---|---|---|---|
|**Symbol**|**Speed Grade**||||||**Unit**|
||**A-2**||**A-3**||**A-4**|||
||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|_tIOD_||0.7||0.8||0.9|ns|
|_tIOC_||1.7||1.8||1.9|ns|
|_tIOE_||1.7||1.8||1.9|ns|
|_tIOCO_||1.0||1.0||1.0|ns|
|_tIOCOMB_||0.3||0.2||0.1|ns|
|_tIOSU_|1.4||1.6||1.8||ns|
|_tIOH_|0.0||0.0||0.0||ns|
|_tIOCLR_||1.2||1.2||1.2|ns|
|_tIN_||1.5||1.6||1.7|ns|
|_tOD1_||1.1||1.4||1.7|ns|
|_tOD2_||1.6||1.9||2.2|ns|
|_tOD3_||4.6||4.9||5.2|ns|
|_tXZ_||1.4||1.6||1.8|ns|
|_tZX1_||1.4||1.6||1.8|ns|
|_tZX2_||1.9||2.1||2.3|ns|
|_tZX3_||4.9||5.1||5.3|ns|



_**Table 47. EPF81500A Interconnect Timing Parameters**_ 

|**_Table 47. EPF81500A Interconnect Timing Parameters_**|**_Table 47. EPF81500A Interconnect Timing Parameters_**|**_Table 47. EPF81500A Interconnect Timing Parameters_**|**_Table 47. EPF81500A Interconnect Timing Parameters_**|**_Table 47. EPF81500A Interconnect Timing Parameters_**|**_Table 47. EPF81500A Interconnect Timing Parameters_**|**_Table 47. EPF81500A Interconnect Timing Parameters_**|**_Table 47. EPF81500A Interconnect Timing Parameters_**|
|---|---|---|---|---|---|---|---|
|**Symbol**|**Speed Grade**||||||**Unit**|
||**A-2**||**A-3**||**A-4**|||
||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|_tLABCASC_||0.3||0.3||0.4|ns|
|_tLABCARRY_||0.3||0.3||0.4|ns|
|_tLOCAL_||0.5||0.6||0.8|ns|
|_tROW_||6.2||6.2||6.2|ns|
|_tCOL_||3.0||3.0||3.0|ns|
|_tDIN_C_||5.0||5.0||5.5|ns|
|_tDIN_D_||8.2||8.2||8.7|ns|
|_tDIN_IO_||5.0||5.0||5.5|ns|



**Altera Corporation** 

**49** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

_**Table 48. EPF81500A LE Timing Parameters**_ 

|**_Table 48. EPF81500A LE Timing Parameters_**|**_Table 48. EPF81500A LE Timing Parameters_**|**_Table 48. EPF81500A LE Timing Parameters_**|**_Table 48. EPF81500A LE Timing Parameters_**|**_Table 48. EPF81500A LE Timing Parameters_**|**_Table 48. EPF81500A LE Timing Parameters_**|**_Table 48. EPF81500A LE Timing Parameters_**|**_Table 48. EPF81500A LE Timing Parameters_**|
|---|---|---|---|---|---|---|---|
|**Symbol**|**Speed Grade**||||||**Unit**|
||**A-2**||**A-3**||**A-4**|||
||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|_tLUT_||2.0||2.5||3.2|ns|
|_tCLUT_||0.0||0.0||0.0|ns|
|_tRLUT_||0.9||1.1||1.5|ns|
|_tGATE_||0.0||0.0||0.0|ns|
|_tCASC_||0.6||0.7||0.9|ns|
|_tCICO_||0.4||0.5||0.6|ns|
|_tCGEN_||0.4||0.5||0.7|ns|
|_tCGENR_||0.9||1.1||1.5|ns|
|_tC_||1.6||2.0||2.5|ns|
|_tCH_|4.0||4.0||4.0||ns|
|_tCL_|4.0||4.0||4.0||ns|
|_tCO_||0.4||0.5||0.6|ns|
|_tCOMB_||0.4||0.5||0.6|ns|
|_tSU_|0.8||1.1||1.2||ns|
|_tH_|0.9||1.1||1.5||ns|
|_tPRE_||0.6||0.7||0.8|ns|
|_tCLR_||0.6||0.7||0.8|ns|



_**Table 49. EPF81500A External Timing Parameters**_ 

|**_Table 49. EPF81500A External Timing Parameters_**|**_Table 49. EPF81500A External Timing Parameters_**|**_Table 49. EPF81500A External Timing Parameters_**|**_Table 49. EPF81500A External Timing Parameters_**|**_Table 49. EPF81500A External Timing Parameters_**|**_Table 49. EPF81500A External Timing Parameters_**|**_Table 49. EPF81500A External Timing Parameters_**|**_Table 49. EPF81500A External Timing Parameters_**|
|---|---|---|---|---|---|---|---|
|**Symbol**|**Speed Grade**||||||**Unit**|
||**A-2**||**A-3**||**A-4**|||
||**Min**|**Max**|**Min**|**Max**|**Min**|**Max**||
|**tDRR**||16.1||20.1||25.1|ns|
|**tODH**|1.0||1.0||1.0||ns|



**Altera Corporation** 

**50** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

## **Power Consumption** 

The supply power (P) for FLEX 8000 devices can be calculated with the following equation: 

**==> picture [229 x 10] intentionally omitted <==**

Typical I CCSTANDBY values are shown as I CC0 in Table 11 on page 28 and Table 15 on page 30. The PIO value, which depends on the device output load characteristics and switching frequency, can be calculated using the guidelines given in _Application Note 74 (Evaluating Power for Altera Devices)_ . The ICCACTIVE value depends on the switching frequency and the application logic. This value can be calculated based on the amount of current that each LE typically consumes. 

The following equation shows the general formula for calculating ICCACTIVE: 

ICCACTIVE = K × **fMAX** × N × **togLC** × --------------------------MHz µ A × LE **-** 

The parameters in this equation are shown below: 

**fMAX** = Maximum operating frequency in MHz N = Total number of logic cells used in the device **togLC** = Average percentage of logic cells toggling at each clock K = Constant, shown in Table 50 

## _**Table 50. Values for Constant K**_ 

|**_Table 50. Values for Constant K_**|**_Table 50. Values for Constant K_**|
|---|---|
|**Device**|**K**|
|5.0-V FLEX 8000 devices|75|
|3.3-V FLEX 8000 devices|60|



This calculation provides an ICC estimate based on typical conditions with no output load. The actual I CC value should be verified during operation because this measurement is sensitive to the actual pattern in the device and the environmental operating conditions. 

Figure 20 shows the relationship between ICC and operating frequency for several LE utilization values. 

**Altera Corporation** 

**51** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

_**Figure 20.  FLEX 8000 I CCACTIVE vs. Operating Frequency**_ 

## **5.0-V FLEX 8000 Devices** 

**==> picture [277 x 390] intentionally omitted <==**

**----- Start of picture text -----**<br>
1,000<br>1,500 LEs<br>800<br>600<br>ICC Supply 1,000 LEs<br>Current (mA)<br>400<br>500 LEs<br>200<br>0 30 60<br>Frequency (MHz)<br>3.3-V FLEX 8000 Devices<br>100<br>90 200 LEs<br>80<br>70 150 LEs<br>60<br>Current (mA)ICC Supply 50 100 LEs<br>40<br>30<br>50 LEs<br>20<br>10<br>0 30 60<br>Frequency (MHz)<br>**----- End of picture text -----**<br>


## **Configuration & Operation** 

f 

The FLEX 8000 architecture supports several configuration schemes to load a design into the device(s) on the circuit board. This section summarizes the device operating modes and available device configuration schemes. 

For more information, go to _Application Note 33 (Configuring FLEX 8000 Devices)_ and _Application Note 38 (Configuring Multiple FLEX 8000 Devices)_ . 

**Altera Corporation** 

**52** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

## **Operating Modes** 

The FLEX 8000 architecture uses SRAM elements that require configuration data to be loaded whenever the device powers up and begins operation. The process of physically loading the SRAM programming data into the device is called _configuration_ . During initialization, which occurs immediately after configuration, the device resets registers, enables I/O pins, and begins to operate as a logic device. The I/O pins are tri-stated during power-up, and before and during configuration. The configuration and initialization processes together are called _command mode_ ; normal device operation is called _user mode_ . 

SRAM elements allow FLEX 8000 devices to be reconfigured in-circuit with new programming data that is loaded into the device. Real-time reconfiguration is performed by forcing the device into command mode with a device pin, loading different programming data, reinitializing the device, and resuming user-mode operation. The entire reconfiguration process requires less than 100 ms and can be used to dynamically reconfigure an entire system. In-field upgrades can be performed by distributing new configuration files. 

## **Configuration Schemes** 

The configuration data for a FLEX 8000 device can be loaded with one of six configuration schemes, chosen on the basis of the target application. Both active and passive schemes are available. In the active configuration schemes, the FLEX 8000 device functions as the controller, directing the loading operation, controlling external configuration devices, and completing the loading process. The clock source for all active configuration schemes is an oscillator on the FLEX 8000 device that operates between 2 MHz and 6 MHz. In the passive configuration schemes, an external controller guides the FLEX 8000 device. Table 51 shows the data source for each of the six configuration schemes. 

_**Table 51. Data Source for Configuration**_ 

|**_Table 51. Data Source for Configuration_**|**_Table 51. Data Source for Configuration_**|**_Table 51. Data Source for Configuration_**|
|---|---|---|
|**Configuration Scheme**|**Acronym**|**Data Source**|
|Active serial|AS|Altera configuration device|
|Active parallel up|APU|Parallel configuration device|
|Active parallel down|APD|Parallel configuration device|
|Passive serial|PS|Serial data path|
|Passive parallel synchronous|PPS|Intelligent host|
|Passive parallel asynchronous|PPA|Intelligent host|



**Altera Corporation** 

**53** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

## **Device Pin-Outs** 

Tables 52 through 54 show the pin names and numbers for the dedicated pins in each FLEX 8000 device package. 

_**Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs  (Part 1 of 3)**_ 

|**_Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs  (Part 1 of 3)_**|**_Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs  (Part 1 of 3)_**|**_Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs  (Part 1 of 3)_**|**_Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs  (Part 1 of 3)_**|**_Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs  (Part 1 of 3)_**|**_Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs  (Part 1 of 3)_**|**_Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs  (Part 1 of 3)_**|**_Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs  (Part 1 of 3)_**|
|---|---|---|---|---|---|---|---|
|**Pin Name**|**84-Pin**<br>**PLCC**<br>**EPF8282A**|**84-Pin**<br>**PLCC**<br>**EPF8452A**<br>**EPF8636A**|**100-Pin**<br>**TQFP**<br>**EPF8282A**<br>**EPF8282AV**|**100-Pin**<br>**TQFP**<br>**EPF8452A**|**144-Pin**<br>**TQFP**<br>**EPF8820A**|**160-Pin**<br>**PGA**<br>**EPF8452A**|**160-Pin**<br>**PQFP**<br>**EPF8820A**<br>_(1)_|
|`nSP` _(2)_|75|75|75|76|110|R1|1|
|`MSEL0` _(2)_|74|74|74|75|109|P2|2|
|`MSEL1` _(2)_|53|53|51|51|72|A1|44|
|`nSTATUS` _(2)_|32|32|24|25|37|C13|82|
|`nCONFIG` _(2)_|33|33|25|26|38|A15|81|
|`DCLK` _(2)_|10|10|100|100|143|P14|125|
|`CONF_DONE` _(2)_|11|11|1|1|144|N13|124|
|`nWS`|30|30|22|23|33|F13|87|
|`nRS`|48|48|42|45|31|C6|89|
|`RDCLK`|49|49|45|46|12|B5|110|
|`nCS`|29|29|21|22|4|D15|118|
|`CS`|28|28|19|21|3|E15|121|
|`RDYnBUSY`|77|77|77|78|20|P3|100|
|`CLKUSR`|50|50|47|47|13|C5|107|
|`ADD17`|51|51|49|48|75|B4|40|
|`ADD16`|36|55|28|54|76|E2|39|
|`ADD15`|56|56|55|55|77|D1|38|
|`ADD14`|57|57|57|57|78|E1|37|
|`ADD13`|58|58|58|58|79|F3|36|
|`ADD12`|60|60|59|60|83|F2|32|
|`ADD11`|61|61|60|61|85|F1|30|
|`ADD10`|62|62|61|62|87|G2|28|
|`ADD9`|63|63|62|64|89|G1|26|
|`ADD8`|64|64|64|65|92|H1|22|
|`ADD7`|65|65|65|66|94|H2|20|
|`ADD6`|66|66|66|67|95|J1|18|
|`ADD5`|67|67|67|68|97|J2|16|
|`ADD4`|69|69|68|70|102|K2|11|
|`ADD3`|70|70|69|71|103|K1|10|
|`ADD2`|71|71|71|72|104|K3|8|
|`ADD1`|76|72|76|73|105|M1|7|



**Altera Corporation** 

**54** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

_**Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs  (Part 2 of 3)**_ 

|**_Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs  (Part 2 of 3)_**|**_Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs  (Part 2 of 3)_**|**_Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs  (Part 2 of 3)_**|**_Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs  (Part 2 of 3)_**|**_Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs  (Part 2 of 3)_**|**_Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs  (Part 2 of 3)_**|**_Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs  (Part 2 of 3)_**|**_Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs  (Part 2 of 3)_**|
|---|---|---|---|---|---|---|---|
|**Pin Name**|**84-Pin**<br>**PLCC**<br>**EPF8282A**|**84-Pin**<br>**PLCC**<br>**EPF8452A**<br>**EPF8636A**|**100-Pin**<br>**TQFP**<br>**EPF8282A**<br>**EPF8282AV**|**100-Pin**<br>**TQFP**<br>**EPF8452A**|**144-Pin**<br>**TQFP**<br>**EPF8820A**|**160-Pin**<br>**PGA**<br>**EPF8452A**|**160-Pin**<br>**PQFP**<br>**EPF8820A**<br>_(1)_|
|`ADD0`|78|76|78|77|106|N3|6|
|`DATA7`|3|2|90|89|131|P8|140|
|`DATA6`|4|4|91|91|132|P10|139|
|`DATA5`|6|6|92|95|133|R12|138|
|`DATA4`|7|7|95|96|134|R13|136|
|`DATA3`|8|8|97|97|135|P13|135|
|`DATA2`|9|9|99|98|137|R14|133|
|`DATA1`|13|13|4|4|138|N15|132|
|`DATA0`|14|14|5|5|140|K13|129|
|`SDOUT` _(3)_|79|78|79|79|23|P4|97|
|`TDI` _(4)_|55|45_(5)_|54|–|96|–|17|
|`TDO` _(4)_|27|27_(5)_|18|–|18|–|102|
|`TCK` _(4)_,_(6)_|72|44_(5)_|72|–|88|–|27|
|`TMS` _(4)_|20|43_(5)_|11|–|86|–|29|
|`TRST` _(7)_|52|52_(8)_|50|–|71|–|45|
|Dedicated<br>Inputs_(10)_|12, 31, 54,<br>73|12, 31, 54,<br>73|3, 23, 53, 73|3, 24, 53,<br>74|9, 26, 82,<br>99|C3, D14,<br>N2, R15|14, 33, 94,<br>113|
|`VCCINT`|17, 38, 59,<br>80|17, 38, 59,<br>80|6, 20, 37, 56,<br>70, 87|9, 32, 49,<br>59, 82|8, 28, 70,<br>90, 111|B2, C4, D3,<br>D8, D12,<br>G3, G12,<br>H4, H13,<br>J3, J12,<br>M4, M7,<br>M9, M13,<br>N12|3, 24, 46,<br>92, 114,<br>160|
|`VCCIO`|–|–|–|–|16, 40, 60,<br>69, 91,<br>112, 122,<br>141|–|23, 47, 57,<br>69, 79,<br>104, 127,<br>137, 149,<br>159|



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**FLEX 8000 Programmable Logic Device Family Data Sheet** 

_**Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs  (Part 3 of 3)**_ 

|**_Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs  (Part 3 of 3)_**|**_Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs  (Part 3 of 3)_**|**_Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs  (Part 3 of 3)_**|**_Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs  (Part 3 of 3)_**|**_Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs  (Part 3 of 3)_**|**_Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs  (Part 3 of 3)_**|**_Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs  (Part 3 of 3)_**|**_Table 52. FLEX 8000 84-, 100-, 144- & 160-Pin Package Pin-Outs  (Part 3 of 3)_**|
|---|---|---|---|---|---|---|---|
|**Pin Name**|**84-Pin**<br>**PLCC**<br>**EPF8282A**|**84-Pin**<br>**PLCC**<br>**EPF8452A**<br>**EPF8636A**|**100-Pin**<br>**TQFP**<br>**EPF8282A**<br>**EPF8282AV**|**100-Pin**<br>**TQFP**<br>**EPF8452A**|**144-Pin**<br>**TQFP**<br>**EPF8820A**|**160-Pin**<br>**PGA**<br>**EPF8452A**|**160-Pin**<br>**PQFP**<br>**EPF8820A**<br>_(1)_|
|`GND`|5, 26, 47, 68|5, 26, 47,<br>68|2, 13, 30, 44,<br>52, 63, 80,<br>94|19, 44, 69,<br>94|7, 17, 27,<br>39, 54,<br>80, 81,<br>100,101,<br>128, 142|C12, D4,<br>D7, D9,<br>D13, G4,<br>G13, H3,<br>H12, J4,<br>J13, L1,<br>M3, M8,<br>M12, M15,<br>N4|12, 13, 34,<br>35, 51, 63,<br>75, 80, 83,<br>93, 103,<br>115, 126,<br>131, 143,<br>155|
|No Connect<br>(N.C.)|–|–|–|2, 6, 13, 30,<br>37, 42, 43,<br>50, 52, 56,<br>63, 80, 87,<br>92, 93, 99|–|–|–|
|Total User I/O<br>Pins_(9)_|64|64|74|64|108|116|116|



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**FLEX 8000 Programmable Logic Device Family Data Sheet** 

_**Table 53.  FLEX 8000 160-, 192- & 208-Pin Package Pin-Outs (Part 1 of 2)**_ 

|**_Table 53.  FLEX 8000 160-, 192- & 208-Pin Package Pin-Outs (Part 1 of 2)_**|**_Table 53.  FLEX 8000 160-, 192- & 208-Pin Package Pin-Outs (Part 1 of 2)_**|**_Table 53.  FLEX 8000 160-, 192- & 208-Pin Package Pin-Outs (Part 1 of 2)_**|**_Table 53.  FLEX 8000 160-, 192- & 208-Pin Package Pin-Outs (Part 1 of 2)_**|**_Table 53.  FLEX 8000 160-, 192- & 208-Pin Package Pin-Outs (Part 1 of 2)_**|**_Table 53.  FLEX 8000 160-, 192- & 208-Pin Package Pin-Outs (Part 1 of 2)_**|**_Table 53.  FLEX 8000 160-, 192- & 208-Pin Package Pin-Outs (Part 1 of 2)_**|
|---|---|---|---|---|---|---|
|**Pin Name**|**160-Pin**<br>**PQFP**<br>**EPF8452A**|**160-Pin**<br>**PQFP**<br>**EPF8636A**|**192-Pin PGA**<br>**EPF8636A**<br>**EPF8820A**|**208-Pin**<br>**PQFP**<br>**EPF8636A**_(1)_|**208-Pin**<br>**PQFP**<br>**EPF8820A** _(1)_|**208-Pin**<br>**PQFP**<br>**EPF81188A** _(1)_|
|`nSP` _(2)_|120|1|R15|207|207|5|
|`MSEL0` _(2)_|117|3|T15|4|4|21|
|`MSEL1` _(2)_|84|38|T3|49|49|33|
|`nSTATUS` _(2)_|37|83|B3|108|108|124|
|`nCONFIG` _(2)_|40|81|C3|103|103|107|
|`DCLK` _(2)_|1|120|C15|158|158|154|
|`CONF_DONE`<br>_(2)_|4|118|B15|153|153|138|
|`nWS`|30|89|C5|114|114|118|
|`nRS`|71|50|B5|66|116|121|
|`RDCLK`|73|48|C11|64|137|137|
|`nCS`|29|91|B13|116|145|142|
|`CS`|27|93|A16|118|148|144|
|`RDYnBUSY`|125|155|A8|201|127|128|
|`CLKUSR`|76|44|A10|59|134|134|
|`ADD17`|78|43|R5|57|43|46|
|`ADD16`|91|33|U3|43|42|45|
|`ADD15`|92|31|T5|41|41|44|
|`ADD14`|94|29|U4|39|40|39|
|`ADD13`|95|27|R6|37|39|37|
|`ADD12`|96|24|T6|31|35|36|
|`ADD11`|97|23|R7|30|33|31|
|`ADD10`|98|22|T7|29|31|30|
|`ADD9`|99|21|T8|28|29|29|
|`ADD8`|101|20|U9|24|25|26|
|`ADD7`|102|19|U10|23|23|25|
|`ADD6`|103|18|U11|22|21|24|
|`ADD5`|104|17|U12|21|19|18|
|`ADD4`|105|13|R12|14|14|17|
|`ADD3`|106|11|U14|12|13|16|
|`ADD2`|109|9|U15|10|11|10|
|`ADD1`|110|7|R13|8|10|9|
|`ADD0`|123|157|U16|203|9|8|
|`DATA7`|144|137|H17|178|178|177|
|`DATA6`|150|132|G17|172|176|175|
|`DATA5`|152|129|F17|169|174|172|



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**FLEX 8000 Programmable Logic Device Family Data Sheet** 

_**Table 53.  FLEX 8000 160-, 192- & 208-Pin Package Pin-Outs (Part 2 of 2)**_ 

|**_Table 53.  FLEX 8000 160-, 192- & 208-Pin Package Pin-Outs (Part 2 of 2)_**|**_Table 53.  FLEX 8000 160-, 192- & 208-Pin Package Pin-Outs (Part 2 of 2)_**|**_Table 53.  FLEX 8000 160-, 192- & 208-Pin Package Pin-Outs (Part 2 of 2)_**|**_Table 53.  FLEX 8000 160-, 192- & 208-Pin Package Pin-Outs (Part 2 of 2)_**|**_Table 53.  FLEX 8000 160-, 192- & 208-Pin Package Pin-Outs (Part 2 of 2)_**|**_Table 53.  FLEX 8000 160-, 192- & 208-Pin Package Pin-Outs (Part 2 of 2)_**|**_Table 53.  FLEX 8000 160-, 192- & 208-Pin Package Pin-Outs (Part 2 of 2)_**|
|---|---|---|---|---|---|---|
|**Pin Name**|**160-Pin**<br>**PQFP**<br>**EPF8452A**|**160-Pin**<br>**PQFP**<br>**EPF8636A**|**192-Pin PGA**<br>**EPF8636A**<br>**EPF8820A**|**208-Pin**<br>**PQFP**<br>**EPF8636A**_(1)_|**208-Pin**<br>**PQFP**<br>**EPF8820A** _(1)_|**208-Pin**<br>**PQFP**<br>**EPF81188A** _(1)_|
|`DATA4`|154|127|E17|165|172|170|
|`DATA3`|157|124|G15|162|171|168|
|`DATA2`|159|122|F15|160|167|166|
|`DATA1`|11|115|E16|149|165|163|
|`DATA0`|12|113|C16|147|162|161|
|`SDOUT` _(3)_|128|152|C7_(11)_|198|124|119|
|`TDI` _(4)_|–|55|R11|72|20|–|
|`TDO` _(4)_|–|95|B9|120|129|–|
|`TCK` _(4)_,_(6)_|–|57|U8|74|30|–|
|`TMS` _(4)_|–|59|U7|76|32|–|
|`TRST` _(7)_|–|40|R3|54|54|–|
|Dedicated<br>Inputs_(10)_|5, 36, 85, 116|6, 35, 87, 116|A5, U5, U13,<br>A13|7, 45, 112,<br>150|17, 36, 121,<br>140|13, 41, 116,<br>146|
|`VCCINT`<br>(5.0 V)|21, 41, 53, 67,<br>80, 81, 100, 121,<br>133, 147, 160|4, 5, 26, 85,<br>106|C8, C9, C10,<br>R8, R9, R10,<br>R14|5, 6, 33, 110,<br>137|5, 6, 27, 48,<br>119, 141|4, 20, 35, 48,<br>50, 102, 114,<br>131, 147|
|`VCCIO`<br>(5.0 V or<br>3.3 V)|–|25, 41, 60, 70,<br>80, 107, 121,<br>140, 149, 160|D3, D4, D9,<br>D14, D15, G4,<br>G14, L4, L14,<br>P4, P9, P14|32, 55, 78, 91,<br>102, 138, 159,<br>182, 193, 206|26, 55, 69, 87,<br>102, 131, 159,<br>173, 191, 206|3, 19, 34, 49,<br>69, 87, 106,<br>123, 140, 156,<br>174, 192|
|`GND`|13, 14, 28, 46,<br>60, 75, 93, 107,<br>108, 126, 140,<br>155|15, 16, 36, 37,<br>45, 51, 75, 84,<br>86, 96, 97,<br>117, 126, 131,<br>154|C4, D7, D8,<br>D10, D11, H4,<br>H14, K4, K14,<br>P7, P8, P10,<br>P11|19, 20, 46, 47,<br>60, 67, 96,<br>109, 111, 124,<br>125, 151, 164,<br>171, 200|15, 16, 37, 38,<br>60, 78, 96,<br>109, 110, 120,<br>130, 142, 152,<br>164, 182, 200|11, 12, 27, 28,<br>42, 43, 60, 78,<br>96, 105, 115,<br>122, 132, 139,<br>148, 155, 159,<br>165, 183, 201|
|No Connect<br>(N.C.)|2, 3, 38, 39, 70,<br>82, 83, 118, 119,<br>148|2, 39, 82, 119|C6, C12, C13,<br>C14, E3, E15,<br>F3, J3, J4,<br>J14, J15, N3,<br>N15, P3, P15,<br>R4_(12)_|1, 2, 3, 16, 17,<br>18, 25, 26, 27,<br>34, 35, 36, 50,<br>51, 52, 53,<br>104, 105, 106,<br>107, 121, 122,<br>123, 130, 131,<br>132, 139, 140,<br>141, 154, 155,<br>156, 157, 208|1, 2, 3, 50, 51,<br>52, 53, 104,<br>105, 106, 107,<br>154, 155, 156,<br>157, 208|1, 2, 51, 52, 53,<br>54, 103, 104,<br>157, 158, 207,<br>208|
|Total User<br>I/O Pins_(9)_|116|114|132, 148_(13)_|132|148|144|



**Altera Corporation** 

**58** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

_**Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 1 of 3)**_ 

|**_Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 1 of 3)_**|**_Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 1 of 3)_**|**_Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 1 of 3)_**|**_Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 1 of 3)_**|**_Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 1 of 3)_**|**_Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 1 of 3)_**|**_Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 1 of 3)_**|
|---|---|---|---|---|---|---|
|**Pin Name**|**225-Pin**<br>**BGA**<br>**EPF8820A**|**232-Pin**<br>**PGA**<br>**EPF81188A**|**240-Pin**<br>**PQFP**<br>**EPF81188A**|**240-Pin**<br>**PQFP**<br>**EPF81500A**|**280-Pin**<br>**PGA**<br>**EPF81500A**|**304-Pin**<br>**RQFP**<br>**EPF81500A**|
|`nSP` _(2)_|A15|C14|237|237|W1|304|
|`MSEL0` _(2)_|B14|G15|21|19|N1|26|
|`MSEL1` _(2)_|R15|L15|40|38|H3|51|
|`nSTATUS` _(2)_|P2|L3|141|142|G19|178|
|`nCONFIG` _(2)_|R1|R4|117|120|B18|152|
|`DCLK` _(2)_|B2|C4|184|183|U18|230|
|`CONF_DONE` _(2)_|A1|G3|160|161|M16|204|
|`nWS`|L4|P1|133|134|F18|167|
|`nRS`|K5|N1|137|138|G18|171|
|`RDCLK`|F1|G2|158|159|M17|202|
|`nCS`|D1|E2|166|167|N16|212|
|`CS`|C1|E3|169|170|N18|215|
|`RDYnBUSY`|J3|K2|146|147|J17|183|
|`CLKUSR`|G2|H2|155|156|K19|199|
|`ADD17`|M14|R15|58|56|E3|73|
|`ADD16`|L12|T17|56|54|E2|71|
|`ADD15`|M15|P15|54|52|F4|69|
|`ADD14`|L13|M14|47|45|G1|60|
|`ADD13`|L14|M15|45|43|H2|58|
|`ADD12`|K13|M16|43|41|H1|56|
|`ADD11`|K15|K15|36|34|J3|47|
|`ADD10`|J13|K17|34|32|K3|45|
|`ADD9`|J15|J14|32|30|K4|43|
|`ADD8`|G14|J15|29|27|L1|34|
|`ADD7`|G13|H17|27|25|L2|32|
|`ADD6`|G11|H15|25|23|M1|30|
|`ADD5`|F14|F16|18|16|N2|20|
|`ADD4`|E13|F15|16|14|N3|18|
|`ADD3`|D15|F14|14|12|N4|16|
|`ADD2`|D14|D15|7|5|U1|8|
|`ADD1`|E12|B17|5|3|U2|6|
|`ADD0`|C15|C15|3|1|V1|4|
|`DATA7`|A7|A7|205|199|W13|254|
|`DATA6`|D7|D8|203|197|W14|252|
|`DATA5`|A6|B7|200|196|W15|250|



**Altera Corporation** 

**59** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

_**Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 2 of 3)**_ 

|**_Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 2 of 3)_**|**_Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 2 of 3)_**|**_Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 2 of 3)_**|**_Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 2 of 3)_**|**_Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 2 of 3)_**|**_Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 2 of 3)_**|**_Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 2 of 3)_**|
|---|---|---|---|---|---|---|
|**Pin Name**|**225-Pin**<br>**BGA**<br>**EPF8820A**|**232-Pin**<br>**PGA**<br>**EPF81188A**|**240-Pin**<br>**PQFP**<br>**EPF81188A**|**240-Pin**<br>**PQFP**<br>**EPF81500A**|**280-Pin**<br>**PGA**<br>**EPF81500A**|**304-Pin**<br>**RQFP**<br>**EPF81500A**|
|`DATA4`|A5|C7|198|194|W16|248|
|`DATA3`|B5|D7|196|193|W17|246|
|`DATA2`|E6|B5|194|190|V16|243|
|`DATA1`|D5|A3|191|189|U16|241|
|`DATA0`|C4|A2|189|187|V17|239|
|`SDOUT` _(3)_|K1|N2|135|136|F19|169|
|`TDI`|F15_(4)_|–|–|63_(14)_|B1_(14)_|80_(14)_|
|`TDO`|J2_(4)_|–|–|117|C17|149|
|`TCK`_(6)_|J14_(4)_|–|–|116_(14)_|A19_(14)_|148_(14)_|
|`TMS`|J12_(4)_|–|–|64_(14)_|C2_(14)_|81_(14)_|
|`TRST` _(7)_|P14|–|–|115_(14)_|A18_(14)_|145_(14)_|
|Dedicated Inputs<br>_(10)_|F4, L1, K12,<br>E15|C1, C17, R1,<br>R17|10, 51, 130,<br>171|8, 49, 131,<br>172|F1, F16, P3,<br>P19|12, 64, 164,<br>217|
|`VCCINT`<br>(5.0 V)|F5, F10, E1,<br>L2, K4, M12,<br>P15, H13,<br>H14, B15,<br>C13|E4, H4, L4,<br>P12, L14,<br>H14, E14,<br>R14, U1|20, 42, 64, 66,<br>114, 128, 150,<br>172, 236|18, 40, 60, 62,<br>91, 114, 129,<br>151, 173, 209,<br>236|B17, D3, D15,<br>E8, E10, E12,<br>E14, R7, R9,<br>R11, R13,<br>R14, T14|24, 54, 77,<br>144, 79, 115,<br>162, 191, 218,<br>266, 301|
|`VCCIO`<br>(5.0 V or 3.3 V)|H3, H2, P6,<br>R6, P10, N10,<br>R14, N13,<br>H15, H12,<br>D12, A14,<br>B10, A10, B6,<br>C6, A2, C3,<br>M4, R2|N10, M13,<br>M5, K13, K5,<br>H13, H5, F5,<br>E10, E8, N8,<br>F13|19, 41, 65, 81,<br>99, 116, 140,<br>162, 186, 202,<br>220, 235|17, 39, 61, 78,<br>94, 108, 130,<br>152, 174, 191,<br>205, 221, 235|D14, E7, E9,<br>E11, E13, R6,<br>R8, R10, R12,<br>T13, T15|22, 53, 78, 99,<br>119, 137, 163,<br>193, 220, 244,<br>262, 282, 300|



**Altera Corporation** 

**60** 

**FLEX 8000 Programmable Logic Device Family Data Sheet** 

_**Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 3 of 3)**_ 

|**_Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 3 of 3)_**|**_Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 3 of 3)_**|**_Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 3 of 3)_**|**_Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 3 of 3)_**|**_Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 3 of 3)_**|**_Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 3 of 3)_**|**_Table 54. FLEX 8000 225-, 232-, 240-, 280- & 304-Pin Package Pin-Outs (Part 3 of 3)_**|
|---|---|---|---|---|---|---|
|**Pin Name**|**225-Pin**<br>**BGA**<br>**EPF8820A**|**232-Pin**<br>**PGA**<br>**EPF81188A**|**240-Pin**<br>**PQFP**<br>**EPF81188A**|**240-Pin**<br>**PQFP**<br>**EPF81500A**|**280-Pin**<br>**PGA**<br>**EPF81500A**|**304-Pin**<br>**RQFP**<br>**EPF81500A**|
|`GND`|B1, D4, E14,<br>F7, F8, F9,<br>F12, G6, G7,<br>G8, G9, G10,<br>H1, H4, H5,<br>H6, H7, H8,<br>H9, H10, H11,<br>J6, J7, J8, J9,<br>J10, K6, K7,<br>K8, K9, K11,<br>L15, N3, P1|A1, D6, E11,<br>E7, E9, G4,<br>G5, G13,<br>G14, J5, J13,<br>K4, K14, L5,<br>L13, N4, N7,<br>N9, N11, N14|8, 9, 30, 31,<br>52, 53, 72, 90,<br>108, 115, 129,<br>139, 151, 161,<br>173, 185, 187,<br>193, 211, 229|6, 7, 28, 29,<br>50, 51, 71, 85,<br>92, 101, 118,<br>119, 140, 141,<br>162, 163, 184,<br>185, 186, 198,<br>208, 214, 228|D4, D5, D16,<br>E4, E5, E6,<br>E15, E16, F5,<br>F15, G5, G15,<br>H5, H15, J5,<br>J15, K5, K15,<br>L5, L15, M5,<br>M15, N5,<br>N15, P4, P5,<br>P15, P16, R4,<br>R5, R15, R16,<br>T4, T5, T16,<br>U17|9, 11, 36, 38,<br>65, 67, 90,<br>108, 116,<br>128, 150,<br>151, 175, 177,<br>206, 208, 231,<br>232, 237, 253,<br>265, 273, 291|
|No Connect<br>(N.C.)|–|–|61, 62, 119,<br>120, 181, 182,<br>239, 240|–|–|10, 21, 23, 25,<br>35, 37, 39, 40,<br>41, 42, 52, 55,<br>66, 68, 146,<br>147, 161, 173,<br>174, 176, 187,<br>188, 189, 190,<br>192, 194, 195,<br>205, 207, 219,<br>221, 233, 234,<br>235, 236, 302,<br>303|
|Total User I/O<br>Pins_(9)_|148|180|180|177|204|204|



**Altera Corporation** 

**61** 

## **FLEX 8000 Programmable Logic Device Family Data Sheet** 

## _**Notes to tables:**_ 

- (1) Perform a complete thermal analysis before committing a design to this device package. See _Application Note 74 (Evaluating Power for Altera Devices)_ for more information. 

- (2) This pin is a dedicated pin and is not available as a user I/O pin. 

- (3) `SDOUT` will drive out during configuration. After configuration, it may be used as a user I/O pin. By default, the MAX+PLUS II software will not use `SDOUT` as a user I/O pin; the user can override the MAX+PLUS II software and use `SDOUT` as a user I/O pin. 

- (4) If the device is not configured to use the JTAG BST circuitry, this pin is available as a user I/O pin. 

- (5) JTAG pins are available for EPF8636A devices only. These pins are dedicated user I/O pins. 

- (6) If this pin is used as an input in user mode, ensure that it does not toggle before or during configuration. 

- (7) `TRST` is a dedicated input pin for JTAG use. This pin must be grounded if JTAG BST is not used. 

- (8) Pin 52 is a VCC pin on EPF8452A devices only. 

- (9) The user I/O pin count includes dedicated input pins and all I/O pins. 

- (10) Unused dedicated inputs should be tied to ground on the board. 

- (11) `SDOUT` does not exist in the EPF8636GC192 device. 

- (12) These pins are no connect (N.C.) pins for EPF8636A devices only. They are user I/O pins in EPF8820A devices. 

- (13) EPF8636A devices have 132 user I/O pins; EPF8820A devices have 148 user I/O pins. 

- (14) For EPF81500A devices, these pins are dedicated JTAG pins and are not available as user I/O pins. If JTAG BST is not used, `TDI` , `TCK` , `TMS` , and `TRST` should be tied to `GND` . 

## **Revision History** 

The information contained in the _FLEX 8000 Programmable Logic Device Family Data Sheet_ version 11.1 supersedes information published in previous versions. The _FLEX 8000 Programmable Logic Device Family Data Sheet_ version 11.1 contains the following change: minor textual updates. 

**Altera Corporation** 

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