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ECMF02-2AMX6
Common Mode Filter, USB 2.0 and MIPI D-PHY/MDDI, µQFN-6
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- Manufacturer: STMICROELECTRONICS
- Product type:
- SVHC: No SVHC (25-Jun-2025)
- No. of Pins: 6Pins
- Product Range: ECMF Series
- Filter Circuit: Common-Mode
- EMI Filter Type: Common Mode Filter with ESD Protection
- No. of Data Lines: 2 Data Lines
- Filter Case / Package: QFN
| Delivery and price | |
|---|---|
| Units per pack | 9000 |
| Price | 0.151 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
## **ECMF02-2AMX6**
## Common mode filter with ESD protection for USB 2.0 and MIPI D-PHY/MDDI interface
Datasheet - production data
## **Applications**
- Mobile phones
- Notebook, laptop
- Portable devices
- PND
## **Description**
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QFN-6L<br>**----- End of picture text -----**<br>
The device is a highly integrated common mode filter designed to suppress EMI/RFI common mode noise on high speed differential serial buses like MIPI D-PHY, MDDI or USB 2.0.
Also it can protect and filter one differential lane.
## **Features**
**Figure 1: Pin configuration**
- High common mode attenuation:
- -34 dB at 900 MHz
-
- -20 dB between 800 MHz and 2.2 GHz
-
- Large bandwidth: 1.7 GHz
- Very low PCB space consumption
- Thin package: 0.55 mm max.
- RoHS package
- High reduction of parasitic elements through integration
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D+ D+<br>ESD ESD<br>D- D-<br>ESD ESD<br>GND NC<br>**----- End of picture text -----**<br>
## **Complies with the following standards**
- IEC 61000-4-2 (exceeds level 4)
- ±15 kV (air discharge)
- ±8 kV (contact discharge)
March 2017
DocID17815 Rev 3
1/13
This is information on a product in full production.
_www.st.com_
**Characteristics**
**ECMF02-2AMX6**
## **1 Characteristics**
**Table 1: Absolute maximum ratings (Tamb = 25 °C)**
|**Symbol**|**Parameter**|**Parameter**|**Value**|**Unit**|
|---|---|---|---|---|
|VPP|Peak pulse voltage|IEC 61000-4-2:<br>Contact discharge<br>Air discharge|8<br>20|kV|
|IDC|Maximum DC current||200|mA|
|Tj|Maximumjunction temperature range||-55 to +125|°C|
|Tstg|Storage temperature range||-55 to +150||
|TL|Maximum temperature for solderingduring10 s||260||
**Figure 2: Electrical characteristics (definitions)**
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**Table 2: Electrical characteristics (Tamb = 25 °C)**
|**Symbol**|**Test condition**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|
|VBR|IR= 1 mA|6|||V|
|IRM|VRM= 1.5 Vper line|||100|nA|
|RDC|DC serial resistance||1.8|2.5|Ω|
Compliant with USB 2.0 high speed sync field test (150 mV diff).
2/13
DocID17815 Rev 3
**ECMF02-2AMX6**
**Characteristics**
## **1.1 Characteristics (curves)**
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Figure 3: Differential insertion losses Figure 4: Differential insertion losses<br>(Z0 diff = 100 Ω) (Z0 diff = 90 Ω)<br>0 SDD21 (dB) 0 SDD21 (dB)<br>-0.2 | - 0.2 L L<br>-0.4 PE TE TPN ETT - 0.4 a a XN<br>-0.6 eS - 0.6 AI PTE PTE NTI TTT<br>-0.8 a a - 0.8 WAT TPT NITE<br>-1 IE TE ENTE - 1 PU IE PPP<br>-1.2 EL ETE IE, ENE - 1.2 a<br>-1.4 EE a | - 1.4 PUIINee<br>-1.6 - 1.6<br>-1.8 Heat eet ee - 1.8 HEREC<br>-2 TAT - 2 Ce CooN<br>-2.2 EAI EI It - 2.2 |<br>-2.4 a en - 2.4 PU TE [TEI]<br>-2.6 - 2.6<br>-2.8-3 neseHHI CELEee F(Hz) CMM - -2.83 ettHHH CHT etoECHCEHHaTN F(Hz)<br>300k 1M 3M 10M 30M 100M 300M 1G 3G 300k 1M 3M 10M 30M 100M 300M 1G 3G<br>**----- End of picture text -----**<br>
**Figure 5: Common mode attenuation (Z0 com = 50 Ω)**
**Figure 6: Common mode attenuation (Z0 com = 45 Ω)**
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0 SCC21 (dB) 0 SCC21 (dB)<br>- 2 - 2<br>- 4 TT TTT TPNJ TTT - 4 TonCOM tionCCI oNCINI<br>- 6- 8 ENEE - 6- 8 EEEE<br>- 10 Ce te ee - 10 COO]<br>- 12 Cee - 12 COTE CCIE PTIOTT<br>- 14 - 14<br>- 16 ce aera er a - 16 ERA<br>- 18 - 18<br>- 20 - 20<br>- 22 HC e metiemet em a - 22 itCOO aseCIEeneeat<br>- 24 Cee - 24 ny<br>- 26 CO - 26 AE|<br>- 28 Cee - 28 CO i<br>- 30 LL ie - 30 CO<br>- 32 a ee | - 32 COO||CI Ce<br>- 34- 36 ca t F(Hz) - 34- 36 a LL, F(Hz)<br>300k 1M 3M 10M 30M 100M 300M 1G 3G 300k 1M 3M 10M 30M 100M 300M 1G 3G<br>Figure 8: Differential (ZDD21) and common mode<br>Figure 7: Differential return loss (Z0 diff = 100 Ω) 0 diff = 100 Ω) = 100 Ω)<br>(ZCC21) impedance versus frequency<br>0 SDD11 Too / SDD22 (dB) 1E4 ZDD21 and ZCC21 (Ω)<br>- 5 SDD11<br>SDD22<br>H e | MEH<br>- 10<br>1E3<br>- 15 IT<br>AN IN |<br>- 20 ATI<br>HeIN 1E2<br>- 25 A N<br>TT TT Ace<br>- 30<br>{TT Aq ML 1E1<br>- 35<br>- 40 me ) F(Hz) | F(Hz)<br>300k 1M 3M 10M 30M 100M 300M 1G 3G 1E7 ZDD 1E8 ZCC 1E9 6E9<br>**----- End of picture text -----**<br>
**Figure 7: Differential return loss (Z0 diff = 100 Ω) 0 diff = 100 Ω) = 100 Ω)**
DocID17815 Rev 3
3/13
**Characteristics**
**ECMF02-2AMX6**
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Figure 9: ESD response to IEC 61000-4-2<br>Figure 10: ESD response to IEC 61000-4-2<br>(+8 kV contact discharge)<br>(-8 kV contact discharge)<br>20 V/Div 20 ns/Div 20 V/Div 20 ns/Div<br>82.3 V<br>PIN 6 C2 PIN 6<br>C2<br>-71.1 V<br>112 V PIN 5<br>PIN 5 C3<br>C3<br>-115 V<br>50 V/Div 20 ns/Div 50 V/Div 20 ns/Div<br>**----- End of picture text -----**<br>
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Figure 11: Low power pulse response Figure 12: USB 2.0 HSync measurement result<br>500 mV/div Pulse: 50 ns, tr = tf = 5 ns 200 mV/Div<br>| | }<br>nonin flo on<br>FI Hh) dw Aj WY] “A » | |<br>200 ns/di v<br>500 mV/div 5 ns/Div<br>200 mV/Div<br>ly pul} Io Tah — gh nh ph yy lh<br>PV Py PV PY Py Py Py ry<br>poet tt th i<br>dha | \AJ Mi J laa) My, Ww] ‘my<br>earingore ’ : ,<br>200 ns/div 5 ns/Div<br>**----- End of picture text -----**<br>
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Figure 13: USB 2.0 eye diagram, mask T1<br>**----- End of picture text -----**<br>
4/13
DocID17815 Rev 3
**Application** schematics
## **ECMF02-2AMX6**
## **2 Application schematics**
**Figure 14: MIPI D-PHY**
**Figure 15: USB 2.0**
DocID17815 Rev 3
5/13
**ECMF02-2AMX6**
**Package** information
## **3 Package information**
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK[®] packages, depending on their level of environmental compliance. ECOPACK[®] specifications, grade definitions and product status are available at: _**www.st.com**_ . ECOPACK[®] is an ST trademark.
## **3.1 QFN-6L package information**
**Figure 16: QFN-6L package outline**
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**Table 3: QFN-6L package mechanical data**
|**Ref.**||**Dimensions**|**Dimensions**|**Dimensions**|||
|---|---|---|---|---|---|---|
|||**Millimeters**|||**Inches**||
||**Min.**|**Typ.**|**Max.**|**Min.**|**Typ.**|**Max.**|
|A|0.45|0.50|0.55|0.018|0.020|0.022|
|A1|0.00|0.02|0.05|0.00|0.0008|0.0009|
|b|0.18|0.25|0.30|0.007|0.010|0.012|
|D|1.65|1.70|1.75|0.065|0.067|0.069|
|E|1.45|1.50|1.55|0.057|0.059|0.061|
|e|0.45|0.50|0.55|0.018|0.020|0.022|
|L|0.30|0.40|0.50|0.012|0.016|0.020|
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**Package** information
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Figure 17: Footprint recommendations,<br>Figure 18: Marking layout<br>dimensions in mm (inches)<br>0 . 25 pin 1<br>(0.0098) | a<br>0 . 6<br><<br>1<br>(0 . 1075) . 9 t—C~tS [— ~~ | (0 . 00 . 27)7 X X XX : MarkingY : Year<br>y Q : Quarter<br>| Y Q<br>**----- End of picture text -----**<br>
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Figure 20: Tape and reel orientation<br>Figure 19: Package orientation in reel<br>SS COO0O00 ——————————0 0 O ¥ \<br>° thickness 0.1 mm<br>| 2 x MaximumPa cover tape<br>LY WI BJ BH) J ™" Sprocket hole<br>Pin 1 located according to EIA-481<br>Note: Pocket dimensions are not on scale<br>Pocket shape may vary depending on package<br>**----- End of picture text -----**<br>
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Figure 21: Reel dimensions in mm Figure 22: Inner box dimension definition in mm<br>**----- End of picture text -----**<br>
DocID17815 Rev 3
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**ECMF02-2AMX6**
**==> picture [96 x 10] intentionally omitted <==**
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Package information<br>**----- End of picture text -----**<br>
**Figure 23: Tape dimension definitions**
**Table 4: Tape mechanical data**
|**Ref.**|**Dimensions**|**Dimensions**|**Dimensions**|
|---|---|---|---|
||**Millimeters**|||
||**Min.**|**Typ.**|**Max.**|
|P0|3.9|4.0|4.1|
|P1|3.9|4.0|4.1|
|P2|1.95|2|2.05|
|Ø D0|1.5|1.55|1.6|
|Ø D1|1|||
|F|3.4|3.5|3.6|
|K0|0.65|0.7|0.75|
|W|7.7|8|8.3|
8/13
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**ECMF02-2AMX6**
**Recommendation** on PCB assembly
## **4 Recommendation on PCB assembly**
## **4.1 Stencil opening design**
1. General recommendation on stencil opening design
- a. Stencil opening dimensions: L (Length), W (Width), T (Thickness).
- 2. General design rule
- a. Stencil thickness (T) = 75 ~ 125 μm
- 𝑊
- b. Aspect ratio = 𝑇 ≥1.5 𝐿×𝑊
- c. Aspect area = ≥0.66 2𝑇(𝐿+𝑊)
3. Reference design
- a. Stencil opening thickness: 100 μm
- b. Stencil opening for leads: Opening to footprint ratio is 90%.
- **Figure 24: Recommended stencil window position**
**Figure 25: Recommended stencil window position**
DocID17815 Rev 3
9/13
**Recommendation** on PCB assembly
**ECMF02-2AMX6**
## **4.2 Solder paste**
1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004.
2. “No clean” solder paste is recommended.
3. Offers a high tack force to resist component movement during high speed.
4. Solder paste with fine particles: powder particle size is 20-45 μm.
## **4.3 Placement**
1. Manual positioning is not recommended.
2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering
3. Standard tolerance of ±0.05 mm is recommended.
4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages.
5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool.
6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools.
## **4.4**
## **PCB design preference**
1. To control the solder paste amount, the closed via is recommended instead of open vias.
2. The position of tracks and open vias in the solder area should be well balanced. A symmetrical layout is recommended, to avoid any tilt phenomena caused by asymmetrical solder paste due to solder flow away.
## **4.5**
## **Layout recommendation**
Connection to PCB GND must be as short as possible to ensure ESD remaining voltage and SCC21 performance.
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Figure 26: Layout recommendation<br>**----- End of picture text -----**<br>
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Zdiff according to<br>the application<br>Vias to GND plane<br>**----- End of picture text -----**<br>
DocID17815 Rev 3
10/13
**ECMF02-2AMX6**
**Recommendation** on PCB assembly
## **4.6 Reflow profile**
**Figure 27: ST ECOPACK[®] recommended soldering reflow profile for PCB mounting**
Minimize air convection currents in the reflow oven to avoid component movement. Maximum soldering profile corresponds to the latest IPC/JEDEC J-STD-020.
DocID17815 Rev 3
11/13
**Ordering** information
**ECMF02-2AMX6**
## **5 Ordering information**
**Figure 28: Ordering information scheme**
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**----- Start of picture text -----**<br>
ECMF 02 – 2 A xxx<br>Function<br>ESD common mode filter<br>Number of lines<br>02 = 2 lines<br>Number of ESD protected lines<br>2 = 2 ESD protected lines<br>Version<br>Package<br>MX6 = QFN-6L<br>**----- End of picture text -----**<br>
**Table 5: Ordering information**
|**Order code**|**Marking**|**Package**|**Weight**|**Base qty.**|**Delivery mode**|
|---|---|---|---|---|---|
|ECMF02-2AMX6|KD_(1)_|QFN-6L|3.35 mg|3000|Tape and reel 7"|
**Notes:**
(1)The marking can be rotated by 90° to differentiate assembly location
## **6 Revision history**
**Table 6: Document revision history**
|**Date**|**Revision**|**Changes**|
|---|---|---|
|10-Aug-2010|1|Initial release.|
|28-Jun-2011|2|Added_Complies with the following standards:_, and Air discharge<br>parameter in_Table 1_. Removed Figure 6. Sdd41 / Sdd23 inter-lane<br>differential cross-couplingmeasurements.|
|01-Mar-2017|3|Updated marking in_Figure 17_and_Figure 18_and inserted_Figure 9_.<br>Removed Figure 11 and Figure 14.<br>Updated cover page,_Section 3.1: "QFN-6L package information"_,<br>_Section 1: "Characteristics"_and_Table 5: "Ordering information"_.|
12/13
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**ECMF02-2AMX6**
## **IMPORTANT NOTICE – PLEASE READ CAREFULLY**
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.
No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
- © 2017 STMicroelectronics – All rights reserved
DocID17815 Rev 3
13/13
Updated at March 31, 2026
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