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DSC1224CI2-100M0000
MEMS Oscillator, 100 MHz, SMD, 3.2mm x 2.5mm, 25 ppm, 3.3 V, DSC1224 Series, LVPECL / LVDS / HCSL
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- Manufacturer: MICROCHIPDIRECT
- Product type: MEMS Oscillators
- SVHC: No SVHC (04-Feb-2026)
- Frequency Nom: 100MHz
- Product Range: DSC1224 Series
- Supply Voltage Nom: 3.3V
- Frequency Stability + / -: 25ppm
- Operating Temperature Max: 85°C
- Operating Temperature Min: -40°C
- Oscillator Case / Package: SMD, 3.2mm x 2.5mm
- Oscillator Output Compatibility: LVPECL / LVDS / HCSL
| Delivery and price | |
|---|---|
| Units per pack | 500 |
| Price | 0.892 € |
| Current stock | 25+ |
| Lead time | 22 days |
Datasheet
## **DSC12X2/3/4** ## **High Performance Differential MEMS Oscillators** ## **Features** - Very Low RMS Phase Jitter: <650 fs (typ.) - High Stability: ±20 ppm, ±25 ppm, ±50 ppm - Wide Temperature Range: - Automotive: –40°C to +125°C (DSC12x LVDS Only) - For AEC-Q100 qualified parts, refer to DSA1200 Family - Ext. Industrial: –40°C to +105°C - Industrial: –40°C to +85°C - Commercial: –20°C to +70°C - Supports LVPECL, LVDS, or HCSL Differential Outputs - PCIe Gen1-6 Compliant Output - Wide Frequency Range: 2.5 MHz to 450 MHz - Small Industry Standard Footprints: - 2.5 mm x 2.0 mm - 3.2 mm x 2.5 mm - 5.0 mm x 3.2 mm - 7.0 mm x 5.0 mm ## **General Description** The DSC12x2/3/4 family of high performance oscillators utilizes the latest generation of silicon MEMS technology that reduces close-in noise and provides excellent jitter and stability over a wide range of supply voltages and temperatures. By eliminating the need for quartz or SAW technology, MEMS oscillators significantly enhance reliability and accelerate product development, while meeting stringent clock performance criteria for a variety of communications, storage, and networking applications. The DSC12x2/3/4 family features a control function on pin 1 or pin 2 that permits either a standby feature (complete power down when STDBY is low), output enable (output is tri-stated with OE low), or a frequency select (choice of two frequencies selected by FS high/low). See the Product Identification System section for detailed information. All oscillators are available in industry-standard packages, including the small 2.5 mm x 2.0 mm, and are “drop-in” replacements for standard 6-pin LVPECL/LVDS/HCSL crystal oscillators. - Excellent Shock and Vibration Immunity - Qualified to MIL-STD-883 - High Reliability - 20x Better MTF than Quartz Oscillators - Supply Range of 2.25 to 3.6V - Standby, Frequency Select, and Output Enable Functions - Lead-Free and RoHS Compliant ## **Applications** - Storage Area Networks - Passive Optical Networks - 10/100G Ethernet - HD/SD/SDI Video and Surveillance - PCI Express Gen 1/2/3/4/5/6 - Display Port ## **Package Types** ||**DSC12x2/3/4**|**DSC12x2/3/4**|**DSC12x2/3/4**||| |---|---|---|---|---|---| ||6-Lead VDFN||6-Lead VDFN||| |OE/STDBY/FS||1||6|VDD| ||||||| ||NC|2||5|CLK–| ||||||| ||GND|3||4|CLK+| ||||||| |1<br>OE/STDBY/FS<br>NC<br>GND<br>6<br>5<br>4<br>2<br>3<br>~~“~~E~~E~~|||||VDD<br>CLK+<br>CLK–| DS20006011G-page 1 2019 - 2025 Microchip Technology Inc. and its subsidiaries **DSC12X2/3/4** ## **Functional Block Diagrams** **==> picture [384 x 388] intentionally omitted <==** **----- Start of picture text -----**<br> Pin 1 DIGITAL SUPPLY Pin 6<br>CONTROL REGULATION VDD<br>OE/STDBY/FS<br>Pin 2 MEMS<br>RESONATOR<br>NC<br>Pin 5<br>TEMP SENSOR + PLL OUTPUT CLK–<br>CONTROL & DIV Pin 4<br>Pin 3 COMPENSATION CLK+<br>GND<br>Pin 1 DIGITAL SUPPLY Pin 6<br>CONTROL REGULATION VDD<br>NC<br>MEMS<br>Pin 2<br>RESONATOR<br>OE/STDBY/FS<br>Pin 5<br>TEMP SENSOR + PLL OUTPUT CLK–<br>CONTROL & DIV Pin 4<br>Pin 3 COMPENSATION CLK+<br>GND “bos<br>**----- End of picture text -----**<br> DS20006011G-page 2 2019 - 2025 Microchip Technology Inc. and its subsidiaries **DSC12X2/3/4** ## **1.0 ELECTRICAL CHARACTERISTICS** ## **Absolute Maximum Ratings †** Supply Voltage .......................................................................................................................................... –0.3V to +4.0V Input Voltage .....................................................................................................................................–0.3V to VDD + 0.3V ESD Protection (HBM) ............................................................................................................................................... 4 kV ESD Protection (MM)................................................................................................................................................400V ESD Protection (CDM)............................................................................................................................................ 1.5 kV **† Notice:** Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods may affect device reliability. ## **ELECTRICAL CHARACTERISTICS** **Electrical Characteristics:** VDD = 2.5V ±10% or 3.3V ±10%; TA = –40°C to +105°C, unless noted. |**Parameters**|**Sym.**|**Min.**|**Typ.**|**Max.**|**Units**|**Conditions**| |---|---|---|---|---|---|---| |SupplyVoltage|VDD|2.25|—|3.63|V|Note 1| |Supply Current|IDD|—|50|—|mA|LVPECL, fOUT= 100 MHz| |||—|32|—||LVDS, fOUT= 100 MHz| |||—|40|—||HCSL, fOUT= 100 MHz| |||—|23|—||Output disabled (tri-state),<br>fOUT= 100 MHz| |Standby Current|ISTDBY_|—|2.5|5|µA|Input pin = STDBY<br>= Asserted,<br>(VDD= 3.3V)| |Frequency Stability|Δf|—|—|±20|ppm|Includes frequency variations<br>due to initial tolerance, temp.,<br>and power supply voltage| |||—|—|±25||| |||—|—|±50||| |Aging|Δf|—|—|±5|ppm|Firstyear@25°C| |||—|—|±1||Peryear after firstyear| |Startup Time|tSU|—|5.5|6|ms|From 90% VDDto valid clock<br>output, T = +25°C,Note 2| |Input Logic Levels|VIH|0.75 x VDD|—|—|V|Input logic high| ||VIL|—|—|0.25 x VDD||Input logic low| |Output Disable Time|tDA|—|—|25|ns|Note 3| |Output Enable Time|tEN|—|—|6|ms|STDBY| |||—|—|350|ns|OE| |Enable Pull-UpResistor|—|—|1.5|—|MΩ|Pull-upresistor onpin 1,Note 4| - **Note 1:** VDD pin should be filtered with 0.1 µF capacitor. - **2:** tSU is time to 100 ppm stable output frequency after VDD is applied and outputs are enabled. - **3:** tDA: See the Output Waveforms and the Test Circuits sections for more information. - **4:** Output is enabled if pad is floated (not connected). - **5:** Jitter limits are established by Gen 1.1, Gen 2.1, and Gen 3.0 PCIe standards. DS20006011G-page 3 2019 - 2025 Microchip Technology Inc. and its subsidiaries **DSC12X2/3/4** ## **ELECTRICAL CHARACTERISTICS (CONTINUED)** **Electrical Characteristics:** VDD = 2.5V ±10% or 3.3V ±10%; TA = –40°C to +105°C, unless noted. |**Parameters**|**Sym.**|**Min.**|**Typ.**|**Max.**|**Units**|**Conditions**| |---|---|---|---|---|---|---| |**LVPECL(DSC12x2)**||||||| |Frequency|f0|2.5|—|450|MHz|—| |Output Logic Levels|VOH|VDD–<br>1.145|—|—|V|RL= 50Ω| ||VOL|—|—|VDD–<br>1.695||| |Peak-to-Peak Output Swing|VPP|—|800|—|mV|Single-Ended| |Output Transition Time|tR|—|200|250|ps|20% to 80%, RL= 50Ω| ||tF|—|250|300||| |Output DutyCycle|SYM|48|—|52|%|Differential| |Period Jitter RMS|JPER|—|2.0|—|ps|f0= 156.25 MHz, 10k cycles| |Period Jitter Peak-to-Peak|JPTP|—|20|—|ps|f0= 156.25 MHz, 10k cycles| |Integrated Phase Noise<br>(Random)|JPH|—|0.65|—|psRMS|12 kHz to 20 MHz<br>@156.25 MHz| |**LVDS(DSC12x3)**||||||| |Frequency|f0|2.3|—|450|MHz|—| |Output Offset Voltage|VOS|1.15|1.25|1.35|V|R = 100Ω Differential| |Peak-to-Peak Output Swing|VPP|250|350|450|mV|Single-Ended| |Output Transition Time|tR|120|170|220|ps|20% to 80%, RL= 100Ω| ||tF|||||| |Output DutyCycle|SYM|40|—|52|%|Differential| |Period Jitter RMS|JPER|—|2.5|—|ps|f0= 156.25 MHz, 10k cycles| |Period Jitter Peak-to-Peak|JPTP|—|20|—|ps|f0= 156.25 MHz, 10k cycles| |Period Jitter RMS|JPER|—|3|—|ps|f0= 156.25 MHz,<br>TA= –40°C to +125°C| |Period Jitter Peak-to-Peak|JPTP|—|25|—|ps|f0= 156.25 MHz,<br>TA= –40°C to +125°C| |Integrated Phase Noise<br>(Random)|JPH|—|0.65|—|psRMS|12 kHz to 20 MHz<br>@156.25 MHz,<br>TA= –40°C to +105°C| |||—|0.9|—||2 kHz to 20 MHz<br>@156.25 MHz,<br>TA= –40°C to +105°C| |Phase Jitter|JRMS-CC|—|0.025|0.1|psRMS|PCIe Gen 6.0, 64 GT/s| - **Note 1:** VDD pin should be filtered with 0.1 µF capacitor. - **2:** tSU is time to 100 ppm stable output frequency after VDD is applied and outputs are enabled. - **3:** tDA: See the Output Waveforms and the Test Circuits sections for more information. - **4:** Output is enabled if pad is floated (not connected). - **5:** Jitter limits are established by Gen 1.1, Gen 2.1, and Gen 3.0 PCIe standards. DS20006011G-page 4 2019 - 2025 Microchip Technology Inc. and its subsidiaries **DSC12X2/3/4** ## **ELECTRICAL CHARACTERISTICS (CONTINUED)** **Electrical Characteristics:** VDD = 2.5V ±10% or 3.3V ±10%; TA = –40°C to +105°C, unless noted. |**Parameters**|**Sym.**|**Min.**|**Typ.**|**Max.**|**Units**|**Conditions**| |---|---|---|---|---|---|---| |**HCSL(DSC12x4)**||||||| |Frequency|f0|2.3|—|450|MHz|—| |Output Logic Levels|VOH|0.64|—|—|V|RL= 50Ω| ||VOL|—|—|0.1||| |Peak-to-Peak Output Swing|VPP|—|750|—|mV|Single-Ended| |Output Transition Time|tR|200|260|400|ps|20% to 80%, RL= 50Ω| ||tF|250|370|500||| |Output DutyCycle|SYM|48|—|52|%|Differential| |Period Jitter RMS|JPER|—|2|—|ps|f0= 100.00 MHz, 10k cycles| |Period Jitter Peak-to-Peak|JPTP|—|16|—|ps|f0= 100.00 MHz, 10k cycles| |Integrated Phase Noise<br>(Random)|JPH|—|0.617|—|psRMS|12 kHz to 20 MHz @100 MHz<br>TA= –40°C to +105°C| |||—|0.460|—||100 kHz to 20 MHz @100 MHz<br>TA= –40°C to +105°C| |||—|0.212|—||1.875 MHz to 20 MHz<br>@100 MHz<br>TA= –40°C to +105°C| |Phase Jitter|TJ|—|3.42|86|psPP|PCIe Gen 1.1, TJ= DJ+14.069<br>x RJ (BER 10–12),Note 5| ||JRMS-CCHF|—|0.247|3.1|psRMS|PCIe Gen 2.1, 1.5 MHz to<br>Nyquist,Note 5| ||JRMS-CCHF|—|0.08|3.0|psRMS|PCIe Gen 2.1, 10 kHz to 1.5 MHz,<br>Note 5| ||JRMS-CC|—|0.107|1.0|psRMS|PCIe Gen 3.0,Note 5| |||—|0.107|0.30||PCIe Gen 4.0, 16 GT/s| |||—|0.043|0.12||PCIe Gen 5.0, 32 GT/s| |||—|0.054|0.1||PCIe Gen 6.0, 64 GT/s| - **Note 1:** VDD pin should be filtered with 0.1 µF capacitor. - **2:** tSU is time to 100 ppm stable output frequency after VDD is applied and outputs are enabled. - **3:** tDA: See the Output Waveforms and the Test Circuits sections for more information. - **4:** Output is enabled if pad is floated (not connected). - **5:** Jitter limits are established by Gen 1.1, Gen 2.1, and Gen 3.0 PCIe standards. DS20006011G-page 5 2019 - 2025 Microchip Technology Inc. and its subsidiaries ## **DSC12X2/3/4** ## **TEMPERATURE SPECIFICATIONS (Note 1)** |**Parameters**|**Sym.**|**Min.**|**Typ.**|**Max.**|**Units**|**Conditions**| |---|---|---|---|---|---|---| |**Temperature Ranges**||||||| |Maximum Junction Temperature|TJ|—|—|+150|°C|—| |Storage Temperature Range|TS|–55|—|+150|°C|—| |Lead Temperature|—|—|—|+260|°C|Soldering, 40 sec.| **Note 1:** The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air (i.e., TA, TJ, JA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above +150°C can impact the device reliability. DS20006011G-page 6 2019 - 2025 Microchip Technology Inc. and its subsidiaries **DSC12X2/3/4** ## **2.0 PIN DESCRIPTIONS** The descriptions of the pins are listed in Table 2-1 and Table 2-2. ## **TABLE 2-1: DSC120x/1x/2x PIN FUNCTION TABLE** |**Pin Number**|**Pin Name**|**Description**| |---|---|---| |1|OE/STDBY<br>/FS|Controlpin: Output enable/standby/frequencyselect.| |2|NC|No connect.| |3|GND|Power supply ground.| |4|CLK+|Clock output +.| |5|CLK–|Clock output –.| |6|VDD|Power supply.| ## **TABLE 2-2: DSC123x/4x/5x PIN FUNCTION TABLE** |**Pin Number**|**Pin Name**|**Pin Name**|**Description**| |---|---|---|---| |1||NC|No connect.| |2|OE/STDBY<br>/FS||Controlpin: Output enable/standby/frequencyselect.| |3|GND||Power supply ground.| |4|CLK+||Clock output +.| |5|CLK–||Clock output –.| |6|VDD||Power supply.| DS20006011G-page 7 2019 - 2025 Microchip Technology Inc. and its subsidiaries **DSC12X2/3/4** ## **3.0 TERMINATION SCHEME** **==> picture [469 x 254] intentionally omitted <==** **----- Start of picture text -----**<br> V<br>DD V<br>DD<br>0.1μF<br>R1 R2<br>6<br>2 5<br>3 4<br>VDD R1, R2 R3, R4 R3 R4<br>3.3V 130Ω 82Ω<br>2.5V 249Ω 63Ω<br>**----- End of picture text -----**<br> _**FIGURE 3-1:** LVPECL Termination (DSC12x2)._ In Figure 3-1, Thevenin termination for 3.3V operation. Values will differ for VDD = 2.5V **==> picture [469 x 254] intentionally omitted <==** **----- Start of picture text -----**<br> V<br>DD<br>0.1μF<br>6<br>2 5<br>3 4<br>**----- End of picture text -----**<br> _**FIGURE 3-2:** LVDS Termination (DSC12x3)._ DS20006011G-page 8 2019 - 2025 Microchip Technology Inc. and its subsidiaries **DSC12X2/3/4** **==> picture [468 x 293] intentionally omitted <==** **----- Start of picture text -----**<br> V<br>DD<br>0.1μF<br>6<br>R<br>S<br>R<br>S<br>2 5<br>3 4<br>R<br>S<br>The 33Ω series resistors are needed to avoid excessive ringing<br>**----- End of picture text -----**<br> _**FIGURE 3-3:** HCSL Termination (DSC12x4)._ DS20006011G-page 9 2019 - 2025 Microchip Technology Inc. and its subsidiaries **DSC12X2/3/4** ## **4.0 OUTPUT WAVEFORM** **==> picture [468 x 180] intentionally omitted <==** **----- Start of picture text -----**<br> tR tF<br>Output 80%<br>Output voltage swing.<br>50%<br>Refer to table below.<br>Output 20%<br>1/f0 tEN<br>Enable tDA VIH<br>VIL<br>**----- End of picture text -----**<br> _**FIGURE 4-1:** LVPECL, LVDS, and HCSL Output Waveform._ ## **TABLE 4-1: OUTPUT VOLTAGE SWING BY LOGIC TYPE** |**Output Logic Protocol**|**Typical Peak-to-Peak Output Swing**| |---|---| |LVPECL|830 mV| |LVDS|350 mV| |HCSL|675 mV| DS20006011G-page 10 2019 - 2025 Microchip Technology Inc. and its subsidiaries **DSC12X2/3/4** ## **5.0 TEST CIRCUITS** **==> picture [468 x 199] intentionally omitted <==** **----- Start of picture text -----**<br> LVPECL<br>I LVPECL<br>DD<br>6 5 4<br>V<br>DD<br>0.1μF<br>1 2 3 0.01μF<br>VTT = VDD – 2.0V<br>V V<br>DA TT<br>**----- End of picture text -----**<br> _**FIGURE 5-1:**_ _LVPECL Test Circuit._ **==> picture [468 x 209] intentionally omitted <==** **----- Start of picture text -----**<br> LVDS<br>I<br>DD LVDS<br>6 5 4<br>V<br>DD<br>0.01μF<br>1 2 3<br>V<br>DA<br>**----- End of picture text -----**<br> _**FIGURE 5-2:** LVDS Test Circuit._ DS20006011G-page 11 2019 - 2025 Microchip Technology Inc. and its subsidiaries ## **DSC12X2/3/4** **==> picture [468 x 266] intentionally omitted <==** **----- Start of picture text -----**<br> V<br>DD<br>0.1μF<br>6<br>R<br>S<br>R<br>S<br>2 5<br>3 4<br>R<br>S<br>**----- End of picture text -----**<br> _**FIGURE 5-3:** HCSL Test Circuit._ DS20006011G-page 12 2019 - 2025 Microchip Technology Inc. and its subsidiaries **DSC12X2/3/4** ## **6.0 SOLDER REFLOW PROFILE** ## _**FIGURE 6-1:** Solder Reflow Profile._ ## **TABLE 6-1: SOLDER REFLOW** |**_FIGURE 6-1:_**<br>_Solder Reflow Profile._<br>**TABLE 6-1:**<br>**SOLDER REFLOW**|**_FIGURE 6-1:_**<br>_Solder Reflow Profile._<br>**TABLE 6-1:**<br>**SOLDER REFLOW**| |---|---| |**MSL 1 @ 260°C refer to JSTD-020C**|| |Ramp-Up Rate(200°C to Peak Temp)|3°C/Sec. Max.| |Preheat Time 150°C to 200°C|60-180 Sec.| |Time Maintained Above 217°C|60-150 Sec.| |Peak Temperature|255°C to 260°C| |Time within 5°C of Actual Peak|20-40 Sec.| |Ramp-Down Rate|6°C/Sec. Max.| |Time 25°C to Peak Temperature|8 minute Max.| DS20006011G-page 13 2019 - 2025 Microchip Technology Inc. and its subsidiaries **DSC12X2/3/4** ## **7.0 BOARD LAYOUT (RECOMMENDED)** **==> picture [469 x 289] intentionally omitted <==** **----- Start of picture text -----**<br> Via to GND layer<br>1 6<br>Supply bypass<br>capacitor<br>2 5<br>3 4<br>Via to GND layer<br>**----- End of picture text -----**<br> _**FIGURE 7-1:** DSC12x2/3/4 Recommended Board Layout._ DS20006011G-page 14 2019 - 2025 Microchip Technology Inc. and its subsidiaries **DSC12X2/3/4** ## **8.0 PHASE NOISE** _**FIGURE 8-1:** DSC12x4 Phase Noise at 100 MHz._ DS20006011G-page 15 2019 - 2025 Microchip Technology Inc. and its subsidiaries ## **DSC12X2/3/4** _**FIGURE 8-2:** DSC12x2 Phase Noise at 156.25 MHz._ DS20006011G-page 16 2019 - 2025 Microchip Technology Inc. and its subsidiaries **DSC12X2/3/4** ## **9.0 PACKAGING INFORMATION** ## **9.1 Package Marking Information** **==> picture [354 x 356] intentionally omitted <==** **----- Start of picture text -----**<br> 6-Lead VDFN* Example<br>XXXXXXXX 75M00000<br>XXXYYWW DAP1723<br>0SSS 0421<br>Legend: XX...X Product code, customer-specific information, or frequency in MHz<br>without printed decimal point<br>Y Year code (last digit of calendar year)<br>YY Year code (last 2 digits of calendar year)<br>WW Week code (week of January 1 is week ‘01’)<br>SSS Alphanumeric traceability code<br>e3 Pb-free JEDEC [®] designator for Matte Tin (Sn)<br>* This package is Pb-free. The Pb-free JEDEC designator ( )e3<br>can be found on the outer packaging for this package.<br>●, ▲, ▼Pin one index is identified by a dot, delta up, or delta down (triangle<br>Note : In the event the full Microchip part number cannot be marked on one line, it will<br>be carried over to the next line, thus limiting the number of available<br>characters for customer-specific information. Package may or may not include<br>the corporate logo.<br>Underbar (_) and/or Overbar (‾) symbol may not be to scale.<br>**----- End of picture text -----**<br> DS20006011G-page 17 2019 - 2025 Microchip Technology Inc. and its subsidiaries **DSC12X2/3/4** ## **6-Lead Very Thin Dual Flatpack No-Leads (J7A) - 2.5x2.0 mm Body [VDFN]** **==> picture [442 x 496] intentionally omitted <==** **----- Start of picture text -----**<br> Note: For the most current package drawings, please see the Microchip Packaging Specification located at<br>http://www.microchip.com/packaging<br>D A<br>B<br>N<br>(DATUM A)<br>(DATUM B)<br>E<br>NOTE 1<br>2X<br>0.05 C<br>1 2<br>2X<br>TOP VIEW<br>0.05 C<br>0.10 C<br>C A<br>A1<br>SEATING<br>PLANE<br>6X<br>SIDE VIEW 0.08 C<br>2X b2<br>1 2<br>L2<br>5X L1<br>N<br>4X b1<br>e 0.10 C A B<br>0.05 C<br>BOTTOM VIEW<br>**----- End of picture text -----**<br> **==> picture [428 x 37] intentionally omitted <==** **----- Start of picture text -----**<br> Microchip Technology Drawing C04-1005-J7A Rev E Sheet 1 of 2<br>© 2024 Microchip Technology Inc.<br>**----- End of picture text -----**<br> DS20006011G-page 18 2019 - 2025 Microchip Technology Inc. and its subsidiaries **DSC12X2/3/4** ## **6-Lead Very Thin Dual Flatpack No-Leads (J7A) - 2.5x2.0 mm Body [VDFN]** **Note:** For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging |Units|Units|MILLIMETERS|MILLIMETERS|MILLIMETERS| |---|---|---|---|---| |Dimension Limits||MIN|NOM|MAX| |Number of Terminals|N|6||| |Pitch|e|0.825 BSC||| |Overall Height|A|0.80|0.85|0.90| |Standoff|A1|0.00|0.02|0.05| |Overall Length|D|2.50 BSC||| |Overall Width|E|2.00 BSC||| |Terminal Width|b1|0.60|0.65|0.70| |Terminal Width|b2|0.20|0.25|0.30| |Terminal Length|L1|0.60|0.70|0.80| |Terminal Length|L2|0.665|0.765|0.865| ## Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-1005-J7A Rev E Sheet 2 of 2 © 2024 Microchip Technology Inc. DS20006011G-page 19 2019 - 2025 Microchip Technology Inc. and its subsidiaries **DSC12X2/3/4** ## **6-Lead Very Thin Dual Flatpack No-Leads (J7A) - 2.5x2.0 mm Body [VDFN]** **Note:** For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging **==> picture [256 x 236] intentionally omitted <==** **----- Start of picture text -----**<br> X1<br>X2<br>6<br>Y<br>G2 C<br>1 2<br>G1 SILK SCREEN<br>E<br>**----- End of picture text -----**<br> ## RECOMMENDED LAND PATTERN |Units|Units|MILLIMETERS|MILLIMETERS|MILLIMETERS| |---|---|---|---|---| |Dimension Limits||MIN|NOM|MAX| |Contact Pitch|E|0.825 BSC||| |Contact Pad Width(X4)|X1|||0.65| |Contact Pad Width(X2)|X2|||0.25| |Contact Pad Length(X6)|Y|||0.85| |Contact Pad Spacing|C||1.45|| |Space Between Contacts(X4)|G1|0.38||| |Space Between Contacts(X3)|G2|0.60||| Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing C04-3005-J7A Rev E © 2024 Microchip Technology Inc. DS20006011G-page 20 2019 - 2025 Microchip Technology Inc. and its subsidiaries **DSC12X2/3/4** ## **6-Lead Very Thin Plastic Dual Flatpack No-Lead (H5A) - 3.2x2.5 mm Body [VDFN]** **Note:** For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging **==> picture [349 x 479] intentionally omitted <==** **----- Start of picture text -----**<br> D A<br>B<br>N<br>(DATUM A)<br>(DATUM B)<br>E<br>NOTE 1<br>2X<br>0.05 C<br>1 2<br>2X<br>0.05 C TOP VIEW<br>0.10 C A1<br>C<br>A<br>SEATING<br>PLANE<br>6X<br>0.08 C<br>SIDE VIEW<br>2X b2<br>1 2<br>NOTE 1<br>L<br>N<br>4X b1<br>(L1)<br>e 0.07 C A B<br>0.05 C<br>BOTTOM VIEW<br>Microchip Technology Drawing C04-1007-H5A Rev C Sheet 1 of 2<br>**----- End of picture text -----**<br> © 2024 Microchip Technology Inc. DS20006011G-page 21 2019 - 2025 Microchip Technology Inc. and its subsidiaries **DSC12X2/3/4** ## **6-Lead Very Thin Plastic Dual Flatpack No-Lead (H5A) - 3.2x2.5 mm Body [VDFN]** **Note:** For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging |Units|Units|MILLIMETERS|MILLIMETERS|MILLIMETERS| |---|---|---|---|---| |Dimension Limits||MIN|NOM|MAX| |Number of Terminals|N|6||| |Pitch|e|1.05 BSC||| |Overall Height|A|0.80|0.85|0.90| |Standoff|A1|0.00|0.02|0.05| |Overall Length|D|3.20 BSC||| |Overall Width|E|2.50 BSC||| |Terminal Width|b1|0.85|0.90|0.95| |Terminal Width|b2|0.45|0.50|0.55| |Terminal Length|L|0.65|0.70|0.75| |Terminal Pullback|L1|0.10 REF||| ## Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M - BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-1007-H5A Rev C Sheet 2 of 2 - © 2024 Microchip Technology Inc. DS20006011G-page 22 2019 - 2025 Microchip Technology Inc. and its subsidiaries **DSC12X2/3/4** ## **6-Lead Very Thin Plastic Dual Flatpack No-Lead (H5A) - 3.2x2.5 mm Body [VDFN]** **Note:** For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging **==> picture [291 x 195] intentionally omitted <==** **----- Start of picture text -----**<br> X2<br>G2<br>6<br>Y<br>G1 C<br>(CH)<br>1 2<br>X1 SILK SCREEN<br>E<br>**----- End of picture text -----**<br> ## RECOMMENDED LAND PATTERN |Units|Units|MILLIMETERS|MILLIMETERS|MILLIMETERS| |---|---|---|---|---| |Dimension Limits||MIN|NOM|MAX| |Contact Pitch|E|1.05 BSC||| |Contact Pad Spacing|C||1.60|| |Contact Pad Width(X4)|X1|||1.00| |Contact Pad Width(X2)|X2|||0.60| |Contact Pad Length(X6)|Y|||0.85| |Space Between Contacts(X4)|G1|0.75||| |Space Between Contacts(X3)|G2|0.25||| |Pin 1 Index Chamfer(X4)|CH||0.25|| Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-3007-H5A Rev C - © 2024 Microchip Technology Inc. DS20006011G-page 23 2019 - 2025 Microchip Technology Inc. and its subsidiaries **DSC12X2/3/4** ## **6-Lead Very Thin Plastic Dual Flat, No Lead Package (H7A) - 3.2x5.0 x0.9 Body [VDFN]** **==> picture [444 x 572] intentionally omitted <==** **----- Start of picture text -----**<br> Note: For the most current package drawings, please see the Microchip Packaging Specification located at<br>http://www.microchip.com/packaging<br>D A<br>B<br>(DATUM A)<br>(DATUM B)<br>E<br>NOTE 1<br>2X<br>0.05 C<br>2X<br>0.05 C TOP VIEW<br>0.10 C<br>A1<br>C<br>A<br>SEATING<br>PLANE<br>6X<br>(A3) SIDE VIEW 0.08 C<br>NOTE 1<br>1 2<br>(CH) (K)<br>L<br>N<br>6X b<br>e 0.10 C A B<br>0.05 C<br>BOTTOM VIEW<br>Microchip Technology Drawing C04-1009-H7A Rev B Sheet 1 of 2<br>© 2024 Microchip Technology Inc.<br>**----- End of picture text -----**<br> DS20006011G-page 24 2019 - 2025 Microchip Technology Inc. and its subsidiaries **DSC12X2/3/4** ## **6-Lead Very Thin Plastic Dual Flat, No Lead Package (H7A) - 3.2x5.0 x0.9 Body [VDFN]** **Note:** For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging |Units|Units|MILLIMETERS|MILLIMETERS|MILLIMETERS| |---|---|---|---|---| |Dimension Limits||MIN|NOM|MAX| |Number of Terminals|N|6||| |Pitch|e|1.27 BSC||| |Overall Height|A|0.80|0.85|0.90| |Standoff|A1|0.00|0.02|0.05| |Terminal Thickness|A3|0.203 REF||| |Overall Length|D|5.00 BSC||| |Overall Width|E|3.20 BSC||| |Terminal Width|b|0.59|0.64|0.69| |Terminal Length|L|0.90|1.00|1.10| |Terminal 1 Index Chamfer|CH|0.25 REF||| |Terminal-to-Terminal|K|1.20 REF||| Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-1009-H7A Rev B Sheet 2 of 2 © 2024 Microchip Technology Inc. DS20006011G-page 25 2019 - 2025 Microchip Technology Inc. and its subsidiaries **DSC12X2/3/4** ## **6-Lead Very Thin Plastic Dual Flat, No Lead Package (H7A) - 3.2x5.0 x0.9 Body [VDFN]** **==> picture [441 x 305] intentionally omitted <==** **----- Start of picture text -----**<br> Note: For the most current package drawings, please see the Microchip Packaging Specification located at<br>http://www.microchip.com/packaging<br>SILK SCREEN<br>6<br>C (G)<br>Y<br>1 2<br>X<br>E<br>**----- End of picture text -----**<br> ## RECOMMENDED LAND PATTERN |Units|Units|MILLIMETERS|MILLIMETERS|MILLIMETERS| |---|---|---|---|---| |Dimension Limits||MIN|NOM|MAX| |Contact Pitch|E|1.27 BSC||| |Contact Pad Spacing|C||2.30|| |Contact Pad Width(X6)|X|||0.64| |Contact Pad Length(X6|Y|||1.10| |Contact Pad to Contact Pad(X4)|G|1.20 REF||| Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing C04-3009-H7A Rev B © 2024 Microchip Technology Inc. DS20006011G-page 26 2019 - 2025 Microchip Technology Inc. and its subsidiaries **DSC12X2/3/4** ## **6-Lead Very Thin Dual Flatpack, No Lead Package (HPA) - 7x5 mm Body [VDFN]** **Note:** For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging **==> picture [435 x 519] intentionally omitted <==** **----- Start of picture text -----**<br> D A<br>B<br>N<br>(DATUM A)<br>(DATUM B)<br>E<br>NOTE 1<br>2X<br>0.10 C<br>1 2<br>2X<br>0.10 C<br>TOP VIEW<br>A1<br>0.10 C<br>C<br>A<br>SEATING<br>PLANE<br>6X<br>0.08 C<br>SIDE VIEW<br>1 2<br>NOTE 1<br>(L1)<br>L<br>N<br>8X b<br>e 0.10 C A B<br>0.05 C<br>BOTTOM VIEW<br>Microchip Technology Drawing C04-1227-HPA Rev B Sheet 1of 2<br>© 2024 Microchip Technology Inc.<br>**----- End of picture text -----**<br> DS20006011G-page 27 2019 - 2025 Microchip Technology Inc. and its subsidiaries ## **DSC12X2/3/4** ## **6-Lead Very Thin Dual Flatpack, No Lead Package (HPA) - 7x5 mm Body [VDFN]** **Note:** For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging |Units|Units|MILLIMETERS|MILLIMETERS|MILLIMETERS| |---|---|---|---|---| |Dimension Limits||MIN|NOM|MAX| |Number of Terminals|N|6||| |Pitch|e|2.54 BSC||| |Overall Height|A|0.80|0.85|0.90| |Standoff|A1|0.00|0.02|0.05| |Overall Length|D|7.00 BSC||| |Overall Width|E|5.00 BSC||| |Terminal Width|b|1.30|1.40|1.50| |Terminal Length|L|1.00|1.10|1.20| |Pullback|L1|0.10 REF||| Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-1227-HPA Rev B Sheet 2 of 2 © 2024 Microchip Technology Inc. DS20006011G-page 28 2019 - 2025 Microchip Technology Inc. and its subsidiaries **DSC12X2/3/4** ## **6-Lead Very Thin Dual Flatpack, No Lead Package (HPA) - 7x5 mm Body [VDFN]** **==> picture [448 x 285] intentionally omitted <==** **----- Start of picture text -----**<br> Note: For the most current package drawings, please see the Microchip Packaging Specification located at<br>http://www.microchip.com/packaging<br>6<br>C<br>Y1<br>1 2<br>X1<br>SILK SCREEN<br>E<br>**----- End of picture text -----**<br> ## RECOMMENDED LAND PATTERN |Units|Units|MILLIMETERS|MILLIMETERS|MILLIMETERS| |---|---|---|---|---| |Dimension Limits||MIN|NOM|MAX| |Contact Pitch|E|2.54 BSC||| |Contact Pad Spacing|C||3.90|| |Contact Pad Width(X6)|X1|||1.55| |Contact Pad Length(X6)|Y1|||1.40| Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during reflow process Microchip Technology Drawing C04-3227-HPA Rev B © 2024 Microchip Technology Inc. DS20006011G-page 29 2019 - 2025 Microchip Technology Inc. and its subsidiaries **DSC12X2/3/4** ## **NOTES:** DS20006011G-page 30 2019 - 2025 Microchip Technology Inc. and its subsidiaries **DSC12X2/3/4** ## **APPENDIX A: REVISION HISTORY** ## **Revision A (April 2019)** - Initial release of DSC12x2/3/4 as Microchip data sheet DS20006011A. ## **Revision B (June 2020)** - Revisions to the data sheet made in the Electrical Characteristics table under HCSL: Added new rows for Integrated Phase Noise and Phase Jitter. - Also added a new bullet under the Features section. ## **Revision C (January 2021)** - Updated Phase Jitter maximum values for JRMS-CC in the Electrical Characteristics table and added a sixth note. - Updated package drawing for 6-Lead VDFN 2.5 mm x 2.0 mm Package Outline and Recommended Land Pattern. - Updated Figure 3-1. ## **Revision D (March 2021)** - Removed Note 6 from the Electrical Characteristics table. ## **Revision E (March 2022)** - Added PCI Express Gen 5 to the Applications list. ## **Revision F (May 2023)** - Added PCI Express Gen 6 to the Applications list and the.Features list. - Corrected the maximum value for Peak-to-Peak Output Swing in the LVDS (DSC12x3) section of the Electrical Characteristics table. - Added PCIe Gen 6 Phase Jitter values to the LVDS (DSC12x3) and HCSL (DSC12x4) sections of the Electrical Characteristics table. ## **Revision G (June 2025)** - Added DSA1200 reference to Features and the Product Identification System sections for customers seeking AEC-Q100 qualified parts. - Updated the package outline drawings to the most current versions. DS20006011G-page 31 2019 - 2025 Microchip Technology Inc. and its subsidiaries **DSC12X2/3/4** ## **NOTES:** DS20006011G-page 32 2019 - 2025 Microchip Technology Inc. and its subsidiaries **DSC12X2/3/4** ## **PRODUCT IDENTIFICATION SYSTEM** To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office. |**PRODUCT IDENTIFICATION SYSTEM**<br>To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.|**PRODUCT IDENTIFICATION SYSTEM**<br>To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.|**PRODUCT IDENTIFICATION SYSTEM**<br>To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.|**PRODUCT IDENTIFICATION SYSTEM**<br>To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.|**PRODUCT IDENTIFICATION SYSTEM**<br>To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.|**PRODUCT IDENTIFICATION SYSTEM**<br>To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.|**PRODUCT IDENTIFICATION SYSTEM**<br>To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.|**PRODUCT IDENTIFICATION SYSTEM**<br>To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.|**PRODUCT IDENTIFICATION SYSTEM**<br>To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.|**PRODUCT IDENTIFICATION SYSTEM**<br>To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.| |---|---|---|---|---|---|---|---|---|---| ||||||||||| ||**PART NO.**||||||||| ||||||||||| |**Device:**<br>DSC12:<br>High Performance Differential MEMS<br>Oscillators (Note 1)<br>**Control Pin:**<br>0<br>=<br>Pin 1 STDBY<br>with Pull-up<br>1<br>=<br>Pin 1 Frequency Select with Pull-up<br>2<br>=<br>Pin 1OE withPull-up<br>3<br>=<br>Pin 2 STDBY<br>with Pull-up<br>4<br>=<br>Pin 2 Frequency Select with Pull-up<br>5<br>=<br>Pin 2 OE with Pull-up<br>**Output Format:**<br>2<br>=<br>LVPECL<br>3<br>=<br>LVDS<br>4<br>=<br>HCSL<br>**Package:**<br>N<br>=<br>7 mm x 5 mm 6-Lead VDFN<br>B<br>=<br>5 mm x 3.2 mm 6-Lead CDFN<br>C<br>=<br>3.2 mm x 2.5 mm 6-Lead VDFN<br>D<br>=<br>2.5 mm x 2 mm 6-Lead VDFN<br>**Temperature:**<br>A<br>=<br>–40°C to +125°C(Available on certain options)<br>L<br>=<br>–40°C to +105°C<br>I<br>=<br>–40°C to +85°C<br>E<br>=<br>–20°C to +70°C<br>**Frequency**<br>**Stability:**<br>1<br>=<br>±50 ppm<br>2<br>=<br>±25 ppm<br>3<br>=<br>±20 ppm<br>**Output Frequency:**<br>xMxxxxxx= <10 MHz<br>xxMxxxxx= <100 MHz<br>xxxMxxxx= >100 MHz<br>CCCCC=<br>with Frequency Select<br>PROG =<br>TimeFlash<br>**Media Type:**<br><blank>=<br>Bulk<br>T<br>=<br>1,000/Reel<br>B<br>=<br>3,000/Reel|||||||||| |**Note 1:**<br>For AEC-Q100 qualified parts, please refer to the DSA1200<br>family.|||||||||| **Note 1:** For AEC-Q100 qualified parts, please refer to the DSA1200 family. DS20006011G-page 31 2019 - 2025 Microchip Technology Inc. and its subsidiaries **DSC12X2/3/4** ## **NOTES:** DS20006011G-page 32 2019 - 2025 Microchip Technology Inc. and its subsidiaries ## **Microchip Information** ## **Trademarks** The “Microchip” name and logo, the “M” logo, and other names, logos, and brands are registered and unregistered trademarks of Microchip Technology Incorporated or its affiliates and/or subsidiaries in the United States and/or other countries (“Microchip Trademarks”). Information regarding Microchip Trademarks can be found at https://www.microchip.com/en-us/about/legalinformation/microchiptrademarks. ISBN: 979-8-3371-1458-3 ## **Legal Notice** This publication and the information herein may be used only with Microchip products, including to design, test, and integrate Microchip products with your application. Use of this information in any other manner violates these terms. Information regarding device applications is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. Contact your local Microchip sales office for additional support or, obtain additional support at www.microchip.com/en-us/support/design-help/client-support-services. THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE, OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL, OR CONSEQUENTIAL LOSS, DAMAGE, COST, OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. ## **Microchip Devices Code Protection Feature** Note the following details of the code protection feature on Microchip products: - Microchip products meet the specifications contained in their particular Microchip Data Sheet. - Microchip believes that its family of products is secure when used in the intended manner, within operating specifications, and under normal conditions. - Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of Microchip product is strictly prohibited and may violate the Digital Millennium Copyright Act. - Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is “unbreakable”. Code protection is constantly evolving. Microchip is committed to continuously improving the code protection features of our products. DS20006011G-page 35 2019 - 2025 Microchip Technology Inc. and its subsidiaries
Updated at April 29, 2026
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