DS4550E+

_Rev 0; 9/04_ 

## _**I[2] C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory**_ 

## _**General Description**_ 

The DS4550 is a 9-bit, nonvolatile (NV) I/O expander with 64 bytes of NV user memory controlled by either an I[2] C-compatible serial interface or an IEEE 1149.1 JTAG port. The DS4550 offers a digitally programmable alternative to hardware jumpers and mechanical switches that are being used to control digital logic nodes. Each I/O pin is independently configurable. The outputs are open drain with selectable pullups. Each output has the ability to sink up to 16mA, and since the device is NV, it powers up in the desired state allowing it to control digital logic inputs immediately on powerup without having to wait for the host CPU to initiate control. 

## _**Applications**_ 

RAM-Based FPGA Bank Switching for Multiple Profiles 

Selecting Between Boot Flash 

## _**Features**_ 

- ♦ **Programmable Replacement for Mechanical Jumpers and Switches** 

- ♦ **Nine NV Inputs/Outputs** 

- ♦ **64-Byte NV User Memory (EEPROM)** 

- ♦ **I[2] C-Compatible Serial Interface and JTAG** 

- ♦ **Up to 8 Devices can be Multidropped on the Same I[2] C Bus** 

- ♦ **IEEE 1149.1 Boundary Scan Compliant** 

- ♦ **Open-Drain Outputs with Configurable Pullups** 

- ♦ **Outputs Capable of Sinking 16mA** 

- ♦ **Low Power Consumption** 

- ♦ **Wide Operating Voltage Range: 2.7V to 5.5V** 

- ♦ **Operating Temperature Range: -40°C to +85°C** 

Setting ASIC Configurations/Profiles 

Servers 

Network Storage 

Routers 

Telecom Equipment 

## _**Ordering Information**_ 

||**_Ordering_**|**_Information_**|
|---|---|---|
|**PART**|**TEMP RANGE**|**PIN-PACKAGE**|
|DS4550E|-40°C to +85°C|20 TSSOP|



_Add “/T&R” for tape and reel orders._ 

PC Peripherals 

## _**Pin Configuration**_ 

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TOP VIEW<br>I/O_0 1 20 GND<br>I/O_1 2 19 I/O_8<br>I/O_2 3 18 I/O_7<br>I/O_3 4 17 I/O_6<br>I/O_4 5 16 I/O_5<br>DS4550<br>A0 6 15 A2<br>A1 7 14 TDO<br>TCK 8 13 TDI<br>TMS 9 12 SCL<br>VCC 10 11 SDA<br>TSSOP<br>**----- End of picture text -----**<br>


## _**Typical Operating Circuit**_ 

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VCC<br>0.1μF<br>VCC DS4550 I/O_0<br>A0 I/O_1<br>FPGA<br>4.7k A1 I/O_2<br>A2 I/O_3<br>GND I/O_4 CLOCK<br>I/O_5 GENERATOR<br>I [2] C  SCL I/O_6<br>CPU SPEED<br>INTERFACE SDA I/O_7 SELECT<br>TCK I/O_8<br>JTAG  TMS<br>INTERFACE TDI<br>TDO<br>**----- End of picture text -----**<br>


**______________________________________________** _**Maxim Integrated Products**_ **1** 

_**For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.**_ 

## _**I[2] C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory**_ 

## **ABSOLUTE MAXIMUM RATINGS** 

Voltage on VCC, SDA, and SCL Pins Relative to Ground.............................................-0.5V to +6.0V Voltage on A0, A1, A2, TCK, TMS, TDI, and I/O_n [n = 0 to 8] Relative to Ground...................................-0.5V to VCC + 0.5V, not to exceed +6.0V. 

EEPROM Programming Temperature Range .........0°C to +70°C Storage Temperature Range .............................-55°C to +125°C Soldering Temperature .....................See IPC/JEDEC J-STD-020 Specification 

Operating Temperature Range ...........................-40°C to +85°C 

_Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability._ 

## **RECOMMENDED OPERATING CONDITIONS** 

(TA = -40°C to +85°C) 

|(TA= -40°C to +85°C)|||||
|---|---|---|---|---|
|**PARAMETER**|**SYMBOL**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|SupplyVoltage|VCC|(Note 1)|+2.7<br>+5.5|V|
|Input Logic 1|VIH||0.7 x<br>VCC<br>VCC+<br>0.3|V|
|Input Logic 0|VIL||-0.3<br>0.3 x<br>VCC|V|
||||||



## **DC ELECTRICAL CHARACTERISTICS** 

(VCC = +2.7V to +5.5V, TA = -40°C to +85°C, unless otherwise noted.) 

|(VCC= +2.7V to +5.5V, TA= -40°C|to +85°C, unl|ess otherwise noted.)|||
|---|---|---|---|---|
|**PARAMETER**|**SYMBOL**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|StandbyCurrent|ISTBY|(Note 2)|2<br>10|µA|
|Input Leakage|IL||-1.0<br>+1.0|µA|
|Input Current each I/Opin|II/O|0.4 < VI/O< 0.9 x VCC|-1.0<br>+1.0|µA|
|Low-Level Output Voltage (SDA)|VOL SDA|3mA sink current|0.4|V|
|||6mA sink current|0.6||
|I/O Pins Low-Level Output<br>Voltage|VOL I/O|16mA sink current|0.4|V|
|Low-Level Output Voltage(TDO)|VOL TDO|4mA sink current|0.4|V|
|High-Level Output Voltage(TDO)|VOH TDO|1mA source current|2.4|V|
|I/O Pin PullupResistors|RPU||4.0<br>5.5<br>7.5|kΩ|
|TMS, TDI PullupResistors|RJPU||7.5<br>10<br>12.5|kΩ|
|I/O Capacitance|CI/O|(Note 3)|10|pF|
|Power-On Reset Voltage|VPOR||1.6|V|
||||||



**2** 

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## _**I[2] C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory**_ 

## **AC ELECTRICAL CHARACTERISTICS-–I[2] C Interface (See Figure 5)** 

(VCC = +2.7V to +5.5V, TA = -40°C to +85°C, unless otherwise noted. Timing referenced to VIL(MAX) and VIH(MIN).) 

|**PARAMETER**|**SYMBOL**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|---|---|---|---|---|
|SCL Clock Frequency|fSCL|(Note 4)|0<br>400|kHz|
|Bus Free Time Between Stop and<br>Start Conditions|tBUF||1.3|µs|
|Hold Time (Repeated) Start<br>Condition|tHD:STA|(Note 5)|0.6|µs|
|Low Period of SCL|tLOW||1.3|µs|
|High Period of SCL|tHIGH||0.6|µs|
|Data Hold Time|tHD:DAT||0<br>0.9|µs|
|Data SetupTime|tSU:DAT||100|ns|
|Start SetupTime|tSU:STA||0.6|µs|
|SDA and SCL Rise Time|tR|(Note 6)|20 +<br>0.1CB<br>300|ns|
|SDA and SCL Fall Time|tF|(Note 6)|20 +<br>0.1CB<br>300|ns|
|StopSetupTime|tSU:STO||0.6|µs|
|SDA and SCL Capacitive<br>Loading|CB|(Note 6)|400|pF|
|EEPROM Write Time|tWR|I2C EEPROM write (Note 7)|10<br>20|ms|
||||||



##  **AC ELECTRICAL CHARACTERISTICS JTAG Interface (See Figure 1)** 

(VCC = +2.7V to +5.5V, TA = -40°C to +85°C, unless otherwise noted.) 

|(VCC= +2.7V to +5.5V, TA= -40C|o +85C, unl|ess otherwise noted.)|||
|---|---|---|---|---|
|**PARAMETER**|**SYMBOL**|**CONDITIONS**|**MIN**<br>**TYP**<br>**MAX**|**UNITS**|
|TCK Clock Period|t1||1000|ns|
|TCK Clock High/Low Time|t2, t3|(Note 8)|50<br>500|ns|
|TCK to TDI, TMS SetupTime|t4||15|ns|
|TCK to TDI,TMS Hold Time|t5||10|ns|
|TCK to TDO Delay|t6||50|ns|
|TCK to TDO High-Z Delay|t7||50|ns|
|EEPROM Write Time|tWR|JTAG EEPROM write (Note 9)|10<br>20|ms|
||||||



**3** 

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## _**I[2] C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory**_ 

## **NONVOLATILE MEMORY CHARACTERISTICS** 

(VCC = +2.7V to +5.5V, unless otherwise noted.) 

||**PARAMETER**<br>EEPROM Writes|**SYMBOL**|**CONDITIONS**<br>+70°C (Note 3)|**MIN**<br>**TYP**<br>**MAX**<br>50,000|**UNITS**|
|---|---|---|---|---|---|



- **Note 1:** All voltages referenced to ground. 

- **Note 2:** ISTBY is specified with SDA = SCL = TMS = TDI = VCC, outputs floating, and inputs connected to VCC or GND. 

- **Note 3:** Guaranteed by design. 

- **Note 4:** Timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I[2] C standard mode timing. 

- **Note 5:** After this period, the first clock pulse is generated. 

- **Note 6:** CBtotal capacitance of one bus line in picofarads. 

- **Note 7:** EEPROM write time applies to all the EEPROM memory and SRAM-shadowed EEPROM memory when SEE = 0. The EEPROM write time begins after a stop condition occurs. 

- **Note 8:** TCK can be stopped either high or low. 

- **Note 9:** EEPROM write begins immediately after the UPDATE-DR state that latches the data to be written. The EEPROM cannot be accessed until the EEPROM write has completed. However, the remainder of the JTAG functionality is active and accessible during the EEPROM write. 

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t1<br>t2 t3<br>TCK<br>t4 t5<br>TDI, TMS<br>t6<br>t7<br>TDO<br>**----- End of picture text -----**<br>


_Figure 1. JTAG Timing Diagram_ 

**4** 

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## _**I[2] C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory**_ 

## _**Typical Operating Characteristics**_ 

(VCC = +5.0V, TA = +25°C; TDI, TDO, TMS pins are no connects, unless otherwise noted.) 

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SUPPLY CURRENT SUPPLY CURRENT SUPPLY CURRENT<br>vs. SUPPLY VOLTAGE vs. TEMPERATURE vs. SCL FREQUENCY<br>2 2.5 20<br>I/O0-I/O7 CONTROL BITS = 0 I/O0-I/O7 CONTROL BITS = 0<br>I/O0-I/O7 PULLUPS DISABLED I/O0-I/O7 PULLUPS DISABLED 18<br>VCC = SDA = SCL = TCK 2 16<br>1.5<br>14<br>1.5 12 V CC  = SDA = TCK = 5.0V<br>1 VCC = SDA = SCL = 5.5V = TCK 10<br>1 8<br>6<br>0.5<br>0.5 VCC = SDA = SCL = 2.7V = TCK 4<br>2 VCC = SDA = TCK = 2.7V<br>0 0 0<br>2.5 3 3.5 4 4.5 5 5.5 -40 -20 0 20 40 60 80 0 100 200 300 400<br>SUPPLY VOLTAGE (V) TEMPERATURE (°C) SCL FREQUENCY (kHz)<br>DS4550 toc01 DS4550 toc02 DS4550 toc03<br>A)SUPPLY CURRENT (µ A)SUPPLY CURRENT (µ A)SUPPLY CURRENT (µ<br>**----- End of picture text -----**<br>


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SUPPLY CURRENT I/O OUTPUT VOLTAGE<br>vs. TCK FREQUENCY vs. SUPPLY VOLTAGE<br>25<br>SDA = SCL = VCC PULL-UPS ENABLED<br>5<br>PULL-DOWNS DISABLED<br>20<br>4<br>15<br>VCC = 5.0V 3 HIGH IMPEDANCE<br>10<br>2<br>5 VCC = 2.7V EEPROM RECALL AT VPOR<br>1<br>0 0<br>0 250 500 750 1000 1250 1500 1750 2000 0 1 2 3 4 5<br>TCK FREQUENCY (kHz) SUPPLY VOLTAGE (V)<br>DS4550 toc04 DS4550 toc05<br>A)<br>µ<br>SUPPLY CURRENT (<br>I/O OUTPUT VOLTAGE (V)<br>**----- End of picture text -----**<br>


**5** 

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## _**I[2] C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory**_ 

## _**Pin Description**_ 

|||**_Pin Description_**|
|---|---|---|
|**PIN**|**NAME**|**FUNCTION**|
|1|I/O_0|Input/Output 0. Bidirectional I/Opin.|
|2|I/O_1|Input/Output 1. Bidirectional I/Opin.|
|3|I/O_2|Input/Output 2. Bidirectional I/Opin.|
|4|I/O_3|Input/Output 3. Bidirectional I/Opin.|
|5|I/O_4|Input/Output 4. Bidirectional I/Opin.|
|6|A0|I2C Address Input. Inputs A0, A1, and A2 determine the I2C slave address of the device.|
|7|A1|I2C Address Input. Inputs A0, A1, and A2 determine the I2C slave address of the device.|
|8|TCK|JTAG Test Clock. This signal is used to shift data into TDI on the rising edge and out of TDO on the<br>falling edge.|
|9|TMS|JTAG Test Mode Select. This pin is sampled on the rising edge of TCK and used to place the TAP<br>into the various defined JTAG states. This pin has an internal pullup resistor.|
|10|VCC|Power SupplyVoltage|
|11|SDA|I2C Serial Data Open-Drain Input/Output|
|12|SCL|I2C Serial Clock Input|
|13|TDI|JTAG Test Data Input. Test instructions and data are clocked into this pin on the rising edge of TCK.<br>This pin has an internal pullup resistor.|
|14|TDO|JTAG Test Data Output. Test instructions and data are clocked out of this pin on the falling edge of<br>TCK. If not used, this pin should be left open circuit.|
|15|A2|I<br>2C Address Input. Inputs A0, A1, and A2 determine the I2C slave address of the device.|
|16|I/O_5|Input/Output 5. Bidirectional I/Opin.|
|17|I/O_6|Input/Output 6. Bidirectional I/Opin.|
|18|I/O_7|Input/Output 7. Bidirectional I/Opin.|
|19|I/O_8|Input/Output 8. Bidirectional I/Opin.|
|20|GND|Ground|
||||



**6** 

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## _**I[2] C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory**_ 

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Block Diagram<br>VCC<br>VCC DS4550<br>SDA BSC<br>SCL BSC I/O CONTROL<br>I [2] C<br>A0 BSC INTERFACE REGISTERS I/O CELL VCC (x9)<br>A1 BSC<br>A2 BSC<br>PULLUP ENABLE (F0h-F1h) BSC<br>VCC EEPROM RPU<br>64 BYTES<br>USER  I/O_n<br>MEMORY [n = 0 TO 8]<br>RJPU RJPU I/O CONTROL (F2h-F3h) BSC<br>TMS<br>JTAG<br>TDI<br>CONTROL<br>TDO PORT I/O STATUS (F8h-F9h) BSC<br>TCK<br>GND<br>BOUNDARY SCAN CELL (BSC)<br>**----- End of picture text -----**<br>


## _**Detailed Description**_ 

The DS4550 contains nine bidirectional, NV, input/output (I/O) pins, and a 64-byte EEPROM user memory. The I/O pins and user memory are accessible through either the I[2] C compatible serial bus or the IEEE 1149.1 JTAG interface. 

## _**Programmable NV I/O Pins**_ 

Each programmable I/O pin consists of an input and an open-collector output with a selectable internal pullup resistor. To enable the pullups for each I/O pin, write to the Pullup Enable Registers (F0h and F1h). To pull the output low or place the pulldown transistor into a high- 

impedance state, write to the I/O Control Registers (F2h and F3h). To read the voltage levels present on the I/O pins, read the I/O Status Registers (F8h and F9h). To determine the status of the output register, read the I/O Control Registers and the Pullup Resistor Registers. The I/O Control Registers and the Pullup Enable Registers are all SRAM-shadowed EEPROM registers. It is possible to disable the EEPROM writes of the registers using the SEE bit in the Configuration Register. This reduces the time required to write to the register and increases the amount of times the I/O pins can be adjusted before the EEPROM is worn out. 

**7** 

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## _**I[2] C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory**_ 

## _**Memory Map and Memory Types**_ 

The DS4550 memory map is shown in Table 1. Three different types of memory are present in the DS4550: EEPROM, SRAM-shadowed EEPROM, and SRAM. Memory locations specified as EEPROM are NV. Writing to these locations results in an EEPROM write cycle for a time specified by tWR in the _AC Electrical Characteristics_ table. Locations specified as SRAMshadowed EEPROM can be configured to operate in one of two modes specified by the SEE bit (the LSB of the Configuration Register, F4h). When the SEE bit = 0 

(default), the memory location acts like EEPROM. However, when SEE = 1, shadow SRAM is written to instead of the EEPROM. This eliminates both the EEPROM write time, tWR, as well as the concern of wearing out the EEPROM. This is ideal for applications that wish to constantly write to the I/Os. Power-up default states can be programmed for the I/Os in EEPROM (with SEE = 0) and then once powered up, SEE can be written to a 1 so that the I/Os can be updated periodically in SRAM. The final type of memory present in the DS4550 is standard SRAM. 

**Table 1. DS4550 Memory Map** 

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FACTORY<br>ADDRESS TYPE NAME FUNCTION<br>DEFAULT<br>00h to 3Fh EEPROM User Memory 64 Bytes of General-Purpose User EEPROM. 00h<br>40 to E7h  Reserved Undefined Address Space for Future Expansion. Reads and writes to <br>this space will have no affect on the device.<br>E8 to EFh EEPROM Reserved  <br>Pullup Enable for I/O_0 to I/O_7. I/O_0 is the LSB and I/O_7 is the<br>Pullup Enable<br>F0h MSB. Set the corresponding bit to enable the pullup; clear the bit to 00h<br>0<br>disable the pullup.<br>Pullup Enable for I/O_8. I/O_8 is the LSB. Only the LSB is used. Set<br>Pullup Enable<br>F1h the LSB bit to enable the pullup on I/O_8; clear the LSB to disable the 00h<br>1<br>pullup.<br>SRAM I/O Control for I/O_0 to I/O_7. I/O_0 is the LSB and I/O_7 is the MSB.<br>Shadowed Clearing the corresponding bit of the register pulls the selected I/O<br>F2h EEPROM I/O Control 0 pin low; setting the bit places the pulldown transistor into a high- FFh<br>impedance state. When the pulldown is high impedance, the output<br>[EEPROM will float if no pullup/down is connected to the pin.<br>writes are<br>disabled if I/O Control for I/O_8. I/O_8 is the LSB. Only the LSB is used. Clearing<br>the SEE bit the LSB of the register pulls the I/O_8 pin low; setting the LSB will<br>F3h I/O Control 1 place the pulldown transistor into a high-impedance state. When the 01h<br>= 1]<br>pulldown is high impedance, the output will float if no pullup/down is<br>connected to the pin.<br>Configuration Register. The LSB is the SEE bit. When set, this bit<br>F4h Configuration disables writes to the EEPROM; writing only effects the shadow 00h<br>SRAM. When set to 0, both the EEPROM and the shadow SRAM is<br>written<br>F5h to F7h User Memory 3 bytes of General-Purpose User EEPROM 00h<br>I/O Status for I/O_0 to I/O_7. I/O_0 is the LSB and I/O_7 is the MSB.<br>F8h I/O Status 0 Writing to this register has no effect. Read this register to determine <br>the state of the I/O_0 to I/O_7 pins.<br>I/O Status for I/O_8. I/O_8 is the LSB. Only the LSB is used; the other<br>F9h SRAM I/O Status 1 bits could be any value when read. Writing to this register has no <br>effect. Read this register to determine the state of the I/O_8 pin.<br>FAh to FFh SRAM User 6 Bytes of General-Purpose SRAM <br>Memory<br>**----- End of picture text -----**<br>


**8 _____________________________________________________________________** 

## _**I[2] C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory**_ 

## _**Slave Address and Address Pins**_ 

The DS4550’s I[2] C slave address is determined by the state of the A0, A1, and A2 address pins as shown in Figure 2. Address pins connected to GND result in a ‘0’ in the corresponding bit position in the slave address. Conversely, address pins connected to VCC result in a ‘1’ in the corresponding bit positions. I[2] C communication is described in detail in a later section. 

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MSB LSB<br>1 0 1 0 A2 A1 A0 R/W<br>SLAVE  READ/WRITE<br>ADDRESS* BIT<br>*THE SLAVE ADDRESS IS DETERMINED BY<br>  ADDRESS PINS A0, A1, AND A2.<br>**----- End of picture text -----**<br>


## _**IEEE 1149.1 JTAG Operation**_ 

The DS4550 contains an IEEE 1149.1 compliant JTAG port in addition to the I[2] C serial bus. Either can be used to access the internal memory. _However, the device contains no bus arbitration and hence both busses cannot be used at the same time._ All of the I/O pins on the DS4550 are IEEE 1149.1 boundary-scan compliant. I/O_0 to I/O_8 as well as the I[2] C port pins, contain the typical JTAG boundary scan cells, which allow the pins to be polled or forced high/low using standard JTAG instructions. The DS4550 also contains some extensions to normal JTAG functionality, which allows access to the internal memory. In particular, the DS4550 has three device-specific test data registers (Memory Address, Memory Read, and Memory Write) and three device-specific instructions (ADDRESS, READ, and WRITE), which provide memory access. 

_Figure 2. DS4550 I[2] C Slave Address Byte_ 

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EEPROM<br>TEST REGISTERS<br>MSB LSB<br>MEMORY ADDRESS REGISTER<br>[LENGTH = 8 BITS]<br>MEMORY READ REGISTER<br>[LENGTH = 8 BITS]<br>MEMORY WRITE REGISTER<br>[LENGTH = 8 BITS]<br>MUX 1<br>BOUNDARY SCAN REGISTER<br>[LENGTH = 33 BITS]<br>IDENTIFICATION REGISTER<br>[LENGTH = 32 BITS]<br>BYPASS REGISTER<br>[LENGTH = 1 BIT]<br>INSTRUCTION REGISTER TDO<br>[LENGTH = 4 BITS] MUX 2<br>VCC VCC<br>MSB LSB<br>RJPU RJPU<br>TDI<br>TMS TEST ACCESS PORT<br>(TAP) CONTROLLER<br>TCK<br>**----- End of picture text -----**<br>


_Figure 3. DS4550 JTAG Block Diagram_ 

**9** 

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## _**I[2] C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory**_ 

## _**Test Access Port (TAP) Controller State Machine**_ 

The TAP controller is a finite state machine that responds to the logic level at TMS on the rising edge of TCK (see Figure 4). 

**Test-Logic-Reset.** Upon power-up, the TAP controller is in the Test-Logic-Reset state. The Instruction Register contains the IDCODE instruction. All system logic of the device operates normally. 

**Run-Test/Idle.** The Run-Test/Idle state is used between scan operations or during specific tests. The Instruction Register and test data registers remain idle. 

**Select-DR-Scan.** All test data registers retain their previous state. With TMS LOW, a rising edge of TCK moves the controller into the Capture-DR state and initiates a scan sequence. TMS HIGH during a rising edge on TCK moves the controller to the Select-IR-Scan state. 

**Capture-DR.** Data can be parallel-loaded into the test data registers selected by the current instruction. If the instruction does not call for a parallel load or the selected test data register does not allow parallel loads, the test data register remains at its current value. On the 

rising edge of TCK, the controller goes to the Shift-DR state if TMS is LOW or it goes to the Exit1-DR state if TMS is HIGH. 

**Shift-DR.** The test data register selected by the current instruction is connected between TDI and TDO and shifts data one stage toward its serial output on each rising edge of TCK while TMS is LOW. On the rising edge of TCK, the controller goes to the Exit1-DR state if TMS is HIGH. 

**Exit1-DR.** While in this state, a rising edge on TCK puts the controller in the Update-DR state. A rising edge on TCK with TMS LOW puts the controller in the Pause-DR state. 

**Pause-DR.** Shifting of the test data registers is halted while in this state. All test data registers retain their previous state. The controller remains in this state while TMS is LOW. A rising edge on TCK with TMS HIGH puts the controller in the Exit2-DR state. 

**Exit2-DR.** A rising edge on TCK with TMS HIGH while in this state puts the controller in the Update-DR state. A rising edge on TCK with TMS LOW enters the Shift-DR state. 

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1 TEST-LOGIC-RESET<br>0<br>1 1 1<br>0 RUN-TEST/IDLE SELECT-DR-SCAN SELECT-IR-SCAN<br>0 0<br>1 1<br>CAPTURE-DR CAPTURE-IR<br>0 0<br>SHIFT-DR 0 SHIFT-IR 0<br>1 1<br>1 1<br>EXIT1-DR EXIT1-IR<br>0 0<br>PAUSE-DR 0 PAUSE-IR 0<br>1 1<br>0 0<br>EXIT2-DR EXIT2-IR<br>1 1<br>UPDATE-DR UPDATE-IR<br>1 0 1 0<br>**----- End of picture text -----**<br>


_Figure 4. TAP Controller State Diagram_ 

**10 ____________________________________________________________________** 

## _**I[2] C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory**_ 

**Update-DR.** A falling edge on TCK while in the Update-DR state latches the data from the shift register path of the test data registers into a set of output latches. This prevents changes at the parallel output because of changes in the shift register. On the rising edge of TCK, the controller goes to the Run-Test/Idle state if TMS is LOW or it goes to the Select-DR-Scan state if TMS is HIGH. 

**Select-IR-Scan.** All test data registers retain their previous state. The Instruction Register remains unchanged during this state. With TMS LOW, a rising edge on TCK moves the controller into the Capture-IR state. TMS HIGH during a rising edge on TCK puts the controller back into the Test-Logic-Reset state. 

**Capture-IR.** The Capture-IR state is used to load the shift register in the Instruction Register with a fixed value. This value is loaded on the rising edge of TCK. If TMS is HIGH on the rising edge of TCK, the controller enters the Exit1-IR state. If TMS is LOW on the rising edge of TCK, the controller enters the Shift-IR state. 

**Shift-IR.** In this state, the shift register in the Instruction register is connected between TDI and TDO and shifts data one stage for every rising edge of TCK toward the TDO serial output while TMS is LOW. The parallel outputs of the Instruction Register as well as all test data registers remain at their previous states. A rising edge on TCK with TMS HIGH moves the controller to the Exit1-IR state. A rising edge on TCK with TMS LOW keeps the controller in the Shift-IR state while moving data one stage through the Instruction Shift Register. 

**Exit1-IR.** A rising edge on TCK with TMS LOW puts the controller in the Pause-IR state. If TMS is HIGH on the rising edge of TCK, the controller enters the Update-IR state. 

**Pause-IR.** Shifting of the Instruction shift register is halted temporarily. With TMS HIGH, a rising edge on TCK puts the controller in the Exit2-IR state. The controller remains in the Pause-IR state if TMS is LOW during a rising edge on TCK. 

**Exit2-IR.** A rising edge on TCK with TMS HIGH puts the controller in the Update-IR state. The controller loops back to Shift-IR if TMS is LOW during a rising edge of TCK in this state. 

**Update-IR.** The instruction code that has been shifted into the Instruction shift register is latched to the parallel outputs of the Instruction Register on the falling edge of TCK as the controller enters this state. Once latched, this instruction becomes the current instruction. A rising edge on TCK with TMS LOW puts the controller in the Run-Test/Idle state. With TMS HIGH, the controller enters the Select-DR-Scan state. 

_**Instruction Register**_ 

The Instruction Register contains a shift register as well as a latched parallel output and is 4 bits in length. When the TAP controller enters the Shift-IR state, the Instruction shift register is connected between TDI and TDO. While in the Shift-IR state, a rising edge on TCK with TMS LOW shifts the data one stage toward the serial output at TDO. A rising edge on TCK in the Exit1-IR state or the Exit2-IR state with TMS HIGH moves the controller to the UpdateIR state. The falling edge of that same TCK latches the data in the Instruction shift register to the Instruction Register parallel output. Instructions supported by the DS4550 and its respective operational binary codes are shown in Table 2 below. 

**SAMPLE/PRELOAD.** This is a mandatory instruction for the IEEE 1149.1 specification that supports two functions. The digital I/Os of the device can be sampled at the Boundary Scan test data register without interfering with the normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the device to shift data into the Boundary Scan test data register through TDI using the Shift-DR state. 

**BYPASS.** When the BYPASS instruction is latched into the Instruction register, TDI connects to TDO through the 1-bit Bypass test data register. This allows data to pass from TDI to TDO without affecting the device’s normal operation. 

**EXTEST.** This instruction allows testing of all interconnections to the device. When the EXTEST instruction is latched in the Instruction register, the following actions occur. Once enabled through the Update-IR state, the parallel outputs of all digital output pins are driven. The Boundary Scan test data register is connected between TDI and TDO. The Capture-DR samples all digital inputs into the Boundary Scan test data register. 

**Table 2. Instruction Codes** 

**==> picture [240 x 150] intentionally omitted <==**

**----- Start of picture text -----**<br>
SELECTED INSTRUCTION<br>INSTRUCTION<br>REGISTER CODE<br>SAMPLE/PRELOAD Boundary Scan 0010<br>BYPASS Bypass 1111<br>EXTEST Boundary Scan 0000<br>CLAMP Bypass 0011<br>HIGHZ Bypass 0100<br>IDCODE Identification 0001<br>ADDRESS Memory Address 1001<br>READ Memory Read 1010<br>WRITE Memory Write 1011<br>**----- End of picture text -----**<br>


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## _**I[2] C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory**_ 

**CLAMP.** All digital outputs of the device output data from the Boundary Scan parallel output while connecting the Bypass test data register between TDI and TDO. The outputs do not change during the CLAMP instruction. 

**HIGHZ.** All digital outputs of the device are placed in a high-impedance state. The Bypass test data register is connected between TDI and TDO. 

**IDCODE.** When the IDCODE instruction is latched into the parallel Instruction register, the Identification test data register is selected. The device identification code is loaded into the Identification test data register on the rising edge of TCK following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially through TDO. During Test-LogicReset, the identification code is forced into the Instruction register. The ID code always has a 1 in the LSB position. The next 11 bits identify the manufacturer’s JEDEC number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version. See the diagram below. 

**ADDRESS.** This is an extension to the standard IEEE 1149.1 instruction set to support access to the memory in the DS4550. When the ADDRESS instruction is latched into the Instruction register, TDI connects to TDO through the 8-bit Memory Address test data register during the Shift-DR state. 

**READ.** This is an extension to the standard IEEE 1149.1 instruction set to support access to the memory in the DS4550. When the READ instruction is latched into the Instruction register, TDI connects to TDO through the 8-bit Memory Read test data register during the Shift-DR state. 

**WRITE.** This is an extension to the standard IEEE 1149.1 instruction set to support access to the memory in the DS4550. When the WRITE instruction is latched into the Instruction register, TDI connects to TDO through the 8-bit Memory Write test data register during the Shift-DR state. When EEPROM writes occur using the JTAG interface, the DS4550 will write the whole EEPROM memory page (8 bytes) even though only a single byte is modified. The unmodified bytes of the page are transparently rewritten to their current values. The 

DS4550’s EEPROM write cycles are specified in the _Nonvolatile Memory Characteristics_ table. The specification shown is at the worst-case temperature. It is capable of handling many more writes at room temperature. 

## _**Test Data Registers**_ 

IEEE 1149.1 requires a minimum of two test data registers; the Bypass Register and the Boundary Scan Register. The optional Identification test data register has been included in the DS4550 design along with three DS4550 specific registers (Address, Read, Write) to support access to the EEPROM. 

**Bypass Register.** This is a one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ instructions. It provides a short path between TDI and TDO. 

**Boundary Scan Register.** This register contains both a shift register path and a latched parallel output for all control cells and digital I/O cells. It is 33 bits in length. See Table 3 for the cell bit locations and definitions. 

**Identification Register.** The Identification test data register contains a 32-bit shift register and a 32-bit latched parallel output. This register is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state. 

**Memory Address Register.** This 8-bit register has a latched parallel output that holds the memory address location that is to be read from or written to. This register is selected during the ADDRESS instruction. 

**Memory Read Register.** This 8-bit load-only register will latch the 8-bit value from the memory location indicated by the address contained in the Address test data register during the Capture-DR state. The data can then be shifted out the TDO serial output by 8 rising edges of TCK during the Shift-DR state. See Table 4 for a detailed example. 

**Memory Write Register.** This 8-bit output-only register will write its 8-bit value to the memory location indicated by the address contained in the Address test data register during the Update-DR state. The data is shifted into the Write test data register through the TDI input with 8 rising edges of TCK during the Shift-DR state immediately prior to the Update-DR state. See Table 5 for a detailed example. 

## **32-Bit ID Code** 

**==> picture [502 x 44] intentionally omitted <==**

**----- Start of picture text -----**<br>
MSB                                                                                                                                                                                                 LSB<br>Version (4 Bits) Device ID (16 Bits) Manufacturer ID (11 Bits) Fixed Value (1 Bit)<br>0000 0001000000000000 00010100001 1<br>**----- End of picture text -----**<br>


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## _**I[2] C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory**_ 

## **Table 3. Boundary Scan Control Bits [33 Bits]** 

|**CELL**<br>**NUMBER**|**NAME**|**TYPE**||**CELL**<br>**NUMBER**|**NAME**|**TYPE**|
|---|---|---|---|---|---|---|
|32|A2 input|Input Observe Only||15|IO5 input|Input Observe Only|
|31|A1 input|Input Observe Only||14|IO4pubout|Output|
|30|A0 input|Input Observe Only||13|IO4pdbout|Output|
|29|SCL input|Input Observe Only||12|IO4 input|Input Observe Only|
|28|SDA input|Input Observe Only||11|IO3pubout|Output|
|27|SDA output|Output||10|IO3pdbout|Output|
|26|IO8pubout|Output||9|IO3 input|Input Observe Only|
|25|IO8pdbout|Output||8|IO2pubout|Output|
|24|IO8 input|Input Observe Only||7|IO2pdbout|Output|
|23|IO7pubout|Output||6|IO2 input|Input Observe Only|
|22|IO7pdbout|Output||5|IO1pubout|Output|
|21|IO7 input|Input Observe Only||4|IO1pdbout|Output|
|20|IO6pubout|Output||3|IO1 input|Input Observe Only|
|19|IO6pdbout|Output||2|IO0pubout|Output|
|18|IO6 input|Input Observe Only||1|IO0pdbout|Output|
|17|IO5pubout|Output||0|IO0 input|Input Observe Only|
|16|IO5 pdbout|Output|||||
||||||||



## **Table 4. EEPROM Read Cycle** 

|**.**|||
|---|---|---|
|**STEP**|**TAP STATE**|**COMMENTS**|
|Select<br>Address<br>Register|Select-IR-Scan||
||Capture-IR||
||Shift-IR(4 x TCK)|The 4-bit instruction is shifted in through TDI.|
||Exit1-IR||
||Update-IR||
|Load<br>EEPROM<br>Address|Select-DR-Scan||
||Capture-DR|No-op.|
||Shift-DR(8 x TCK)|The 8-bit address is shifted in through TDI.|
||Exit1-DR||
||Update-DR|The shifted 8-bit Address Register data is output latched.|
|Select<br>Read<br>Register|Select-IR-Scan||
||Capture-IR||
||Shift-IR(4 x TCK)|The 4-bit instruction is shifted in through TDI.|
||Exit1-IR||
||Update-IR||
|Read<br>EEPROM<br>Data|Select-DR-Scan||
||Capture-DR|The 8-bit EEPROM data is loaded into the EEPROM Read Register.|
||Shift-DR(8 x TCK)|The 8-bit data is shifted out through TDO.|
||Exit1-DR||
||Update-DR|No-op.|
||||



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## _**I[2] C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory**_ 

## **Table 5. EEPROM Write Cycle** 

|**Table 5.**|**EEPROM Write Cycl**||
|---|---|---|
|**STEP**|**TAP STATE**|**COMMENTS**|
|Select<br>Address<br>Register|Select-IR-Scan||
||Capture-IR||
||Shift-IR(4 x TCK)|The 4-bit instruction is shifted in through TDI.|
||Exit1-IR||
||Update-IR||
|Load<br>EEPROM<br>Address|Select-DR-Scan||
||Capture-DR|No-op.|
||Shift-DR(8 x TCK)|The 8-bit address is shifted in through TDI.|
||Exit1-DR||
||Update-DR|The shifted 8-bit Address Register data is output latched.|
|Select<br>Write<br>Register|Select-IR-Scan||
||Capture-IR||
||Shift-IR(4 x TCK)|The 4-bit instruction is shifted in through TDI.|
||Exit1-IR||
||Update-IR||
|Write<br>EEPROM<br>Data|Select-DR-Scan||
||Capture-DR|No-op.|
||Shift-DR(8 x TCK)|The 8-bit data is shifted in through TDI.|
||Exit1-DR||
||Update-DR|The shifted 8-bit EEPROM Write Register data is output latched and written to the<br>EEPROM.|
||||



## _**I[2] C Serial Interface Description**_ 

## _**I[2] C Definitions**_ 

The following terminology is commonly used to describe I[2] C data transfers. 

**Master Device:** The master device controls the slave devices on the bus. The master device generates SCL clock pulses, start and stop conditions. 

**Slave Devices:** Slave devices send and receive data at the master’s request. 

**Bus Idle or Not Busy:** Time between stop and start conditions when both SDA and SCL are inactive and in their logic high states. When the bus is idle it often initiates a low-power mode for slave devices. 

**Start Condition:** A start condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a start condition. See the timing diagram for applicable timing. 

**Stop Condition:** A stop condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a stop condition. See the timing diagram for applicable timing. 

**Repeated Start Condition:** The master can use a repeated start condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated starts are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated start condition is issued identically to a normal start condition. See the timing diagram for applicable timing. 

**Bit Write:** Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the setup and hold-time requirements (see Figure 5). Data is shifted into the device during the rising edge of the SCL. 

**14** 

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## _**I[2] C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory**_ 

**Bit Read:** At the end a write operation, the master must release the SDA bus line for the proper amount of setup time (see Figure 5) before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses including when it is reading bits from the slave. 

**Acknowledgement (ACK and NACK):** An Acknowledgement (ACK) or Not Acknowledge (NACK) is always the 9th bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the 9th bit. A device performs a NACK by transmitting a one during the 9th bit. Timing (Figure 5) for the ACK and NACK is identical to all other bit writes. An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data. 

**Byte Write:** A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8-bits transmitted by the master are done according to the bit write definition and the acknowledgement is read using the bit read definition. 

**Byte Read:** A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit read definition above, and the master transmits an ACK using the bit write definition to receive additional data bytes. The master must NACK the last byte read to terminated communication so the slave returns control of the SDA to the master. 

**Slave Address Byte:** Each slave on the I[2] C bus responds to a slave address byte sent immediately following a start condition. The slave address byte contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit. 

**==> picture [502 x 199] intentionally omitted <==**

**----- Start of picture text -----**<br>
SDA<br>tBUF<br>tHD:STA tSP<br>tLOW tR tF<br>SCL<br>tHD:STA tHIGH tSU:STA<br>STOP START tSU:DAT REPEATED tSU:STO<br>START<br>tHD:DAT<br>NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN)<br>**----- End of picture text -----**<br>


_Figure 5. I[2] C Timing Diagram_ 

**15** 

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## _**I[2] C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory**_ 

The DS4550’s slave address of the DS4550 is determined by the state of the A0, A1, and A2 address pins as shown in Figure 2. Address pins connected to GND result in a ‘0’ in the corresponding bit position in the slave address. Conversely, address pins connected to VCC result in a ‘1’ in the corresponding bit positions. 

When the R/W bit is 0 (such as in A0h), the master is indicating it will write data to the slave. If R/W = 1, (A1h in this case), the master is indicating it wants to read from the slave. 

If an incorrect slave address is written, the DS4550 assumes the master is communicating with another I[2] C device and ignores the communication until the next start condition is sent. 

**Memory Address:** During an I[2] C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte. 

## _**I[2] C Communication**_ 

**Writing a Single Byte to a Slave:** The master must generate a start condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a stop condition. Remember the master must read the slave’s acknowledgement during all byte write operations. 

**Writing Multiple Bytes to a Slave:** To write multiple bytes to a slave, the master generates a start condition, writes the slave address byte (R/W = 0), writes the memory address, writes up to 8 data bytes, and generates a stop condition. 

The DS4550 is capable of writing up to 8 bytes (1 page or row) with a single I[2] C write transaction. This is internally controlled by an address counter that allows data to be written to consecutive addresses without transmitting a memory address before each data byte is sent. The address counter limits the write to one 8-byte page. Attempts to write to additional pages of memory without sending a stop condition between pages results in the address counter wrapping around to the beginning of the present row. The first row begins at address 00h and subsequent rows begin at multiples of 8 there on (08h, 10h, 18h, 20h, etc). 

To prevent address wrapping from occurring, the master must send a stop condition at the end of the page, and then wait for the bus free or EEPROM write time to 

elapse. Then the master can generate a new start condition, write the slave address byte (R/W = 0), and the first memory address of the next memory row before continuing to write data. 

**Acknowledge Polling:** Any time an EEPROM page is written, the DS4550 requires the EEPROM write time (tWR) after the stop condition to write the contents of the page to EEPROM. During the EEPROM write time, the device does not acknowledge its slave address because it is busy. It is possible to take advantage of this phenomenon by repeatedly addressing the DS4550, which allows communication to continue as soon as the DS4550 is ready. The alternative to acknowledge polling is to wait for a maximum period of tWR to elapse before attempting to access the device. 

**EEPROM Write Cycles:** When EEPROM writes occur using the I[2] C interface, the DS4550 writes the whole EEPROM memory page even if only a single byte on a page was modified. Writes that do not modify all 8 bytes on the page are valid and do not corrupt any other bytes on the same page. Because the whole page is written, even bytes on the page that were not modified during the transaction are still subject to a write cycle. The DS4550’s EEPROM write cycles are specified in the _Nonvolatile Memory Characteristics_ table. The specification shown is at the worst-case temperature. It is capable of handling many more writes at room temperature. 

**Reading a Single Byte from a Slave:** Unlike the write operation that uses the specified memory address byte to define where the data is to be written, the read operation occurs at the present value of the memory address counter. To read a single byte from the slave, the master generates a start condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a stop condition. However, since requiring the master to keep track of the memory address counter is impractical, the following method should be used to perform reads from a specified memory location. 

**Manipulating the Address Counter for Reads:** A dummy write cycle can be used to force the address counter to a particular value. To do this, the master generates a start condition, writes the slave address byte (R/W = 0), writes the memory address where it desires to read, generates a repeated start condition, writes the slave address byte (R/W = 1), reads data with ACK or NACK as applicable, and generates a stop condition. 

**16** 

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## _**I[2] C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory**_ 

See Figure 6 for a read example using the repeated start condition to specify the starting memory location. 

**Reading Multiple Bytes from a Slave:** The read operation can be used to read multiple bytes with a single transfer. When reading bytes from the slave, the master simply ACKs the data byte if it desires to read another byte before terminating the transaction. After the master reads the last byte, it must NACK to indicate the end of the transfer and generate a stop condition. 

## _**Applications Information**_ 

## _**Power Supply Decoupling**_ 

To achieve best results, it is highly recommended that a decoupling capacitor is used on the IC power-supply pins. Typical values of decoupling capacitors are 0.01µF and 0.1µF. Use a high-quality, ceramic, surface-mount capacitor, and mount it as close as possible to the VCC and GND pins of the IC to minimize lead inductance. 

**==> picture [502 x 317] intentionally omitted <==**

**----- Start of picture text -----**<br>
TYPICAL I [2] C WRITE TRANSACTION<br>MSB LSB MSB LSB MSB LSB<br>START 1 0 1 0 A2 A1 A0 R/W SLAVE b7 b6 b5 b4 b3 b2 b1 b0 SLAVE b7 b6 b5 b4 b3 b2 b1 b0 SLAVE STOP<br>ACK ACK ACK<br>SLAVE READ/ REGISTER ADDRESS DATA<br>ADDRESS* WRITE<br>*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0, A1, AND A2.<br>EXAMPLE I [2] C TRANSACTIONS (WHEN A0, A1, AND A2 ARE CONNECTED TO GND)<br>A0h F2h<br>A) SINGLE BYTE WRITE START 1 0 1 0 0 0 0 0 SLAVE 1 1 1 1 0 0 1 0 SLAVE 0 0 0 0 0 0 0 0 SLAVE STOP<br>-WRITE I/O CONTROL 0 ACK ACK ACK<br>REGISTER TO 00h<br>A0h F8h A1h DATA<br>B) SINGLE BYTE READ START 1 0 1 0 0 0 0 0 SLAVE 1 1 1 1 1 0 0 0 SLAVE REPEATED 1 0 1 0 0 0 0 1 SLAVE I/O STATUS MASTER STOP<br>-READ I/O STATUS 0 RESISTER ACK ACK START ACK NACK<br>A0h F0h FFh<br>C) SINGLE BYTE WRITE START 1 0 1 0 0 0 0 0 SLAVE 1 1 1 1 0 0 0 0 SLAVE 1 1 1 1 1 1 1 1 SLAVE STOP<br>-WRITE PULLUP ENABLE 0 ACK ACK ACK<br>REGISTER TO FFh<br>A0h F2h 00h 00h<br>D) TWO BYTE WRITE START 1 0 1 0 0 0 0 0 SLAVE 1 1 1 1 0 0 1 0 SLAVE 0 0 0 0 0 0 0 0 SLAVE 0 0 0 0 0 0 0 0 SLAVE STOP<br>-WRITE I/O CONTROL 0 AND ACK ACK ACK ACK<br>I/O CONTROL 1 REGISTERS TO 00h<br>A0h F8h A1h DATA DATA<br>D) TWO BYTE READ-READ I/O STATUS 0 AND I/O START 1 0 1 0 0 0 0 0 SLAVEACK 1 1 1 1 1 0 0 0 SLAVEACK REPEATEDSTART 1 0 1 0 0 0 0 1 SLAVEACK I/O STATUS 0 MASTERACK I/O STATUS 1 MASTERNACK STOP<br>STATUS 1 RGISTERS<br>**----- End of picture text -----**<br>


_Figure 6. I[2] C Communication Examples_ 

**17** 

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## _**I[2] C and JTAG Nonvolatile 9-Bit I/O Expander Plus Memory**_ 

## _**Chip Topology**_ 

TRANSISTOR COUNT: 21,161 SUBSTRATE CONNECTED TO GROUND 

## _**Package Information**_ 

For the latest package outline information, go to **www.maxim-ic.com/DallasPackInfo** . 

_Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time._ 

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