CYW43439KUBGT

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## **Please note that Cypress is an Infineon Technologies Company.** 

The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. 

## **Continuity of document content** 

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## **Continuity of ordering part numbers** 

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www.infineon.com 

**CYW43439** 

Single-Chip IEEE 802.11 b/g/n MAC/Baseband/ Radio with Integrated Bluetooth 5.2 Compliance 

The Cypress CYW43439 is a highly integrated single-chip solution and offers the lowest RBOM in the industry for smartphones, tablets, and a wide range of other portable devices. The chip includes a 2.4 GHz WLAN IEEE 802.11 b/g/n MAC/baseband/radio, and Bluetooth 5.0 compliance. In addition, it integrates a power amplifier (PA) that meets the output power requirements of most handheld systems, a low-noise amplifier (LNA) for best-in-class receiver sensitivity, and an internal transmit/receive (iTR) RF switch, further reducing the overall solution cost and printed circuit board area. 

The WLAN host interface supports gSPI and SDIO v2.0 modes, providing a raw data transfer rate up to 200 Mbps when operating in 4-bit mode at a 50 MHz bus frequency. An independent, high-speed UART is provided for the Bluetooth host interface. 

Using advanced design techniques and process technology to reduce active and idle power, the CYW43439 is designed to address the needs of highly mobile devices that require minimal power consumption and compact size. It includes a power management unit that simplifies the system power topology and allows for operation directly from a rechargeable mobile platform battery while maximizing battery life. 

The CYW43439 implements the world’s most advanced Enhanced Collaborative Coexistence algorithms and hardware mechanisms, allowing for an extremely collaborative WLAN and Bluetooth coexistence. 

## **Features** 

## **IEEE 802.11x Key Features** 

- Single-band 2.4 GHz IEEE 802.11b/g/n. 

- Integrated iTR switch supports a single 2.4 GHz antenna shared between WLAN and Bluetooth. 

- Supports explicit IEEE 802.11n transmit beamforming. 

- Supports standard SDIO v2.0 and gSPI host interfaces. 

- Supports Space-Time Block Coding (STBC) in the receiver. 

- Integrated ARM Cortex-M3 processor and on-chip memory for complete WLAN subsystem functionality, minimizing the need to wake up the applications processor for standard WLAN functions. This allows for further minimization of power consumption, while maintaining the ability to fieldupgrade with future features. On-chip memory includes 512 KB SRAM and 640 KB ROM. 

## **Bluetooth/BLE Key Features** 

- Qualified for Bluetooth Core Specification 5.0 compliance 

- Supports Bluetooth 5.0's LE Secure Connections 

- Bluetooth Class 1 or Class 2 transmitter operation. 

- Supports extended Synchronous Connections (eSCO), for enhanced voice quality by allowing for retransmission of dropped packets. 

- Adaptive Frequency Hopping (AFH) for reducing radio frequency interference. 

- Interface support — Host Controller Interface (HCI) using a high-speed UART interface and PCM for audio data. 

- Low-power consumption improves battery life of handheld devices. 

- Supports multiple simultaneous Advanced Audio Distribution Profiles (A2DP) for stereo sound. 

## **General Features** 

- Supports a battery voltage range from 3.0V to 4.8V with an internal switching regulator. 

- Programmable dynamic power management. 

- 4 Kbit One-Time Programmable (OTP) memory for storing board parameters. 

- Can be routed on low-cost 1 x 1 PCB stack-ups. 

- 63-ball WLBGA package (4.87 mm × 2.87 mm, 0.4 mm pitch). 

- Security: 

- ❐ WPA, WPA2 and WPA3 support for powerful encryption 

- ❐ and authentication. 

- ❐ AES in WLAN hardware for faster data encryption and IEEE 802.11i compatibility. 

- ❐ Reference WLAN subsystem provides Wi–Fi Protected Setup (WPS). 

- Worldwide regulatory support: Global products supported with worldwide homologated design. 

**Cypress Semiconductor Corporation** Document Number: 002-30348 Rev. *D 

• 198 Champion Court 

San Jose, CA 95134-1709 • 408-943-2600 Revised April 17, 2023 

• 

**CYW43439** 

**Figure 1. CYW43439 System Block Diagram** 

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VDDIO VBAT<br>WL_REG_ON<br>WLAN<br>WL_IRQ<br>Host I/F<br>SDIO*/SPI<br>2.4 GHz WLAN +<br>CLK_REQ<br>Bluetooth TX/RX<br>BPF<br>BT_REG_ON<br>CYW43439<br>PCM<br>Bluetooth<br>BT_DEV_WAKE<br>Host I/F<br>BT_HOST_WAKE<br>UART<br>**----- End of picture text -----**<br>


Document Number: 002-30348 Rev. *D 

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**CYW43439** 

## **Contents** 

|**1. **|**Overview............................................................  5**|**Overview............................................................  5**||7.5.2<br>Host Controller Power Management ......30|
|---|---|---|---|---|
||1.1|Overview ............................................................. 5||7.5.3<br>BBC Power Management .......................32|
||1.2|Features .............................................................. 6||7.5.4<br>FM Power Management .........................32<br>7.5.5<br>Wideband Speech ..................................32|
||1.3|Standards Compliance ........................................ 6||7.5.6<br>Packet Loss Concealment ......................32|
|**2. **|**Power Supplies and Power Management.......  8**|||7.5.7<br>Codec Encoding .....................................33<br>7.5.8<br>Multiple Simultaneous A2DP Audio|
||2.1|Power Supply Topology ...................................... 8||Streams ..................................................33|
||2.2|CYW43439 PMU Features .................................. 8|7.6|Adaptive Frequency Hopping .............................33|
||2.3|WLAN Power Management ............................... 11|7.7|Advanced Bluetooth/WLAN Coexistence ...........33|
||2.4|PMU Sequencing .............................................. 11|7.8|Fast Connection (Interlaced Page and Inquiry|
||2.5|Power-Off Shutdown ......................................... 12||Scans) ................................................................33|
||2.6|Power-Up/Power-Down/Reset Circuits ............. 12|**8. Microprocessor and Memory Unit for**||
|**3. **|**Frequency References ...................................  13**||**Bluetooth.........................................................  34**||
||3.1|Crystal Interface and Clock Generation ............ 13|8.1|RAM, ROM, and Patch Memory .........................34|
||3.2|TCXO ................................................................ 13|8.2|Reset ..................................................................34|
||3.3|External 32.768 kHz Low-Power Oscillator ....... 15|**9. Bluetooth Peripheral Transport Unit.............  35**||
|**4. **|**WLAN System Interfaces ...............................  16**<br>4.1<br>SDIO v2.0 .......................................................... 16<br>4.1.1<br>SDIO Pin Descriptions ........................... 16||9.1|PCM Interface ....................................................35<br>9.1.1<br>Slot Mapping ...........................................35<br>9.1.2<br>Frame Synchronization ...........................35<br>9.1.3<br>Data Formatting ......................................35|
||4.2|Generic SPI Mode ............................................. 17||9.1.4<br>Wideband Speech Support .....................35|
|||4.2.1<br>SPI Protocol ........................................... 18||9.1.5<br>PCM Interface Timing .............................36|
|||4.2.2<br>gSPI Host-Device Handshake ............... 21<br>4.2.3<br>Boot-Up Sequence ................................ 22|9.2|UART Interface ..................................................40|
|**5. **|**WLAN Radio Subsystem ................................  25**<br>5.1<br>Receive Path ..................................................... 26||**10.CPU and Global Functions ............................  42**<br>10.1 WLAN CPU and Memory Subsystem ................42||
||5.2|Transmit Path .................................................... 26|10.2|One-Time Programmable Memory .....................42|
||5.3|Calibration ......................................................... 26|10.3|GPIO Interface ...................................................42|
||||10.4|External Coexistence Interface ..........................43|
|**6. **|**Bluetooth Overview ........................................  27**||10.5|JTAG Interface ...................................................43|
||6.1|Features ............................................................ 27|10.6|UART Interface ..................................................43|
||6.2|Bluetooth Radio ................................................. 28|||
|||6.2.1<br>Transmit ................................................. 28|**11.WLAN Software Architecture.........................  44**||
|||6.2.2<br>Digital Modulator .................................... 28|11.1|Host Software Architecture ................................44|
|||6.2.3<br>Digital Demodulator and Bit Synchronizer 28|11.2|Device Software Architecture .............................44|
|||6.2.4<br>Power Amplifier ..................................... 28||11.2.1 Remote Downloader ...............................44|
|||6.2.5<br>Receiver ................................................ 28<br>6.2.6<br>Digital Demodulator and Bit Synchronizer 28|11.3|Wireless Configuration Utility .............................44|
|||6.2.7<br>Receiver Signal Strength Indicator ........ 28|**12.Pinout and Signal Descriptions.....................  45**||
|||6.2.8<br>Local Oscillator Generation ................... 28<br>6.2.9<br>Calibration ............................................. 28|12.1|Ball Map .............................................................45|
||||12.2|WLBGA Ball List in Ball Number Order with X-Y|
|**7. **|**Bluetooth Baseband Core..............................  29**|||Coordinates  .......................................................46|
||7.1|Bluetooth Standard Features ............................ 29|12.3|WLBGA Ball List Ordered By Ball Name ............48|
||7.2|Bluetooth 5.2 Features ...................................... 29|12.4|Signal Descriptions ............................................49|
||7.3|Link Control Layer ............................................. 29|12.5|WLAN GPIO Signals and Strapping Options .....52|
||7.4|Test Mode Support ............................................ 30|12.6|Chip Debug Options ...........................................52|
||7.5|Bluetooth Power Management Unit .................. 30|12.7|I/O States ...........................................................53|
|||7.5.1<br>RF Power Management ......................... 30|||



Document Number: 002-30348 Rev. *D 

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**CYW43439** 

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|||
|---|---|
|13.DC Characteristics..........................................  55|
|13.1|Absolute Maximum Ratings .............................. 55|
|13.2|Environmental Ratings ...................................... 55|
|13.3|Electrostatic Discharge Specifications .............. 55|
|13.4|Recommended Operating Conditions and DC|
|Characteristics .................................................. 56|
|14.WLAN RF Specifications ................................  58|
|14.1|2.4 GHz Band General RF Specifications ......... 58|
|14.2|WLAN 2.4 GHz Receiver Performance|
|Specifications .................................................... 59|
|14.3|WLAN 2.4 GHz Transmitter Performance|
|Specifications .................................................... 62|
|14.4|General Spurious Emissions Specifications ...... 63|
|15.Bluetooth RF Specifications..........................  64|
|16.Internal Regulator Electrical Specifications.  70|
|16.1|Core Buck Switching Regulator ........................ 70|
|16.2|3.3V LDO (LDO3P3) ......................................... 71|
|16.3|CLDO ................................................................ 72|
|16.4|LNLDO .............................................................. 73|
|17.System Power Consumption .........................  74|
|17.1|WLAN Current Consumption ............................. 74|
|17.1.1|2.4 GHz Mode ....................................... 74|
|17.2|Bluetooth Consumption ..................................... 75|

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|||
|---|---|
|18.Interface Timing and AC Characteristics .....  76|
|18.1|SDIO Default Mode Timing ................................76|
|18.2|SDIO High-Speed Mode Timing .........................77|
|18.3|gSPI Signal Timing .............................................78|
|18.4|JTAG Timing ......................................................78|
|19.Power-Up Sequence and Timing...................  79|
|19.1|Sequencing of Reset and Regulator Control|
|Signals ...............................................................79|
|19.1.1|Description of Control Signals ................79|
|19.1.2|Control Signal Timing Diagrams .............80|
|20.Package Information ......................................  82|
|20.1|Package Thermal Characteristics ......................82|
|20.1.1|Junction Temperature Estimation and PSI|
|Versus Theta|........................................82|
|jc|
|21.Mechanical Information..................................  83|
|22.Ordering Information......................................  85|
|26.Additional Information ...................................  85|
|26.1|Acronyms and Abbreviations .............................85|
|26.2|IoT Resources ....................................................85|
|Document History........................................................... 86|
|Sales, Solutions, and Legal Information ...................... 87|
|Worldwide Sales and Design Support ..............................87|
|Products ...........................................................................87|
|PSoC® Solutions ..............................................................87|
|Cypress Developer Community ........................................87|
|Technical Support .............................................................87|

**----- End of picture text -----**<br>


Document Number: 002-30348 Rev. *D 

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**CYW43439** 

## **1.  Overview** 

## **1.1  Overview** 

The Cypress CYW43439 provides the highest level of integration for a mobile or handheld wireless system, with integrated IEEE 802.11 b/g/n. It provides a small form-factor solution with minimal external components to drive down cost for mass volumes and allows for handheld device flexibility in size, form, and function. The CYW43439 is designed to address the needs of highly mobile devices that require minimal power consumption and reliable operation. 

Figure 2 shows the interconnection of all the major physical blocks in the CYW43439 and their associated external interfaces, which are described in greater detail in subsequent sections. 

**Figure 2. CYW43439 Block Diagram** 

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Cortex<br>Debug<br>M3<br>AHB<br>- Bll<br>AHB to APB<br>= Bridge RAM<br>APB = ROM<br>WD Timer Patch<br>— InterCtrl<br>SW Timer [id DMA<br>GPIO Bus Arb<br>Ctrl ARM IP<br>=e<br>JTAG supported over SDIO or BT PCM<br>SDIO or gSPI<br>SWREG Power<br>BPL<br>UART LDOx2 Supply<br>Buffer Modem RF SDIO ControlPMU LPO Sleep CLK<br>APU Digital  gSPI XTAL OSC. XTAL<br>Debug  Demod.  POR WL_REG_ON<br>i P| UART = BT Clock/  & Bit  hej [ of<br>Hopper Sync ARM<br>Digital BlueRF  PA CM3 WDT<br>I/O Interface OTP<br>PCM LCU DigitalMod. GPIO GPIO<br>RAM UART UART<br>RX/TX JTAG* Supported over SDIO or BT PCM<br>i= b im ROM FI<br>GPIO<br>Dbl Buffer ) OL<br>IF<br>BT PHY PLL<br>= Wake/ BT Clock Control _-ii- BT‐WLAN<br>Sleep CtrlWiMax Coex Sleep‐ Clock  PMU  ECI 2.4 GHzPA<br>time  PMU<br>Keeping Management Ctrl Shared LNA<br>BPF<br>WiMax<br>Coex. LPO XO  POR<br>Buffer<br>Wd WLAN P|<br>PTU<br>* Via GPIO configuration, JTAG is supported over SDIO or BT PCM<br>ETM JTAG* SDP<br>AHB Bus Matrix<br>Common and  Radio Digital<br>JTAG*<br>I/O Port Control Backplane<br>MAC LNPPHY Radio<br>2.4 GHz<br>IEEE 802.11a/b/g/n<br>XTAL VBAT VREGs BT_REG_ON<br>**----- End of picture text -----**<br>


Document Number: 002-30348 Rev. *D 

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**CYW43439** 

## **1.2  Features** 

The CYW43439 supports the following WLAN and Bluetooth features: 

■ IEEE 802.11b/g/n single-band radio with an internal power amplifier, LNA, and T/R switch 

- BT5.2 Compliance 

- LE over SDIO 

- LE Mesh 

- Bluetooth 5.2 with integrated Class 1 PA 

- Concurrent Bluetooth, and WLAN operation 

- On-chip WLAN driver execution capable of supporting IEEE 802.11 functionality 

- Simultaneous BT/WLAN reception with a single antenna 

- WLAN host interface options: 

- ❐ SDIO v2.0, including default and high-speed timing. 

- ❐ gSPI—up to a 50 MHz clock rate 

- BT UART (up to 4 Mbps) host digital interface that can be used concurrently with the above WLAN host interfaces. 

■ ECI—enhanced coexistence support, which coordinates BT SCO transmissions around WLAN receptions. 

- PCM for BT audio 

- HCI high-speed UART (H4 and H5) transport support 

- Wideband speech support (16 bits, 16 kHz sampling PCM, through PCM interfaces) 

- Bluetooth SmartAudio[®] technology improves voice and music quality to headsets. 

- Bluetooth low power inquiry and page scan 

- Bluetooth Low Energy (BLE) support 

- Bluetooth Packet Loss Concealment (PLC) 

- Multiple simultaneous A2DP audio streams 

## **1.3  Standards Compliance** 

The CYW43439 supports the following standards: 

■ Bluetooth 5.2 compliance (Basic Rate, Enhanced Data Rate and Bluetooth Low Energy) 

■ IEEE 802.11n—Handheld Device Class (Section 11) 

■ IEEE 802.11b 

■ IEEE 802.11g 

- IEEE 802.11d 

■ IEEE 802.11h 

■ IEEE 802.11i 

■ The CYW43439 will support the following future drafts/standards: 

■ IEEE 802.11r — Fast Roaming (between APs) ■ IEEE 802.11k — Resource Management ■ IEEE 802.11w — Secure Management Frames ■ IEEE 802.11 Extensions: ■ IEEE 802.11e QoS Enhancements (as per the WMM[®] specification is already supported) ■ IEEE 802.11i MAC Enhancements ■ IEEE 802.11r Fast Roaming Support 

Document Number: 002-30348 Rev. *D 

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**CYW43439** 

## ■ IEEE 802.11k Radio Resource Measurement 

The CYW43439 supports the following security features and proprietary protocols: 

## ■ Security: 

- ❐ WEP 

- ❐ WPA[™] Personal 

- ❐ WPA2[™] Personal 

❐ WPA3[™] 

❐ WMM 

❐ WMM-PS (U-APSD) 

❐ WMM-SA 

❐ WAPI 

❐ AES (Hardware Accelerator) 

- ❐ TKIP (host-computed) 

- ❐ CKIP (SW Support) 

## ■ Proprietary Protocols: 

- ❐ CCXv2 

- ❐ CCXv3 

- ❐ CCXv4 

- ❐ CCXv5 

■ IEEE 802.15.2 Coexistence Compliance — on silicon solution compliant with IEEE 3-wire requirements. 

Document Number: 002-30348 Rev. *D 

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**CYW43439** 

## **2.  Power Supplies and Power Management** 

## **2.1  Power Supply Topology** 

One Buck regulator, multiple LDO regulators, and a power management unit (PMU) are integrated into the CYW43439. All regulators are programmable via the PMU. These blocks simplify power supply design for Bluetooth and WLAN functions in embedded designs. 

A single VBAT (3.0V to 4.8V DC maximum) and VDDIO supply (1.8V to 3.3V) can be used, with all additional voltages being provided by the regulators in the CYW43439. 

Two control signals, BT_REG_ON and WL_REG_ON, are used to power up the regulators and take the respective circuit blocks out of reset. The CBUCK CLDO and LNLDO power up when any of the reset signals are deasserted. All regulators are powered down only when both BT_REG_ON and WL_REG_ON are deasserted. The CLDO and LNLDO can be turned on and off based on the dynamic demands of the digital baseband. 

The CYW43439 allows for an extremely low power-consumption mode by completely shutting down the CBUCK, CLDO, and LNLDO regulators. When in this state, LPLDO1 provides the CYW43439 with all required voltage, further reducing leakage currents. **Note:** VBAT should be connected to the LDO_VDDBAT5V and SR_VDDBAT5V pins of the device. 

**Note:** VDDIO should be connected to the  WCC_VDDIO pin of the device. 

## **2.2  CYW43439 PMU Features** 

The PMU supports the following: 

- VBAT to 1.35Vout (170 mA nominal, 370 mA maximum) Core-Buck (CBUCK) switching regulator 

- VBAT to 3.3Vout (250 mA nominal, 450 mA maximum 800 mA peak maximum) LDO3P3 

- 1.35V to 1.2Vout (100 mA nominal, 150 mA maximum) LNLDO 

- 1.35V to 1.2Vout (80 mA nominal, 200 mA maximum) CLDO with bypass mode for deep sleep 

- Additional internal LDOs (not externally accessible) 

■ PMU internal timer auto-calibration by the crystal clock for precise wake-up timing from extremely low power-consumption mode. Figure 3 and Figure 4 show the typical power topology of the CYW43439. 

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**CYW43439** 

## **Figure 3. Typical Power Topology (1 of 2)** 

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VBAT SR_VDDBAT5V be a WL RF—TX Mixer and PA(not all versions)<br>Mini PMU<br>CYW434391.2V Internal VCOLDO80 mA (NMOS) 1.2V WL RF—LOGEN<br>VBAT: pf Internal RXLDO10 mA (NMOS) L |] 1.2V S|r WL RF—RX LNA<br>Operational:Performance: 3.0—4.8V3.0—4.8V VDD1P35 Internal ADCLDO10 mA (NMOS) 1.2V WL RF—ADC REF<br>Absolute Maximum: 5.5V<br>VDDIO Internal TXLDO80 mA (PMOS) 1.2V a WL RF—TX<br>Operational: 1.8—3.3V 1.35V - f |<br>Internal AFELDO<br>= 80 mA (NMOS) 1.2V ———— WL RF—AFE and TIA<br>Core Buck  10 mA average,<br>(320 mA)Int_SR_VBAT Peak: 370 mAAvg: 170 mARegulator  SR_VLX 2.2 uH Mini PMU is placed in WL radio 600 @ WLRF_XTAL_VDD1P2 > 10 mA at start‐upWL RF—RFPLL PFD and MMD<br>SW1 0603 100 MHz WL RF—XTAL<br>1.2V<br>SR_VBAT5V LDO_VDD_1P5 LNLDO FM_RF_VDD 4.6 mA<br>VBAT SR_PVSS 4.7 u0402 F (100 mA) VOUT_LNLDO 2.2 uF0402 0.1 uF0201 BTFM_PLL_VDD 6.4 mA FM LNA, Mixer, TIA, VCO<br>GND PMU_VSS FM PLL, LOGEN, Audio DAC/BT PLL<br>BT_VCO_VDD<br>BT LNA, Mixer, VCO<br>BT_IF_VDD<br>BT ADC, Filter<br>WCC_VDDIO WCC_VDDIO (40 mA) LPLDO1(5 mA) ~ —_<br>_—s os LE<br>WLAN/BT/CLB/Top, Always On<br>VDDC1<br>CL LDO 1.3V, 1.2V, or 0.95V WL OTP<br>Peak: 200 mAAvg: 80 mA (AVS) VDDC2<br>(Bypass in deep‐sleep) VOUT_CLDO 2.2 uF0402 WL Digital and PHY<br>WL_REG_ON o_wl_resetb<br>BT_REG_ON o_bt_resetb<br>WL VDDM (SROMs & AOS)<br>Supply ball Supply bump/pad Power switch<br>[| L_| e a BT VDDM<br>Ground ball Ground bump/pad No power switch<br>[| | =<br>BT/WLAN reset No dedicated power switch, but internal power‐<br>balls External to chip down modes and block‐specific power switches<br>[| L_| = BT Digital<br>1.1V<br>**----- End of picture text -----**<br>


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**CYW43439** 

**Figure 4. Typical Power Topology (2 of 2)** 

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CYW43439<br>6.4 mA<br>1.8V, 2.5V, and 3.3V SS WL BBPLL/DFLL<br>SS WL OTP 3.3V<br>LDO3P3 with<br>VBAT Back‐Power  VOUT_3P3 WLRF_PA_VDD 480 to 800 mA<br>Protection WL RF—PA (2.4 GHz)<br>VDDBAT5VLDO_ (Peak 450‐800 mA200 mA Average) 3.3V 4.7 uF0402 0201 uF1 2.5V Cap‐less  6.4 mA<br>LNLDO WL RF—ADC, AFE, LOGEN,<br>22  (10 mA) LNA, NMOS Mini‐PMU LDOs<br>ohm<br>Placed inside WL Radio<br>Peak: 70 mA<br>BT_PAVDD Average: 15 mA<br>[ S BT Class 1 PA O<br>1 uF<br>0201<br>Power switch<br>External to chip<br>- No power switch<br>Supply ball<br>: aac<br>= No dedicated power switch, but internal power‐<br>down modes and block‐specific power switches<br>**----- End of picture text -----**<br>


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**CYW43439** 

## **2.3  WLAN Power Management** 

The CYW43439 has been designed with the stringent power consumption requirements of mobile devices in mind. All areas of the chip design are optimized to minimize power consumption. Silicon processes and cell libraries were chosen to reduce leakage current and supply voltages. Additionally, the CYW43439 integrated RAM is a high volatile memory with dynamic clock control. The dominant supply current consumed by the RAM is leakage current only. Additionally, the CYW43439 includes an advanced WLAN power management unit (PMU) sequencer. The PMU sequencer provides significant power savings by putting the CYW43439 into various power management states appropriate to the operating environment and the activities that are being performed. The power management unit enables and disables internal regulators, switches, and other blocks based on a computation of the required resources and a table that describes the relationship between resources and the time needed to enable and disable them. Power-up sequences are fully programmable. Configurable, free-running counters (running at the 32.768 kHz LPO clock) in the PMU sequencer are used to turn on/turn off individual regulators and power switches. Clock speeds are dynamically changed (or gated altogether) for the current mode. Slower clock speeds are used wherever possible. 

The CYW43439 WLAN power states are described as follows: 

- Active mode— All WLAN blocks in the CYW43439 are powered up and fully functional with active carrier sensing and frame transmission and receiving. All required regulators are enabled and put in the most efficient mode based on the load current. Clock speeds are dynamically adjusted by the PMU sequencer. 

- Doze mode—The radio, analog domains, and most of the linear regulators are powered down. The rest of the CYW43439 remains powered up in an IDLE state. All main clocks (PLL, crystal oscillator) are shut down to reduce active power to the minimum. The 32.768 kHz LPO clock is available only for the PMU sequencer. This condition is necessary to allow the PMU sequencer to wake up the chip and transition to Active mode. In Doze mode, the primary power consumed is due to leakage current. 

- Deep-sleep mode—Most of the chip, including analog and digital domains, and most of the regulators are powered off. Logic states in the digital core are saved and preserved to retention memory in the always-on domain before the digital core is powered off. To avoid lengthy hardware reinitialization, the logic states in the digital core are restored to their pre-deep-sleep settings when a wakeup event is triggered by an external interrupt, a host resume through the SDIO bus, or by the PMU timers. 

- Power-down mode—The CYW43439 is effectively powered off by shutting down all internal regulators. The chip is brought out of this mode by external logic re-enabling the internal regulators. 

## **2.4  PMU Sequencing** 

The PMU sequencer is used to minimize system power consumption. It enables and disables various system resources based on a computation of required resources and a table that describes the relationship between resources and the time required to enable and disable them. 

Resource requests can derive from several sources: clock requests from cores, the minimum resources defined in the _ResourceMin_ register, and the resources requested by any active resource request timers. The PMU sequencer maps clock requests into a set of resources required to produce the requested clocks. 

Each resource is in one of the following four states: 

- enabled 

- disabled 

- transition_on 

## ■ transition_off 

The timer value is 0 when the resource is enabled or disabled and nonzero during state transition. The timer is loaded with the time_on or time_off value of the resource when the PMU determines that the resource must be enabled or disabled. That timer decrements on each 32.768 kHz PMU clock. When it reaches 0, the state changes from transition_off to disabled or transition_on to enabled. If the time_on value is 0, the resource can transition immediately from disabled to enabled. Similarly, a time_off value of 0 indicates that the resource can transition immediately from enabled to disabled. The terms _enable sequence_ and _disable sequence_ refer to either the immediate transition or the timer load-decrement sequence. 

During each clock cycle, the PMU sequencer performs the following actions: 

- Computes the required resource set based on requests and the resource dependency table. 

- Decrements all timers whose values are nonzero. If a timer reaches 0, the PMU clears the ResourcePending bit for the resource and inverts the ResourceState bit. 

- Compares the request with the current resource status and determines which resources must be enabled or disabled. 

- Initiates a disable sequence for each resource that is enabled, no longer being requested, and has no powered-up dependents. 

- Initiates an enable sequence for each resource that is disabled, is being requested, and has all of its dependencies enabled. 

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**CYW43439** 

## **2.5  Power-Off Shutdown** 

The CYW43439 provides a low-power shutdown feature that allows the device to be turned off while the host, and any other devices in the system, remain operational. When the CYW43439 is not needed in the system, VDDIO_RF and VDDC are shut down while VDDIO remains powered. This allows the CYW43439 to be effectively off while keeping the I/O pins powered so that they do not draw extra current from any other devices connected to the I/O. 

During a low-power shutdown state, provided VDDIO remains applied to the CYW43439, all outputs are tristated, and most input signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths or create loading on any digital signals in the system, and enables the CYW43439 to be fully integrated in an embedded device and to take full advantage of the lowest power-savings modes. 

When the CYW43439 is powered on from this state, it is the same as a normal power-up, and the device does not retain any information about its state from before it was powered down. 

## **2.6  Power-Up/Power-Down/Reset Circuits** 

The CYW43439 has two signals (see Table 1) that enable or disable the Bluetooth and WLAN circuits and the internal regulator blocks, allowing the host to control power consumption. For timing diagrams of these signals and the required power-up sequences, see Section 19.: “Power-Up Sequence and Timing” . 

**Table 1. Power-Up/Power-Down/Reset Control Signals** 

|**Signal**|**Description**|
|---|---|
|WL_REG_ON|This signal is used by the PMU (with BT_REG_ON) to power-up the WLAN section. It is also OR-gated with the<br>BT_REG_ON input to control the internal CYW43439 regulators. When this pin is high, the regulators are enabled<br>and the WLAN section is out of reset. When this pin is low, the WLAN section is in reset. If BT_REG_ON and<br>WL_REG_ON are both low, the regulators are disabled. This pin has an internal 200 kpull-down resistor that<br>is enabled by default. It can be disabled through programming.|
|BT_REG_ON|This signal is used by the PMU (with WL_REG_ON) to decide whether or not to power down the internal<br>CYW43439 regulators. If BT_REG_ON and WL_REG_ON are low, the regulators will be disabled. This pin has<br>an internal 200 kpull-down resistor that is enabled by default. It can be disabled through programming.|



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**CYW43439** 

## **3.  Frequency References** 

An external crystal is used for generating all radio frequencies and normal operation clocking. As an alternative, an external frequency reference driven by a temperature-compensated crystal oscillator (TCXO) signal may be used. No software settings are required to differentiate between the two. In addition, a low-power oscillator (LPO) is provided for lower power mode timing. 

## **3.1  Crystal Interface and Clock Generation** 

The CYW43439 can use an external crystal to provide a frequency reference. The recommended configuration for the crystal oscillator, including all external components, is shown in Figure 5. Consult the reference schematics for the latest configuration. 

**Figure 5. Recommended Oscillator Configuration** 

**==> picture [202 x 157] intentionally omitted <==**

**----- Start of picture text -----**<br>
C<br>WLRF_XTAL_XOP<br>12 – 27 pF<br>C<br>WLRF_XTAL_XON<br>R<br>12 – 27 pF<br>Note : Resistor value determined by crystal drive level.<br>See reference schematics for details.<br>**----- End of picture text -----**<br>


The CYW43439 uses a fractional-N synthesizer to generate the radio frequencies, clocks, and data/packet timing so that it can operate using numerous frequency references. The frequency reference can be an external source such as a TCXO or a crystal interfaced directly to the CYW43439. 

The default frequency reference setting is a 37.4 MHz crystal or TCXO. The signal requirements and characteristics for the crystal interface are shown in Table 2. 

**Note:** Although the fractional-N synthesizer can support many reference frequencies, frequencies other than the default require support to be added in the driver, plus additional extensive system testing. Contact Cypress for further details. 

## **3.2  TCXO** 

As an alternative to a crystal, an external precision TCXO can be used as the frequency reference, provided that it meets the phase noise requirements listed in Table 2. 

If the TCXO is dedicated to driving the CYW43439, it should be connected to the WLRF_XTAL_XOP pin through an external capacitor with value ranges from 200 pF to 1000 pF as shown in Figure 6. 

**Figure 6. Recommended Circuit to Use with an External Dedicated TCXO** 

**==> picture [233 x 62] intentionally omitted <==**

**----- Start of picture text -----**<br>
200 pF – 1000 pF<br>TCXO WLRF_XTAL_XOP<br>NC WLRF_XTAL_XON<br>**----- End of picture text -----**<br>


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**CYW43439** 

**Table 2. Crystal Oscillator and External Clock Requirements and Performance** 

|**Parameter**<br>~~eee~~|**Conditions/Notes**<br>~~eee~~|**Crystal**<br>~~eee~~|**Crystal**<br>~~eee~~|**Crystal**<br>~~eee~~|**External Frequency**<br>**Reference**<br>~~eee~~|**External Frequency**<br>**Reference**<br>~~eee~~|**External Frequency**<br>**Reference**<br>~~eee~~|~~eee~~|
|---|---|---|---|---|---|---|---|---|
|||**Min.**<br>~~eee~~<br>~~a~~|**Typ.**<br>~~eee~~<br>~~a~~|**Max.**<br>~~eee~~<br>~~a~~|**Min.**<br>~~eee~~<br>~~a~~|**Typ.**<br>~~eee~~<br>~~a~~|**Max.**<br>~~eee~~<br>~~a~~|**Units**<br>~~eee~~<br>~~a~~|
|Frequency<br>~~a~~|–|–|37.4[1]|–|–|–|–|MHz|
|Crystal load capacitance<br>~~a~~|–|–|12|–|–|–|–|pF|
|ESR<br>~~a~~<br>~~a~~|–<br>~~ee~~|–<br>~~ee~~|–<br>~~ee~~|60|–|–|–|Ω|
|Drive level<br>~~ee~~<br>~~a~~|External crystal must be able to<br>tolerate this drive level.<br>~~ee~~<br>~~ee~~|200<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|–<br>~~ee~~|–<br>~~ee~~|–<br>~~ee~~|–<br>~~ee~~|μW<br>~~ee~~|
|Input Impedance (WLRF_X-<br>TAL_XOP)<br>~~a~~|Resistive<br>~~ee~~<br>~~eee~~|–<br>~~ee~~<br>~~eee~~|–<br>~~ee~~<br>~~eee~~|–<br>~~eee~~|10k<br>~~eee~~|100k<br>~~eee~~|–<br>~~eee~~|Ω<br>~~eee~~|
||Capacitive<br>~~ee~~<br>~~eee~~<br>~~a~~|–<br>~~ee~~<br>~~eee~~|–<br>~~ee~~<br>~~eee~~|–<br>~~eee~~|–<br>~~eee~~|–<br>~~eee~~|7<br>~~eee~~|pF<br>~~eee~~|
|WLRF_XTAL_XOP input voltage <br>~~a~~|AC-coupled analog signal|–|–|–|400[2]|–|1260|mVp-p|
|WLRF_XTAL_XOP input low<br>level<br>~~a~~<br>~~a~~<br>~~a~~|DC-coupled digital signal<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|–<br>~~ee~~|–|0|–|0.2|V|
|WLRF_XTAL_XOP input high<br>level<br>~~a~~<br>~~a~~|DC-coupled digital signal<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|–<br>~~ee~~|–|1.0|–|1.26|V|
|Frequency tolerance<br>Initial + over temperature<br>~~a~~<br>~~a~~|–<br>~~ee~~<br>~~ee~~|–20<br>~~ee ~~<br>~~ee~~|–<br> ~~ee~~<br>~~ee~~|20|–20|–|20|ppm|
|Duty cycle<br>~~a~~|37.4 MHz clock<br>|–<br><br>~~ee~~|–<br><br>~~ee~~|–<br>|40<br>|50<br>|60<br>|%<br>|
|Phase Noise[2], [3]<br>(IEEE 802.11 b/g)<br>~~aes~~|37.4 MHz clock at 10 kHz offset<br>~~es~~|–<br>~~es~~<br>~~ee~~|–<br>~~es~~<br>~~ee~~|–<br>~~es~~|–<br>~~es~~|–<br>~~es~~|–129<br>~~es~~|dBc/Hz<br>~~es~~|
||37.4 MHz clock at 100 kHz offset<br>~~es~~<br>~~a~~|–<br>~~es~~<br>~~ee~~<br>~~a~~<br>~~ee~~|–<br>~~es~~<br>~~ee~~<br>~~a~~<br>~~ee~~|–<br>~~es~~<br>~~a~~|–<br>~~es~~<br>~~a~~|–<br>~~es~~<br>~~a~~|–136<br>~~es~~<br>~~a~~|dBc/Hz<br>~~es~~<br>~~a~~|
|Phase Noise[2], [3]<br>(IEEE 802.11n, 2.4 GHz)<br>~~es~~<br>~~ee~~|37.4 MHz clock at 10 kHz offset<br>~~es~~<br>~~a~~<br>~~ee~~|–<br>~~es~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~|–<br>~~es~~<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~ee~~|–<br>~~es~~<br>~~a~~<br>~~ee~~|–<br>~~es~~<br>~~a~~<br>~~ee~~|–<br>~~es~~<br>~~a~~<br>~~ee~~|–134<br>~~es~~<br>~~a~~<br>~~ee~~|dBc/Hz<br>~~es~~<br>~~a~~<br>~~ee~~|
||37.4 MHz clock at 100 kHz offset<br>~~ee~~<br>~~a~~|–<br>~~ee~~<br>~~ee~~<br>~~a~~|–<br>~~ee~~<br>~~ee~~<br>~~a~~|–<br>~~ee~~<br>~~a~~|–<br>~~ee~~<br>~~a~~|–<br>~~ee~~<br>~~a~~|–141<br>~~ee~~<br>~~a~~|dBc/Hz<br>~~ee~~<br>~~a~~|



2. For a clock reference other than 37.4 MHz, 20 × log10(f/37.4) dB should be added to the limits, where f = the reference clock frequency in MHz. 

3. Phase noise is assumed flat above 100 kHz. 

4. The CYW43439 supports a 26 MHz reference clock sharing option. See the phase noise requirement in the table. 

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**CYW43439** 

## **3.3  External 32.768 kHz Low-Power Oscillator** 

The CYW43439 uses a secondary low-frequency sleep clock for low-power mode timing. Either the internal low-precision LPO or an external 32.768 kHz precision oscillator is required. The internal LPO frequency range is approximately 33 kHz ± 30% over process, voltage, and temperature, which is adequate for some applications. However, one trade-off caused by this wide LPO tolerance is a small current consumption increase during power save mode that is incurred by the need to wake up earlier to avoid missing beacons. 

Whenever possible, the preferred approach is to use a precision external 32.768 kHz clock that meets the requirements listed in Table 3. 

**Note:** The CYW43439 will auto-detect the LPO clock. If it senses a clock on the EXT_SLEEP_CLK pin, it will use that clock. If it doesn't sense a clock, it will use its own internal LPO. 

- To use the internal LPO: Tie EXT_SLEEP_CLK to ground. Do not leave this pin floating. 

- To use an external LPO: Connect the external 32.768 kHz clock to EXT_SLEEP_CLK. 

**Table 3. External 32.768 kHz Sleep-Clock Specifications** 

|**Parameter**|**LPO Clock**|**Units**|
|---|---|---|
|Nominal input frequency|32.768|kHz|
|Frequency accuracy|±200|ppm|
|Duty cycle|30–70|%|
|Input signal amplitude|200–3300|mV, p-p|
|Signal type|Square wave or sine wave|–|
|Input impedance[5]|>100|kΩ|
||<5|pF|
|Clock jitter|<10,000|ppm|



## **Note** 

5. When power is applied or switched off. 

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**CYW43439** 

## **4.  WLAN System Interfaces** 

## **4.1  SDIO v2.0** 

The CYW43439 WLAN section supports SDIO version 2.0. for both 1-bit (25 Mbps) and 4-bit modes (100 Mbps), as well as high speed 4-bit mode (50 MHz clocks—200 Mbps). It has the ability to map the interrupt signal on a GPIO pin. This out-of-band interrupt signal notifies the host when the WLAN device wants to turn on the SDIO interface. The ability to force control of the gated clocks from within the WLAN chip is also provided. 

SDIO mode is enabled using the strapping option pins. See Table 17 for details. 

Three functions are supported: 

■ Function 0 standard SDIO function. The maximum block size is 32 bytes. 

■ Function 1 backplane function to access the internal System-on-a-Chip (SoC) address space. The maximum block size is 64 bytes. 

■ Function 2 WLAN function for efficient WLAN packet transfer through DMA. The maximum block size is 512 bytes. 

_4.1.1  SDIO Pin Descriptions_ 

**Table 4. SDIO Pin Descriptions** 

|**SD 4-Bit Mode**|**SD 1-Bit Mode**|**gSPI Mode**|
|---|---|---|
|DATA0<br>Data line 0|DATA<br>Data line|DO<br>Data output|
|DATA1<br>Data line 1 or Interrupt|IRQ<br>Interrupt|IRQ<br>Interrupt|
|DATA2<br>Data line 2|NC<br>Not used|NC<br>Not used|
|DATA3<br>Data line 3|NC<br>Not used|CS<br>Card select|
|CLK<br>Clock|CLK<br>Clock|SCLK<br>Clock|
|CMD<br>Command line|CMD<br>Command line|DI<br>Data input|



**Figure 7. Signal Connections to SDIO Host (SD 4-Bit Mode)** 

**==> picture [216 x 66] intentionally omitted <==**

**----- Start of picture text -----**<br>
CLK<br>CMD<br>SD Host CYW43439<br>DAT[3:0]<br>**----- End of picture text -----**<br>


**Figure 8. Signal Connections to SDIO Host (SD 1-Bit Mode)** 

**==> picture [211 x 97] intentionally omitted <==**

**----- Start of picture text -----**<br>
CLK<br>CMD<br>SD Host CYW43439<br>DATA<br>IRQ<br>**----- End of picture text -----**<br>


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**CYW43439** 

## **4.2  Generic SPI Mode** 

In addition to the full SDIO mode, the CYW43439 includes the option of using the simplified generic SPI (gSPI) interface/protocol. Characteristics of the gSPI mode include: 

- Up to 50 MHz operation 

- Fixed delays for responses and data from the device 

- Alignment to host gSPI frames (16 or 32 bits) 

- Up to 2 KB frame size per transfer 

- Little-endian and big-endian configurations 

- A configurable active edge for shifting 

- Packet transfer through DMA for WLAN 

gSPI mode is enabled using the strapping option pins. See Table 17 for details. 

## **Figure 9. Signal Connections to SDIO Host (gSPI Mode)** 

**==> picture [215 x 91] intentionally omitted <==**

**----- Start of picture text -----**<br>
SCLK<br>DI<br>DO<br>SD Host CYW43439<br>IRQ<br>CS<br>**----- End of picture text -----**<br>


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**CYW43439** 

wewa CYPRESS ~~|~~ **CYW43439** 

## _4.2.1  SPI Protocol_ 

The SPI protocol supports both 16-bit and 32-bit word operation. Byte endianess is supported in both modes. Figure 10 and Figure 11 show the basic write and write/read commands. 

**Figure 10. gSPI Write Protocol** 

**Figure 11. gSPI Read Protocol** 

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**CYW43439** 

## **Command Structure** 

The gSPI command structure is 32 bits. The bit positions and definitions are shown in Figure 12. 

## **Figure 12. gSPI Command Structure** 

**==> picture [382 x 189] intentionally omitted <==**

**----- Start of picture text -----**<br>
CYW_SPID Command Structure<br>31 30 29 28 27 11 10 0<br>C A F1 F0 Address – 17 bits Packet length - 11bits *<br>* 11’h0 = 2048 bytes<br>Fun ction No:  00 – Func 0 : All SPI-specific registers<br>01 – Func 1 : Registers and memories belonging to other blocks in the  chip (64 bytes max)<br>10 – Func 2 : DMA channel 1. WLAN packets up to 2048 bytes.<br>11 – Func 3 : DMA channel 2 (optional). Packets up to 2048 bytes.<br>Access :  0 – Fixed address<br>1 – Incremental address<br>Command :  0 – Read<br>1 – Write<br>**----- End of picture text -----**<br>


## **Write** 

The host puts the first bit of the data onto the bus half a clock-cycle before the first active edge following the CS going low. The following bits are clocked out on the falling edge of the gSPI clock. The device samples the data on the active edge. 

## **Write/Read** 

The host reads on the rising edge of the clock requiring data from the device to be made available before the first rising-clock edge of the data. The last clock edge of the fixed delay word can be used to represent the first bit of the following data word. This allows data to be ready for the first clock edge without relying on asynchronous delays. 

## **Read** 

The read command always follows a separate write to set up the WLAN device for a read. This command differs from the write/read command in the following respects: a) chip selects go high between the command/address and the data, and b) the time interval between the command/address is not fixed. 

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**CYW43439** 

## **Status** 

The gSPI interface supports status notification to the host after a read/write transaction. This status notification provides information about packet errors, protocol errors, available packets in the RX queue, etc. The status information helps reduce the number of interrupts to the host. The status-reporting feature can be switched off using a register bit, without any timing overhead. The gSPI bus timing for read/write transactions with and without status notification are as shown in Figure 13 below and Figure 14. See Table 5 for information on status-field details. 

## **Figure 13. gSPI Signal Timing Without Status** 

**==> picture [391 x 316] intentionally omitted <==**

**----- Start of picture text -----**<br>
Write<br>CS<br>SCLK endert'eebtbeaderrd6| andertrrttLe-4eserttotre |<br>neeWr [pean] Y enWepenaY<br>MOSI C31 C31 C30 C30 C1 C1 C0 C0 D31 D31 D30 D30 D1 D1 D0 D0<br>Command 32 bits Write Data 16*n bits<br>Write-Read CS<br>roa r--4<br>SCLK wendottot --41roto4<br>MOSI ( C31 C31 X C30 C30 XXMoospray C0 C0 >?<br>MISO ( D31 D31 Xx D30 D30 XxXnrpry2xXKX») D1 D1 D0 D0<br>Command Response Read Data 16*n bits<br>32 bits Delay<br>Read CS<br>eqcqt4otob cqgq4ot1 ot<br>SCLK<br>C31 C31 C30 C30 C0 C0<br>MOSI ( X XXeeerry2 >?<br>MISO ( D31 D31 xX D30 D30 xXneerry2xX) D0 D0<br>Command Response Read Data<br>32 bits Delay 16*n bits<br>**----- End of picture text -----**<br>


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**CYW43439** 

**Figure 14. gSPI Signal Timing with Status (Response Delay = 0)** 

**==> picture [388 x 247] intentionally omitted <==**

**----- Start of picture text -----**<br>
W rite C S<br>S C LK 11 1y H H roy~<br>M O S I Cx C 31 C 31 xXKK C 1 C 1 C 0 C 0 D 31 D 31 (xX D 1 D 1 D 0 D 0 »<br>M IS O S 31 S 31 S 1 S 1 S 0 S 0<br>C om m and 32 bits W rite D ata 16 *n bits S tatus 32 bits<br>W rite-R ead C S<br>S C LK _-41 1 -_-44H t 'H 't<br>M O S I C 31 C 31 NUL C 0 C 0<br>M IS O D 31 D 31 D 1 D 1 D 0 D 0 S 31 S 31 S 0 S 0<br>C om m and 32 bits R ead D ata 16*n bits S tatus 32 bits<br>R ead C S<br>S C LK w--41 1 --4rd; t 'H il<br>M O S I C 31 C 31 NLU C 0 C 0<br>M IS O D 31 D 31 fT D 1 D 1 D 0 D 0 S 31 S 31 ins S 0 S 0<br>C om m and 32 bits R ead D ata 16*n bits S tatus 32 bits<br>**----- End of picture text -----**<br>


**Table 5. gSPI Status Field Details** 

|**Bit**|**Name**|**Description**|
|---|---|---|
|0|Data not available|The requested read data is not available.|
|1|Underflow|FIFO underflow occurred due to current (F2, F3) read command.|
|2|Overflow|FIFO overflow occurred due to current (F1, F2, F3) write command.|
|3|F2 interrupt|F2 channel interrupt.|
|5|F2 RX ready|F2 FIFO is ready to receive data (FIFO empty).|
|7|Reserved|–|
|8|F2 packet available|Packet is available/ready in F2 TX FIFO.|
|9:19|F2 packet length|Length of packet available in F2 FIFO|



## _4.2.2  gSPI Host-Device Handshake_ 

To initiate communication through the gSPI after power-up, the host needs to bring up the WLAN chip by writing to the wake-up WLAN register bit. Writing a 1 to this bit will start up the necessary crystals and PLLs so that the CYW43439 is ready for data transfer. The device can signal an interrupt to the host indicating that the device is awake and ready. This procedure also needs to be followed for waking up the device in sleep mode. The device can interrupt the host using the WLAN IRQ line whenever it has any information to pass to the host. On getting an interrupt, the host needs to read the interrupt and/or status register to determine the cause of the interrupt and then take necessary actions. 

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**CYW43439** 

## _4.2.3  Boot-Up Sequence_ 

After power-up, the gSPI host needs to wait 50 ms for the device to be out of reset. For this, the host needs to poll with a read command to F0 address 0x14. Address 0x14 contains a predefined bit pattern. As soon as the host gets a response back with the correct register content, it implies that the device has powered up and is out of reset. After that, the host needs to set the wake-up WLAN bit (F0 reg 0x00 bit 7). Wake-up WLAN turns the PLL on; however, the PLL doesn't lock until the host programs the PLL registers to set the crystal frequency. 

For the first time after power-up, the host needs to wait for the availability of the low-power clock inside the device. Once it is available, the host needs to write to a PMU register to set the crystal frequency. This will turn on the PLL. After the PLL is locked, the chipActive interrupt is issued to the host. This indicates device awake/ready status. See Table 6 for information on gSPI registers. 

In Table 6, the following notation is used for register access: 

## ■ R: Readable from host and CPU 

■ W: Writable from host 

## ■ U: Writable from CPU 

**Table 6. gSPI Registers** 

|**Address**<br>~~ee~~|**Register**<br>~~GG~~<br>~~a~~|**Bit**<br>~~GG~~<br>~~ee~~|**Access**<br>~~GG~~<br>~~ee~~|**Default**<br>~~GG~~<br>~~ee eee~~|**Description**<br>~~GG~~<br>~~eee~~|
|---|---|---|---|---|---|
|x0000<br>~~ee~~<br>~~Pe~~<br>~~SS~~|Word length<br>~~GG~~<br>~~a~~|0<br>~~GG~~<br>~~ee~~|R/W/U<br>~~GG~~<br>~~ee~~|0<br>~~GG~~<br>~~ee eee~~|0: 16-bit word length<br>1: 32-bit word length<br>~~GG~~<br>~~eee~~|
||Endianess<br>~~a~~<br>~~Peott~~|1<br>~~ee~~<br>~~ott~~|R/W/U<br>~~ee ~~<br>~~ott~~|0<br> ~~ee eee~~|0: Little endian<br>1: Big endian<br>~~eee~~|
||High-speed mode<br>~~Peott~~|4<br>~~ott~~|R/W/U<br>~~ott~~|1|0: Normal mode. Sample on SPICLK rising edge, output<br>on falling edge.<br>1: High-speed mode. Sample and output on rising edge<br>of SPICLK (default).|
||Interrupt polarity<br>~~Pe ott~~|5<br>~~ott~~|R/W/U<br>~~ott~~|1|0: Interrupt active polarity is low.<br>1: Interrupt active polarity is high (default).|
||Wake-up<br>~~eT~~<br>~~SS~~|7<br>~~eT~~|R/W<br>~~eT~~|0<br>~~eT~~|A write of 1 denotes a wake-up command from host to<br>device. This will be followed by an F2 interrupt from the<br>gSPI device to host, indicating device awake status.<br>~~eT~~<br>~~ee~~|
|x0002<br>~~SS~~<br>~~**e**~~<br>~~a~~|Status enable<br>~~eT~~<br>~~SS~~<br>~~**e**e~~|0<br>~~eT~~<br>~~ee~~|R/W<br>~~eT~~<br>~~ee~~|1<br>~~eT~~<br>~~ee~~|0: No status sent to host after a read/write.<br>1: Status sent to host after a read/write.<br>~~eT~~<br>~~ee~~<br>~~ee~~|
||Interrupt with status<br>~~SS~~<br>~~**e**e~~<br>~~s~~|1<br>~~ee~~<br>~~eG~~|R/W<br>~~ee~~<br>~~eG GQ~~|0<br>~~ee~~<br>~~GQ~~|0: Do not interrupt if status is sent.<br>1: Interrupt host even if status is sent.<br>~~ee~~<br>~~ee~~<br>~~GQ~~|
|x0003<br>~~SS~~<br>~~**e**~~<br>~~a~~|Reserved<br>~~SS~~<br>~~**e**e ~~<br>~~s~~|–<br> ~~ee~~<br>~~eG~~|–<br>~~ee ~~<br>~~eG GQ~~|–<br> ~~ee~~<br>~~GQ~~|–<br>~~ee~~<br>~~ee~~<br>~~GQ~~|
|x0004<br>~~=~~<br>~~Bf~~|Interrupt register<br>~~s ~~<br>~~=~~<br>~~Bf~~|0<br> ~~eG~~<br>~~=~~<br>~~a~~|R/W<br>~~eG GQ~~<br>~~=~~<br>~~es~~|0<br>~~GQ~~<br>~~=~~|Requested data not available. Cleared by writing a 1 to<br>this location.<br>~~GQ~~<br>~~=~~|
|||1<br>~~=~~<br>~~a~~|R<br>~~=~~<br>~~es~~|0<br>~~=~~|F2/F3 FIFO underflow from the last read.<br>~~=~~|
|||2<br>~~=~~<br>~~a~~<br>~~aa~~<br><br>~~a~~|R<br>~~=~~<br>~~es~~<br>~~aa~~<br>~~es~~<br>|0<br>~~=~~<br>~~aa~~|F2/F3 FIFO overflow from the last write.<br>~~=~~|
|||5<br>~~=~~<br>~~aa~~<br>~~a~~<br>~~a~~|R<br>~~=~~<br>~~aa~~<br>~~aes~~<br>|0<br>~~=~~<br>~~aa~~|F2 packet available<br>~~=~~|
|||6<br>~~=~~<br><br>~~a~~<br>~~a~~|R<br>~~=~~<br>~~es~~<br>~~a~~<br>~~es~~|0<br>~~=~~|F3 packet available<br>~~=~~|
|||7<br>~~=~~<br><br>~~a ~~<br>~~a~~|R<br>~~=~~<br>~~es~~<br> ~~a~~<br>~~es~~|0<br>~~=~~|F1 overflow from the last write.<br>~~=~~|
|x0005<br>~~Bf~~<br>~~a~~<br>~~ee~~|Interrupt register<br>~~Bf~~<br>~~ee~~<br>|5<br>~~a~~<br>~~a~~|R<br>~~es~~<br>~~es~~|0|F1 Interrupt|
|||6<br>~~a~~<br>~~a~~<br>~~a~~|R<br>~~es~~<br>~~es~~<br>~~ee~~|0|F2 Interrupt|
|||7<br>~~a~~<br>~~a~~<br>~~a~~<br>~~ee~~<br>|R<br>~~es~~<br>~~es~~<br>~~ee~~<br>~~ee~~<br>|0|F3 Interrupt<br>~~ee~~|
|x0006, x0007<br>~~Bf~~<br>~~a~~<br>~~ee~~|Interrupt enable<br>register<br>~~Bf~~<br>~~ee~~<br>~~ee~~|15:0<br>~~a~~<br>~~a~~<br>~~ee~~<br>~~eG~~|R/W/U<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~eG~~|16'hE0E7<br>~~GR (~~|Particular interrupt is enabled if a corresponding bit is<br>set.<br>~~ee~~<br>~~(~~|
|x0008 to x000B <br>~~ee~~|Status register<br>~~ee~~<br>~~ee~~|31:0<br>~~ee~~<br>~~eG~~|R<br>~~ee~~<br>~~eG~~|32'h0000<br>~~GR (~~|Same as status bit definitions<br>~~ee~~<br>~~(~~|



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**CYW43439** 

**Table 6. gSPI Registers (Cont.)** 

|**Address**<br>~~a~~|**Register**<br>~~eG~~|**Bit**<br>~~eG~~|**Access**<br>~~Ge~~|**Default**<br>~~Ge~~|**Description**<br>~~Ge~~|
|---|---|---|---|---|---|
|x000C, x000D|F1 info. register|0<br>~~a~~|R|1|F1 enabled|
|||1<br>~~a~~|R|0|F1 ready for data transfer|
|||13:2<br>~~a~~|R/U|12'h40|F1 maximum packet size|
|x000E, x000F|F2 info. register|0<br>~~a~~<br>~~a~~|R/U|1|F2 enabled|
|||1<br>~~a~~|R|0|F2 ready for data transfer|
|||15:2<br>~~a~~|R/U|14'h800|F2 maximum packet size|
|x0014 to x0017 <br>~~a~~|Test-Read only<br>register|31:0|R|32'hFEEDB<br>EAD|This register contains a predefined pattern, which the<br>host can read to determine if the gSPI interface is<br>working properly.|
|x0018 to x001B <br>~~a~~|Test–R/W register|31:0|R/W/U|32'h000000<br>00|This is a dummy register where the host can write some<br>pattern and read it back to determine if the gSPI interface<br>is working properly.|
|x001C to x001F|Response delay<br>registers|7:0|R/W|0x1D = 4,<br>other<br>registers = 0|Individual response delays for F0, F1, F2, and F3. The<br>value of the registers is the number of byte delays that<br>are introduced before data is shifted out of the gSPI<br>interface during host reads.|



Figure 15 shows the WLAN boot-up sequence from power-up to firmware download, including the initial device power-on reset (POR) evoked by the WL_REG_ON signal. After initial power-up, the WL_REG_ON signal can be held low to disable the CYW43439 or pulsed low to induce a subsequent reset. 

**Note:** The CYW43439 has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 3 ms after VDDC and VDDIO have both passed the 0.6V threshold. 

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**CYW43439** 

**==> picture [452 x 445] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 15. WLAN Boot-Up Sequence<br>VBAT Ramp time from 0V to 4.3V > 40 µs<br>0<br> LE 0.6V<br>VDDIO S oe > 2 Sleep Clock cycles<br>WL_REG_ON a<br>< 1.5 ms<br>VDDC<br>(from internal PMU) ee <—_ < 3 ms  _><br>Internal POR<br>After a fixed delay following internal POR going high,<br>< 50 ms<br>the device responds to host F0 (address 0x14) reads.<br>Device requests a reference clock. fn<br>15  [1] ms<br>After 15 ms [1] the reference clock<br>is assumed to be up.  Access to<br>PLL registers is possible.<br>SPI Host Interaction:<br>Host polls F0 (address 0x14) until it reads<br>a predefined pattern.<br>Host sets wake‐up‐wlan bit<br>and waits 15 ms [1] , the<br>maximum time for  After 15  [1] ms, the host<br>reference clock availability. programs the PLL registers to<br>set the crystal frequency.<br>WL_IRQ Chip‐active interrupt is asserted after the PLL locks.<br>Host downloads<br>code.<br>1<br>This wait time is programmable in sleep‐clock increments from 1 to 255 (30 us to 15 ms).<br>**----- End of picture text -----**<br>


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**CYW43439** 

## **5.  WLAN Radio Subsystem** 

The CYW43439 includes an integrated WLAN RF transceiver that has been optimized for use in 2.4 GHz Wireless LAN systems. It is designed to provide low power, low cost, and robust communications for applications operating in the globally available 2.4 GHz unlicensed ISM band. The transmit and receive sections include all on-chip filtering, mixing, and gain control functions. Improvements to the radio design include shared TX/RX baseband filters and high immunity to supply noise. 

Figure 16 shows the radio functional block diagram. 

**Figure 16. Radio Functional Block Diagram** 

**==> picture [445 x 415] intentionally omitted <==**

**----- Start of picture text -----**<br>
WL DAC<br>é<br>WL TXLPF<br>WL PA WL PGA WL DAC<br>HAL : -<br>WL TX G‐Mixer WL TXLPF<br>WLAN BB Voltage<br>Regulators<br>WLRF_2G_RF<br>4 ~ 6 nH<br>Recommend<br>Q = 40<br>WL ADC<br>10 pF<br>WL RXLPF<br>WLRF_2G_eLG<br>SLNA WL G‐LNA12 WL ADC<br>hy a }-—C<br>WL RX G‐Mixer WL RXLPF<br>Gm WL ATX CLB<br>BT LNA GM WL GTXWL ARX WL LOGEN WL PLL<br>WL GRX<br>Shared XO<br>BT TXBT RX BT LOGEN BT PLL A<br>2 LPO/Ext LPO/RCAL |<br>BT ADC<br>é<br>BT RXLPF<br>BT LNA Load BT ADC<br>g<br>a r t<br>BT RX Mixer BT RXLPF BT BB BT<br>BT PA<br>|<br>BT DAC<br>a |<br>BT DAC<br>{ : -<br>BT TX Mixer BT TXLPF<br>**----- End of picture text -----**<br>


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**CYW43439** 

## **5.1  Receive Path** 

The CYW43439 has a wide dynamic range, direct conversion receiver. It employs high-order on-chip channel filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. 

## **5.2  Transmit Path** 

Baseband data is modulated and upconverted to the 2.4 GHz ISM band. A linear on-chip power amplifier is included, which is capable of delivering high output powers while meeting IEEE 802.11b/g/n specifications without the need for an external PA. This PA is supplied by an internal LDO that is directly supplied by VBAT, thereby eliminating the need for a separate PALDO. Closed-loop output power control is integrated. 

## **5.3  Calibration** 

The CYW43439 features dynamic on-chip calibration, eliminating process variation across components. This enables the CYW43439 to be used in high-volume applications because calibration routines are not required during manufacturing testing. These calibration routines are performed periodically during normal radio operation. Automatic calibration examples include baseband filter calibration for optimum transmit and receive performance and LOFT calibration for leakage reduction. In addition, I/Q calibration, R calibration, and VCO calibration are performed on-chip. 

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**CYW43439** 

## **6.  Bluetooth Overview** 

The CYW43439 is a Bluetooth 5.2 compliance, baseband processor and 2.4 GHz transceiver. It features the highest level of integration and eliminates all critical external components, thus minimizing the footprint, power consumption, and system cost of a Bluetooth plus WLAN solution. 

The CYW43439 is the optimal solution for any Bluetooth voice and/or data application that also requires WLAN. The Bluetooth subsystem presents a standard Host Controller Interface (HCI) via a high speed UART and PCM interface for audio. The CYW43439 incorporates all Bluetooth 5.2 compliance features including secure simple pairing, sniff subrating, and encryption pause and resume. CYW43439 also supports Bluetooth 5.2 compliance LE Secure Connections. 

The CYW43439 Bluetooth radio transceiver provides enhanced radio performance to meet the most stringent mobile phone temperature applications and the tightest integration into mobile handsets and portable devices. It is fully compatible with any of the standard TCXO frequencies and provides full radio compatibility to operate simultaneously with GPS, WLAN, NFC, and cellular radios. The Bluetooth transmitter also features a Class 1 power amplifier with Class 2 capability. 

## **6.1  Features** 

## **Major Bluetooth features of the CYW43439 include:** 

- Supports key features of upcoming Bluetooth standards 

- Fully supports Bluetooth Core Specification 5.2 plus enhanced data rate (EDR) features: 

- ❐ Adaptive Frequency Hopping (AFH) 

- ❐ Quality of Service (QoS) 

- ❐ Extended Synchronous Connections (eSCO)—voice connections 

- ❐ Fast connect (interlaced page and inquiry scans) 

- ❐ Secure Simple Pairing (SSP) 

- ❐ Sniff Subrating (SSR) 

- ❐ Encryption Pause Resume (EPR) ❐ Extended Inquiry Response (EIR) ❐ Link Supervision Timeout (LST) 

- UART baud rates up to 4 Mbps 

- Supports Bluetooth 5.2 compliance LE Secure Connections optional feature 

- Multipoint operation with up to seven active slaves 

- ❐ Maximum of seven simultaneous active ACL links 

- ❐ Maximum of three simultaneous active SCO and eSCO connections with scatternet support 

- Trigger Beacon fast connect (TBFC) 

- Narrowband and wideband packet loss concealment 

- Scatternet operation with up to four active piconets with background scan and support for scatter mode 

- High-speed HCI UART transport support with low-power out-of-band BT_DEV_WAKE and BT_HOST_WAKE signaling (see “Host Controller Power Management” ) 

- Channel-quality driven data rate and packet type selection 

- Standard Bluetooth test modes 

- Extended radio and production test mode features 

- Full support for power savings modes 

- ❐ Bluetooth clock request 

- ❐ Bluetooth standard sniff ❐ Deep-sleep modes and software regulator shutdown 

■ TCXO input and auto-detection of all standard handset clock frequencies. Also supports a low-power crystal, which can be used during power save mode for better timing accuracy. 

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**CYW43439** 

## **6.2  Bluetooth Radio** 

The CYW43439 has an integrated radio transceiver that has been optimized for use in 2.4 GHz Bluetooth wireless systems. It has been designed to provide low-power, low-cost, robust communications for applications operating in the globally available 2.4 GHz unlicensed ISM band. It is fully compliant with the Bluetooth Radio Specification and EDR specification and meets or exceeds the requirements to provide the highest communication link quality of service. 

## _6.2.1  Transmit_ 

The CYW43439 features a fully integrated zero-IF transmitter. The baseband transmit data is GFSK-modulated in the modem block and upconverted to the 2.4 GHz ISM band in the transmitter path. The transmitter path has signal filters, an I/Q upconverter, an output power amplifier, and RF filters. The transmitter path also incorporates /4–DQPSK for 2 Mbps and 8–DPSK for 3 Mbps to support EDR. The transmitter section is compatible with the Bluetooth Low Energy specification. The transmitter PA bias can also be adjusted to provide Bluetooth Class 1 or Class 2 operation. 

## _6.2.2  Digital Modulator_ 

The digital modulator performs the data modulation and filtering required for the GFSK, /4–DQPSK, and 8–DPSK signal. The fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted signal and is much more stable than direct VCO modulation schemes. 

## _6.2.3  Digital Demodulator and Bit Synchronizer_ 

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bitsynchronization algorithm. 

## _6.2.4  Power Amplifier_ 

The fully integrated PA supports Class 1 or Class 2 output using a highly linearized, temperature-compensated design. This provides greater flexibility in front-end matching and filtering. Due to the linear nature of the PA combined with some integrated filtering, external filtering is required to meet the Bluetooth and regulatory harmonic and spurious requirements. For integrated mobile handset applications in which Bluetooth is integrated next to the cellular radio, external filtering can be applied to achieve near-thermal noise levels for spurious and radiated noise emissions. The transmitter features a sophisticated on-chip transmit signal strength indicator (TSSI) block to keep the absolute output power variation within a tight range across process, voltage, and temperature. 

## _6.2.5  Receiver_ 

The receiver path uses a low-IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit synchronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high-order on-chip channel filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology with built-in out-of-band attenuation enables the CYW43439 to be used in most applications with minimal off-chip filtering. For integrated handset operation, in which the Bluetooth function is integrated close to the cellular transmitter, external filtering is required to eliminate the desensitization of the receiver by the cellular transmit signal. 

## _6.2.6  Digital Demodulator and Bit Synchronizer_ 

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit synchronization algorithm. 

## _6.2.7  Receiver Signal Strength Indicator_ 

The radio portion of the CYW43439 provides a Receiver Signal Strength Indicator (RSSI) signal to the baseband so that the controller can take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the transmitter should increase or decrease its output power. 

## _6.2.8  Local Oscillator Generation_ 

Local Oscillator (LO) generation provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. The LO generation subblock employs an architecture for high immunity to LO pulling during PA operation. The CYW43439 uses an internal RF and IF loop filter. 

## _6.2.9  Calibration_ 

The CYW43439 radio transceiver features an automated calibration scheme that is self contained in the radio. No user interaction is required during normal operation or during manufacturing to optimize performance. Calibration optimizes the performance of all the major blocks within the radio to within 2% of optimal conditions, including filter gain and phase characteristics, matching between key components, and key gain blocks. This takes into account process variation and temperature variation. Calibration occurs transparently during normal operation during the settling time of the hops and calibrates for temperature variations as the device cools and heats during normal operation in its environment. 

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**CYW43439** 

## **7.  Bluetooth Baseband Core** 

The Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high-performance Bluetooth operation. The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it, handles data flow control, schedules SCO/ACL TX/RX transactions, monitors Bluetooth slot usage, optimally segments and packages data into baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these functions, it independently handles HCI event types and HCI command types. 

The following transmit and receive functions are also implemented in the BBC hardware to increase the reliability and security of data before sending and receiving it over the air: 

- Symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC), data decryption, and data dewhitening in the receiver. 

- Data framing, FEC generation, HEC generation, CRC generation, key generation, data encryption, and data whitening in the transmitter. 

## **7.1  Bluetooth Standard Features** 

The BBC supports all Bluetooth standard features, with the following benefits: 

- Dual-mode classic Bluetooth and classic Low Energy (BT and BLE) operation. 

- Low energy physical layer 

- Low energy link layer 

- Enhancements to HCI for low energy 

- Low energy direct test mode 

- 128 AES-CCM secure connection for both BT and BLE 

**Note:** The CYW43439 is compatible with the Bluetooth Low Energy operating mode, which provides a dramatic reduction in the power consumption of the Bluetooth radio and baseband. The primary application for this mode is to provide support for low data rate devices, such as sensors and remote controls. 

## **7.2  Bluetooth 5.2 Features** 

CYW43439supports Bluetooth 5.2’s new LE Secure Connections feature to enable secure connection establishment using the EllipticCurve Diffie-Hellman algorithm. 

## **7.3  Link Control Layer** 

The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the link control unit (LCU). This layer contains the command controller that takes commands from the software, and other controllers that are activated or configured by the command controller, to perform the link control tasks. Each task performs a different state in the Bluetooth link controller. 

- Major states: 

- ❐ Standby 

- ❐ Connection 

## ■ Substates: 

- ❐ Page 

- ❐ Page Scan 

- ❐ Inquiry 

- ❐ Inquiry Scan 

- ❐ Sniff 

- ❐ BLE Adv 

- ❐ BLE Scan/Initiation 

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**CYW43439** 

## **7.4  Test Mode Support** 

The CYW43439 fully supports Bluetooth Test mode as described in Core System Package [Host volume] Part D Test Support of the Bluetooth Core Specification. This includes the transmitter tests, normal and delayed loopback tests, and reduced hopping sequence. 

In addition to the standard Bluetooth Test Mode, the CYW43439 also supports enhanced testing features to simplify RF debugging and qualification as well as type-approval testing. These features include: 

- Fixed frequency carrier-wave (unmodulated) transmission 

- ❐ Simplifies some type-approval measurements (Japan) 

- ❐ Aids in transmitter performance analysis 

- Fixed frequency constant receiver mode 

- ❐ Receiver output directed to an I/O pin 

- ❐ Allows for direct BER measurements using standard RF test equipment 

- ❐ Facilitates spurious emissions testing for receive mode 

- Fixed frequency constant transmission 

- ❐ Eight-bit fixed pattern or PRBS-9 

- ❐ Enables modulated signal measurements with standard RF test equipment 

## **7.5  Bluetooth Power Management Unit** 

The Bluetooth Power Management Unit (PMU) provides power management features that can be invoked by either software through power management registers or packet handling in the baseband core. The power management functions provided by the CYW43439 are: 

- RF Power Management 

- Host Controller Power Management 

- BBC Power Management 

- FM Power Management 

## _7.5.1  RF Power Management_ 

The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4 GHz transceiver. The transceiver then processes the power-down functions accordingly. 

## _7.5.2  Host Controller Power Management_ 

When running in UART mode, the CYW43439 can be configured so that dedicated signals are used for power management handshaking between the CYW43439 and the host. The basic power saving functions supported by those handshaking signals include the standard Bluetooth defined power savings modes and standby modes of operation. 

Table 7 describes the power-control handshake signals used with the UART interface. 

**Table 7. Power Control Pin Description** 

|**Signal**|**Type**|**Description**|
|---|---|---|
|BT_DEV_WAKE|I|Bluetooth device wake-up signal: Signal from the host to the CYW43439 indicating that the host<br>requires attention.<br>■Asserted: The Bluetooth device must wake up or remain awake.<br>■Deasserted: The Bluetooth device may sleep when sleep criteria are met.<br>The polarity of this signal is software configurable and can be asserted high or low.|
|BT_HOST_WAKE|O|Host wake-up signal. Signal from the CYW43439 to the host indicating that the CYW43439<br>requires attention.<br>■Asserted: Host device must wake up or remain awake.<br>■Deasserted: Host device may sleep when sleep criteria are met.<br>The polarity of this signal is software configurable and can be asserted high or low.|
|CLK_REQ|O|The CYW43439 asserts CLK_REQ when Bluetooth or WLAN directs the host to turn on the<br>reference clock. The CLK_REQ polarity is active-high. Add an external 100 kΩ pull-down resistor<br>to ensure the signal is deasserted when the CYW43439 powers up or resets when VDDIO is<br>present.|
|**Note:**Pad function Control Register is set to 0 for these pins.|||



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**CYW43439** 

## **Figure 17. Startup Signaling Sequence** 

LPO Host IOs unconfigured VDDIO Host IOs configured T1 HostResetX ~~a~~ BT_GPIO_0 (BT_DEV_WAKE) T2 BTH IOs unconfigured BTH IOs configured BT_REG_ON BT_GPIO_1 (BT_HOST_WAKE) T3 Host side drives BT_UART_CTS_N ~~a~~ this line low BTH device drives this BT_UART_RTS_N T4 line low indicating transport is ready CLK_REQ_OUT T5 Driven Pulled Notes : T1 is the time for host to settle it’s IOs after a reset. T2 is the time for host to drive BT_REG_ON high after the Host IOs are configured. T3 is the time for BTH (Bluetooth) device to settle its IOs after a reset and reference clock settling time has elapsed. T4 is the time for BTH device to drive BT_UART_RTS_N low after the host drives  BT_UART_CTS_N low. This assumes the BTH device has already completed initialization. T5 is the time for BTH device to drive CLK_REQ_OUT high after BT_REG_ON goes high. Note this pin is used for designs that use an external reference clock source from the Host. This pin is irrelevant for Crystal reference clock based designs where the BTH device generates it’s own reference clock from an external crystal connected to it’s oscillator circuit. Timing diagram assumes VBAT is present. 

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**CYW43439** 

## _7.5.3  BBC Power Management_ 

The following are low-power operations for the BBC: 

- Physical layer packet-handling turns the RF on and off dynamically within transmit/receive packets. 

- Bluetooth-specified low-power connection modes: sniff and hold. While in these modes, the CYW43439 runs on the low-power oscillator and wakes up after a predefined time period. 

- A low-power shutdown feature allows the device to be turned off while the host and any other devices in the system remain operational. When the CYW43439 is not needed in the system, the RF and core supplies are shut down while the I/O remains powered. This allows the CYW43439 to effectively be off while keeping the I/O pins powered, so they do not draw extra current from any other I/ O-connected devices. 

During the low-power shut-down state, provided VDDIO remains applied to the CYW43439, all outputs are tristated, and most input signals are disabled. Input voltages must remain within the limits defined for normal operation. This is done to prevent current paths or create loading on digital signals in the system and enables the CYW43439 to be fully integrated in an embedded device to take full advantage of the lowest power-saving modes. 

Two CYW43439 input signals are designed to be high-impedance inputs that do not load the driving signal even if the chip does not have VDDIO power supplied to it: the frequency reference input (WRF_TCXO_IN) and the 32.768 kHz input (LPO). When the CYW43439 is powered on from this state, it is the same as a normal power-up, and the device does not contain any information about its state from the time before it was powered down. 

## _7.5.4  FM Power Management_ 

The CYW43439 FM subsystem can operate independently of, or in tandem with, the Bluetooth RF and BBC subsystems. The FM subsystem power management scheme operates in conjunction with the Bluetooth RF and BBC subsystems. The FM block does not have a low power state, it is either ON or OFF. 

**Note:** Cypress does not support FM. This section and other sections that refer to FM operation and pinout are retained in this document to provide customers data about the use of Bluetooth while keeping FM powered down. 

## _7.5.5  Wideband Speech_ 

The CYW43439 provides support for wideband speech (WBS) technology. The CYW43439 can perform subband-codec (SBC), as well as mSBC, encoding and decoding of linear 16 bits at 16 kHz (256 kbps rate) transferred over the PCM bus. 

## _7.5.6  Packet Loss Concealment_ 

Packet Loss Concealment (PLC) improves the apparent audio quality for systems with marginal link performance. Bluetooth messages are sent in packets. When a packet is lost, it creates a gap in the received audio bit-stream. Packet loss can be mitigated in several ways: 

- Fill in zeros. 

- Ramp down the output audio signal toward zero (this is the method used in current Bluetooth headsets). 

- Repeat the last frame (or packet) of the received bit-stream and decode it as usual (frame repeat). 

These techniques cause distortion and popping in the audio stream. The CYW43439 uses a proprietary waveform extension algorithm to provide dramatic improvement in the audio quality. Figure 18 and Figure 19 show audio waveforms with and without Packet Loss Concealment. Cypress PLC/BEC algorithms also support wideband speech. 

## **Figure 18. CVSD Decoder Output Waveform Without PLC** 

**==> picture [135 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
Packet losses causes ramp-down<br>**----- End of picture text -----**<br>


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**CYW43439** 

## **Figure 19. CVSD Decoder Output Waveform After Applying PLC** 

## _7.5.7  Codec Encoding_ 

The CYW43439 can support SBC and mSBC encoding and decoding for wideband speech. 

## _7.5.8  Multiple Simultaneous A2DP Audio Streams_ 

The CYW43439 has the ability to take a single audio stream and output it to multiple Bluetooth devices simultaneously. This allows a user to share his or her music (or any audio stream) with a friend. 

## **7.6  Adaptive Frequency Hopping** 

The CYW43439 gathers link quality statistics on a channel by channel basis to facilitate channel assessment and channel map selection. The link quality is determined using both RF and baseband signal processing to provide a more accurate frequency-hop map. 

## **7.7  Advanced Bluetooth/WLAN Coexistence** 

The CYW43439 includes advanced coexistence technologies that are only possible with a Bluetooth/WLAN integrated die solution. These coexistence technologies are targeted at small form-factor platforms, such as cell phones and media players, including applications such as VoWLAN + SCO and Video-over-WLAN + High Fidelity BT Stereo. 

Support is provided for platforms that share a single antenna between Bluetooth and WLAN. Dual-antenna applications are also supported. The CYW43439 radio architecture allows for lossless simultaneous Bluetooth and WLAN reception for shared antenna applications. This is possible only via an integrated solution (shared LNA and joint AGC algorithm). It has superior performance versus implementations that need to arbitrate between Bluetooth and WLAN reception. 

The CYW43439 integrated solution enables MAC-layer signaling (firmware) and a greater degree of sharing via an enhanced coexistence interface. Information is exchanged between the Bluetooth and WLAN cores without host processor involvement. 

The CYW43439 also supports Transmit Power Control (TPC) on the STA together with standard Bluetooth TPC to limit mutual interference and receiver desensitization. Preemption mechanisms are utilized to prevent AP transmissions from colliding with Bluetooth frames. Improved channel classification techniques have been implemented in Bluetooth for faster and more accurate detection and elimination of interferers (including non-WLAN 2.4 GHz interference). 

The Bluetooth AFH classification is also enhanced by the WLAN core’s channel information. 

## **7.8  Fast Connection (Interlaced Page and Inquiry Scans)** 

The CYW43439 supports page scan and inquiry scan modes that significantly reduce the average inquiry response and connection times. These scanning modes are compatible with the Bluetooth version 2.1 page and inquiry procedures. 

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**CYW43439** 

## **8.  Microprocessor and Memory Unit for Bluetooth** 

The Bluetooth microprocessor core is based on the ARM Cortex-M3 32-bit RISC processor with embedded ICE-RT debug and JTAG interface units. It runs software from the link control (LC) layer up to the host controller interface (HCI). 

The ARM core is paired with a memory unit that contains 576 KB of ROM for program storage and boot ROM, and 160 KB of RAM for data scratch-pad and patch RAM code. The internal ROM allows for flexibility during power-on reset (POR) to enable the same device to be used in various configurations. At power-up, the lower-layer protocol stack is executed from the internal ROM memory. 

External patches may be applied to the ROM-based firmware to provide flexibility for bug fixes or feature additions. These patches may be downloaded from the host to the CYW43439 through the UART transports. 

## **8.1  RAM, ROM, and Patch Memory** 

The CYW43439 Bluetooth core has 160 KB of internal RAM which is mapped between general purpose scratch-pad memory and patch memory, and 576 KB of ROM used for the lower-layer protocol stack, test mode software, and boot ROM. The patch memory is used for bug fixes and feature additions to ROM memory code. 

## **8.2  Reset** 

The CYW43439 has an integrated power-on reset circuit that resets all circuits to a known power-on state. The BT POR circuit is out of reset after BT_REG_ON goes high. If BT_REG_ON is low, then the POR circuit is held in reset. 

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**CYW43439** 

## **9.  Bluetooth Peripheral Transport Unit** 

## **9.1  PCM Interface** 

The CYW43439 supports two independent PCM interfaces. The PCM interface on the CYW43439 can connect to linear PCM codec devices in master or slave mode. In master mode, the CYW43439 generates the PCM_CLK and PCM_SYNC signals, and in slave mode, these signals are provided by another master on the PCM interface and are inputs to the CYW43439. The configuration of the PCM interface may be adjusted by the host through the use of vendor-specific HCI commands. 

## _9.1.1  Slot Mapping_ 

The CYW43439 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM interface. These three channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate of 128 kHz, 512 kHz, or 1024 kHz. The corresponding number of slots for these interface rates is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to allow other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCM clock during the last bit of the slot. 

## _9.1.2  Frame Synchronization_ 

The CYW43439 supports both short- and long-frame synchronization in both master and slave modes. In short-frame synchronization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge of the bit clock and expects the first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident with the first bit of the first slot. 

## _9.1.3  Data Formatting_ 

The CYW43439 may be configured to generate and accept several different data formats. For conventional narrowband speech mode, the CYW43439 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0’s, 1’s, a sign bit, or a programmed value on the output. The default format is 13-bit 2’s complement data, left justified, and clocked MSB first. 

## _9.1.4  Wideband Speech Support_ 

When the host encodes Wideband Speech (WBS) packets in transparent mode, the encoded packets are transferred over the PCM bus for an eSCO voice connection. In this mode, the PCM bus is typically configured in master mode for a 4 kHz sync rate with 16bit samples, resulting in a 64 kbps bit rate. The CYW43439 also supports slave transparent mode using a proprietary rate-matching scheme. In SBC-code mode, linear 16-bit data at 16 kHz (256 kbps rate) is transferred over the PCM bus. 

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wa CYPRESS ~~nee eee~~ **CYW43439** 

## _9.1.5  PCM Interface Timing_ 

## **Short Frame Sync, Master Mode** 

**Figure 20. PCM Timing Diagram (Short Frame Sync, Master Mode)** 

**==> picture [402 x 149] intentionally omitted <==**

**----- Start of picture text -----**<br>
1<br>2 3<br>PCM_BCLK<br>4<br>PCM_SYNC<br>8<br>PCM_OUT High Impedance<br>5<br>6 7<br>PCM_IN<br>**----- End of picture text -----**<br>


**Table 8. PCM Interface Timing Specifications (Short Frame Sync, Master Mode)** 

|**Ref No.**<br>~~a~~<br>~~es~~|**Characteristics**|**Minimum**|**Typical**|**Maximum**|**Unit**|
|---|---|---|---|---|---|
|1<br>~~a~~<br>~~es~~|PCM bit clock frequency|–|–|12|MHz|
|2<br>~~es~~<br>~~a~~|PCM bit clock low|41|–|–|ns|
|3<br>~~a~~<br>~~a~~|PCM bit clock high|41|–|–|ns|
|4<br>~~a~~|PCM_SYNC delay|0|–|25|ns|
|5<br>~~a~~<br>~~a~~|PCM_OUT delay|0|–|25|ns|
|6<br>~~a~~|PCM_IN setup|8|–|–|ns|
|7<br>~~a~~<br>~~a~~|PCM_IN hold|8|–|–|ns|
|8|Delay from rising edge of PCM_BCLK during last bit period to<br>PCM_OUT becoming high impedance|0|–|25|ns|



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**CYW43439** 

## **Short Frame Sync, Slave Mode** 

**Figure 21. PCM Timing Diagram (Short Frame Sync, Slave Mode)** 

**==> picture [398 x 157] intentionally omitted <==**

**----- Start of picture text -----**<br>
1<br>2 3<br>PCM_BCLK<br>4<br>5<br>PCM_SYNC<br>9<br>PCM_OUT High Impedance<br>6<br>7 8<br>PCM_IN<br>**----- End of picture text -----**<br>


**Table 9. PCM Interface Timing Specifications (Short Frame Sync, Slave Mode)** 

|**Ref No.**<br>~~a~~|**Characteristics**|**Minimum**|**Typical**|**Maximum**|**Unit**|
|---|---|---|---|---|---|
|1<br>~~a~~|PCM bit clock frequency<br>~~GO~~|–<br>~~GO~~|–<br>~~GO~~|12<br>~~GO~~|MHz<br>~~GO~~|
|2<br>~~a~~<br>~~a~~|PCM bit clock low<br>~~GO~~|41<br>~~GO~~|–<br>~~GO~~|–<br>~~GO~~|ns<br>~~GO~~|
|3<br>~~a~~|PCM bit clock high<br>~~GO~~|41<br>~~GO~~|–<br>~~GO~~|–<br>~~GO~~|ns<br>~~GO~~|
|4<br>~~a~~<br>~~a~~|PCM_SYNC setup<br>~~GO~~|8<br>~~GO~~|–<br>~~GO~~|–<br>~~GO~~|ns<br>~~GO~~|
|5<br>~~a~~|PCM_SYNC hold<br>~~GO~~|8<br>~~GO~~|–<br>~~GO~~|–<br>~~GO~~|ns<br>~~GO~~|
|6<br>~~a~~<br>~~a~~|PCM_OUT delay<br>~~GO~~|0<br>~~GO~~|–<br>~~GO~~|25<br>~~GO~~|ns<br>~~GO~~|
|7<br>~~a~~|PCM_IN setup<br>~~GO~~|8<br>~~GO~~|–<br>~~GO~~|–<br>~~GO~~|ns<br>~~GO~~|
|8<br>~~a~~<br>~~a~~|PCM_IN hold<br>~~GO~~|8<br>~~GO~~|–<br>~~GO~~|–<br>~~GO~~|ns<br>~~GO~~|
|9|Delay from rising edge of PCM_BCLK during last bit period to<br>PCM_OUT becoming high impedance|0|–|25|ns|



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wa CYPRESS ~~I~~ **CYW43439** 

## **Long Frame Sync, Master Mode** 

**Figure 22. PCM Timing Diagram (Long Frame Sync, Master Mode)** 

**==> picture [415 x 129] intentionally omitted <==**

**----- Start of picture text -----**<br>
1<br>2 3<br>PCM_BCLK<br>S<br>4<br>PCM_SYNC<br>8<br>PCM_OUT Bit 0 Bit 1 High Impedance<br>5<br>6 7<br>PCM_IN Bit 0 Bit 1<br>**----- End of picture text -----**<br>


**Table 10. PCM Interface Timing Specifications (Long Frame Sync, Master Mode)** 

|**Ref No.**<br>~~a~~|**Characteristics**|**Minimum**|**Typical**|**Maximum**|**Unit**|
|---|---|---|---|---|---|
|1<br>~~—~~|PCM bit clock frequency<br>~~a~~|–|–|12|MHz|
|2<br>~~—~~<br>|PCM bit clock low<br>~~a~~<br> ~~eG~~|41<br>~~eG~~|–|–|ns|
|3<br>~~| ~~<br>|PCM bit clock high<br> <br>~~a~~|41<br>|–|–|ns|
|4<br>~~| ~~<br>~~| ~~<br>|PCM_SYNC delay<br> <br> ~~a~~<br> ~~eG~~|0<br><br>~~eG~~|–|25|ns|
|5<br>~~| ~~<br><br>~~—————~~|PCM_OUT delay<br> <br>~~a~~<br>~~—————~~|0<br><br>~~—————~~|–<br>~~—————~~|25<br>~~—————~~|ns<br>~~—————~~|
|6<br>~~| ~~<br>~~| ~~<br>~~—————~~|PCM_IN setup<br> <br> ~~a~~<br>~~—————~~|8<br><br>~~—————~~|–<br>~~—————~~|–<br>~~—————~~|ns<br>~~—————~~|
|7<br>~~—————~~|PCM_IN hold<br>~~—————~~|8<br>~~—————~~|–<br>~~—————~~|–<br>~~—————~~|ns<br>~~—————~~|
|8<br>~~—————~~<br>~~ee~~|Delay from rising edge of PCM_BCLK during last bit period to<br>PCM_OUT becoming high impedance<br>~~—————~~<br>~~ee~~|0<br>~~—————~~<br>~~ee~~|–<br>~~—————~~<br>~~ee~~|25<br>~~—————~~<br>~~ee~~|ns<br>~~—————~~<br>~~ee~~|



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**CYW43439** 

## **Long Frame Sync, Slave Mode** 

**Figure 23. PCM Timing Diagram (Long Frame Sync, Slave Mode)** 

**==> picture [398 x 124] intentionally omitted <==**

**----- Start of picture text -----**<br>
1<br>2 3<br>PCM_BCLK<br>4<br>5<br>PCM_SYNC<br>9<br>PCM_OUT Bit 0 Bit 1 HIGH IMPEDANCE<br>6<br>7 8<br>PCM_IN Bit 0 Bit 1<br>**----- End of picture text -----**<br>


**Table 11. PCM Interface Timing Specifications (Long Frame Sync, Slave Mode)** 

|**Ref No.**<br>~~a~~|**Characteristics**<br>~~RG~~|**Minimum**<br>~~RG~~|**Typical**<br>~~RG~~|**Maximum**<br>~~RG~~|**Unit**<br>~~RG~~|
|---|---|---|---|---|---|
|1<br>~~GG~~|PCM bit clock frequency<br>~~GG~~|–<br>~~GG~~|–<br>~~GG~~|12<br>~~GG~~|MHz<br>~~GG~~|
|2<br>~~GG~~<br>~~a~~|PCM bit clock low<br>~~GG~~<br>~~DO~~|41<br>~~GG~~<br>~~DO~~|–<br>~~GG~~<br>~~DO~~|–<br>~~GG~~<br>~~DO~~|ns<br>~~GG~~<br>~~DO~~|
|3<br>~~GO~~|PCM bit clock high<br>~~GO~~|41<br>~~GO~~|–<br>~~GO~~|–<br>~~GO~~|ns<br>~~GO~~|
|4<br>~~GO~~<br>~~a~~|PCM_SYNC setup<br>~~GO~~<br>~~DO~~|8<br>~~GO~~<br>~~DO~~|–<br>~~GO~~<br>~~DO~~|–<br>~~GO~~<br>~~DO~~|ns<br>~~GO~~<br>~~DO~~|
|5<br>~~GO~~|PCM_SYNC hold<br>~~GO~~|8<br>~~GO~~|–<br>~~GO~~|–<br>~~GO~~|ns<br>~~GO~~|
|6<br>~~GO~~<br>~~a~~|PCM_OUT delay<br>~~GO~~<br>~~DO~~|0<br>~~GO~~<br>~~DO~~|–<br>~~GO~~<br>~~DO~~|25<br>~~GO~~<br>~~DO~~|ns<br>~~GO~~<br>~~DO~~|
|7<br>~~GO~~|PCM_IN setup<br>~~GO~~|8<br>~~GO~~|–<br>~~GO~~|–<br>~~GO~~|ns<br>~~GO~~|
|8<br>~~GO~~<br>~~a~~|PCM_IN hold<br>~~GO~~<br>~~DO~~|8<br>~~GO~~<br>~~DO~~|–<br>~~GO~~<br>~~DO~~|–<br>~~GO~~<br>~~DO~~|ns<br>~~GO~~<br>~~DO~~|
|9|Delay from rising edge of PCM_BCLK during last bit period to<br>PCM_OUT becoming high impedance|0|–|25|ns|



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**CYW43439** 

## **9.2  UART Interface** 

The CYW43439 has a single UART for Bluetooth. The UART is a standard 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from 9600 bps to 4.0 Mbps. The interface features an automatic baud rate detection capability that returns a baud rate selection. Alternatively, the baud rate may be selected through a vendor-specific UART HCI command. 

The UART has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support EDR. Access to the FIFOs is conducted through the Advanced High Performance Bus (AHB) interface through either DMA or the CPU. The UART supports the Bluetooth 5.2 compliance UART HCI specification: H4 and H5. The default baud rate is 115.2 Kbaud. 

The UART supports the 3-wire H5 UART transport as described in the Bluetooth specification ( _Three-wire UART Transport Layer_ ). Compared to H4, the H5 UART transport reduces the number of signal lines required by eliminating the CTS and RTS signals. 

The CYW43439 UART can perform XON/XOFF flow control and includes hardware support for the Serial Line Input Protocol (SLIP). It can also perform a wake-on activity function. For example, activity on the RX or CTS inputs can wake the chip from a sleep state. 

Normally, the UART baud rate is set by a configuration record downloaded after device reset or by automatic baud rate detection, and the host does not need to adjust the baud rate. Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command that allows the host to adjust the contents of the baud rate registers. The CYW43439 UARTs operate correctly with the host UART as long as the combined baud rate error of the two devices is within ±2% (see Table 12). 

**Table 12. Example of Common Baud Rates** 

|**Desired Rate**|**Actual Rate**|**Error (%)**|
|---|---|---|
|4000000<br>~~a~~|4000000|0.00|
|3692000<br>~~a~~|3692308|0.01|
|3000000<br>~~a~~<br>~~a~~|3000000|0.00|
|2000000<br>~~a~~|2000000|0.00|
|1500000<br>~~a~~<br>~~a~~|1500000|0.00|
|1444444<br>~~a~~|1454544|0.70|
|921600<br>~~a~~<br>~~a~~|923077|0.16|
|460800<br>~~a~~|461538|0.16|
|230400<br>~~a~~<br>~~a~~|230796|0.17|
|115200<br>~~a~~|115385|0.16|
|57600<br>~~a~~<br>~~a~~|57692|0.16|
|38400<br>~~a~~|38400|0.00|
|28800<br>~~a~~<br>~~a~~|28846|0.16|
|19200<br>~~a~~|19200|0.00|
|14400<br>~~a~~<br>~~a~~|14423|0.16|
|9600<br>~~a~~|9600|0.00|



UART timing is defined in Figure 24 and Table 13. 

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**CYW43439** 

**Figure 24. UART Timing** 

**==> picture [477 x 135] intentionally omitted <==**

**----- Start of picture text -----**<br>
UART_CTS_N<br>1 2<br>UART_TXD<br>Midpoint of STOP bit Midpoint of STOP bit<br>UART_RXD<br>3<br>UART_RTS_N<br>**----- End of picture text -----**<br>


**Table 13. UART Timing Specifications** 

|**Ref No.**|**Characteristics**|**Minimum**|**Typical**|**Maximum**|**Unit**|
|---|---|---|---|---|---|
|1|Delay time, UART_CTS_N low to UART_TXD valid|–|–|1.5|Bit periods|
|2|Setup time, UART_CTS_N high before midpoint<br>of stop bit|–|–|0.5|Bit periods|
|3|Delay time, midpoint of stop bit to UART_RTS_N high|–|–|0.5|Bit periods|



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**CYW43439** 

## **10.  CPU and Global Functions** 

## **10.1  WLAN CPU and Memory Subsystem** 

The CYW43439 includes an integrated ARM Cortex-M3 processor with internal RAM and ROM. The ARM Cortex-M3 processor is a low-power processor that features low gate count, low interrupt latency, and low-cost debugging. It is intended for deeply embedded applications that require fast interrupt response features. The processor implements the ARM architecture v7-M with support for the Thumb-2 instruction set. ARM Cortex-M3 provides a 30% performance gain over ARM7TDMI. 

At 0.19 µW/MHz, the Cortex-M3 is the most power efficient general purpose microprocessor available, outperforming 8- and 16-bit devices on MIPS/µW. It supports integrated sleep modes. 

ARM Cortex-M3 uses multiple technologies to reduce cost through improved memory utilization, reduced pin overhead, and reduced silicon area. ARM Cortex-M3 supports independent buses for code and data access (ICode/DCode and system buses). ARM CortexM3 supports extensive debug features including real-time tracing of program execution. 

On-chip memory for the CPU includes 512 KB SRAM and 640 KB ROM. 

## **10.2  One-Time Programmable Memory** 

Various hardware configuration parameters may be stored in an internal 4096-bit One-Time Programmable (OTP) memory, which is read by system software after a device reset. In addition, customer-specific parameters, including the system vendor ID and the MAC address, can be stored, depending on the specific board design. 

The initial state of all bits in an unprogrammed OTP device is 0. After any bit is programmed to a 1, it cannot be reprogrammed to 0. The entire OTP array can be programmed in a single write cycle using a utility provided with the Cypress WLAN manufacturing test tools. Alternatively, multiple write cycles can be used to selectively program specific bytes, but only bits which are still in the 0 state can be altered during each programming cycle. 

Prior to OTP memory programming, all values should be verified using the appropriate editable nvram.txt file, which is provided with the reference board design package. Documentation on the OTP development process is available on the Cypress customer support portal (http://www.Cypress.com/support). 

## **10.3  GPIO Interface** 

Five general purpose I/O (GPIO) pins are available on the CYW43439 that can be used to connect to various external devices. 

GPIOs are tristated by default. Subsequently, they can be programmed to be either input or output pins via the GPIO control register. They can also be programmed to have internal pull-up or pull-down resistors. 

GPIO_0 is normally used as a WL_HOST_WAKE signal. 

The CYW43439 supports a 2-wire coexistence configuration using GPIO_1 and GPIO_2. 

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**CYW43439** 

## **10.4  External Coexistence Interface** 

The CYW43439 supports a 2-wire coexistence interface to enable signaling between the device and an external colocated wireless device in order to manage wireless medium sharing for optimal performance. The external colocated device can be any of the following ICs: GPS, WiMAX or UWB. An External IC is used in this section for illustration. 

Figure 25 shows a 2-wire LTE coexistence example. The following definitions apply to the GPIOs in the figure: 

■ GPIO_1: WLAN_SECI_TX output to an External IC. 

■ GPIO_2: WLAN_SECI_RX input from an External IC. 

**Figure 25. 2-Wire Coexistence Interface to an External IC** 

**==> picture [220 x 109] intentionally omitted <==**

**----- Start of picture text -----**<br>
GPIO_1 WLAN_SECI_TX<br>UART_IN<br>WLAN GPIO_2 WLAN_SECI_RX<br>Coexistence  UART_OUT<br>Interface<br>BT<br>LTE/IC<br>B L 7<br>Notes:<br> OR ing to generate ISM_RX_PRIORITY for ERCX_TXCONF or BT_RX_PRIORITY is achieved by<br>setting the GPIO mask registers appropriately.<br>WLAN_SECI_OUT and WLAN_SECI_IN are multiplexed on the GPIOs.<br>**----- End of picture text -----**<br>


See Figure 24 and Table 13: “UART Timing Specifications”  for UART timing. 

## **10.5  JTAG Interface** 

The CYW43439 supports the IEEE 1149.1 JTAG boundary scan standard over SDIO for performing device package and PCB assembly testing during manufacturing. In addition, the JTAG interface allows Cypress to assist customers by using proprietary debug and characterization test tools during board bring-up. Therefore, it is highly recommended to provide access to the JTAG pins by means of test points or a header on all PCB designs. 

## **10.6  UART Interface** 

One UART interface can be enabled by software as an alternate function on the JTAG pins. UART_RX is available on the JTAG_TDI pin, and UART_TX is available on the JTAG_TDO pin. 

The UART is primarily for debugging during development. By adding an external RS-232 transceiver, this UART enables the CYW43439 to operate as RS-232 data termination equipment (DTE) for exchanging and managing data with other serial devices. It is compatible with the industry standard 16550 UART, and it provides a FIFO size of 64 × 8 in each direction. 

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**CYW43439** 

## **11.  WLAN Software Architecture** 

## **11.1  Host Software Architecture** 

The host driver (DHD) provides a transparent connection between the host operating system and the CYW43439 media (for example, WLAN) by presenting a network driver interface to the host operating system and communicating with the CYW43439 over an interface-specific bus (SPI, SDIO, and so on) to: 

■ Forward transmit and receive frames between the host network stack and the CYW43439 device. 

■ Pass control requests from the host to the CYW43439 device, returning the CYW43439 device responses. 

The driver communicates with the CYW43439 over the bus using a control channel and a data channel to pass control messages and data messages. The actual message format is based on the BDC protocol. 

## **11.2  Device Software Architecture** 

The wireless device, protocol, and bus drivers are run on the embedded ARM processor using a Cypress-defined operating system called HNDRTE, which transfers data over a propriety Cypress format over the SDIO/SPI interface between the host and device (BDC/ LMAC). The data portion of the format consists of IEEE 802.11 frames wrapped in a Cypress encapsulation. The host architecture provides all missing functionality between a network device and the Cypress device interface. The host can also be customized to provide functionality between the Cypress device interface and a full network device interface. 

This transfer requires a message-oriented (framed) interconnect between the host and device. The SDIO bus is an addressed bus— each host-initiated bus operation contains an explicit device target address—and does not natively support a higher-level data frame concept. Cypress has implemented a hardware/software message encapsulation scheme that ignores the bus operation code address and prefixes each frame with a 4-byte length tag for framing. The device presents a packet-level interface over which data, control, and asynchronous event (from the device) packets are supported. 

The data and control packets received from the bus are initially processed by the bus driver and then passed on to the protocol driver. If the packets are data packets, they are transferred to the wireless device driver (and out through its medium), and a data packet received from the device medium follows the same path in the reverse direction. If the packets are control packets, the protocol header is decoded by the protocol driver. If the packets are wireless IOCTL packets, the IOCTL API of the wireless driver is called to configure the wireless device. The microcode running in the D11 core processes all time-critical tasks. 

## _11.2.1  Remote Downloader_ 

When the CYW43439 powers up, the DHD initializes and downloads the firmware to run in the device. 

**Figure 26. WLAN Software Architecture** 

**==> picture [83 x 137] intentionally omitted <==**

**----- Start of picture text -----**<br>
DHD Host Driver<br>SPI/SDIO<br>BDC/LMAC Protocol<br>Wireless Device Driver<br>D11 Core<br>**----- End of picture text -----**<br>


## **11.3  Wireless Configuration Utility** 

The device driver that supports the Cypress IEEE 802.11 family of wireless solutions provides an input/output control (IOCTL) interface for making advanced configuration settings. The IOCTL interface makes it possible to make settings that are normally not possible when using just the native operating system-specific IEEE 802.11 configuration mechanisms. The utility uses IOCTLs to query or set a number of different driver/chip operating properties. 

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**CYW43439** 

## **12.  Pinout and Signal Descriptions** 

## **12.1  Ball Map** 

Figure 27 shows the 63-ball WLBGA ball map. 

**Figure 27. 63-Ball WLBGA Ball Map (Bottom View)** 

|~~a~~|**A**<br>~~a~~|**B**<br>~~a~~|**C**<br>~~a~~|**D**|**E**<br>~~Sa~~|**F**<br>~~Sa~~|**G**<br>~~Sa~~|**H**<br>~~Sa~~|**J**|**K**|**L**|**M**||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**1**<br>~~a~~|BT_UART_<br>RXD<br>~~a~~|BT_DEV_<br>WAKE<br>~~a~~|BT_HOST_<br>WAKE<br>~~a~~||FM_RF_IN<br>~~Sa~~|BT_VCO_<br>VDD<br>~~Sa~~|BT_IF_<br>VDD<br>~~Sa~~|BT_PAVDD<br>~~Sa~~|WLRF_<br>2G_eLG|WLRF_<br>2G_RF||WLRF_<br>PA_VDD|**1**|
|**2**|BT_UART_<br>TXD|BT_UART_<br>CTS_N|FM_OUT1|FM_OUT2|FM_RF_<br>VDD|BTFM_<br>PLL_VDD|BTFM_<br>PLL_VSS|BT_IF_VSS|WLRF_<br>LNA_GND|WLRF_<br>GENERAL_<br>GND|WLRF_PA_<br>GND|WLRF_VDD<br>_<br>1P35|**2**|
|**3**|||BT_UART_<br>RTS_N|VDDC|FM_RF_VS<br>S|||BT_VCO_V<br>SS|WLRF_GPI<br>O||WLRF_VCO<br>_GND|WLRF_XTA<br>L_VDD1P2|**3**|
|**4**||BT_PCM_<br>OUT|BT_PCM_IN|VSSC|||VDDC|WLRF_AFE<br>_GND|||WLRF_XTA<br>L_GND|WLRF_XTA<br>L_XOP|**4**|
|**5**|BT_PCM_<br>CLK|BT_PCM_<br>SYNC||||LPO_IN|||VSSC||GPIO_2|WLRF_XTA<br>L_XON|**5**|
|**6**|SR_VLX|PMU_AVSS|VOUT_CLD<br>O|VOUT_LNL<br>DO|BT_REG_O<br>N|WCC_VDDI<br>O|WL_REG_O<br>N|GPIO_1|GPIO_0|SDIO_<br>DATA_0|SDIO_CMD|CLK_REQ|**6**|
|**7**<br>~~|~~|SR_PVSS<br>~~|~~|SR_<br>VDDBAT5V|LDO_VDD1<br>P5|~~ft~~|VOUT_3P3<br>~~ft~~|LDO_<br>VDDBAT5V|~~ff~~|SDIO_<br>DATA_1|SDIO_<br>DATA_3<br>~~mT~~|~~mT~~|SDIO_<br>DATA_2<br>~~mT~~|SDIO_CLK<br>~~mT~~|**7**<br>~~mT~~|
|~~|~~|**A**<br>~~|~~|**B**|**C**|**D**<br>~~ft~~|**E**<br>~~ft~~|**F**|**G**<br>~~ff~~|**H**|**J**<br>~~mT~~|**K**<br>~~mT~~|**L**<br>~~mT~~|**M**<br>~~mT~~|~~mT~~|



Document Number: 002-30348 Rev. *D 

Page 45 of 87 

**CYW43439** 

## **12.2  WLBGA Ball List in Ball Number Order with X-Y Coordinates** 

Table 14 provides ball numbers and names in ball number order. The table includes the X and Y coordinates for a top view with a (0,0) center. 

**Table 14. CYW43439 WLBGA Ball List — Ordered By Ball Number** 

|**Ball Number**<br>~~GC~~|**Ball Name**<br>~~GC~~|**X Coordinate**<br>~~GC~~|**Y Coordinate**<br>~~GC~~|
|---|---|---|---|
|A1<br>~~eG~~|BT_UART_RXD<br>~~eG~~|–1200.006<br>~~eG~~|2199.996<br>~~eG~~|
|A2<br>~~a~~|BT_UART_TXD<br>~~G~~|–799.992<br>~~G~~|2199.996<br>~~G~~|
|A5<br>~~a ~~<br>~~eG~~|BT_PCM_CLK or BT_I2S_CLK<br> ~~G~~<br>~~eG~~|399.996<br>~~G~~<br>~~eG~~|2199.996<br>~~G~~<br>~~eG~~|
|A6<br>~~CO~~|SR_VLX<br>~~CO~~|799.992<br>~~CO~~<br>~~C~~|2199.978<br>~~CO~~|
|A7<br>~~CO~~<br>~~eG~~|SR_PVSS<br>~~CO~~<br>~~eG~~|1199.988<br>~~CO~~<br>~~eG~~<br>~~C~~|2199.978<br>~~CO~~<br>~~eG~~|
|B1<br>~~GC~~|BT_DEV_WAKE<br>~~GC~~|–1200.006<br>~~C~~<br>~~GC~~|1800<br>~~GC~~|
|B2<br>~~GG~~|BT_UART_CTS_N<br>~~GG~~|–799.992<br>~~GG~~|1800<br>~~GG~~|
|B4<br>~~GG~~<br>~~GG~~|BT_PCM_OUT or BT_I2S_DO<br>~~GG~~<br>~~GG~~|0<br>~~GG~~<br>~~GG~~|1800<br>~~GG~~<br>~~GG~~|
|B5<br>~~CO~~|BT_PCM_SYNC or BT_I2S_WS<br>~~CO~~|399.996<br>~~CO~~|1800<br>~~CO~~|
|B6<br>~~CO~~<br>~~eG~~|PMU_AVSS<br>~~CO~~<br>~~eG~~|799.992<br>~~CO~~<br>~~eG~~|1799.982<br>~~CO~~<br>~~eG~~|
|B7<br>~~GG~~|SR_VBAT5V<br>~~GG~~|1199.988<br>~~GG~~|1799.982<br>~~GG~~|
|C1<br>~~GG~~|BT_HOST_WAKE<br>~~GG~~|–1200.006<br>~~GG~~|1399.995<br>~~GG~~|
|C2<br>~~GG~~|FM_OUT1<br>~~GG~~|–799.992<br>~~GG~~|1399.986<br>~~GG~~|
|C3<br>~~a~~|BT_UART_RTS_N<br>~~G~~|–399.996<br>~~G~~|1399.995<br>~~G~~|
|C4<br>~~a ~~<br>~~eG~~|BT_PCM_IN or BT_I2S_DI<br> ~~G~~<br>~~eG~~|0<br>~~G~~<br>~~eG~~|1399.995<br>~~G~~<br>~~eG~~|
|C6<br>~~CO~~|VOUT_CLDO<br>~~CO~~|799.992<br>~~CO~~|1399.986<br>~~CO~~|
|C7<br>~~CO~~<br>~~GG~~|LDO_VDD15V<br>~~CO~~<br>~~GG~~|1199.988<br>~~CO~~<br>~~GG~~|1399.986<br>~~CO~~<br>~~GG~~|
|D2<br>~~GG~~|FM_OUT2<br>~~GG~~|–799.992<br>~~GG~~|999.99<br>~~GG~~|
|D3<br>~~GG~~|VDDC<br>~~GG~~|–399.996<br>~~GG~~|999.999<br>~~GG~~|
|D4<br>~~GG~~<br>~~GG~~|VSSC<br>~~GG~~<br>~~GG~~|0<br>~~GG~~<br>~~GG~~|999.999<br>~~GG~~<br>~~GG~~|
|D6<br>~~a~~|VOUT_LNLDO<br>~~G~~|799.992<br>~~G~~|999.99<br>~~G~~|
|E1<br>~~a ~~<br>~~eG~~|FM_RF_IN<br> ~~G~~<br>~~eG~~|–1199.988<br>~~G~~<br>~~eG~~|599.994<br>~~G~~<br>~~eG~~|
|E2<br>~~CO~~|FM_RF_VDD<br>~~CO~~|–799.992<br>~~CO~~|599.994<br>~~CO~~|
|E3<br>~~CO~~<br>~~GG~~|FM_RF_VSS<br>~~CO~~<br>~~GG~~|–399.996<br>~~CO~~<br>~~GG~~|599.994<br>~~CO~~<br>~~GG~~|
|E6<br>~~GG~~|BT_REG_ON<br>~~GG~~|799.992<br>~~GG~~|599.994<br>~~GG~~|
|E7<br>~~GG~~|VOUT_3P3<br>~~GG~~|1199.988<br>~~GG~~|599.994<br>~~GG~~|
|F1<br>~~GG~~|BT_VCO_VDD<br>~~GG~~|–1199.988<br>~~GG~~|199.998<br>~~GG~~|
|F2<br>~~CO~~|BTFM_PLL_VDD<br>~~CO~~|–799.992<br>~~CO~~|199.998<br>~~CO~~|
|F5<br>~~CO~~<br>~~eG~~|LPO_IN<br>~~CO~~<br>~~eG~~|399.996<br>~~CO~~<br>~~eG~~|199.998<br>~~CO~~<br>~~eG~~|
|F6<br>~~GG~~|WCC_VDDIO<br>~~GG~~|800.001<br>~~GG~~|199.998<br>~~GG~~|
|F7<br>~~GG~~|LDO_VBAT5V<br>~~GG~~|1199.988<br>~~GG~~|199.998<br>~~GG~~|
|G1<br>~~GG~~|BT_IF_VDD<br>~~GG~~|–1199.988<br>~~GG~~|–199.998<br>~~GG~~|
|G2<br>~~a~~|BTFM_PLL_VSS<br>~~G~~|–799.992<br>~~G~~|–199.998<br>~~G~~|
|G4<br>~~a ~~<br>~~eG~~|VDDC<br> ~~G~~<br>~~eG~~|0<br>~~G~~<br>~~eG~~|–199.998<br>~~G~~<br>~~eG~~|
|G6<br>~~CO~~|WL_REG_ON<br>~~CO~~|800.001<br>~~CO~~|–199.998<br>~~CO~~|



Document Number: 002-30348 Rev. *D 

Page 46 of 87 

**CYW43439** 

**Table 14. CYW43439 WLBGA Ball List — Ordered By Ball Number (Cont.)** 

|**Ball Number**<br>~~GC~~|**Ball Name**<br>~~GC~~|**X Coordinate**<br>~~GC~~|**Y Coordinate**<br>~~GC~~|
|---|---|---|---|
|H1<br>~~GG~~|BT_PAVDD<br>~~GG~~|–1199.988<br>~~GG~~|–599.994<br>~~GG~~|
|H2<br>~~GG~~|BT_IF_VSS<br>~~GG~~|–799.992<br>~~GG~~|–599.994<br>~~GG~~|
|H3<br>~~GG~~<br>~~GG~~|BT_VCO_VSS<br>~~GG~~<br>~~GG~~|–399.996<br>~~GG~~<br>~~GG~~|–599.994<br>~~GG~~<br>~~GG~~|
|H4<br>~~a~~|WLRF_AFE_GND<br>~~G~~|0<br>~~G~~|–599.994<br>~~G~~|
|H6<br>~~a ~~<br>~~eG~~|GPIO_1<br> ~~G~~<br>~~eG~~|800.001<br>~~G~~<br>~~eG~~|–599.994<br>~~G~~<br>~~eG~~|
|H7<br>~~CO~~|SDIO_DATA_1<br>~~CO~~|1200.006<br>~~CO~~|–599.994<br>~~CO~~|
|J1<br>~~CO~~<br>~~eG~~|WLRF_2G_eLG<br>~~CO~~<br>~~eG~~|–1199.988<br>~~CO~~<br>~~eG~~|–999.99<br>~~CO~~<br>~~eG~~|
|J2<br>~~GG~~|WLRF_LNA_GND<br>~~GG~~|–799.992<br>~~GG~~|–999.99<br>~~GG~~|
|J3<br>~~GG~~|WLRF_GPIO<br>~~GG~~|–399.996<br>~~GG~~|–999.99<br>~~GG~~|
|J5<br>~~GG~~|VSSC<br>~~GG~~|399.996<br>~~GG~~|–999.999<br>~~GG~~|
|J6<br>~~CO~~|GPIO_0<br>~~CO~~|800.001<br>~~CO~~|–999.999<br>~~CO~~|
|J7<br>~~CO~~<br>~~eG~~|SDIO_DATA_3<br>~~CO~~<br>~~eG~~|1200.006<br>~~CO~~<br>~~eG~~|–999.999<br>~~CO~~<br>~~eG~~|
|K1<br>~~GG~~|WLRF_2G_RF<br>~~GG~~|–1199.988<br>~~GG~~|–1399.986<br>~~GG~~|
|K2<br>~~GG~~|WLRF_GENERAL_GND<br>~~GG~~|–799.992<br>~~GG~~|–1399.986<br>~~GG~~|
|K6<br>~~GG~~<br>~~GG~~|SDIO_DATA_0<br>~~GG~~<br>~~GG~~|800.001<br>~~GG~~<br>~~GG~~|–1399.995<br>~~GG~~<br>~~GG~~|
|L2<br>~~a~~|WLRF_PA_GND<br>~~G~~|–799.992<br>~~G~~|–1799.982<br>~~G~~|
|L3<br>~~a ~~<br>~~eG~~|WLRF_VCO_GND<br> ~~G~~<br>~~eG~~|–399.996<br>~~G~~<br>~~eG~~|–1799.982<br>~~G~~<br>~~eG~~|
|L4<br>~~CO~~|WLRF_XTAL_GND<br>~~CO~~|0<br>~~CO~~|–1799.982<br>~~CO~~|
|L5<br>~~CO~~<br>~~GG~~|GPIO_2<br>~~CO~~<br>~~GG~~|399.996<br>~~CO~~<br>~~GG~~|–1799.991<br>~~CO~~<br>~~GG~~|
|L6<br>~~GG~~|SDIO_CMD<br>~~GG~~|800.001<br>~~GG~~|–1799.991<br>~~GG~~|
|L7<br>~~GG~~|SDIO_DATA_2<br>~~GG~~|1200.006<br>~~GG~~|–1799.991<br>~~GG~~|
|M1<br>~~GG~~<br>~~GG~~|WLRF_PA_VDD<br>~~GG~~<br>~~GG~~|–1199.988<br>~~GG~~<br>~~GG~~|–2199.978<br>~~GG~~<br>~~GG~~|
|M2<br>~~CO~~|WLRF_VDD_1P35<br>~~CO~~|–799.992<br>~~CO~~|–2199.978<br>~~CO~~|
|M3<br>~~CO~~<br>~~eG~~|WLRF_XTAL_VDD1P2<br>~~CO~~<br>~~eG~~|–399.996<br>~~CO~~<br>~~eG~~|–2199.978<br>~~CO~~<br>~~eG~~|
|M4<br>~~CO~~|WLRF_XTAL_XOP<br>~~CO~~|0<br>~~CO~~|–2199.978<br>~~CO~~|
|M5<br>~~CO~~<br>~~GG~~|WLRF_XTAL_XON<br>~~CO~~<br>~~GG~~|399.996<br>~~CO~~<br>~~GG~~|–2199.978<br>~~CO~~<br>~~GG~~|
|M6<br>~~GG~~|CLK_REQ<br>~~GG~~|800.001<br>~~GG~~|–2199.996<br>~~GG~~|
|M7<br>~~GD~~|SDIO_CLK<br>~~GD~~|1200.006<br>~~GD~~|–2199.996<br>~~GD~~|



Document Number: 002-30348 Rev. *D 

Page 47 of 87 

**CYW43439** 

## **12.3  WLBGA Ball List Ordered By Ball Name** 

Table 15 provides the ball numbers and names in ball name order. 

**Table 15. CYW43439 WLBGA Ball List — Ordered By Ball Name** 

|**Ball Name**<br>**Ball Number**<br>BT_DEV_WAKE<br>B1<br>BT_HOST_WAKE<br>C1<br>SDIO_CMD<br>L6<br>SDIO_DATA_0<br>K6<br>**Ball Name**<br>**Ball Number**<br>~~PSS~~<br>~~Os~~<br>~~PT~~|
|---|
|BT_IF_VDD<br>G1<br>SDIO_DATA_1<br>H7<br>~~Qf~~|
|BT_IF_VSS<br>H2<br>SDIO_DATA_2<br>L7|
|BT_PAVDD<br>H1<br>SDIO_DATA_3<br>J7<br>~~Cf~~|
|BT_PCM_CLK or BT_I2S_CLK<br>A5<br>SR_PVSS<br>A7|
|BT_PCM_IN or BT_I2S_DI<br>C4<br>BT_PCM_OUT or BT_I2S_DO<br>B4<br>BT_PCM_SYNC or BT_I2S_WS<br>B5<br>BT_REG_ON<br>E6<br>SR_VDDBAT5V<br>B7<br>SR_VLX<br>A6<br>VDDC<br>D3<br>VDDC<br>G4<br>~~SO~~<br>~~(~~<br>~~Os~~<br>~~SO OD~~<br>~~sO fC~~|
|BT_UART_CTS_N<br>B2<br>BT_UART_RTS_N<br>C3<br>VOUT_3P3<br>E7<br>VOUT_CLDO<br>C6<br>~~OO~~<br>~~Of~~|
|BT_UART_RXD<br>A1<br>BT_UART_TXD<br>A2<br>VOUT_LNLDO<br>D6<br>VSSC<br>D4<br>~~Os~~<br>~~sO~~<br>~~(~~|
|BT_VCO_VDD<br>F1<br>VSSC<br>J5<br>~~Qf~~|
|BT_VCO_VSS<br>H3<br>BTFM_PLL_VDD<br>F2<br>WCC_VDDIO<br>F6<br>WL_REG_ON<br>G6<br>~~OO~~<br>~~sO fC~~|
|BTFM_PLL_VSS<br>G2<br>WLRF_2G_eLG<br>J1|
|CLK_REQ<br>M6<br>FM_OUT1<br>C2<br>FM_OUT2<br>D2<br>FM_RF_IN<br>E1<br>FM_RF_VDD<br>E2<br>FM_RF_VSS<br>E3<br>WLRF_2G_RF<br>K1<br>WLRF_AFE_GND<br>H4<br>WLRF_GENERAL_GND<br>K2<br>WLRF_GPIO<br>J3<br>WLRF_LNA_GND<br>J2<br>WLRF_PA_GND<br>L2<br>~~SO~~<br>~~(~~<br>~~Os~~<br>~~SO ~~Or<br>~~CG~~<br>~~OO~~<br>~~Of~~|
|GPIO_0<br>J6<br>GPIO_1<br>H6<br>WLRF_PA_VDD<br>M1<br>WLRF_VCO_GND<br>L3<br>~~Os~~<br>~~PT~~|
|GPIO_2<br>L5<br>WLRF_VDD_1P35<br>M2<br>~~Qf~~|
|LDO_VDD1P5<br>C7<br>LDO_VDDBAT5V<br>F7<br>WLRF_XTAL_GND<br>L4<br>WLRF_XTAL_VDD1P2<br>M3<br>~~OO~~<br>~~sO fC~~|
|LPO_IN<br>F5<br>WLRF_XTAL_XON<br>M5|
|PMU_AVSS<br>B6<br>SDIO_CLK<br>M7<br>WLRF_XTAL_XOP<br>M4<br>~~Cf~~<br>~~D~~<br>~~a~~|



Document Number: 002-30348 Rev. *D 

Page 48 of 87 

**CYW43439** 

## **12.4  Signal Descriptions** 

Table 16 provides the WLBGA package signal descriptions. 

**Table 16. WLBGA Signal Descriptions** 

|**Signal Name**|**WLBGA**<br>**Ball**|**Type**|**Description**|
|---|---|---|---|
|**RF Signal Interface**||||
|WLRF_2G_RF<br>~~GC~~|K1<br>~~GC~~|O<br>~~GC~~|2.4 GHz BT and WLAN RF output port<br>~~GC~~|
|**SDIO Bus Interface**<br>~~GC~~<br>~~pt~~||||
|SDIO_CLK<br>~~GO~~|M7<br>~~GO~~|I<br>~~GO~~|SDIO clock input<br>~~GO~~|
|SDIO_CMD<br>~~GO~~<br>~~a~~|L6<br>~~GO~~<br>~~GG~~|I/O<br>~~GO~~<br>~~GG~~|SDIO command line<br>~~GO~~<br>~~GG~~|
|SDIO_DATA_0<br>~~GG~~|K6<br>~~GG~~|I/O<br>~~GG~~|SDIO data line 0<br>~~GG~~|
|SDIO_DATA_1<br>~~GG~~<br>~~a~~|H7<br>~~GG~~<br>~~GG~~|I/O<br>~~GG~~<br>~~GG~~|SDIO data line 1.<br>~~GG~~<br>~~GG~~|
|SDIO_DATA_2<br>~~GG~~|L7<br>~~GG~~|I/O<br>~~GG~~|SDIO data line 2. Also used as a strapping option (seeTable 19).<br>~~GG~~|
|SDIO_DATA_3<br>~~GG~~<br>~~Oo~~|J7<br>~~GG~~<br>~~Oo~~|I/O<br>~~GG~~<br>~~Oo~~|SDIO data line 3<br>~~GG~~<br>~~Oo~~|
|**Note:**Per Section 6 of the SDIO specification, 10 to 100 kΩ pull-ups are required on the four DATA lines and the CMD line. This requirement must<br>be met during all operating states by using external pull-up resistors or properly programming internal SDIO host pull-ups.<br>~~Oo~~||||
|**WLAN GPIO Interface**<br>~~Oo~~||||
|WLRF_GPIO<br>~~GC~~|J3<br>~~GC~~|I/O<br>~~GC~~|Test pin. Not connected in normal operation.<br>~~GC~~|
|**Clocks**<br>~~GC~~<br>~~pe~~||||
|WLRF_XTAL_XON<br>~~pp~~|M5<br>~~pp~~|O<br>~~pp~~|XTAL oscillator output<br>~~pp~~|
|WLRF_XTAL_XOP<br>~~pp~~<br>~~ee~~|M4<br>~~pp~~<br>~~ee~~|I<br>~~pp~~<br>~~ee~~|XTAL oscillator input<br>~~pp~~<br>~~ee~~|
|CLK_REQ<br>~~ee~~|M6<br>~~ee~~|O<br>~~ee~~|External system clock request—Used when the system clock is not provided<br>by a dedicated crystal (for example, when a shared TCXO is used). Asserted<br>to indicate to the host that the clock is required. Shared by BT, and WLAN.<br>~~ee~~|
|LPO_IN|F5|I|External sleep clock input (32.768 kHz). If an external 32.768 kHz clock<br>cannot be provided, pull this pin low. However, BLE will be always on and<br>cannot go to deep sleep.|
|**FM Receiver[6]**<br>~~pe~~||||
|FM_OUT1<br>~~GG~~|C2<br>~~GG~~|O<br>~~GG~~|FM analog output 1<br>~~GG~~|
|FM_OUT2<br>~~eG~~|D2<br>~~eG~~|O<br>~~eG~~|FM analog output 2<br>~~eG~~|
|FM_RF_IN<br>~~eG~~|E1<br>~~eG~~|I<br>~~eG~~|FM radio antenna port<br>~~eG~~|
|FM_RF_VDD<br>~~eG~~<br>~~eG~~|E2<br>~~eG~~<br>~~eG ~~|I<br>~~eG~~<br> ~~Ge~~|FM power supply<br>~~eG~~<br>~~Ge~~|
|**Bluetooth PCM**||||
|BT_PCM_CLK or BT_I2S_CLK<br>~~eG~~|A5<br>~~eG~~|I/O<br>~~eG~~|PCM or I2S clock; can be master (output) or slave (input)<br>~~eG~~|
|BT_PCM_IN or BT_I2S_DI<br>~~eG~~|C4<br>~~eG~~|I<br>~~eG~~|PCM or I2S data input sensing<br>~~eG~~|
|BT_PCM_OUT or BT_I2S_DO<br>~~eG~~<br>~~eG~~|B4<br>~~eG~~<br>~~eG~~|O<br>~~eG~~<br>~~eG~~|PCM or I2S data output<br>~~eG~~<br>~~eG~~|
|BT_PCM_SYNC or BT_I2S_WS<br>~~a~~|B5<br>~~OG~~|I/O<br>~~OG~~|PCM SYNC or I2S_WS; can be master (output) or slave (input)<br>~~OG~~|



Document Number: 002-30348 Rev. *D 

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**CYW43439** 

**Table 16. WLBGA Signal Descriptions (Cont.)** 

|**Signal Name**<br>~~Ds~~<br>~~EE~~|**WLBGA**<br>**Ball**<br>~~Ds~~<br>~~EE~~|**Type**<br>~~Ds~~<br>~~EE~~|**Description**<br>~~Ds~~<br>~~EE~~<br>~~eee~~|
|---|---|---|---|
|**Bluetooth UART and Wake**<br>~~EE~~<br>~~eee~~||||
|BT_UART_CTS_N<br>~~EE~~<br>~~es~~|B2<br>~~EE~~<br>~~es~~|I<br>~~EE~~<br>~~es~~|UART clear-to-send. Active-low clear-to-send signal for the HCI UART<br>interface.<br>~~EE~~<br>~~eee~~<br>~~es~~|
|BT_UART_RTS_N<br>~~a ~~|C3<br> ~~ee~~|O<br>~~ee~~|UART request-to-send. Active-low request-to-send signal for the HCI UART<br>interface.<br>~~ee~~|
|BT_UART_RXD<br>~~a~~|A1|I|UART serial input. Serial data input for the HCI UART interface.|
|BT_UART_TXD<br>~~a~~|A2|O|UART serial output. Serial data output for the HCI UART interface.|
|BT_DEV_WAKE<br>~~aBC~~|B1<br>~~BC~~|I/O<br>~~BC~~|DEV_WAKE or general-purpose I/O signal.<br>~~BC~~|
|BT_HOST_WAKE<br>~~aBC~~|C1<br>~~BC~~|I/O<br>~~BC~~|HOST_WAKE or general-purpose I/O signal.<br>~~BC~~|
|**Note:**By default, the Bluetooth BT WAKE signals provide GPIO/WAKE functionality, and the UART pins provide UART functionality. Through<br>software configuration, the PCM interface can also be routed over the BT_WAKE/UART signals as follows:<br>■PCM_CLK on the UART_RTS_N pin<br>■PCM_OUT on the UART_CTS_N pin<br>■PCM_SYNC on the BT_HOST_WAKE pin<br>■PCM_IN on the BT_DEV_WAKE pin<br>In this case, the BT HCI transport included sleep signaling will operate using UART_RXD and UART_TXD; that is, using a 3-Wire UART Transport.<br>~~BC~~||||
|**Miscellaneous**<br>~~BC~~<br>~~a~~||||
|WL_REG_ON<br>~~a~~|G6<br>~~a~~|I<br>~~a~~|Used by PMU to power up or power down the internal regulators used by the<br>WLAN section. Also, when deasserted, this pin holds the WLAN section in<br>reset. This pin has an internal 200 kpull-down resistor that is enabled by<br>default. It can be disabled through programming.<br>~~a~~|
|BT_REG_ON|E6|I|Used by PMU to power up or power down the internal regulators used by the<br>Bluetooth/FM section. Also, when deasserted, this pin holds the Bluetooth/<br>FM1section in reset. This pin has an internal 200 kpull-down resistor that<br>is enabled by default. It can be disabled through programming.|
|GPIO_0<br>~~ee~~|J6<br>~~ee~~|I/O<br>~~ee~~|Programmable GPIO pins. This pin becomes an output pin when it is used<br>as WLAN_HOST_WAKE/out-of-band signal.<br>~~ee~~|
|GPIO_1<br>~~ee~~<br>~~a~~|H6<br>~~ee~~<br>~~a~~|I/O<br>~~ee~~<br>~~a~~|Programmable GPIO pins<br>~~ee~~<br>~~a~~|
|GPIO_2<br>~~a~~|L5<br>~~a~~|I/O<br>~~a~~|Programmable GPIO pins<br>~~a~~|
|WLRF_2G_eLG<br>~~a~~<br>~~a~~|J1<br>~~a~~<br>~~a~~|I<br>~~a~~<br>~~a~~|Connect to an external inductor. See the reference schematic for details.<br>~~a~~<br>~~a~~|
|**Integrated Voltage Regulators**<br>~~a~~||||
|SR_VDDBAT5V<br>~~a~~<br>~~eS~~|B7<br>~~a~~<br>~~eS~~|I<br>~~a~~<br>~~eS~~|SR VBAT input power supply<br>~~a~~<br>~~eS~~|
|SR_VLX<br>~~a ~~|A6<br> ~~ee~~|O<br>~~ee~~|CBUCK switching regulator output. SeeTable 34for details of the inductor<br>and capacitor required on this output.<br>~~ee~~|
|LDO_VDDBAT5V<br>~~a~~|F7<br>~~a~~|I<br>~~a~~|LDO VBAT<br>~~a~~|
|LDO_VDD1P5<br>~~a~~<br>~~a~~|C7<br>~~a~~<br>~~a~~|I<br>~~a~~<br>~~a~~|LNLDO input<br>~~a~~<br>~~a~~|
|VOUT_LNLDO<br>~~a~~|D6<br>~~a~~|O<br>~~a~~|Output of low-noise LNLDO<br>~~a~~|
|VOUT_CLDO<br>~~a~~<br>~~a~~|C6<br>~~a~~<br>~~a~~|O<br>~~a~~<br>~~a~~|Output of core LDO<br>~~a~~<br>~~a~~|
|**Bluetooth Power Supplies**<br>~~a~~||||
|BT_PAVDD<br>~~a~~|H1<br>~~a~~|I<br>~~a~~|Bluetooth PA power supply<br>~~a~~|
|BT_IF_VDD<br>~~a~~|G1<br>~~a~~|I<br>~~a~~|Bluetooth IF block power supply<br>~~a~~|
|BTFM_PLL_VDD[6]<br>~~a~~<br>~~a~~|F2<br>~~a~~<br>~~a~~|I<br>~~a~~<br>~~a~~|Bluetooth RF PLL power supply<br>~~a~~<br>~~a~~|
|BT_VCO_VDD<br>~~a~~|F1<br>~~a~~|I<br>~~a~~|Bluetooth RF power supply<br>~~a~~|



Document Number: 002-30348 Rev. *D 

Page 50 of 87 

**CYW43439** 

**Table 16. WLBGA Signal Descriptions (Cont.)** 

|**Signal Name**|**WLBGA**<br>**Ball**|**Type**|**Description**|
|---|---|---|---|
|**Power Supplies**||||
|WLRF_XTAL_VDD1P2<br>~~GC~~|M3<br>~~GC~~|I<br>~~GC~~|XTAL oscillator supply<br>~~GC~~|
|WLRF_PA_VDD<br>~~GC~~<br>~~a~~|M1<br>~~GC~~<br>~~GG~~|I<br>~~GC~~<br>~~GG~~|Power amplifier supply<br>~~GC~~<br>~~GG~~|
|WCC_VDDIO<br>~~GG~~|F6<br>~~GG~~|I<br>~~GG~~|VDDIO input supply. Connect to VDDIO.<br>~~GG~~|
|WLRF_VDD_1P35<br>~~GG~~<br>~~a~~|M2<br>~~GG~~<br>~~GG~~|I<br>~~GG~~<br>~~GG~~|LNLDO input supply<br>~~GG~~<br>~~GG~~|
|VDDC<br>~~GG~~|D3, G4<br>~~GG~~|I<br>~~GG~~|Core supply for WLAN and BT.<br>~~GG~~|
|VOUT_3P3<br>~~GG~~<br>~~eG~~|E7<br>~~GG~~<br>~~eG~~|O<br>~~GG~~<br>~~eG~~|3.3V output supply. See the reference schematic for details.<br>~~GG~~<br>~~eG~~|
|**Ground**||||
|BT_IF_VSS<br>~~GG~~|H2<br>~~GG~~|I<br>~~GG~~|1.2V Bluetooth IF block ground<br>~~GG~~|
|BTFM_PLL_VSS<br>~~GG~~|G2<br>~~GG~~|I<br>~~GG~~|Bluetooth/FM1RF PLL ground<br>~~GG~~|
|BT_VCO_VSS<br>~~GG~~<br>~~a~~|H3<br>~~GG~~<br>~~GG~~|I<br>~~GG~~<br>~~GG~~|1.2V Bluetooth RF ground<br>~~GG~~<br>~~GG~~|
|FM_RF_VSS1<br>~~GG~~|E3<br>~~GG~~|I<br>~~GG~~|FM RF ground<br>~~GG~~|
|PMU_AVSS<br>~~GG~~<br>~~a~~|B6<br>~~GG~~<br>~~GG~~|I<br>~~GG~~<br>~~GG~~|Quiet ground<br>~~GG~~<br>~~GG~~|
|SR_PVSS<br>~~GG~~|A7<br>~~GG~~|I<br>~~GG~~|Switcher-power ground<br>~~GG~~|
|VSSC<br>~~GG~~<br>~~a~~|D4, J5<br>~~GG~~<br>~~GG~~|I<br>~~GG~~<br>~~GG~~|Core ground for WLAN and BT<br>~~GG~~<br>~~GG~~|
|WLRF_AFE_GND<br>~~GG~~|H4<br>~~GG~~|I<br>~~GG~~|AFE ground<br>~~GG~~|
|WLRF_LNA_GND<br>~~GG~~<br>~~a~~|J2<br>~~GG~~<br>~~GG~~|I<br>~~GG~~<br>~~GG~~|2.4 GHz internal LNA ground<br>~~GG~~<br>~~GG~~|
|WLRF_GENERAL_GND<br>~~GG~~|K2<br>~~GG~~|I<br>~~GG~~|Miscellaneous RF ground<br>~~GG~~|
|WLRF_PA_GND<br>~~GG~~<br>~~a~~|L2<br>~~GG~~<br>~~GG~~|I<br>~~GG~~<br>~~GG~~|2.4 GHz PA ground<br>~~GG~~<br>~~GG~~|
|WLRF_VCO_GND<br>~~GG~~|L3<br>~~GG~~|I<br>~~GG~~|VCO/LO generator ground<br>~~GG~~|
|WLRF_XTAL_GND<br>~~GG~~<br>~~GC~~|L4<br>~~GG~~<br>~~GC~~|I<br>~~GG~~<br>~~GC~~|XTAL ground<br>~~GG~~<br>~~GC~~|



**Note** 6. Cypress does not support FM on CYW4356. 

Document Number: 002-30348 Rev. *D 

Page 51 of 87 

**CYW43439** 

## **12.5  WLAN GPIO Signals and Strapping Options** 

The pins listed in Table 17 are sampled at power-on reset (POR) to determine the various operating modes. Sampling occurs a few milliseconds after an internal POR or deassertion of the external POR. After the POR, each pin assumes the GPIO or alternative function specified in the signal descriptions table. Each strapping option pin has an internal pull-up (PU) or pull-down (PD) resistor that determines the default mode. To change the mode, connect an external PU resistor to VDDIO or a PD resistor to ground using a 10 kΩ resistor or less. 

**Note:** Refer to the reference board schematics for more information. 

**Table 17. GPIO Functions and Strapping Options** 

|**Pin Name**|**WLBGA Pin #**|**Default**|**Function**|**Description**|
|---|---|---|---|---|
|SDIO_DATA_2|L7|1|WLAN host interface<br>select|This pin selects the WLAN host interface mode. The<br>default is SDIO. For gSPI, pull this pin low.|



## **12.6  Chip Debug Options** 

The chip can be accessed for debugging via the JTAG interface, multiplexed on the SDIO_DATA_0 through SDIO_DATA_3 (and SDIO_CLK) I/O or the Bluetooth PCM I/O depending on the bootstrap state of GPIO_1 and GPIO_2. 

Table 18 shows the debug options of the device. 

**Table 18. Chip Debug Options** 

|**JTAG_SEL**|**GPIO_2**|**GPIO_1**|**Function**|**SDIO I/O Pad Function**|**BT PCM I/O Pad Function**|
|---|---|---|---|---|---|
|0|0|0|Normal mode|SDIO|BT PCM|
|0|0|1|JTAG over SDIO|JTAG|BT PCM|
|0|1|0|JTAG over BT PCM|SDIO|JTAG|
|0|1|1|SWD over GPIO_1/GPIO_2|SDIO|BT PCM|



Document Number: 002-30348 Rev. *D 

Page 52 of 87 

**CYW43439** 

## **12.7  I/O States** 

The following notations are used in Table 19: 

■ I: Input signal 

■ O: Output signal 

■ I/O: Input/Output signal 

■ PU = Pulled up 

■ PD = Pulled down 

■ NoPull = Neither pulled up nor pulled down 

## **Table 19. I/O States[[7]]** 

|**Name**<br>~~ee es~~|**I/O**<br>~~es~~|**Keeper[8]**<br>~~es~~|**Active Mode**<br>~~ee~~|**Low Power State/Sleep**<br>**(All Power Present)**|**Power-Down[9]**<br>**WL_REG_ON = 0**<br>**BT_REG_ON = 0**|**Out-of-Reset;**<br>**(WL_REG_ON = 1;**<br>**BT_REG_ON =**<br>**Do Not Care)**|**(WL_REG_ON**<br>**= 1**<br>**BT_REG_ON =**<br>**0) VDDIOs**<br>**Present**|**Out-of-Reset;**<br>**(WL_REG_ON = 0**<br>**BT_REG_ON = 1)**<br>**VDDIOs Present**|**Power Rail**|
|---|---|---|---|---|---|---|---|---|---|
|WL_REG_ON<br>~~ee es~~|I<br>~~es~~|N<br>~~es~~|Input; PD (pull-down<br>can be disabled)<br>~~ee~~|Input; PD (pull-down can<br>be disabled)|Input; PD (of 200K)|Input; PD (200k)|Input; PD<br>(200k)|–|–|
|BT_REG_ON<br>~~ee es~~<br>~~pA~~|I<br>~~es~~<br>~~pA~~|N<br>~~es ~~<br>~~poo~~|Input; PD (pull down<br>can be disabled)<br> ~~ee~~<br>~~poo~~|Input; PD (pull down can<br>be disabled)<br>~~poo~~|Input; PD (of 200K)<br>~~poo~~|Input; PD (200k)|Input; PD<br>(200k)|Input; PD (200k)|–|
|CLK_REQ<br>~~pA~~<br>~~ee ee~~|I/O<br>~~pA~~<br>~~ee~~|Y<br>~~poo~~<br>~~ee~~|Open drain or push-pull<br>(programmable). Active<br>high.<br>~~poo~~<br>~~ee~~|Open drain or push-pull<br>(programmable). Active<br>high<br>~~poo~~|PD<br>~~poo~~|Open drain, active<br>high.|Open drain,<br>active high.|Open drain,<br>active high.|WCC_VDDIO|
|BT_HOST_<br>WAKE<br>~~pA~~<br>~~ee ee~~<br>~~ee ee~~|I/O<br>~~pA ~~<br>~~ee~~<br>~~ee~~|Y<br> ~~poo~~<br>~~ee~~<br>~~ee~~|I/O; PU, PD, NoPull<br>(programmable)<br>~~poo~~<br>~~ee~~|I/O; PU, PD, NoPull<br>(programmable)<br>~~poo~~|High-Z, NoPull<br>~~poo~~|–|Input, PD|Output, Drive low|WCC_VDDIO|
|BT_DEV_WAKE<br>~~ee ee~~<br>~~ee ee~~|I/O<br>~~ee~~<br>~~ee~~|Y<br>~~ee~~<br>~~ee~~|I/O; PU, PD, NoPull<br>(programmable)<br>~~ee~~|Input; PU, PD, NoPull<br>(programmable)|High-Z, NoPull|–|Input, PD|Input, PD|WCC_VDDIO|
|BT_UART_CTS<br>~~ee ee~~<br>~~Po~~<br>~~re~~|I<br>~~ee~~<br>~~Po~~<br>~~Oe ee~~|Y<br>~~ee~~<br>~~Po~~<br>~~ee ns~~|Input; NoPull<br>~~Po~~<br>~~ns~~|Input; NoPull<br>~~Po~~<br>~~(OO~~|High-Z, NoPull<br>~~Po~~<br>~~(OO~~|–<br>~~Po~~<br>~~(OO~~|Input; PU<br>~~Po~~<br>~~(OO~~|Input, NoPull<br>~~Po~~<br>~~(OO~~|WCC_VDDIO<br>~~Po~~<br>~~(OO~~|
|BT_UART_RTS<br>~~Po~~<br>~~re~~<br>~~Po~~|O<br>~~Po~~<br>~~Oe ee~~|Y<br>~~Po~~<br>~~ee ns~~|Output; NoPull<br>~~Po~~<br>~~ns~~|Output; NoPull<br>~~Po~~<br>~~(OO~~|High-Z, NoPull<br>~~Po~~<br>~~(OO~~|–<br>~~Po~~<br>~~(OO~~|Input; PU<br>~~Po~~<br>~~(OO~~|Output, NoPull<br>~~Po~~<br>~~(OO~~|WCC_VDDIO<br>~~Po~~<br>~~(OO~~|
|BT_UART_RXD<br>~~re ~~<br>~~Po~~<br>~~Po~~|I<br> ~~Oe ee~~|Y<br>~~ee ns~~|Input; PU<br>~~ns~~|Input; NoPull<br>~~(OO~~|High-Z, NoPull<br>~~(OO~~|–<br>~~(OO~~|Input; PU<br>~~(OO~~|Input, NoPull<br>~~(OO~~|WCC_VDDIO<br>~~(OO~~|
|BT_UART_TXD<br>~~Po~~<br>~~Po~~<br>~~ee ee~~|O<br>~~ee~~|Y<br>~~ee~~|Output; NoPull<br>~~ee~~|Output; NoPull|High-Z, NoPull|–|Input; PU|Output, NoPull|WCC_VDDIO|
|SDIO_DATA_0<br>~~Po~~<br>~~ee ee~~<br>~~ee ee~~|I/O<br>~~ee~~<br>~~ee~~|N<br>~~ee~~<br>~~ee~~|SDIO MODE -> NoPull<br>~~ee~~<br>~~ee~~|SDIO MODE -> NoPull|SDIO MODE -><br>NoPull|SDIO MODE -> PU|SDIO MODE -><br>NoPull|Input; PU|WCC_VDDIO|
|SDIO_DATA_1<br>~~ee ee~~<br>~~ee ee~~<br>~~ee ee~~|I/O<br>~~ee~~<br>~~ee~~<br>~~ee~~|N<br>~~ee~~<br>~~ee~~<br>~~ee ee~~|SDIO MODE -> NoPull<br>~~ee~~<br>~~ee~~<br>~~ee~~|SDIO MODE -> NoPull|SDIO MODE -><br>NoPull|SDIO MODE -> PU|SDIO MODE -><br>NoPull|Input; PU|WCC_VDDIO|
|SDIO_DATA_2<br>~~ee ee~~<br>~~ee ee~~|I/O<br>~~ee~~<br>~~ee~~|N<br>~~ee ~~<br>~~ee ee~~|SDIO MODE -> NoPull<br> ~~ee~~<br>~~ee~~|SDIO MODE -> NoPull|SDIO MODE -><br>NoPull|SDIO MODE -> PU|SDIO MODE -><br>NoPull|Input; PU|WCC_VDDIO|



Document Number: 002-30348 Rev. *D 

Page 53 of 87 

**CYW43439** GeCYPRESS ~~mamma~~ 

## **Table 19. I/O States[[7]] (Cont.)** 

|**Name**|**I/O**|**Keeper[8]**|**Active Mode**|**Low Power State/Sleep**<br>**(All Power Present)**<br>~~es~~|**Power-Down[9]**<br>**WL_REG_ON = 0**<br>**BT_REG_ON = 0**<br>~~es~~|**Out-of-Reset;**<br>**(WL_REG_ON = 1;**<br>**BT_REG_ON =**<br>**Do Not Care)**|**(WL_REG_ON**<br>**= 1**<br>**BT_REG_ON =**<br>**0) VDDIOs**<br>**Present**|**Out-of-Reset;**<br>**(WL_REG_ON = 0**<br>**BT_REG_ON = 1)**<br>**VDDIOs Present**|**Power Rail**|
|---|---|---|---|---|---|---|---|---|---|
|SDIO_DATA_3<br>~~ee~~|I/O<br>~~ee~~|N<br>~~ee~~|SDIO MODE -> NoPull<br>~~ee~~|SDIO MODE -> NoPull<br>~~ee~~<br>~~es~~|SDIO MODE -><br>NoPull<br>~~ee~~<br>~~es~~|SDIO MODE -> PU<br>~~ee~~|SDIO MODE -><br>NoPull<br>~~ee~~|Input; PU<br>~~ee~~|WCC_VDDIO<br>~~ee~~|
|SDIO_CMD<br>~~ee~~<br>~~po~~<br>~~FO~~|I/O<br>~~ee~~<br>~~po~~<br>~~Oe~~|N<br>~~ee~~<br>~~po~~|SDIO MODE -> NoPull<br>~~ee~~<br>~~po~~<br>~~Ge~~|SDIO MODE -> NoPull<br>~~ee~~<br>~~es~~<br>~~po~~<br>~~Qe~~|SDIO MODE -><br>NoPull<br>~~ee~~<br>~~es~~<br>~~po~~<br>~~OGG~~|SDIO MODE -> PU<br>~~ee~~<br>~~po~~<br>~~OGG~~|SDIO MODE -><br>NoPull<br>~~ee~~<br>~~po~~<br>~~OGG~~|Input; PU<br>~~ee~~<br>~~po~~<br>~~OGG~~|WCC_VDDIO<br>~~ee~~<br>~~po~~<br>~~OGG~~|
|SDIO_CLK<br>~~po~~<br>~~FO~~|I<br>~~po~~<br>~~Oe~~|N<br>~~po~~|SDIO MODE -> NoPull<br>~~po~~<br>~~Ge~~|SDIO MODE -> NoPull<br>~~po~~<br>~~Qe~~|SDIO MODE -><br>NoPull<br>~~po~~<br>~~OGG~~|SDIO MODE -><br>NoPull<br>~~po~~<br>~~OGG~~|SDIO MODE -><br>NoPull<br>~~po~~<br>~~OGG~~|Input<br>~~po~~<br>~~OGG~~|WCC_VDDIO<br>~~po~~<br>~~OGG~~|
|BT_PCM_CLK<br>~~FO~~<br>~~a~~|I/O<br>~~Oe~~|Y|Input; NoPull[10]<br>~~Ge~~|Input; NoPull[10]<br>~~Qe ~~|High-Z, NoPull<br> ~~OGG~~|–<br>~~OGG~~|Input, PD<br>~~OGG~~|Input, PD<br>~~OGG~~|WCC_VDDIO<br>~~OGG~~|
|BT_PCM_IN<br>~~a~~<br>~~a CC~~|I/O<br>~~CC~~|Y<br>~~CC~~|Input; NoPull[10]<br>~~CC~~|Input; NoPull[10]<br>~~CC~~|High-Z, NoPull<br>~~CC~~|–<br>~~CC~~|Input, PD<br>~~CC~~|Input, PD<br>~~CC~~|WCC_VDDIO<br>~~CC~~|
|BT_PCM_OUT<br>~~a CC~~<br>~~a CC~~<br>~~Oe~~|I/O<br>~~CC~~<br>~~CC~~<br>~~Oe~~|Y<br>~~CC~~<br>~~CC~~<br>|Input; NoPull[10]<br>~~CC~~<br>~~CC~~<br>|Input; NoPull[10]<br>~~CC~~<br>~~CC~~<br>|High-Z, NoPull<br>~~CC~~<br>~~CC~~<br>~~CC~~<br>|–<br>~~CC~~<br>~~CC~~<br>~~CC~~<br>|Input, PD<br>~~CC~~<br>~~CC~~<br>~~CC~~<br>|Input, PD<br>~~CC~~<br>~~CC~~<br>|WCC_VDDIO<br>~~CC~~<br>~~CC~~<br>|
|BT_PCM_SYNC<br>~~a CC~~<br>~~a eC~~<br>~~Oe~~|I/O<br>~~CC~~<br>~~eC~~<br>~~Oe~~|Y<br>~~CC~~<br>~~eC~~<br>~~Qe~~|Input; NoPull[10]<br>~~CC~~<br>~~eC~~<br>~~GO~~|Input; NoPull[10]<br>~~CC~~<br>~~eC~~<br>~~GO~~|High-Z, NoPull<br>~~CC~~<br>~~eC~~<br>~~CC~~<br>|–<br>~~CC~~<br>~~eC~~<br>~~CC~~<br>|Input, PD<br>~~CC~~<br>~~eC~~<br>~~CC~~<br>|Input, PD<br>~~CC~~<br>~~eC~~<br>|WCC_VDDIO<br>~~CC~~<br>~~eC~~<br>|
|JTAG_SEL<br>~~Oe~~<br>~~FO~~<br>~~a~~|I<br>~~Oe~~<br>~~Oe~~|Y<br>~~Qe~~|PD<br>~~GO~~<br>~~Ge~~|PD<br>~~GOGO~~<br>~~Qe~~|High-Z, NoPull<br>~~CC~~<br>~~GO~~<br>~~OGG~~|Input, PD<br>~~CC~~<br>~~GO~~<br>~~OGG~~|PD<br>~~CC~~<br>~~GO~~<br>~~OGG~~|Input, PD<br>~~GO~~<br>~~OGG~~|WCC_VDDIO<br>~~GO~~<br>~~OGG~~|
|GPIO_0<br>~~Oe~~<br>~~FO~~<br>~~a~~|I/O<br>~~Oe~~<br>~~Oe~~|Y<br>~~Qe~~|TBD<br>~~GO~~<br>~~Ge~~|Active mode<br>~~GOGO~~<br>~~Qe~~|High-Z, NoPull[11]<br>~~CC~~<br>~~GO~~<br>~~OGG~~|Input, SDIO OOB Int,<br>NoPull<br>~~CC~~<br>~~GO~~<br>~~OGG~~|Active mode<br>~~CC~~<br>~~GO~~<br>~~OGG~~|Input, NoPull<br>~~GO~~<br>~~OGG~~|WCC_VDDIO<br>~~GO~~<br>~~OGG~~|
|GPIO_1<br><br>~~FO~~<br>~~a~~|I/O<br><br>~~Oe~~|Y<br>|TBD<br><br>~~Ge~~|Active mode<br>~~GO~~<br>~~Qe~~|High-Z, NoPull[11]<br>~~GO~~<br>~~OGG~~|Input, PD<br>~~GO~~<br>~~OGG~~|Active mode<br>~~GO~~<br>~~OGG~~|Input, Strap, PD<br>~~GO~~<br>~~OGG~~|WCC_VDDIO<br>~~GO~~<br>~~OGG~~|
|GPIO_2<br>~~a~~<br>~~pt~~|I/O<br>~~Oe~~<br>~~pt~~|Y<br>~~Pd~~|TBD<br>~~Ge~~<br>~~Pd~~|Active mode<br>~~Qe ~~<br>~~Pd~~|High-Z, NoPull[11]<br> ~~OGG~~<br>~~Pd~~|Input, GCI GPIO[7],<br>NoPull<br>~~OGG~~<br>~~Pd~~|Active mode<br>~~OGG~~<br>~~Pd~~|Input, Strap, NoPull <br>~~OGG~~<br>~~Pd~~|WCC_VDDIO<br>~~OGG~~<br>~~Pd~~|



9. In the Power-down state (xx_REG_ON = 0): High-Z; NoPull => The pad is disabled because power is not supplied. 

10. Depending on whether the PCM interface is enabled and the configuration is master or slave mode, it can be either an output or input. 

11. The GPIO pull states for the active and low-power states are hardware defaults. They can all be subsequently programmed as a pull-up or pull-down. 

Document Number: 002-30348 Rev. *D 

Page 54 of 87 

**CYW43439** 

## **13.  DC Characteristics** 

**Note:** Values in this data sheet are design goals and are subject to change based on the results of device characterization. 

## **13.1  Absolute Maximum Ratings** 

**Caution!** The absolute maximum ratings in Table 20 indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Excluding VBAT, operation at the absolute maximum conditions for extended periods can adversely affect long-term reliability of the device. 

**Table 20. Absolute Maximum Ratings** 

|**Rating**|**Symbol**|**Value**|**Unit**|
|---|---|---|---|
|DC supply for VBAT and PA driver supply|VBAT|–0.5 to +6.0[12]|V|
|DC supply voltage for digital I/O|VDDIO|–0.5 to 3.9|V|
|DC supply voltage for RF switch I/Os|VDDIO_RF|–0.5 to 3.9|V|
|DC input supply voltage for CLDO and LNLDO|–|–0.5 to 1.575|V|
|DC supply voltage for RF analog|VDDRF|–0.5 to 1.32|V|
|DC supply voltage for core|VDDC|–0.5 to 1.32|V|
|Maximum undershoot voltage for I/O[13]|Vundershoot|–0.5|V|
|Maximum overshoot voltage for I/O[13]|Vovershoot|VDDIO + 0.5|V|
|Maximum junction temperature|Tj|125|°C|



## **Notes** 

12. Continuous operation at 6.0V is supported. 

13. Duration not to exceed 25% of the duty cycle. 

## **13.2  Environmental Ratings** 

The environmental ratings are shown in Table 21. 

**Table 21. Environmental Ratings** 

|**Characteristic**|**Value**|**Units**|**Conditions/Comments**|
|---|---|---|---|
|Ambient temperature (TA)|–30 to +70°C[14]|C|Operation|
|Storage temperature|–40 to +125°C|C|–|
|Relative humidity|Less than 60|%|Storage|
||Less than 85|%|Operation|



## **Note** 

14. Functionality is guaranteed, but specifications require derating at extreme temperatures (see the specification tables for details). 

## **13.3  Electrostatic Discharge Specifications** 

Extreme caution must be exercised to prevent electrostatic discharge (ESD) damage. Proper use of wrist and heel grounding straps to discharge static electricity is required when handling these devices. Always store unused material in its antistatic packaging. 

**Table 22. ESD Specifications** 

|**Pin Type**|**Symbol**|**Condition**|**ESD Rating**|**Unit**|
|---|---|---|---|---|
|ESD, Handling Reference:<br>NQY00083, Section 3.4,<br>Group D9, Table B|ESD_HAND_HBM|Human Body Model Contact Discharge per<br>JEDEC EID/JESD22-A114|1000|V|
|Machine Model (MM)|ESD_HAND_MM|Machine Model Contact|30|V|
|CDM|ESD_HAND_CDM|Charged Device Model Contact Discharge per<br>JEDEC EIA/JESD22-C101|300|V|



Document Number: 002-30348 Rev. *D 

Page 55 of 87 

**CYW43439** 

## **13.4  Recommended Operating Conditions and DC Characteristics** 

Functional operation is not guaranteed outside the limits shown in Table 23, and operation outside these limits for extended periods can adversely affect long-term reliability of the device. 

## **Table 23. Recommended Operating Conditions and DC Characteristics** 

|**Element**<br>~~a~~|**Symbol**<br>~~a~~<br>~~ee eee~~|**Value**<br>~~LP~~<br>~~a~~<br>~~eee~~|**Value**<br>~~LP~~<br>~~a~~<br>~~eee~~|**Value**<br>~~LP~~<br>~~a~~<br>~~eee~~|**Unit**<br>~~a~~<br>~~eee~~|
|---|---|---|---|---|---|
|||**Minimum**<br>~~LP~~<br>~~a~~<br>~~eee~~|**Typical**<br>~~LP~~<br>~~a~~<br>~~eee~~|**Maximum**<br>~~LP~~<br>~~a~~<br>~~eee~~||
|DC supply voltage for VBAT<br>~~a~~|VBAT<br>~~ee eee~~<br>~~a~~|3.0[15]<br>~~eee~~<br>~~a~~|–<br>~~eee~~<br>~~a~~|4.8[16]<br>~~eee~~<br>~~a~~|V<br>~~eee~~<br>~~a~~|
|DC supply voltage for core<br>~~a~~<br>~~a~~|VDD<br>~~a~~<br>~~a~~|1.14<br>~~a~~<br>~~a~~|1.2<br>~~a~~<br>~~a~~|1.26<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~|
|DC supply voltage for RF blocks in chip<br>~~a~~|VDDRF<br>~~a~~<br>~~ee~~|1.14<br>~~a~~|1.2<br>~~a~~|1.26<br>~~a~~|V<br>~~a~~|
|DC supply voltage for digital I/O<br>~~a~~<br>~~ee~~|VDDIO,<br>VDDIO_SD<br>~~a~~<br>~~ee~~<br>~~ee~~|1.71<br>~~a~~<br>~~ee~~|–<br>~~a~~<br>~~ee~~|3.63<br>~~a~~<br>~~ee~~|V<br>~~a~~<br>~~ee~~|
|DC supply voltage for RF switch I/Os<br>~~ee~~<br>~~a~~|VDDIO_RF<br>~~ee~~<br>~~ee~~<br>~~a~~|3.13<br>~~ee~~<br>~~a~~|3.3<br>~~ee~~<br>~~a~~|3.46<br>~~ee~~<br>~~a~~|V<br>~~ee~~<br>~~a~~|
|External TSSI input<br>~~a~~|TSSI<br>~~a~~|0.15<br>~~a~~|–<br>~~a~~|0.95<br>~~a~~|V<br>~~a~~|
|Internal POR threshold<br>~~a~~<br>~~ee~~|Vth_POR<br>~~a~~<br>~~ee~~|0.4<br>~~a~~<br>~~ee~~|–<br>~~a~~<br>~~ee~~|0.7<br>~~a~~<br>~~ee~~|V<br>~~a~~<br>~~ee~~|
|**SDIO Interface I/O Pins**<br>~~a~~||||||
|**For VDDIO_SD = 1.8V:**<br>~~a~~<br>~~OO~~||||||
|Input high voltage<br>~~a~~|VIH<br>~~a~~|1.27<br>~~a~~|–<br>~~a~~|–<br>~~a~~|V<br>~~a~~|
|Input low voltage<br>~~a~~<br>~~a~~|VIL<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|0.58<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~|
|Output high voltage @ 2 mA<br>~~a~~|VOH<br>~~a~~|1.40<br>~~a~~|–<br>~~a~~|–<br>~~a~~|V<br>~~a~~|
|Output low voltage @ 2 mA<br>~~a~~<br>~~a~~<br>~~OO~~|VOL<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|0.45<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~|
|**For VDDIO_SD = 3.3V:**<br>~~OO~~||||||
|Input high voltage<br>~~OO~~<br>~~a~~|VIH<br>~~a~~|0.625 × VDDIO<br>~~a~~|–<br>~~a~~|–<br>~~a~~|V<br>~~a~~|
|Input low voltage<br>~~ee~~|VIL<br>~~ee~~|–<br>~~ee~~|–<br>~~ee~~|0.25 ×<br>VDDIO<br>~~ee~~|V<br>~~ee~~|
|Output high voltage @ 2 mA<br>~~a~~|VOH<br>~~a~~<br>~~ee~~|0.75 × VDDIO<br>~~a~~<br>~~ee~~|–<br>~~a~~<br>~~ee~~|–<br>~~a~~|V<br>~~a~~|
|Output low voltage @ 2 mA<br>~~ee~~|VOL<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|0.125 ×<br>VDDIO<br>~~ee~~|V<br>~~ee~~|
|**Other Digital I/O Pins**<br>~~ee ee ee~~<br>~~a~~||||||
|**For VDDIO = 1.8V:**<br>~~a~~<br>~~OO~~||||||
|Input high voltage<br>~~a~~|VIH<br>~~a~~<br>~~ee~~|0.65 × VDDIO<br>~~a~~|–<br>~~a~~|–<br>~~a~~|V<br>~~a~~|
|Input low voltage<br>~~a~~<br>~~ee~~|VIL<br>~~a~~<br>~~ee~~<br>~~ee~~|–<br>~~a~~<br>~~ee~~|–<br>~~a~~<br>~~ee~~|0.35 ×<br>VDDIO<br>~~a~~<br>~~ee~~|V<br>~~a~~<br>~~ee~~|
|Output high voltage @ 2 mA<br>~~ee~~<br>~~a~~|VOH<br>~~ee~~<br>~~ee~~<br>~~a~~|VDDIO – 0.45<br>~~ee~~<br>~~a~~|–<br>~~ee~~<br>~~a~~|–<br>~~ee~~<br>~~a~~|V<br>~~ee~~<br>~~a~~|
|Output low voltage @ 2 mA<br>~~a~~|VOL<br>~~a~~|–<br>~~a~~|–<br>~~a~~|0.45<br>~~a~~|V<br>~~a~~|
|**For VDDIO = 3.3V:**<br>~~a~~<br>~~OO~~||||||
|Input high voltage<br>~~a~~|VIH<br>~~a~~|2.00<br>~~a~~|–<br>~~a~~|–<br>~~a~~|V<br>~~a~~|
|Input low voltage<br>~~a~~<br>~~a~~|VIL<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|0.80<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~|
|Output high voltage @ 2 mA<br>~~a~~|VOH<br>~~a~~|VDDIO – 0.4<br>~~a~~|–<br>~~a~~|–<br>~~a~~|V<br>~~a~~|
|Output low Voltage @ 2 mA<br>~~a~~<br>~~a~~|VOL<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|0.40<br>~~a~~<br>~~a~~|V<br>~~a~~<br>~~a~~|



Document Number: 002-30348 Rev. *D 

Page 56 of 87 

**CYW43439** 

**Table 23. Recommended Operating Conditions and DC Characteristics (Cont.)** 

|**Element**|**Symbol**|**Value**|**Value**|**Value**|**Unit**|
|---|---|---|---|---|---|
|||**Minimum**|**Typical**|**Maximum**||
|**RF Switch Control Output Pins[17]**||||||
|For VDDIO_RF = 3.3V:||||||
|Output high voltage @ 2 mA|VOH|VDDIO – 0.4|–|–|V|
|Output low voltage @ 2 mA|VOL|–|–|0.40|V|
|Input capacitance|CIN|–|–|5|pF|



## **Notes** 

15. The CYW43439 is functional across this range of voltages. However, optimal RF performance specified in the data sheet is guaranteed only for 3.2V < VBAT < 4.8V. 

16. The maximum continuous voltage is 4.8V. Voltages up to 6.0V for up to 10 seconds, cumulative duration over the lifetime of the device are allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration over the lifetime of the device are allowed. 

17. Programmable 2 mA to 16 mA drive strength. Default is 10 mA. 

Document Number: 002-30348 Rev. *D 

Page 57 of 87 

**CYW43439** 

## **14.  WLAN RF Specifications** 

The CYW43439 includes an integrated direct conversion radio that supports the 2.4 GHz band. This section describes the RF characteristics of the 2.4 GHz radio. 

**Note:** Values in this data sheet are design goals and may change based on device characterization results. 

Unless otherwise stated, the specifications in this section apply when the operating conditions are within the limits specified in Table 21: “Environmental Ratings”  and Table 23: “Recommended Operating Conditions and DC Characteristics” . Functional operation outside these limits is not guaranteed. 

Typical values apply for the following conditions: 

■ VBAT = 3.6V. 

■ Ambient temperature +25°C. 

**Figure 28. RF Port Location** 

**==> picture [277 x 126] intentionally omitted <==**

**----- Start of picture text -----**<br>
Chip<br>C2<br>Port<br>TX Filter<br>— |<br>CYW43439 10 pF Antenna<br>C1 Port<br>L1<br>RX<br>4.7 nH<br>10 pF<br>**----- End of picture text -----**<br>


**Note:** All specifications apply at the chip port unless otherwise specified. 

## **14.1  2.4 GHz Band General RF Specifications** 

**Table 24. 2.4 GHz Band General RF Specifications** 

|**Item**|**Condition**|**Minimum**|**Typical**|**Maximum**|**Unit**|
|---|---|---|---|---|---|
|TX/RX switch time|Including TX ramp down|–|–|5|µs|
|RX/TX switch time|Including TX ramp up|–|–|2|µs|



Document Number: 002-30348 Rev. *D 

Page 58 of 87 

**CYW43439** 

## **14.2  WLAN 2.4 GHz Receiver Performance Specifications** 

**Note:** Unless otherwise specified, the specifications in Table 25 are measured at the chip port (for the location of the chip port, see Figure 28 

**Table 25. WLAN 2.4 GHz Receiver Performance Specifications** 

|**Parameter**<br>~~es~~|**Condition/Notes**<br>~~es~~|**Minimum**<br>~~es~~|**Typical**<br>~~es~~|**Maximum**<br>~~es~~|**Unit**<br>~~es~~|
|---|---|---|---|---|---|
|Frequency range<br>~~a~~|–|2400|–|2500|MHz|
|RX sensitivity (8% PER for 1024<br>octet PSDU)[18]<br>~~a~~|1 Mbps DSSS<br>~~a~~|–97.5|–99.5|–|dBm|
||2 Mbps DSSS<br>~~a~~|–93.5|–95.5|–|dBm|
||5.5 Mbps DSSS<br>~~a~~<br>~~a~~|–91.5|–93.5|–|dBm|
||11 Mbps DSSS<br>~~a~~|–88.5|–90.5|–|dBm|
|RX sensitivity (10% PER for<br>1000 octet PSDU) at WLAN RF<br>port[18]|6 Mbps OFDM<br>~~a~~<br>~~a~~|–91.5|–93.5|–|dBm|
||9 Mbps OFDM<br>~~a~~|–90.5|–92.5|–|dBm|
||12 Mbps OFDM<br>~~a~~<br>~~a~~|–87.5|–89.5|–|dBm|
||18 Mbps OFDM<br>~~a~~|–85.5|–87.5|–|dBm|
||24 Mbps OFDM<br>~~a~~<br>~~a~~|–82.5|–84.5|–|dBm|
||36 Mbps OFDM<br>~~a~~|–80.5|–82.5|–|dBm|
||48 Mbps OFDM<br>~~a~~<br>~~a~~|–76.5|–78.5|–|dBm|
||54 Mbps OFDM<br>~~a~~|–75.5|–77.5|–|dBm|
|RX sensitivity<br>(10% PER for 4096 octet PSDU).<br>Defined for default parameters:<br>Mixed mode, 800 ns GI.|**20 MHz channel spacing for all MCS rates (Mixed mode)**<br>~~a~~<br>~~TT~~|||||
||MCS7<br>~~a~~|–71.5<br>~~a~~|–73.5<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
||MCS6<br>~~a~~<br>~~a~~|–73.5<br>~~a~~<br>~~a~~|–75.5<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|dBm<br>~~a~~<br>~~a~~|
||MCS5<br>~~a~~|–74.5<br>~~a~~|–76.5<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
||MCS4<br>~~a~~<br>~~a~~|–79.5<br>~~a~~<br>~~a~~|–81.5<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|dBm<br>~~a~~<br>~~a~~|
||MCS3<br>~~a~~|–82.5<br>~~a~~|–84.5<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
||MCS2<br>~~a~~<br>~~a~~|–84.5<br>~~a~~<br>~~a~~|–86.5<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|dBm<br>~~a~~<br>~~a~~|
||MCS1<br>~~a~~|–86.5<br>~~a~~|–88.5<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
||MCS0<br>~~a~~<br>~~a~~|–90.5<br>~~a~~<br>~~a~~|–92.5<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|dBm<br>~~a~~<br>~~a~~|



## **Notes** 

18. Optimal RF performance, as specified in this data sheet, is guaranteed only for temperatures between –10°C and 55°C. 

19. The cellular standard listed for each band indicates the type of modulation used to generate the interfering signal in that band for the purpose of this test. It is not intended to indicate any specific usage of each band in any specific country. 

20. For 65 Mbps, the size is 4096. 

21. The minimum and maximum values shown have a 95% confidence level. 

Document Number: 002-30348 Rev. *D 

Page 59 of 87 

**CYW43439** 

**Table 25. WLAN 2.4 GHz Receiver Performance Specifications  (Cont.)** 

|**Parameter**<br>~~es~~<br>~~po~~|**Condition/Notes**<br>~~es~~<br>~~po~~|**Condition/Notes**<br>~~es~~<br>~~po~~|**Minimum**<br>~~es~~|**Typical**<br>~~es~~|**Maximum**<br>~~es~~|**Unit**<br>~~es~~|
|---|---|---|---|---|---|---|
|Blocking level for 3 dB RX sensi-<br>tivity degradation (without<br>external filtering).[19]<br>~~es~~<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~|704–716 MHz<br>~~es~~<br>~~po~~|LTE<br>~~es~~|–<br>~~es~~|–38.5<br>~~es~~|–<br>~~es~~|dBm<br>~~es~~|
||777–787 MHz<br>~~po~~<br>~~a~~<br>~~po~~|LTE|–|–19.5|–|dBm|
||776–794 MHz<br>~~a~~<br>~~po~~|CDMA2000|–|–19.5|–|dBm|
||815–830 MHz<br>~~po~~<br>~~a~~<br>~~po~~|LTE|–|–29.5|–|dBm|
||816–824 MHz<br>~~a~~<br>~~po~~|CDMA2000|–|–30.5|–|dBm|
||816–849 MHz<br>~~po~~<br>~~a~~<br>~~po~~|LTE|–|–19.0|–|dBm|
||824–849 MHz<br>~~a~~<br>~~po~~|WCDMA|–|–18.5|–|dBm|
||824–849 MHz<br>~~po~~<br>~~a~~<br>~~po~~|CDMA2000|–|–17.5|–|dBm|
||824–849 MHz<br>~~a~~<br>~~po~~|LTE|–|–19.0|–|dBm|
||824–849 MHz<br>~~po~~<br>~~a~~<br>~~po~~|GSM850|–|–19.0|–|dBm|
||830–845 MHz<br>~~a~~<br>~~po~~|LTE|–|–19.0|–|dBm|
||832–862 MHz<br>~~po~~<br>~~a~~<br>~~po~~|LTE|–|–19.0|–|dBm|
||880–915 MHz<br>~~a~~<br>~~po~~|WCDMA|–|–17.5|–|dBm|
||880–915 MHz<br>~~po~~<br>~~a~~<br>~~po~~|LTE|–|–17.5|–|dBm|
||880–915 MHz<br>~~a~~<br>~~po~~|E-GSM|–|–17.5|–|dBm|
||1710–1755 MHz<br>~~po~~<br>~~a~~<br>~~po~~|WCDMA|–|–21.5|–|dBm|
||1710–1755 MHz<br>~~a~~<br>~~po~~|LTE|–|–22.5|–|dBm|
||1710–1755 MHz<br>~~po~~<br>~~a~~<br>~~po~~|CDMA2000|–|–22.0|–|dBm|
||1710–1785 MHz<br>~~a~~<br>~~po~~|WCDMA|–|–21.5|–|dBm|
||1710–1785 MHz<br>~~po~~<br>~~a~~<br>~~po~~|LTE|–|–22.5|–|dBm|
||1710–1785 MHz<br>~~a~~<br>~~po~~|GSM1800|–|–21.0|–|dBm|
||1850–1910 MHz<br>~~po~~<br>~~a~~<br>~~po~~|GSM1900|–|–20.0|–|dBm|
||1850–1910 MHz<br>~~a~~<br>~~po~~|CDMA2000|–|–21.0|–|dBm|
||1850–1910 MHz<br>~~po~~<br>~~a~~<br>~~po~~|WCDMA|–|–20.5|–|dBm|
||1850–1910 MHz<br>~~a~~<br>~~po~~|LTE|–|–21.5|–|dBm|
||1850–1915 MHz<br>~~po~~<br>~~a~~<br>~~po~~|LTE|–|–21.5|–|dBm|
||1920–1980 MHz<br>~~a~~<br>~~po~~|WCDMA|–|–20.5|–|dBm|
||1920–1980 MHz<br>~~po~~<br>~~a~~<br>~~po~~|CDMA2000|–|–21.0|–|dBm|
||1920–1980 MHz<br>~~a~~<br>~~po~~|LTE|–|–21.0|–|dBm|
||2300–2400 MHz<br>~~po~~<br>~~a~~<br>~~po~~|LTE|–|–26.0|–|dBm|
||2500–2570 MHz<br>~~a~~<br>~~po~~|LTE|–|–20.5|–|dBm|
||2570–2620 MHz<br>~~po~~<br>~~a~~<br>~~po~~|LTE|–|–22.5|–|dBm|
||5G<br>~~a~~<br>~~po~~|WLAN|–|>–4|–|dBm|
|Maximum receive level<br>@ 2.4 GHz<br>~~po~~|@ 1, 2 Mbps (8% PER, 1024 octets)<br>~~po~~<br>~~a~~||–6|–|–|dBm|
||@ 5.5, 11 Mbps (8% PER, 1024 octets)<br>~~a~~<br>~~po~~||–12<br>~~po~~|–<br>~~po~~|–<br>~~po~~|dBm<br>~~po~~|
||@ 6–54 Mbps (10% PER, 1000 octets)<br>~~a~~||–15.5|–|–|dBm|



## **Notes** 

18. Optimal RF performance, as specified in this data sheet, is guaranteed only for temperatures between –10°C and 55°C. 

19. The cellular standard listed for each band indicates the type of modulation used to generate the interfering signal in that band for the purpose of this test. It is not intended to indicate any specific usage of each band in any specific country. 

20. For 65 Mbps, the size is 4096. 

21. The minimum and maximum values shown have a 95% confidence level. 

Document Number: 002-30348 Rev. *D 

Page 60 of 87 

**CYW43439** 

**Table 25. WLAN 2.4 GHz Receiver Performance Specifications  (Cont.)** 

|**Parameter**|**Condition/Notes**|**Condition/Notes**|**Minimum**|**Typical**|**Maximum**|**Unit**|
|---|---|---|---|---|---|---|
|Adjacent channel rejection-<br>DSSS.<br>(Difference between interfering<br>and desired signal [25 MHz<br>apart] at 8% PER for 1024 octet<br>PSDU with desired signal level<br>as specified in Condition/Notes.)|11 Mbps DSSS<br>~~ee~~|–70 dBm|35|39|–|dB|
|Adjacent channel rejection-<br>OFDM.<br>(Difference between interfering<br>and desired signal (25 MHz<br>apart) at 10% PER for 1000[20]<br>octet PSDU with desired signal<br>level as specified in Condition/<br>Notes.)<br>~~po~~<br>~~po~~<br>~~po~~<br>~~po~~<br>~~—————————EE~~|6 Mbps OFDM<br>~~ee~~<br>~~po~~|–79 dBm|16|37|–|dB|
||9 Mbps OFDM<br>~~ee~~<br>~~po~~|–78 dBm|15|36.5|–|dB|
||12 Mbps OFDM<br>~~po~~<br>~~a~~<br>~~po~~|–76 dBm|13|34|–|dB|
||18 Mbps OFDM<br>~~a~~<br>~~po~~|–74 dBm|11|32|–|dB|
||24 Mbps OFDM<br>~~po~~<br>~~a~~<br>~~po~~|–71 dBm|8|29.5|–|dB|
||36 Mbps OFDM<br>~~a~~<br>~~po~~|–67 dBm|4|26|–|dB|
||48 Mbps OFDM<br>~~po~~<br>~~a~~<br>~~po~~|–63 dBm<br>|0<br>|23.5<br>|–<br>|dB<br>|
||54 Mbps OFDM<br>~~a~~<br>~~po~~|–62 dBm<br>|–1<br>|22<br>|–<br>|dB<br>|
||65 Mbps OFDM<br>~~popo~~<br>~~—————————EE~~|–61 dBm<br>~~po~~<br>~~—————————EE~~|–2<br>~~po~~<br>~~—————————EE~~|15.5<br>~~po~~<br>~~—————————EE~~|–<br>~~po~~<br>~~—————————EE~~|dB<br>~~po~~<br>~~—————————EE~~|
|RCPI accuracy[21]<br><br>~~—————————EE~~|Range –98 dBm to –75 dBm<br>~~po~~<br>~~—————————EE~~||–3<br>~~po~~<br>~~—————————EE~~|–<br>~~po~~<br>~~—————————EE~~|3<br>~~po~~<br>~~—————————EE~~|dB<br>~~po~~<br>~~—————————EE~~|
||Range above –75 dBm<br>~~—————————EE~~<br>~~po~~||–5<br>~~—————————EE~~<br>~~po~~|–<br>~~—————————EE~~<br>~~po~~|5<br>~~—————————EE~~<br>~~po~~|dB<br>~~—————————EE~~<br>~~po~~|
|Return loss<br>~~—————————EE~~<br>~~a~~|Zo = 50Ω across the dynamic range.<br>~~—————————EE~~<br>~~po~~||10<br>~~—————————EE~~<br>~~po~~|–<br>~~—————————EE~~<br>~~po~~|–<br>~~—————————EE~~<br>~~po~~|dB<br>~~—————————EE~~<br>~~po~~|



**Notes** 

18. Optimal RF performance, as specified in this data sheet, is guaranteed only for temperatures between –10°C and 55°C. 

19. The cellular standard listed for each band indicates the type of modulation used to generate the interfering signal in that band for the purpose of this test. It is not intended to indicate any specific usage of each band in any specific country. 

20. For 65 Mbps, the size is 4096. 

21. The minimum and maximum values shown have a 95% confidence level. 

Document Number: 002-30348 Rev. *D 

Page 61 of 87 

**CYW43439** 

## **14.3  WLAN 2.4 GHz Transmitter Performance Specifications** 

**Note:** Unless otherwise specified, the specifications in Table 25 are measured at the chip port (for the location of the chip port, see Figure 28). **Table 26. WLAN 2.4 GHz Transmitter Performance Specifications** 

|**Parameter**<br>~~a~~|**Condition/Notes**|**Condition/Notes**|**Minimum**|**Typical**|**Maximum**|**Unit**|
|---|---|---|---|---|---|---|
|Frequency range<br>~~eC~~<br>~~ee~~|–<br>~~eC~~<br>~~ee~~||–<br>~~eC~~|–<br>~~eC~~|–<br>~~eC~~|MHz<br>~~eC~~|
|Transmitted power in cellular and<br>WLAN 5G bands (at 21 dBm, 90% duty<br>cycle, 1 Mbps CCK).[22]<br>~~eC~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|776–794 MHz<br>~~eC~~<br>~~ee~~<br>~~ee~~|CDMA2000<br>~~eC~~|–<br>~~eC~~|–167.5<br>~~eC~~|–<br>~~eC~~|dBm/Hz<br>~~eC~~|
||869–960 MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~|CDMAOne, GSM850|–|–163.5|–|dBm/Hz|
||1450–1495 MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~|DAB|–|–154.5|–|dBm/Hz|
||1570–1580 MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~|GPS|–|–152.5|–|dBm/Hz|
||1592–1610 MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~|GLONASS|–|–149.5|–|dBm/Hz|
||1710–1800 MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~|DSC-1800-Uplink|–|–145.5|–|dBm/Hz|
||1805–1880 MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~|GSM1800|–|–143.5|–|dBm/Hz|
||1850–1910 MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~|GSM1900|–|–140.5|–|dBm/Hz|
||1910–1930 MHz<br>~~ee~~<br>~~ee~~<br>~~a~~|TDSCDMA, LTE<br>~~ee~~|–<br>~~ee ee~~|–138.5<br>~~ee~~|–<br>~~ee~~|dBm/Hz<br>~~ee~~|
||1930–1990 MHz<br>~~ee~~<br>~~a~~<br>~~ee~~|GSM1900, CDMAOne,<br>WCDMA<br>~~ee~~|–<br>~~ee ee~~|–139<br>~~ee~~|–<br>~~ee~~|dBm/Hz<br>~~ee~~|
||2010–2075 MHz<br>~~a~~<br>~~ee~~<br>~~ee~~|TDSCDMA<br>~~ee ~~|–<br> ~~ee ee~~|–127.5<br>~~ee~~|–<br>~~ee ~~|dBm/Hz<br> ~~ee~~|
||2110–2170 MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~|WCDMA|–|–124.5|–|dBm/Hz|
||2305–2370 MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~|LTE Band 40|–|–104.5|–|dBm/Hz|
||2370–2400 MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~|LTE Band 40|–|–81.5|–|dBm/Hz|
||2496–2530 MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~|LTE Band 41|–|–94.5|–|dBm/Hz|
||2530–2560 MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~|LTE Band 41|–|–120.5|–|dBm/Hz|
||2570–2690 MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~|LTE Band 41|–|–121.5|–|dBm/Hz|
||5000–5900 MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~|WLAN 5G|–|–109.5|–|–|
|Harmonic level (at 21 dBm with 90%<br>duty cycle, 1 Mbps CCK)<br>~~ee~~<br>~~ee~~<br>~~ee~~|4.8–5.0 GHz<br>~~ee~~<br>~~ee~~<br>~~ee~~|2nd harmonic|–|–26.5|–|dBm/ MHz|
||7.2–7.5 GHz<br>~~ee~~<br>~~ee~~<br>~~ee~~|3rd harmonic|–|–23.5|–|dBm/ MHz|
||9.6–10 GHz<br>~~ee~~<br>~~ee~~|4th harmonic|–|–32.5|–|dBm/ MHz|
|**EVM Does Not Exceed**<br>~~ee~~<br>~~a~~<br>~~ee~~<br>~~eeeeee~~<br>~~ee~~|||||||
|TX power at the chip port for the<br>highest power level setting at 25°C,<br>VBA = 3.6V, and spectral mask and<br>EVM compliance[23], [24]<br>~~ee~~<br>~~ee~~<br>~~ee~~|IEEE 802.11b<br>(DSSS/CCK)<br>~~a~~<br>~~ee~~|–9 dB<br>~~a~~<br>~~ee~~|21<br>~~a~~<br>~~ee~~|–<br>~~a~~<br>~~ee~~|–<br>~~a~~<br>~~ee~~|dBm<br>~~a~~<br>~~ee~~|
||OFDM, BPSK<br>~~ee~~<br>~~ee~~|–8 dB<br>~~ee~~|20.5<br>~~ee~~|–<br>~~ee~~|–<br>~~ee~~|dBm<br>~~ee~~|
||OFDM, QPSK<br>~~ee~~<br>~~ee~~<br>~~ee~~|–13 dB<br>~~ee~~|20.5<br>~~ee~~|–<br>~~ee ~~|–<br> ~~ee ~~|dBm<br> ~~ee~~|
||OFDM, 16-QAM<br>~~ee~~<br>~~ee~~<br>~~a~~|–19 dB<br>~~ee~~|20.5<br>~~ee~~|–<br>~~ee~~|–<br>~~ee~~|dBm<br>~~ee~~|
||OFDM, 64-QAM<br>(R = 3/4)<br>~~ee~~<br>~~a~~<br>~~a~~|–25 dB<br>~~ee~~<br>~~ee~~|18<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~eee~~|dBm<br>~~ee~~<br>~~eee~~|
||OFDM, 64-QAM<br>(R = 5/6)<br>~~a~~<br>~~a~~|–27 dB<br>~~ee ~~<br>~~ee~~|17.5<br> ~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~eee~~|dBm<br>~~ee~~<br>~~eee~~|



## **Notes** 

22. The cellular standards listed indicate only typical usages of that band in some countries. Other standards may also be used within those bands. 

23. TX power for channel 1 and channel 11 is specified separately by nonvolatile memory parameters to ensure band-edge compliance. 

24. Optimal RF performance, as specified in this data sheet, is guaranteed only for temperatures between –10°C and 55°C. 

Document Number: 002-30348 Rev. *D 

Page 62 of 87 

**CYW43439** 

**Table 26. WLAN 2.4 GHz Transmitter Performance Specifications  (Cont.)** 

|**Parameter**<br>~~ae~~|**Condition/Notes**<br>~~ee~~|**Condition/Notes**<br>~~ee~~|**Minimum**<br>~~ee~~|**Typical**<br>~~ee~~|**Maximum**|**Unit**|
|---|---|---|---|---|---|---|
|TX power control<br>dynamic range<br>~~ae ~~<br>~~**a**~~|–<br> ~~ee ~~<br>~~ee~~||9<br> ~~ee~~<br>|–<br>~~ee~~<br>~~ee~~|–<br>~~ee~~|dB<br>~~ee~~|
|Closed loop TX power variation at<br>highest power level setting<br>~~**a**~~|Across full temperature and voltage range.<br>Applies across 5 to 21 dBm output power<br>range.<br>~~ee~~||–<br>|–<br>~~ee~~|±1.5<br>~~ee~~|dB<br>~~ee~~|
|Carrier suppression<br>~~**a**~~|–<br>~~ee ~~||15<br>|–<br> ~~ee~~|–<br>~~ee~~|dBc<br>~~ee~~|
|Gain control step<br>~~a~~|–||–|0.25|–|dB|
|Return loss<br>~~a~~<br>~~a~~<br>~~oe~~|Zo = 50<br>~~a~~||4|6|–|dB|
|Load pull variation for output power,<br>EVM, and Adjacent Channel Power<br>Ratio (ACPR)<br>~~oe~~|VSWR = 2:1.<br>~~oo~~|EVM degradation<br>~~a~~|–|3.5|–|dB|
|||Output power variation<br>~~a~~<br>~~oo~~|–<br>~~oo~~|±2<br>~~oo~~|–<br>~~oo~~|dB<br>~~oo~~|
|||ACPR-compliant power<br>level<br>~~a~~<br>~~oo~~|–<br>~~oo~~|15<br>~~oo~~|–<br>~~oo~~|dBm<br>~~oo~~|
||VSWR = 3:1.<br>~~oo~~|EVM degradation<br>~~a~~<br>~~oo~~<br>~~a~~|–<br>~~oo~~<br>~~a~~|4<br>~~oo~~<br>~~a~~|–<br>~~oo~~<br>~~a~~|dB<br>~~oo~~<br>~~a~~|
|||Output power variation<br>~~a~~|–|±3|–|dB|
|||ACPR-compliant power<br>level<br>~~a~~<br>~~eo~~|–<br>~~eo~~|15<br>~~eo~~|–<br>~~eo~~|dBm<br>~~eo~~|



**Notes** 22. The cellular standards listed indicate only typical usages of that band in some countries. Other standards may also be used within those bands. 23. TX power for channel 1 and channel 11 is specified separately by nonvolatile memory parameters to ensure band-edge compliance. 

24. Optimal RF performance, as specified in this data sheet, is guaranteed only for temperatures between –10°C and 55°C. 

## **14.4  General Spurious Emissions Specifications** 

**Table 27. General Spurious Emissions Specifications** 

|**Parameter**<br>~~a~~|**Condition/Notes**|**Condition/Notes**|**Minimum**|**Typical**|**Maximum**|**Unit**|
|---|---|---|---|---|---|---|
|Frequency range<br>~~a~~|–||2400|–|2500|MHz|
|**General Spurious Emissions**<br>~~Oe~~<br>~~eeeee~~|||||||
|TX emissions<br>~~eee~~|30 MHz < f < 1 GHz<br>~~a~~<br>~~eee~~|RBW = 100 kHz<br>~~a~~<br>~~eee~~|–<br>~~a~~<br>~~eee~~|–99<br>~~a~~<br>~~ee~~|–96<br>~~a~~<br>~~ee~~|dBm<br>~~a~~<br>~~ee~~|
||1 GHz < f < 12.75 GHz<br>~~a~~<br>~~eee~~|RBW = 1 MHz<br>~~a~~<br>~~eee~~|–<br>~~a~~<br>~~eee~~|–44<br>~~a~~<br>~~ee~~|–41<br>~~a~~<br>~~ee~~|dBm<br>~~a~~<br>~~ee~~|
||1.8 GHz < f < 1.9 GHz<br>~~eee~~|RBW = 1 MHz<br>~~eee~~|–<br>~~eee~~|–68<br>~~ee~~|–65<br>~~ee~~|dBm<br>~~ee~~|
||5.15 GHz < f < 5.3 GHz<br>~~eee~~<br>~~a~~|RBW = 1 MHz<br>~~eee~~|–<br>~~eee~~|–88<br>~~ee~~|–85<br>~~ee~~|dBm<br>~~ee~~|
|RX/standby<br>emissions<br>~~eee~~<br>~~SSeS~~|30 MHz < f < 1 GHz<br>~~eee~~<br>~~a~~<br>~~a~~<br>~~SSeS~~|RBW = 100 kHz<br>~~eee~~<br>~~SSeS~~|–<br>~~eee ~~<br>~~SSeS~~|–99<br> ~~ee~~<br>~~SSeS~~|–96<br>~~ee~~<br>~~SSeS~~|dBm<br>~~ee~~<br>~~SSeS~~|
||1 GHz < f < 12.75 GHz<br>~~a~~<br>~~SSeS~~|RBW = 1 MHz<br>~~SSeS~~|–<br>~~SSeS~~|–54<br>~~SSeS~~|–51<br>~~SSeS~~|dBm<br>~~SSeS~~|
||1.8 GHz < f < 1.9 GHz<br>~~a~~<br>~~SSeS~~|RBW = 1 MHz<br>~~SSeS~~|–<br>~~SSeS~~|–88<br>~~SSeS~~|–85<br>~~SSeS~~|dBm<br>~~SSeS~~|
||5.15 GHz < f < 5.3 GHz<br>~~SSeS~~<br>~~a~~|RBW = 1 MHz<br>~~SSeS~~|–<br>~~SSeS~~|–88<br>~~SSeS~~|–85<br>~~SSeS~~|dBm<br>~~SSeS~~|



Document Number: 002-30348 Rev. *D 

Page 63 of 87 

**CYW43439** 

## **15.  Bluetooth RF Specifications** 

**Note:** Values in this data sheet are design goals and are subject to change based on the results of device characterization. Unless otherwise stated, limit values apply for the conditions specified in Table 21 and Table 23. Typical values apply for the following conditions: 

■ VBAT = 3.6V. 

■ Ambient temperature +25°C. 

**Note:** All Bluetooth specifications apply at the chip port. For the location of the chip port, see Figure 28. 

**Table 28. Bluetooth Receiver RF Specifications** 

|**Parameter**<br>~~Ce~~|**Conditions**<br>~~Ce~~|**Minimum**<br>~~Ce~~|**Typical**<br>~~Ce~~|**Maximum**<br>~~Ce~~|**Unit**<br>~~Ce~~|
|---|---|---|---|---|---|
|**Note:**The specifications in this table are measured at the chip output port unless otherwise specified.<br>~~Ce~~<br>~~PR~~||||||
|**General**||||||
|Frequency range<br>~~Ge~~|–<br>~~Ge~~|2402<br>~~Ge~~|–<br>~~Ge~~|2480<br>~~Ge~~|MHz<br>~~Ge~~|
|RX sensitivity|GFSK, 0.1% BER, 1 Mbps<br>~~a~~|–|–94|–|dBm|
||/4–DQPSK, 0.01% BER, 2 Mbps<br>~~a~~<br>~~a~~|–|–96|–|dBm|
||8–DPSK, 0.01% BER, 3 Mbps<br>~~a~~|–|–90|–|dBm|
|Input IP3<br>~~Ge~~|–<br>~~a~~<br>~~Ge~~|–16<br>~~Ge~~<br>~~FO~~|–<br>~~Ge~~<br>~~FO~~|–<br>~~Ge~~<br>~~FO~~|dBm<br>~~Ge~~|
|Maximum input at antenna<br>~~Ce~~|–<br>~~Ce~~|–<br>~~Ce~~<br>~~FO~~|–<br>~~Ce~~<br>~~FO~~|–20<br>~~Ce~~<br>~~FO~~|dBm<br>~~Ce~~|
|**Interference Performance[25]**<br>~~Ce~~<br>~~FO~~<br>~~pT~~<br>~~GO~~||||||
|C/I co-channel<br>~~fe~~|GFSK, 0.1% BER<br>~~fe~~|–<br>~~fe~~<br>~~GO~~|–<br>~~fe~~<br>~~GO~~|11<br>~~fe~~<br>~~GO~~|dB<br>~~fe~~|
|C/I 1 MHz adjacent channel<br>~~fe~~<br>~~Ge~~|GFSK, 0.1% BER<br>~~fe~~<br>~~Ge~~|–<br>~~fe~~<br>~~GO~~<br>~~Ge~~<br>~~GO~~|–<br>~~fe~~<br>~~GO~~<br>~~Ge~~<br>~~GO~~|0.0<br>~~fe~~<br>~~GO~~<br>~~Ge~~<br>~~GO~~|dB<br>~~fe~~<br>~~Ge~~|
|C/I 2 MHz adjacent channel<br>~~Ge~~|GFSK, 0.1% BER<br>~~Ge~~|–<br>~~Ge~~<br>~~GO~~|–<br>~~Ge~~<br>~~GO~~|–30<br>~~Ge~~<br>~~GO~~|dB<br>~~Ge~~|
|C/I3 MHz adjacent channel<br>~~Ge~~<br>~~Ge~~|GFSK, 0.1% BER<br>~~Ge~~<br>~~Ge~~|–<br>~~Ge~~<br>~~GO~~<br>~~Ge~~<br>~~GO~~|–<br>~~Ge~~<br>~~GO~~<br>~~Ge~~<br>~~GO~~|–40<br>~~Ge~~<br>~~GO~~<br>~~Ge~~<br>~~GO~~|dB<br>~~Ge~~<br>~~Ge~~|
|C/I image channel<br>~~Ge~~|GFSK, 0.1% BER<br>~~Ge~~|–<br>~~Ge~~<br>~~GO~~|–<br>~~Ge~~<br>~~GO~~|–9<br>~~Ge~~<br>~~GO~~|dB<br>~~Ge~~|
|C/I 1 MHz adjacent to image channel GFSK, 0.1% BER<br>~~Ge~~<br>~~Ge~~|C/I 1 MHz adjacent to image channel GFSK, 0.1% BER<br>~~Ge~~<br>~~Ge~~|–<br>~~Ge~~<br>~~GO~~<br>~~Ge~~<br>~~GO~~|–<br>~~Ge~~<br>~~GO~~<br>~~Ge~~<br>~~GO~~|–20<br>~~Ge~~<br>~~GO~~<br>~~Ge~~<br>~~GO~~|dB<br>~~Ge~~<br>~~Ge~~|
|C/I co-channel<br>~~Ge~~|/4–DQPSK, 0.1% BER<br>~~Ge~~|–<br>~~Ge~~<br>~~GO~~|–<br>~~Ge~~<br>~~GO~~|13<br>~~Ge~~<br>~~GO~~|dB<br>~~Ge~~|
|C/I 1 MHz adjacent channel<br>~~Ge~~<br>~~Ge~~|/4–DQPSK, 0.1% BER<br>~~Ge~~<br>~~Ge~~|–<br>~~Ge~~<br>~~GO~~<br>~~Ge~~<br>~~GO~~|–<br>~~Ge~~<br>~~GO~~<br>~~Ge~~<br>~~GO~~|0.0<br>~~Ge~~<br>~~GO~~<br>~~Ge~~<br>~~GO~~|dB<br>~~Ge~~<br>~~Ge~~|
|C/I 2 MHz adjacent channel<br>~~Ge~~|/4–DQPSK, 0.1% BER<br>~~Ge~~|–<br>~~Ge~~<br>~~GO~~|–<br>~~Ge~~<br>~~GO~~|–30<br>~~Ge~~<br>~~GO~~|dB<br>~~Ge~~|
|C/I3 MHz adjacent channel<br>~~Ge~~<br>~~Ge~~|/4–DQPSK, 0.1% BER<br>~~Ge~~<br>~~Ge~~|–<br>~~Ge~~<br>~~GO~~<br>~~Ge~~<br>~~GO~~|–<br>~~Ge~~<br>~~GO~~<br>~~Ge~~<br>~~GO~~|–40<br>~~Ge~~<br>~~GO~~<br>~~Ge~~<br>~~GO~~|dB<br>~~Ge~~<br>~~Ge~~|
|C/I image channel<br>~~Ge~~|/4–DQPSK, 0.1% BER<br>~~Ge~~|–<br>~~Ge~~<br>~~GO~~|–<br>~~Ge~~<br>~~GO~~|–7<br>~~Ge~~<br>~~GO~~|dB<br>~~Ge~~|
|C/I 1 MHz adjacent to image channel <br>~~Ge~~<br>~~Ge~~|/4–DQPSK, 0.1% BER<br>~~Ge~~<br>~~Ge~~|–<br>~~Ge~~<br>~~GO~~<br>~~Ge~~<br>~~GO~~|–<br>~~Ge~~<br>~~GO~~<br>~~Ge~~<br>~~GO~~|–20<br>~~Ge~~<br>~~GO~~<br>~~Ge~~<br>~~GO~~|dB<br>~~Ge~~<br>~~Ge~~|
|C/I co-channel<br>~~Ge~~|8–DPSK, 0.1% BER<br>~~Ge~~|–<br>~~Ge~~<br>~~GO~~|–<br>~~Ge~~<br>~~GO~~|21<br>~~Ge~~<br>~~GO~~|dB<br>~~Ge~~|
|C/I 1 MHz adjacent channel<br>~~Ge~~<br>~~Ge~~|8–DPSK, 0.1% BER<br>~~Ge~~<br>~~Ge~~|–<br>~~Ge~~<br>~~GO~~<br>~~Ge~~<br>~~GO~~|–<br>~~Ge~~<br>~~GO~~<br>~~Ge~~<br>~~GO~~|5.0<br>~~Ge~~<br>~~GO~~<br>~~Ge~~<br>~~GO~~|dB<br>~~Ge~~<br>~~Ge~~|
|C/I 2 MHz adjacent channel<br>~~Ge~~|8–DPSK, 0.1% BER<br>~~Ge~~|–<br>~~Ge~~<br>~~GO~~|–<br>~~Ge~~<br>~~GO~~|–25<br>~~Ge~~<br>~~GO~~|dB<br>~~Ge~~|
|C/I3 MHz adjacent channel<br>~~Ge~~<br>~~Ge~~|8–DPSK, 0.1% BER<br>~~Ge~~<br>~~Ge~~|–<br>~~Ge~~<br>~~GO~~<br>~~Ge~~<br>~~GO~~|–<br>~~Ge~~<br>~~GO~~<br>~~Ge~~<br>~~GO~~|–33<br>~~Ge~~<br>~~GO~~<br>~~Ge~~<br>~~GO~~|dB<br>~~Ge~~<br>~~Ge~~|
|C/I Image channel<br>~~Ge~~|8–DPSK, 0.1% BER<br>~~Ge~~|–<br>~~Ge~~<br>~~GO~~|–<br>~~Ge~~<br>~~GO~~|0.0<br>~~Ge~~<br>~~GO~~|dB<br>~~Ge~~|
|C/I 1 MHz adjacent to image channel <br>~~Ge~~<br>~~Ce~~|8–DPSK, 0.1% BER<br>~~Ge~~<br>~~Ce~~|–<br>~~Ge~~<br>~~GO~~<br>~~Ce~~|–<br>~~Ge~~<br>~~GO~~<br>~~Ce~~|–13<br>~~Ge~~<br>~~GO~~<br>~~Ce~~|dB<br>~~Ge~~<br>~~Ce~~|
|**Out-of-Band Blocking Performance (CW)**<br>~~pT~~||||||
|30–2000 MHz<br>~~Ge~~|0.1% BER<br>~~Ge~~|–<br>~~Ge~~|–10.0<br>~~Ge~~|–<br>~~Ge~~|dBm<br>~~Ge~~|
|2000–2399 MHz<br>~~De~~|0.1% BER<br>~~De~~|–<br>~~De~~|–27<br>~~De~~|–<br>~~De~~|dBm<br>~~De~~|



**Note** 25. The Bluetooth reference level for the required signal at the Bluetooth chip port is 3 dB higher than the typical sensitivity level. 

Document Number: 002-30348 Rev. *D 

Page 64 of 87 

**CYW43439** 

**Table 28. Bluetooth Receiver RF Specifications (Cont.)** 

|**Parameter**<br>~~a~~|**Conditions**<br>~~a~~|**Minimum**<br>~~a~~<br>~~(~~|**Typical**<br>~~a~~<br>~~(~~|**Maximum**<br>~~a~~<br>~~(~~|**Unit**<br>~~a~~<br>~~(~~|
|---|---|---|---|---|---|
|2498–3000 MHz<br>~~a~~|0.1% BER<br>~~a~~|–<br>~~(~~<br>~~a~~|–27<br>~~(~~<br>~~a~~|–<br>~~(~~<br>~~a~~|dBm<br>~~(~~<br>~~a~~|
|3000 MHz–12.75 GHz<br>~~a~~|0.1% BER<br>~~a~~|–<br>~~a~~|–10.0<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|**Out-of-Band Blocking Performance, Modulated Interferer (LTE)**<br>~~TT~~||||||
|**GFSK (1 Mbps)**<br>~~TT~~<br>~~pn~~||||||
|2310 MHz<br>~~pn~~<br>~~a~~|LTE band40 TDD 20M BW<br>~~pn~~<br>~~a~~|–<br>~~pn~~<br>~~a~~|–20<br>~~pn~~<br>~~a~~|–<br>~~pn~~<br>~~a~~|dBm<br>~~pn~~<br>~~a~~|
|2330 MHz<br>~~a~~|LTE band40 TDD 20M BW<br>~~a~~|–<br>~~a~~|–19<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|2350 MHz<br>~~a~~<br>~~a~~|LTE band40 TDD 20M BW<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–20<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|dBm<br>~~a~~<br>~~a~~|
|2370 MHz<br>~~a~~|LTE band40 TDD 20M BW<br>~~a~~|–<br>~~a~~|–24<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|2510 MHz<br>~~a~~<br>~~a~~|LTE band7 FDD 20M BW<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–24<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|dBm<br>~~a~~<br>~~a~~|
|2530 MHz<br>~~a~~|LTE band7 FDD 20M BW<br>~~a~~|–<br>~~a~~|–21<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|2550 MHz<br>~~a~~<br>~~a~~|LTE band7 FDD 20M BW<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–21<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|dBm<br>~~a~~<br>~~a~~|
|2570 MHz<br>~~a~~|LTE band7 FDD 20M BW<br>~~a~~|–<br>~~a~~|–20<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|**/4 DPSK (2 Mbps)**<br>~~a~~<br>~~pn~~||||||
|2310 MHz<br>~~a~~|LTE band40 TDD 20M BW<br>~~a~~|–<br>~~a~~|–20<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|2330 MHz<br>~~a~~|LTE band40 TDD 20M BW<br>~~a~~|–<br>~~a~~|–19<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|2350 MHz<br>~~a~~|LTE band40 TDD 20M BW<br>~~a~~|–<br>~~a~~|–20<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|2370 MHz<br>~~a~~|LTE band40 TDD 20M BW<br>~~a~~|–<br>~~a~~|–24<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|2510 MHz<br>~~a~~|LTE band7 FDD 20M BW<br>~~a~~|–<br>~~a~~|–24<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|2530 MHz<br>~~a~~|LTE band7 FDD 20M BW<br>~~a~~|–<br>~~a~~|–20<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|2550 MHz<br>~~a~~|LTE band7 FDD 20M BW<br>~~a~~|–<br>~~a~~|–20<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|2570 MHz<br>~~a~~|LTE band7 FDD 20M BW<br>~~a~~|–<br>~~a~~|–20<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|**8DPSK (3 Mbps)**<br>~~pt~~||||||
|2310 MHz<br>~~a~~|LTE band40 TDD 20M BW<br>~~a~~|–<br>~~a~~|–20<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|2330 MHz<br>~~a~~<br>~~a~~|LTE band40 TDD 20M BW<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–19<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|dBm<br>~~a~~<br>~~a~~|
|2350 MHz<br>~~a~~|LTE band40 TDD 20M BW<br>~~a~~|–<br>~~a~~|–20<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|2370 MHz<br>~~a~~<br>~~a~~|LTE band40 TDD 20M BW<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–24<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|dBm<br>~~a~~<br>~~a~~|
|2510 MHz<br>~~a~~|LTE band7 FDD 20M BW<br>~~a~~|–<br>~~a~~|–24<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|2530 MHz<br>~~a~~<br>~~a~~|LTE band7 FDD 20M BW<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–21<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|dBm<br>~~a~~<br>~~a~~|
|2550 MHz<br>~~a~~|LTE band7 FDD 20M BW<br>~~a~~|–<br>~~a~~|–20<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|2570 MHz<br>~~a~~<br>~~a~~|LTE band7 FDD 20M BW<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–20<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|dBm<br>~~a~~<br>~~a~~|
|**Out-of-Band Blocking Performance, Modulated Interferer (Non-LTE)**<br>~~TT~~||||||
|**GFSK (1 Mbps)[25]**<br>~~TT~~<br>~~pn~~||||||
|698–716 MHz<br>~~pn~~<br>~~a~~|WCDMA<br>~~pn~~<br>~~a~~|–<br>~~pn~~<br>~~a~~|–12<br>~~pn~~<br>~~a~~|–<br>~~pn~~<br>~~a~~|dBm<br>~~pn~~<br>~~a~~|
|776–849 MHz<br>~~OO~~|WCDMA<br>~~OO~~|–<br>~~OO~~|–12<br>~~OO~~|–<br>~~OO~~|dBm<br>~~OO~~|
|824–849 MHz<br>~~OO~~<br>~~a~~|GSM850<br>~~OO~~<br>~~a~~|–<br>~~OO~~<br>~~a~~|–12<br>~~OO~~<br>~~a~~|–<br>~~OO~~<br>~~a~~|dBm<br>~~OO~~<br>~~a~~|
|824–849 MHz<br>~~a~~|WCDMA<br>~~a~~|–<br>~~a~~|–11<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|880–915 MHz<br>~~a~~|E-GSM<br>~~a~~|–<br>~~a~~|–11<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|



Document Number: 002-30348 Rev. *D 

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**CYW43439** 

**Table 28. Bluetooth Receiver RF Specifications (Cont.)** 

|**Parameter**<br>~~a~~|**Conditions**<br>~~a~~|**Minimum**<br>~~a~~<br>~~(~~|**Typical**<br>~~a~~<br>~~(~~|**Maximum**<br>~~a~~<br>~~(~~|**Unit**<br>~~a~~<br>~~(~~|
|---|---|---|---|---|---|
|880–915 MHz<br>~~a~~|WCDMA<br>~~a~~|–<br>~~(~~<br>~~a~~|–16<br>~~(~~<br>~~a~~|–<br>~~(~~<br>~~a~~|dBm<br>~~(~~<br>~~a~~|
|1710–1785 MHz<br>~~a~~|GSM1800<br>~~a~~|–<br>~~a~~|–15<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|1710–1785 MHz<br>~~a~~|WCDMA<br>~~a~~|–<br>~~a~~|–18<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|1850–1910 MHz<br>~~a~~<br>~~a~~|GSM1900<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–20<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|dBm<br>~~a~~<br>~~a~~|
|1850–1910 MHz<br>~~a~~|WCDMA<br>~~a~~|–<br>~~a~~|–17<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|1880–1920 MHz<br>~~a~~<br>~~a~~|TD-SCDMA<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–18<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|dBm<br>~~a~~<br>~~a~~|
|1920–1980 MHz<br>~~a~~|WCDMA<br>~~a~~|–<br>~~a~~|–18<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|2010–2025 MHz<br>~~a~~<br>~~a~~|TD–SCDMA<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–18<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|dBm<br>~~a~~<br>~~a~~|
|2500–2570 MHz<br>~~a~~|WCDMA<br>~~a~~|–<br>~~a~~|–21<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|**/4 DPSK (2 Mbps)[25]**<br>~~a~~<br>~~po~~||||||
|698–716 MHz<br>~~po~~<br>~~a~~|WCDMA<br>~~po~~<br>~~a~~|–<br>~~po~~<br>~~a~~|–8<br>~~po~~<br>~~a~~|–<br>~~po~~<br>~~a~~|dBm<br>~~po~~<br>~~a~~|
|776–794 MHz<br>~~a~~|WCDMA<br>~~a~~|–<br>~~a~~|–8<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|824–849 MHz<br>~~a~~<br>~~a~~|GSM850<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–9<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|dBm<br>~~a~~<br>~~a~~|
|824–849 MHz<br>~~a~~|WCDMA<br>~~a~~|–<br>~~a~~|–9<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|880–915 MHz<br>~~a~~<br>~~a~~|E-GSM<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–8<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|dBm<br>~~a~~<br>~~a~~|
|880–915 MHz<br>~~a~~|WCDMA<br>~~a~~|–<br>~~a~~|–8<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|1710–1785 MHz<br>~~a~~<br>~~a~~|GSM1800<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–14<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|dBm<br>~~a~~<br>~~a~~|
|1710–1785 MHz<br>~~a~~|WCDMA<br>~~a~~|–<br>~~a~~|–14<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|1850–1910 MHz<br>~~a~~<br>~~a~~|GSM1900<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–15<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|dBm<br>~~a~~<br>~~a~~|
|1850–1910 MHz<br>~~a~~|WCDMA<br>~~a~~|–<br>~~a~~|–14<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|1880–1920 MHz<br>~~a~~<br>~~a~~|TD-SCDMA<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–16<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|dBm<br>~~a~~<br>~~a~~|
|1920–1980 MHz<br>~~a~~|WCDMA<br>~~a~~|–<br>~~a~~|–15<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|2010–2025 MHz<br>~~a~~<br>~~a~~|TD-SCDMA<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–17<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|dBm<br>~~a~~<br>~~a~~|
|2500–2570 MHz<br>~~a~~|WCDMA<br>~~a~~|–<br>~~a~~|–21<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|**8DPSK (3 Mbps)[25]**<br>~~a~~<br>~~pn~~||||||
|698–716 MHz<br>~~a~~|WCDMA<br>~~a~~|–<br>~~a~~|–11<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|776–794 MHz<br>~~a~~|WCDMA<br>~~a~~|–<br>~~a~~|–11<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|824–849 MHz<br>~~a~~<br>~~a~~|GSM850<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–11<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|dBm<br>~~a~~<br>~~a~~|
|824–849 MHz<br>~~a~~|WCDMA<br>~~a~~|–<br>~~a~~|–12<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|880–915 MHz<br>~~a~~<br>~~a~~|E-GSM<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–11<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|dBm<br>~~a~~<br>~~a~~|
|880–915 MHz<br>~~a~~|WCDMA<br>~~a~~|–<br>~~a~~|–11<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|1710–1785 MHz<br>~~a~~<br>~~a~~|GSM1800<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–16<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|dBm<br>~~a~~<br>~~a~~|
|1710–1785 MHz<br>~~a~~|WCDMA<br>~~a~~|–<br>~~a~~|–15<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|1850–1910 MHz<br>~~a~~<br>~~a~~|GSM1900<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–17<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|dBm<br>~~a~~<br>~~a~~|
|1850–1910 MHz<br>~~a~~|WCDMA<br>~~a~~|–<br>~~a~~|–17<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|1880–1920 MHz<br>~~a~~<br>~~a~~|TD-SCDMA<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–17<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|dBm<br>~~a~~<br>~~a~~|
|1920–1980 MHz<br>~~a~~|WCDMA<br>~~a~~|–<br>~~a~~|–17<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|2010–2025 MHz<br>~~a~~<br>~~a~~|TD-SCDMA<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–18<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|dBm<br>~~a~~<br>~~a~~|



Document Number: 002-30348 Rev. *D 

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**CYW43439** 

**Table 28. Bluetooth Receiver RF Specifications (Cont.)** 

|**Parameter**<br>~~Ge~~|**Conditions**<br>~~Ge~~|**Minimum**<br>~~Ge~~|**Typical**<br>~~Ge~~|**Maximum**<br>~~Ge~~|**Unit**<br>~~Ge~~|
|---|---|---|---|---|---|
|2500–2570 MHz<br>~~Ge~~|WCDMA<br>~~Ge~~|–<br>~~Ge~~|–21<br>~~Ge~~|–<br>~~Ge~~|dBm<br>~~Ge~~|
|**RX LO Leakage**<br>~~pn~~<br>~~DO~~||||||
|2.4 GHz band<br>~~Fe~~|–<br>~~Fe~~|–<br>~~Fe~~<br>~~DO~~|–90.0<br>~~Fe~~<br>~~DO~~|–80.0<br>~~Fe~~<br>~~DO~~|dBm<br>~~Fe~~|
|**Spurious Emissions**<br>~~Fe~~<br>~~DO~~<br>~~pe~~||||||
|30 MHz–1 GHz<br>~~CO~~||–<br>~~CO~~|–95<br>~~CO~~|–62<br>~~CO~~|dBm<br>~~CO~~|
|1–12.75 GHz<br>~~CO~~<br>~~a~~||–<br>~~CO~~<br>~~a~~|–70<br>~~CO~~<br>~~a~~|–47<br>~~CO~~<br>~~a~~|dBm<br>~~CO~~<br>~~a~~|
|869–894 MHz<br>~~GO~~||–<br>~~GO~~|–147<br>~~GO~~|–<br>~~GO~~|dBm/Hz<br>~~GO~~|
|925–960 MHz<br>~~GO~~<br>~~a~~||–<br>~~GO~~<br>~~a~~|–147<br>~~GO~~<br>~~a~~|–<br>~~GO~~<br>~~a~~|dBm/Hz<br>~~GO~~<br>~~a~~|
|1805–1880 MHz<br>~~GO~~||–<br>~~GO~~|–147<br>~~GO~~|–<br>~~GO~~|dBm/Hz<br>~~GO~~|
|1930–1990 MHz<br>~~GO~~<br>~~a~~||–<br>~~GO~~<br>~~a~~|–147<br>~~GO~~<br>~~a~~|–<br>~~GO~~<br>~~a~~|dBm/Hz<br>~~GO~~<br>~~a~~|
|2110–2170 MHz<br>~~De~~||–<br>~~De~~|–147<br>~~De~~|–<br>~~De~~|dBm/Hz<br>~~De~~|



**Note** 25. The Bluetooth reference level for the required signal at the Bluetooth chip port is 3 dB higher than the typical sensitivity level. 

**Table 29. LTE Specifications for Spurious Emissions** 

|**Parameter**|**Conditions**|**Typical**|**Unit**|
|---|---|---|---|
|2500–2570 MHz|Band 7|–147|dBm/Hz|
|2300–2400 MHz|Band 40|–147|dBm/Hz|
|2570–2620 MHz|Band 38|–147|dBm/Hz|
|2545–2575 MHz|XGP Band|–147|dBm/Hz|



Document Number: 002-30348 Rev. *D 

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**CYW43439** 

**Table 30. Bluetooth Transmitter RF Specifications[[26]]** 

|**Parameter**<br>~~CO~~|**Conditions**<br>~~CO~~|**Minimum**<br>~~CO~~|**Typical**<br>~~CO~~|**Maximum**<br>~~CO~~|**Unit**<br>~~CO~~|
|---|---|---|---|---|---|
|**General**<br>~~pe~~||||||
|Frequency range<br>~~CO~~||2402<br>~~CO~~|–<br>~~CO~~|2480<br>~~CO~~|MHz<br>~~CO~~|
|Basic rate (GFSK) TX power at Bluetooth<br>~~a~~||–<br>~~a~~|12.0<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|QPSK TX power at Bluetooth<br>~~a~~||–<br>~~a~~|8.0<br>~~a~~|–<br>~~a~~|dBm<br>~~a~~|
|8PSK TX power at Bluetooth<br>~~eC~~||–<br>~~eC~~|8.0<br>~~eC~~|–<br>~~eC~~|dBm<br>~~eC~~|
|Power control step<br>~~a~~|–|2|4|8|dB|
|**GFSK In-Band Spurious Emissions**||||||
|–20 dBc BW<br>~~a~~|–<br>~~G~~|–<br>~~G~~|0.93|1|MHz|
|**EDR In-Band Spurious Emissions**<br>~~po~~<br>~~ee~~<br>~~eeee~~<br>~~pO~~||||||
|1.0 MHz < |M – N| < 1.5 MHz<br>~~po~~<br>~~pO~~<br>~~po~~|M – N = the frequency range for which<br>the spurious emission is measured<br>relative to the transmit center<br>frequency.|–<br>~~ee~~<br>~~ee~~|–38<br>~~ee~~<br>~~ee~~|–26.0<br>~~ee~~<br>~~ee~~<br>~~e~~~~**e**~~|dBc<br>~~ee~~<br>~~ee~~<br>~~**ee**~~|
|1.5 MHz < |M – N| < 2.5 MHz<br>~~po~~<br>~~pO~~<br>~~po~~||–<br>~~ee~~<br>~~ee~~|–31<br>~~ee~~<br>~~ee~~|–20.0<br>~~ee~~<br>~~ee~~<br>~~e~~~~**e**~~<br>~~e~~|dBm<br>~~ee~~<br>~~ee~~<br>~~**ee**~~|
||M – N|2.5 MHz[27]<br>~~pO~~<br>~~po~~||–<br>~~ee~~<br>~~ee~~|–43<br>~~ee~~<br>~~ee~~|–40.0<br>~~ee ~~<br>~~e~~~~**e**~~<br>~~ee~~<br>~~e~~|dBm<br> ~~ee~~<br>~~**ee**~~<br>~~ee~~|
|**Out-of-Band Spurious Emissions**<br>~~ee ee~~<br>~~e~~~~**e** ~~~~**ee**~~<br>~~po~~<br>~~e~~<br>~~pT~~||||||
|30 MHz to 1 GHz|–|–|–|–36.0[28, 29]|dBm|
|1 GHz to 12.75 GHz<br>~~a~~|–<br>~~a~~|–<br>~~a~~|–<br>~~a~~|–30.0[29, 30,<br>31]<br>~~a~~|dBm<br>~~a~~|
|1.8 GHz to 1.9 GHz<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–47.0<br>~~a~~<br>~~a~~|dBm<br>~~a~~<br>~~a~~|
|5.15 GHz to 5.3 GHz<br>~~pf~~|–<br>~~pf~~|–<br>~~pf~~|–<br>~~pf~~|–47.0<br>~~pf~~|dBm<br>~~pf~~|
|**GPS Band Spurious Emissions**<br>~~pf~~<br>~~En~~||||||
|Spurious emissions<br>~~a~~|–<br>~~DC~~|–<br>~~DC~~|–103<br>~~DC~~|–<br>~~DC~~|dBm<br>~~DC~~|
|**Out-of-Band Noise Floor[32]**<br>~~a~~<br>~~DC~~<br>~~En~~||||||
|65–108 MHz<br>~~CC~~|FM RX<br>~~CC~~|–<br>~~CC~~|–147<br>~~CC~~|–<br>~~CC~~|dBm/Hz<br>~~CC~~|
|776–794 MHz<br>~~CC~~<br>~~a~~|CDMA2000<br>~~CC~~|–<br>~~CC~~|–146<br>~~CC~~|–<br>~~CC~~|dBm/Hz<br>~~CC~~|
|869–960 MHz<br>~~CC~~|cdmaOne, GSM850<br>~~CC~~|–<br>~~CC~~|–146<br>~~CC~~|–<br>~~CC~~|dBm/Hz<br>~~CC~~|
|925–960 MHz<br>~~CC~~<br>~~a~~|E-GSM<br>~~CC~~|–<br>~~CC~~|–146<br>~~CC~~|–<br>~~CC~~|dBm/Hz<br>~~CC~~|
|1570–1580 MHz<br>~~CC~~|GPS<br>~~CC~~|–<br>~~CC~~|–146<br>~~CC~~|–<br>~~CC~~|dBm/Hz<br>~~CC~~|
|1805–1880 MHz<br>~~CC~~<br>~~a~~|GSM1800<br>~~CC~~|–<br>~~CC~~|–144<br>~~CC~~|–<br>~~CC~~|dBm/Hz<br>~~CC~~|
|1930–1990 MHz<br>~~CC~~|GSM1900, cdmaOne, WCDMA<br>~~CC~~|–<br>~~CC~~|–143<br>~~CC~~|–<br>~~CC~~|dBm/Hz<br>~~CC~~|
|2110–2170 MHz<br>~~CC~~<br>~~a~~|WCDMA<br>~~CC~~|–<br>~~CC~~|–137<br>~~CC~~|–<br>~~CC~~|dBm/Hz<br>~~CC~~|



## **Notes** 

26. Unless otherwise specified, the specifications in this table apply at the chip output port, and output power specifications are with the temperature correction algorithm and TSSI enabled. 

27. Typically measured at an offset of ±3 MHz. 

28. The maximum value represents the value required for Bluetooth qualification as defined in the 5.2 specification. 

29. The spurious emissions during Idle mode are the same as specified in Table 30. 

30. Specified at the Bluetooth antenna port. 

31. Meets this specification using a front-end band-pass filter. 

32. Transmitted power in cellular and FM bands at the Bluetooth antenna port. See Figure 28 for location of the port. 

Document Number: 002-30348 Rev. *D 

Page 68 of 87 

**CYW43439** 

**Table 31. LTE Specifications for Out-of-Band Noise Floor** 

|**Parameter**|**Conditions**|**Typical**|**Unit**|
|---|---|---|---|
|2500–2570 MHz|Band 7|–130|dBm/Hz|
|2300–2400 MHz|Band 40|–130|dBm/Hz|
|2570–2620 MHz|Band 38|–130|dBm/Hz|
|2545–2575 MHz|XGP Band|–130|dBm/Hz|



**Table 32. Local Oscillator Performance** 

|**Parameter**<br>~~eG~~|**Minimum**<br>~~eG~~|**Typical**<br>~~eG~~|**Maximum**<br>~~eG~~|**Unit**<br>~~eG~~|
|---|---|---|---|---|
|**LO Performance**<br>~~eG~~<br>~~pn~~|||||
|Lock time<br>~~eG~~|–<br>~~eG~~|72<br>~~eG~~|–<br>~~eG~~|s<br>~~eG~~|
|Initial carrier frequency tolerance<br>~~eG~~<br>~~GG~~|–<br>~~eG~~<br>~~GG~~|±25<br>~~eG~~<br>~~GG~~|±75<br>~~eG~~<br>~~GG~~|kHz<br>~~eG~~<br>~~GG~~|
|**Frequency Drift**<br>~~Pn~~|||||
|DH1 packet<br>~~Pn~~<br>~~GG~~|–<br>~~Pn~~<br>~~GG~~|±8<br>~~Pn~~<br>~~GG~~|±25<br>~~Pn~~<br>~~GG~~|kHz<br>~~Pn~~<br>~~GG~~|
|DH3 packet<br>~~eG~~|–<br>~~eG~~|±8<br>~~eG~~|±40<br>~~eG~~|kHz<br>~~eG~~|
|DH5 packet<br>~~eG~~<br>~~GG~~|–<br>~~eG~~<br>~~GG~~|±8<br>~~eG~~<br>~~GG~~|±40<br>~~eG~~<br>~~GG~~|kHz<br>~~eG~~<br>~~GG~~|
|Drift rate<br>~~eG~~|–<br>~~eG~~|5<br>~~eG~~|20<br>~~eG~~|kHz/50 μs<br>~~eG~~|
|**Frequency Deviation**<br>~~eG~~|||||
|00001111 sequence in payload[33]<br>~~eG~~|140<br>~~eG~~|155<br>~~eG~~|175<br>~~eG~~|kHz<br>~~eG~~|
|10101010 sequence in payload[34]<br>~~eG~~<br>~~GG~~|115<br>~~eG~~<br>~~GG~~|140<br>~~eG~~<br>~~GG~~|–<br>~~eG~~<br>~~GG~~|kHz<br>~~eG~~<br>~~GG~~|
|Channel spacing|–|1|–|MHz|



## **Notes** 

33. This pattern represents an average deviation in payload. 

34. Pattern represents the maximum deviation in payload for 99.9% of all frequency deviations. 

**Table 33. BLE RF Specifications** 

|**Parameter**|**Conditions**|**Minimum**|**Typical**|**Maximum**|**Unit**|
|---|---|---|---|---|---|
|Frequency range|–|2402|–|2480|MHz|
|RX sense[35]|GFSK, 0.1% BER, 1 Mbps|–|–97|–|dBm|
|TX power[36]|–|–|8.5|–|dBm|
|Mod Char: delta f1 average|–|225|255|275|kHz|
|Mod Char: delta f2 max[37]|–|99.9|–|–|%|
|Mod Char: ratio|–|0.8|0.95|–|%|



**Notes** 

35. The Bluetooth tester is set so that Dirty TX is on. 

36. BLE TX power can be increased to compensate for front-end losses such as BPF, diplexer, switch, etc.). The output is capped at 12 dBm. The BLE TX power at the antenna port cannot exceed the 10 dBm specification limit. 

37. At least 99.9% of all delta F2 max. frequency values recorded over 10 packets must be greater than 185 kHz. 

Document Number: 002-30348 Rev. *D 

Page 69 of 87 

**CYW43439** 

## **16.  Internal Regulator Electrical Specifications** 

**Note:** Values in this data sheet are design goals and are subject to change based on device characterization results. Functional operation is not guaranteed outside of the specification limits provided in this section. 

## **16.1  Core Buck Switching Regulator** 

**Table 34. Core Buck Switching Regulator (CBUCK) Specifications** 

|**Specification**<br>~~re~~|**Notes**<br>~~Ps~~|**Min.**<br>~~tt~~<br>~~Is~~|**Typ.**<br>~~tt~~<br>~~I~~|**Max.**|**Units**|
|---|---|---|---|---|---|
|Input supply voltage (DC)<br>~~re~~<br>~~Pt~~|DC voltage range inclusive of disturbances.<br>~~Ps ~~<br>~~Pt~~|2.4<br> ~~tt~~<br>~~Pt~~<br>~~Is~~|3.6<br>~~tt~~<br>~~Pt~~<br>~~I~~|4.8[38]<br>~~Pt~~|V<br>~~Pt~~|
|PWM mode switching frequency<br>~~PR~~|CCM, load > 100 mA VBAT = 3.6V.<br>~~PR~~|–<br>~~Is ~~<br>~~PR~~|4<br> ~~I~~<br>~~PR~~|–<br>~~PR~~|MHz<br>~~PR~~|
|PWM output current<br>~~I~~|–<br>~~I~~|–<br>~~I~~|–<br>~~I~~|370<br>~~I~~|mA<br>~~I~~|
|Output current limit<br>~~PS~~|–<br>~~PS~~|–<br>~~PS~~|1400<br>~~PS~~|–<br>~~PS~~|mA<br>~~PS~~|
|Output voltage range<br>~~PS~~<br>~~es~~|Programmable, 30 mV steps.<br>Default = 1.35V.<br>~~PS~~<br>~~es~~|1.2<br>~~PS~~<br>~~es~~|1.35<br>~~PS~~<br>~~es~~|1.5<br>~~PS~~<br>~~es~~|V<br>~~PS~~<br>~~es~~|
|PWM output voltage<br>DC accuracy|Includes load and line regulation.<br>Forced PWM mode.|–4|–|4|%|
|PWM ripple voltage, static|Measure with 20 MHz bandwidth limit.<br>Static load, max. ripple based on VBAT = 3.6V,<br>Vout = 1.35V, Fsw = 4 MHz, 2.2 μH<br>inductor L > 1.05 μH, Cap + Board total-ESR <<br>20 mΩ, Cout> 1.9 μF, ESL<200 pH|–|7|20|mVpp|
|PWM mode peak efficiency<br>~~es~~|Peak efficiency at 200 mA load, inductor DCR<br>= 200 mΩ, VBAT = 3.6V, VOUT = 1.35V<br>~~es~~|–<br>~~es~~|85<br>~~es~~|–<br>~~es~~|%<br>~~es~~|
|PFM mode efficiency<br>~~es~~|10 mA load current, inductor DCR = 200 mΩ,<br>VBAT = 3.6V, VOUT = 1.35V<br>~~es~~|–<br>~~es~~|77<br>~~es~~|–<br>~~es~~|%<br>~~es~~|
|Start-up time from power down|VDDIO already ON and steady.<br>Time from REG_ON rising edge to CLDO<br>reaching 1.2V|–<br>~~I~~|400<br>~~I~~|500|µs|
|External inductor<br>~~GR~~|0603 size, 2.2 μH ±20%, DCR = 0.2Ω ± 25%<br>~~GR~~|–<br>~~GR~~<br>~~I~~|2.2<br>~~GR~~<br>~~I~~|–<br>~~GR~~|µH<br>~~GR~~|
|External output capacitor<br>~~es~~|Ceramic, X5R, 0402,<br>ESR <30 mΩ at 4 MHz, 4.7 μF ±20%, 10V<br>~~es~~|2.0[39]<br>~~I ~~<br>~~es~~|4.7<br> ~~I~~<br>~~es~~|10[40]<br>~~es~~|µF<br>~~es~~|
|External input capacitor<br>~~es~~|For SR_VDDBATP5V pin, ceramic, X5R, 0603,<br>ESR < 30 mΩ at 4 MHz, ±4.7 μF ±20%, 10V<br>~~es~~|0.672<br>~~es~~|4.7<br>~~es~~|–<br>~~es~~|µF<br>~~es~~|
|Input supply voltage ramp-up time<br>~~PR~~|0 to 4.3V<br>~~PR~~|40<br>~~PR~~|–<br>~~PR~~|–<br>~~PR~~|µs<br>~~PR~~|



39. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging. 40. Total capacitance includes those connected at the far end of the active load. 

Document Number: 002-30348 Rev. *D 

Page 70 of 87 

**CYW43439** 

## **16.2  3.3V LDO (LDO3P3)** 

**Table 35. LDO3P3 Specifications** 

|**Specification**|**Notes**<br>~~ee~~|**Min.**<br>~~ee ee~~|**Typ.**<br>~~ee~~|**Max.**<br>~~ee~~|**Units**<br>~~ee~~|
|---|---|---|---|---|---|
|Input supply voltage, Vin<br>~~a~~|Min. = Vo+ 0.2V = 3.5V dropout voltage<br>requirement must be met under maximum<br>load for performance specifications.<br>~~a~~<br>~~ee~~|3.1<br>~~a~~<br>~~ee ee~~|3.6<br>~~a~~<br>~~ee~~|4.8[41]<br>~~a~~<br>~~ee~~|V<br>~~a~~<br>~~ee~~|
|Output current<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~ee~~<br>~~a~~|0.001<br>~~a~~<br>~~ee ee~~<br>~~a~~|–<br>~~a~~<br>~~ee~~<br>~~a~~|450<br>~~a~~<br>~~ee~~<br>~~a~~|mA<br>~~a~~<br>~~ee~~<br>~~a~~|
|Nominal output voltage, Vo<br>~~a~~|Default = 3.3V.<br>~~a~~|–<br>~~a~~|3.3<br>~~a~~|–<br>~~a~~|V<br>~~a~~|
|Dropout voltage<br>~~a~~<br>~~a~~|At max. load.<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|200<br>~~a~~<br>~~a~~|mV<br>~~a~~<br>~~a~~|
|Output voltage DC accuracy<br>~~a~~|Includes line/load regulation.<br>~~a~~|–5<br>~~a~~|–<br>~~a~~|+5<br>~~a~~|%<br>~~a~~|
|Quiescent current<br>~~a~~<br>~~a~~|No load<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|66<br>~~a~~<br>~~a~~|85<br>~~a~~<br>~~a~~|µA<br>~~a~~<br>~~a~~|
|Line regulation<br>~~a~~|Vinfrom (Vo+ 0.2V) to 4.8V, max. load<br>~~a~~|–<br>~~a~~|–<br>~~a~~|3.5<br>~~a~~|mV/V<br>~~a~~|
|Load regulation<br>~~a~~<br>~~a~~|load from 1 mA to 450 mA<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|0.3<br>~~a~~<br>~~a~~|mV/mA<br>~~a~~<br>~~a~~|
|PSRR|Vin≥ Vo+ 0.2V,<br>Vo= 3.3V, Co= 4.7 µF,<br>Max. load, 100 Hz to 100 kHz|20|–|–|dB|
|LDO turn-on time<br>~~ee~~|Chip already powered up.<br>~~ee~~|–<br>~~ee~~|160<br>~~ee~~|250|µs|
|External output capacitor, Co<br>~~ee~~|Ceramic, X5R, 0402,<br>(ESR: 5 mΩ–240 mΩ), ± 10%, 10V<br>~~ee~~|1.0[42]<br>~~ee~~|4.7<br>~~ee~~|5.64|µF|
|External input capacitor<br>~~ee~~|For SR_VDDBATA5V pin (shared with band<br>gap) Ceramic, X5R, 0402,<br>(ESR: 30m-200 mΩ), ± 10%, 10V.<br>Not needed if sharing VBAT capacitor 4.7 µF<br>with SR_VDDBATP5V.<br>~~ee~~|–<br>~~ee~~|4.7<br>~~ee~~|–|µF|



## **Note** 

41. The maximum continuous voltage is 4.8V. Voltages up to 6.0V for up to 10 seconds, cumulative duration, over the lifetime of the device are allowed. Voltages as high as 5.0V for up to 250 seconds, cumulative duration, over the lifetime of the device are allowed. 

42. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging. 

Document Number: 002-30348 Rev. *D 

Page 71 of 87 

**CYW43439** 

## **16.3  CLDO** 

**Table 36. CLDO Specifications** 

|**Specification**<br>~~a~~<br>~~a~~|**Notes**<br>~~a~~<br>~~ee~~|**Min.**<br>~~a~~|**Typ.**<br>~~a~~|**Max.**<br>~~a~~|**Units**<br>~~a~~|
|---|---|---|---|---|---|
|Input supply voltage, Vin<br>~~a~~<br>~~a~~|Min. = 1.2 + 0.15V = 1.35V dropout voltage<br>requirement must be met under maximum load.<br>~~a~~<br>~~ee~~|1.3<br>~~a~~|1.35<br>~~a~~|1.5<br>~~a~~|V<br>~~a~~|
|Output current<br>~~a~~|–<br>~~ee~~|0.2|–|200|mA|
|Output voltage, Vo<br>~~a~~<br>~~a~~|Programmable in 10 mV steps. Default = 1.2.V<br>~~ee~~|0.95|1.2|1.26|V|
|Dropout voltage<br>~~a~~|At max. load|–|–|150|mV|
|Output voltage DC accuracy<br>~~a~~<br>~~a~~|Includes line/load regulation|–4|–|+4|%|
|Quiescent current<br>~~a ~~|No load<br>|–<br>|13<br>|–<br>|µA<br>|
||200 mA load<br> ~~OO~~|–<br>~~OO~~|1.24<br>~~OO~~|–<br>~~OO~~|mA<br>~~OO~~|
|Line regulation<br>~~a~~|Vinfrom (Vo+ 0.15V) to 1.5V, maximum load<br>~~a~~|–<br>~~a~~|–<br>~~a~~|5<br>~~a~~|mV/V<br>~~a~~|
|Load regulation<br>~~a~~<br>~~a~~<br>|Load from 1 mA to 300 mA<br>~~a~~<br>~~a~~<br>|–<br>~~a~~<br>~~a~~<br>|0.02<br>~~a~~<br>~~a~~<br>|0.05<br>~~a~~<br>~~a~~<br>|mV/mA<br>~~a~~<br>~~a~~<br>~~—~~|
|Leakage current<br>~~i~~|Power down<br>~~i~~|–<br>~~i~~|5<br>~~i~~|20<br>~~i~~|µA<br>~~i—~~|
||Bypass mode<br>~~i~~<br>~~OO~~|–<br>~~i~~<br>~~OO~~|1<br>~~i~~<br>~~OO~~|3<br>~~i~~<br>~~OO~~|µA<br>~~i—~~<br>~~OO~~|
|PSRR<br><br>~~a~~|@1 kHz, Vin ≥ 1.35V, Co= 4.7 µF<br>|20<br>|–<br>|–<br>|dB<br>~~—~~|
|Start-up time of PMU<br>~~a~~|VDDIO up and steady. Time from the REG_ON rising<br>edge to the CLDO<br>reaching 1.2V.|–|–|700|µs|
|LDO turn-on time|LDO turn-on time when rest of the chip is up.|–|140|180|µs|
|External output capacitor, Co<br>~~a~~<br>~~ee~~|Total ESR: 5 mΩ–240 mΩ<br>~~ee ee~~|1.1[43]<br>~~ee~~|2.2<br>~~ee~~|–<br>~~ee~~|µF<br>~~ee~~|
|External input capacitor<br>~~ee~~|Only use an external input capacitor at the VDD_LDO<br>pin if it is not supplied from CBUCK output.<br>~~ee ee~~|–<br>~~ee~~|1<br>~~ee~~|2.2<br>~~ee~~|µF<br>~~ee~~|



43. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging. 

Document Number: 002-30348 Rev. *D 

Page 72 of 87 

**CYW43439** 

## **16.4  LNLDO** 

**Table 37. LNLDO Specifications** 

|**Specification**<br>~~**a**~~|**Notes**<br>~~ee~~|**Min.**<br>~~ee~~|**Typ.**<br>~~ee~~|**Max.**<br>~~ee~~|**Units**<br>~~ee~~|
|---|---|---|---|---|---|
|Input supply voltage, Vin<br>~~**a**~~|Min. VIN= VO+ 0.15V = 1.35V<br>(where VO= 1.2V) dropout voltage requirement must be<br>met under maximum load.<br>~~ee~~|1.3<br>~~ee~~|1.35<br>~~ee~~|1.5<br>~~ee~~|V<br>~~ee~~|
|Output current<br>~~**a**~~|–<br>~~ee ~~|0.1<br> ~~ee~~|–<br>~~ee~~|150<br>~~ee~~|mA<br>~~ee~~|
|Output voltage, Vo<br>~~a~~|Programmable in 25 mV steps.Default = 1.2V|1.1|1.2|1.275|V|
|Dropout voltage<br>~~a~~<br>~~a~~|At maximum load|–|–|150|mV|
|Output voltage DC accuracy<br>~~aee~~|Includes line/load regulation<br>~~ee ee~~|–4<br>~~ee~~|–<br>~~ee~~|+4<br>~~ee~~|%<br>~~ee~~|
|Quiescent current<br>~~aee~~|No load<br>~~ee ee~~|–<br>~~ee~~|10<br>~~ee~~|12<br>~~ee~~|µA<br>~~ee~~|
||Max. load<br>~~ee ee~~<br>~~a~~|–<br>~~ee~~<br>~~a~~|970<br>~~ee~~<br>~~a~~|990<br>~~ee~~<br>~~a~~|µA<br>~~ee~~<br>~~a~~|
|Line regulation<br>~~ee~~<br>~~a~~|Vinfrom (Vo+ 0.15V) to 1.5V, 200 mA load<br>~~ee ee~~<br>~~a~~|–<br>~~ee~~<br>~~a~~|–<br>~~ee~~<br>~~a~~|5<br>~~ee~~<br>~~a~~|mV/V<br>~~ee~~<br>~~a~~|
|Load regulation<br>~~ee~~|Load from 1 mA to 200 mA:<br>Vin≥ (Vo+ 0.12V)<br>~~ee~~|–<br>~~ee~~|0.025<br>~~ee~~|0.045<br>~~ee~~|mV/mA<br>~~ee~~|
|Leakage current<br>~~a~~<br>~~a~~|Power-down, junction temp. = 85°C<br>|–<br><br>~~ee~~|5<br><br>~~ee~~|20<br>|µA<br>|
|Output noise<br>~~ee~~<br>~~a~~|@30 kHz, 60–150 mA load Co= 2.2 µF<br>@100 kHz, 60–150 mA load Co= 2.2 µF<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|60<br>35<br>~~ee~~|–<br>nV/ _Hz_<br>~~ee~~|
|PSRR<br>~~a~~|@1 kHz, Vin≥ (Vo+ 0.15V), Co= 4.7 μF|20<br>~~ee~~|–<br>~~ee~~|–|dB|
|LDO turn-on time<br>~~a~~<br>~~a~~|LDO turn-on time when rest of chip is up|–<br>~~ee~~|140<br>~~ee~~|180|µs|
|External output capacitor, Co<br>~~a~~|Total ESR (trace/capacitor): 5 mΩ–240 mΩ|0.5[44]|2.2|4.7|µF|
|External input capacitor<br>~~a~~|Only use an external input capacitor at the VDD_LDO pin<br>if it is not supplied from CBUCK output. Total ESR (trace/<br>capacitor): 30 mΩ–200 mΩ|–|1|2.2|µF|



## **Note** 

44. Minimum capacitor value refers to the residual capacitor value after taking into account the part-to-part tolerance, DC-bias, temperature, and aging. 

Document Number: 002-30348 Rev. *D 

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**CYW43439** 

## **17.  System Power Consumption** 

**Note:** The values in this data sheet are design goals and are subject to change based on device characterization.Unless otherwise stated, these values apply for the conditions specified in Table 23: “Recommended Operating Conditions and DC Characteristics” . 

## **17.1  WLAN Current Consumption** 

Table 38 shows typical currents consumed by the CYW43439’s WLAN section. All values shown are with the Bluetooth core in Reset mode with Bluetooth is OFF. 

## _17.1.1  2.4 GHz Mode_ 

**Table 38. 2.4 GHz Mode WLAN Power Consumption** 

|**Mode**<br>~~a~~|**Rate**<br>~~a~~<br>~~**e**e~~|**VBAT = 3.6V, VDDIO = 1.8V, TA 25°C**<br>~~po~~<br>~~a~~<br>~~ee~~|**VBAT = 3.6V, VDDIO = 1.8V, TA 25°C**<br>~~po~~<br>~~a~~<br>~~ee~~|
|---|---|---|---|
|||**VBAT (mA)**<br>~~a~~<br>~~ee~~|**Vio** **(μA)**[46]<br>~~a~~<br>~~ee~~|
|**Sleep Modes**<br>~~a~~<br>~~**e**e~~<br>~~ee~~<br>~~C~~||||
|Leakage (OFF)[45]<br>~~GG~~|N/A<br>~~GG~~|0.0035<br>~~GG~~|0.08<br>~~GG~~|
|Sleep (idle, unassociated)[47]<br>~~GG~~<br>~~GG~~|N/A<br>~~GG~~<br>~~GG~~|0.0058<br>~~GG~~<br>~~GG~~|98<br>~~GG~~<br>~~GG~~|
|Sleep (idle, associated, inter-beacons)[48]<br>~~GG~~|Rate 1<br>~~GG~~|0.0058<br>~~GG~~|98<br>~~GG~~|
|IEEE Power Save PM1 DTIM1 (Avg.)[49]<br>~~GG~~<br>~~GG~~|Rate 1<br>~~GG~~<br>~~GG~~|1.19<br>~~GG~~<br>~~GG~~|83<br>~~GG~~<br>~~GG~~|
|IEEE Power Save PM1 DTIM3 (Avg.)[50]<br>~~GG~~|Rate 1<br>~~GG~~|0.48<br>~~GG~~|87<br>~~GG~~|
|IEEE Power Save PM2 DTIM1 (Avg.)[49]<br>~~GG~~<br>~~GG~~|Rate 1<br>~~GG~~<br>~~GG~~|1.27<br>~~GG~~<br>~~GG~~|83<br>~~GG~~<br>~~GG~~|
|IEEE Power Save PM2 DTIM3 (Avg.)[50]<br>~~GG~~|Rate 1<br>~~GG~~|0.44<br>~~GG~~|98<br>~~GG~~|
|**Active Modes**<br>~~GG~~<br>~~PT~~||||
|Rx Listen Mode[51]<br>~~GG~~|N/A<br>~~GG~~|37<br>~~GG~~|12<br>~~GG~~|
|Rx Active (at –50dBm RSSI)[52]<br>~~GG~~|Rate 1<br>~~GG~~<br>~~a~~|37<br>~~GG~~|12<br>~~GG~~|
||Rate 11<br>~~ee~~|40<br>~~ee~~|12<br>~~ee~~|
||Rate 54<br>~~ee~~<br>~~ee~~|40<br>~~ee~~<br>~~ee~~|12<br>~~ee~~<br>~~ee~~|
||Rate MCS7<br>~~ee~~|43<br>~~ee~~|12<br>~~ee~~|
|Tx[52]|Rate 1 @ 19.5 dBm<br>~~ee~~<br>~~a~~|320<br>~~ee~~|15<br>~~ee~~|
||Rate 11 @ 19.5 dBm<br>~~ee~~|318<br>~~ee~~|15<br>~~ee~~|
||Rate 54 @ 16.5 dBm<br>~~ee~~<br>~~ee~~|282<br>~~ee~~<br>~~ee~~|15<br>~~ee~~<br>~~ee~~|
||Rate MCS7 @ 16 dBm<br>~~es~~|271<br>~~es~~|15<br>~~es~~|



## **Notes** 

45. Leakage (OFF) mode are the BT_REG_ON and WL_REG_ON low . 

46. VIO is specified with all pins idle (not switching) and not driving any loads. 

47. Device is initialized in Sleep mode, but not associated 

48. Device is associated, and then enters Power Save mode (idle between beacons). 

49. Beacon interval = 100 ms; beacon duration = 1 ms @ 1 Mbps (Integrated Sleep + wakeup + beacon). 

50. Beacon interval = 300 ms; beacon duration = 1 ms @ 1 Mbps (Integrated Sleep + wakeup + beacon). 

51. Carrier sense (CCA) when no carrier present. 

52. Tx output power is measured on the chip-out side; duty cycle =100%. Tx Active mode is measured in Packet Engine mode (pseudo-random data) 

Document Number: 002-30348 Rev. *D 

Page 74 of 87 

**CYW43439** 

## **17.2  Bluetooth Consumption** 

The Bluetooth current consumption measurements are shown in Table 39. 

## **Note:** 

- The WLAN core is in reset (WLAN_REG_ON = low) for all measurements provided in Table 39. 

- The BT current consumption numbers are measured based on GFSK TX output power = 10 dBm. 

**Table 39. Bluetooth Current Consumption** 

|**Operating Mode**|**VBAT (VBAT = 3.6V)**<br>**Typical**|**VDDIO (VDDIO = 1.8V)**<br>**Typical**<br>~~G~~|**Units**|
|---|---|---|---|
|Sleep<br>~~a~~|6<br>~~a~~|150<br>~~a~~<br>~~G~~|μA<br>~~a~~|
|Standard 1.28s Inquiry Scan<br>~~a~~<br>~~eG~~|193<br>~~a~~<br>~~eG~~|162<br>~~a~~<br>~~G~~<br>~~eG~~|μA<br>~~a~~<br>~~eG~~|
|500 ms Sniff Master<br>~~a~~|305|172|μA|
|DM1/DH1 Master<br>~~a~~<br>~~eG~~|23.3<br>~~eG~~|–<br>~~eG~~|mA<br>~~eG~~|
|DM3/DH3 Master<br>~~a~~|28.4|–|mA|
|DM5/DH5 Master<br>~~a~~<br>~~eG~~|29.1<br>~~eG~~|–<br>~~eG~~|mA<br>~~eG~~|
|3DH5/3DH5 Master<br>~~a~~|25.1|–|mA|
|SCO HV3 Master<br>~~a~~<br>~~eG~~|11.8<br>~~eG~~|–<br>~~eG~~|mA<br>~~eG~~|
|BLE Scan[53]<br>~~a~~|187|164|μA|
|BLE Adv. – Unconnectable 1.00 sec<br>~~a~~<br>~~eG~~|93<br>~~eG~~|163<br>~~eG~~<br>~~G~~|μA<br>~~eG~~|
|BLE Connected 1 sec<br>~~a~~|71<br>~~a~~|163<br>~~a~~<br>~~G~~|μA<br>~~a~~|



**Note** 53. No devices present. A 1.28 second interval with a scan window of 11.25 ms. 

Document Number: 002-30348 Rev. *D 

Page 75 of 87 

**CYW43439** 

## **18.  Interface Timing and AC Characteristics** 

**Note:** Values in this data sheet are design goals and are subject to change based on the results of device characterization. 

Unless otherwise stated, the specifications in this section apply when the operating conditions are within the limits specified in Table 21 and Table 23. Functional operation outside of these limits is not guaranteed. 

## **18.1  SDIO Default Mode Timing** 

SDIO default mode timing is shown by the combination of Figure 29 and Table 40. 

**Figure 29. SDIO Bus Timing (Default Mode)** 

**==> picture [303 x 199] intentionally omitted <==**

**----- Start of picture text -----**<br>
f P P<br>t W L t W H<br>S D IO _ C L K<br>t T H L t T LH<br>t IS U t IH<br>In p u t<br>O u tp u t<br>t O D LY t O D LY<br>(m ax ) (m in)<br>**----- End of picture text -----**<br>


**Table 40. SDIO Bus Timing[[54]] Parameters (Default Mode)** 

|**Parameter**<br>~~pf~~|**Symbol**<br>~~pf~~|**Minimum**<br>~~pf~~|**Typical**<br>~~pf~~|**Maximum**<br>~~pf~~|**Unit**<br>~~pf~~|
|---|---|---|---|---|---|
|**SDIO CLK (All values are referred to minimum VIH and maximum VIL[55])**<br>~~GO~~||||||
|Frequency—Data Transfer mode<br>~~Ce~~|fPP<br>~~Ce~~|0<br>~~Ce~~<br>~~GO~~<br>~~GO~~|–<br>~~Ce~~<br>~~GO~~<br>~~GO~~|25<br>~~Ce~~<br>~~GO~~<br>~~GO~~|MHz<br>~~Ce~~|
|Frequency—Identification mode<br>~~GO~~|fOD<br>~~GO~~|0<br>~~GO~~<br>~~GO~~<br>~~GO~~<br>~~GO~~|–<br>~~GO~~<br>~~GO~~<br>~~GO~~<br>~~GO~~|400<br>~~GO~~<br>~~GO~~<br>~~GO~~<br>~~GO~~|kHz<br>~~GO~~|
|Clock low time<br>~~CO~~|tWL<br>~~CO~~|10<br>~~GO~~<br>~~CO~~<br>~~GO~~|–<br>~~GO~~<br>~~CO~~<br>~~GO~~|–<br>~~GO~~<br>~~CO~~<br>~~GO~~|ns<br>~~CO~~|
|Clock high time<br>~~GO~~|tWH<br>~~GO~~|10<br>~~GO~~<br>~~GO~~<br>~~GO~~|–<br>~~GO~~<br>~~GO~~<br>~~GO~~|–<br>~~GO~~<br>~~GO~~<br>~~GO~~|ns<br>~~GO~~|
|Clock rise time<br>~~CO~~|tTLH<br>~~CO~~|–<br>~~CO~~<br>~~GO~~<br>~~GO~~|–<br>~~CO~~<br>~~GO~~<br>~~GO~~|10<br>~~CO~~<br>~~GO~~<br>~~GO~~|ns<br>~~CO~~|
|Clock fall time<br>~~ee~~|tTHL<br>~~ee~~|–<br>~~GO~~<br>~~ee~~<br>~~GO~~|–<br>~~GO~~<br>~~ee~~<br>~~GO~~|10<br>~~GO~~<br>~~ee~~<br>~~GO~~|ns<br>~~ee~~|
|**Inputs: CMD, DAT (referenced to CLK)**<br>~~GO~~<br>~~pn~~||||||
|Input setup time<br>~~GO~~|tISU<br>~~GO~~|5<br>~~GO~~|–<br>~~GO~~|–<br>~~GO~~|ns<br>~~GO~~|
|Input hold time<br>~~pO~~|tIH<br>~~pO~~|5<br>~~pO~~|–<br>~~pO~~|–<br>~~pO~~|ns<br>~~pO~~|
|**Outputs: CMD, DAT (referenced to CLK)**<br>~~pe~~<br>~~(OO~~||||||
|Output delay time—Data Transfer mode<br>~~CO~~|tODLY<br>~~CO~~|0<br>~~CO~~<br>~~(OO~~|–<br>~~CO~~<br>~~(OO~~|14<br>~~CO~~<br>~~(OO~~|ns<br>~~CO~~|
|Output delay time—Identification mode<br>~~pf~~|tODLY<br>~~pf~~|0<br>~~(OO~~<br>~~pf~~|–<br>~~(OO~~<br>~~pf~~|50<br>~~(OO~~<br>~~pf~~|ns<br>~~pf~~|



55. min(Vih) = 0.7 × VDDIO and max(Vil) = 0.2 × VDDIO. 

Document Number: 002-30348 Rev. *D 

Page 76 of 87 

**CYW43439** 

## **18.2  SDIO High-Speed Mode Timing** 

SDIO high-speed mode timing is shown by the combination of Figure 30 and Table 41. 

**Figure 30. SDIO Bus Timing (High-Speed Mode)** 

**==> picture [246 x 218] intentionally omitted <==**

**----- Start of picture text -----**<br>
fPP<br>tWL tWH<br>50% VDD<br>\<br>SDIO_CLK<br>tTHL tTLH<br>tISU tIH<br>Input<br>Output<br>a<br>__ tODLY aPL tOH<br>**----- End of picture text -----**<br>


**Table 41. SDIO Bus Timing[[56]] Parameters (High-Speed Mode)** 

|**Parameter**<br>~~rs~~<br>~~RC~~|**Symbol**<br>~~rs~~<br>~~rs~~<br>|**Minimum**<br>~~rs~~<br>~~rs~~<br>|**Typical**<br>~~rs~~<br>|**Maximum**<br>~~rs~~<br>|**Unit**<br>~~rs~~<br>|
|---|---|---|---|---|---|
|**SDIO CLK (all values are referred to minimum VIH and maximum VIL[57])**<br>~~rs~~<br>~~rsrs~~<br>~~RC~~<br>~~errr tr~~||||||
|Frequency – Data Transfer Mode<br>~~RCrs~~|fPP<br>~~rs ~~<br>~~rs~~<br>~~errr tr~~<br>~~I~~|0<br> ~~rs~~<br>~~rs~~<br>~~tr~~|–<br>~~rs~~|50<br>~~rs~~|MHz<br>~~rs~~|
|Frequency – Identification Mode<br>~~rs~~<br>~~ts~~|fOD<br>~~rs~~<br>~~errr tr~~<br>~~ts~~<br>~~I~~<br>~~rr~~|0<br>~~rs~~<br>~~tr~~<br>~~ts~~<br>~~rs~~|–<br>~~rs~~<br>~~ts~~|400<br>~~rs~~<br>~~ts~~|kHz<br>~~rs~~<br>~~ts~~|
|Clock low time<br>~~rr~~|tWL<br>~~I~~<br>~~rr~~<br>~~rr~~<br>~~rs~~|7<br>~~rr~~<br>~~rs~~<br>~~rr~~|–<br>~~rr~~<br>~~es~~|–<br>~~rr~~<br>~~I~~|ns<br>~~rr~~|
|Clock high time<br>~~rs~~|tWH<br>~~rr~~<br>~~rs~~<br>~~rs~~<br>~~rs~~|7<br>~~rs~~<br>~~rs~~<br>~~rr~~<br>~~rs~~|–<br>~~rs~~<br>~~es~~|–<br>~~rs~~<br>~~I~~|ns<br>~~rs~~|
|Clock rise time<br>~~rs~~<br>~~rrr~~|tTLH<br>~~rs~~<br>~~rs~~<br>~~rrr~~<br>~~rs~~<br>~~rs~~|–<br>~~rs~~<br>~~rr ~~<br>~~rrr~~<br>~~rs~~<br>~~rr~~|–<br>~~rs~~<br> ~~es ~~<br>~~rrr~~<br>~~ns~~|3<br>~~rs~~<br> ~~I~~<br>~~rrr~~<br>~~OU~~|ns<br>~~rs~~<br>~~rrr~~|
|Clock fall time<br>~~rs~~|tTHL<br>~~rs ~~<br>~~rs~~<br>~~rs~~|–<br> ~~rs~~<br>~~rs~~<br>~~rr~~|–<br>~~rs~~<br>~~ns~~|3<br>~~rs~~<br>~~OU~~|ns<br>~~rs~~|
|**Inputs: CMD, DAT (referenced to CLK)**<br>~~rs~~<br>~~rs~~<br>~~rr~~<br>~~ns OU~~<br>~~|~~<br>~~rsrr~~<br>~~rsI~~||||||
|Input setup time<br>~~rs~~|tISU<br>~~rs~~<br>~~rs~~<br>~~es~~|6<br>~~rs~~<br>~~rr~~<br>~~re~~|–<br>~~rs~~<br>~~rs~~|–<br>~~rs~~<br>~~I~~|ns<br>~~rs~~|
|Input hold time<br>~~rs~~<br>~~rr~~|tIH<br>~~rs~~<br>~~rs ~~<br>~~rr~~<br>~~es~~|2<br>~~rs~~<br> ~~rr~~<br>~~rr~~<br>~~re~~|–<br>~~rs~~<br>~~rs ~~<br>~~rr~~|–<br>~~rs~~<br> ~~I~~<br>~~rr~~|ns<br>~~rs~~<br>~~rr~~|
|**Outputs: CMD, DAT (referenced to CLK)**<br>~~es re~~<br>~~|~~<br>~~rr~~||||||
|Output delay time – Data Transfer Mode<br>~~|~~<br>~~rs~~|tODLY<br>~~|~~<br>~~rs~~<br>~~rr~~<br>~~rs~~|–<br>~~|~~<br>~~rs~~<br>~~rr~~|–<br>~~|~~<br>~~rs~~<br>~~es~~|14<br>~~|~~<br>~~rs~~<br>~~I~~|ns<br>~~|~~<br>~~rs~~|
|Output hold time<br>~~rs~~|tOH<br>~~rr~~<br>~~rs~~<br>~~rs~~<br>~~rr~~|2.5<br>~~rs~~<br>~~rr~~<br>~~rr~~|–<br>~~rs~~<br>~~es~~|–<br>~~rs~~<br>~~I~~|ns<br>~~rs~~|
|Total system capacitance (each line)<br>~~rs~~<br>~~rs~~|CL<br>~~rs~~<br>~~rs~~<br>~~rs~~<br>~~rr~~|–<br>~~rs~~<br>~~rr ~~<br>~~rs~~<br>~~rr~~|–<br>~~rs~~<br> ~~es ~~<br>~~rs~~|40<br>~~rs~~<br> ~~I~~<br>~~rs~~|pF<br>~~rs~~<br>~~rs~~|



57. min(Vih) = 0.7 × VDDIO and max(Vil) = 0.2 × VDDIO. 

Document Number: 002-30348 Rev. *D 

Page 77 of 87 

**CYW43439** 

## **18.3  gSPI Signal Timing** 

The gSPI device always samples data on the rising edge of the clock. 

**Figure 31. gSPI Timing** 

**==> picture [400 x 143] intentionally omitted <==**

**----- Start of picture text -----**<br>
T1<br>T2<br>T4 T5<br>SPI_CLK<br>f F N y Ve st<br>T6 T7<br>SPI_DIN<br>T8 T9<br>SPI_DOUT<br>(falling edge)<br>T3<br>**----- End of picture text -----**<br>


**Table 42. gSPI Timing Parameters** 

|**Parameter**<br>~~I~~|**Symbol**|**Minimum**<br>~~TET~~|**Maximum**<br>~~TET~~|**Units**<br>~~TET~~|**Note**|
|---|---|---|---|---|---|
|Clock period<br>~~OO~~|T1<br>~~OO~~|20.8<br>~~OO~~<br>~~TET~~|–<br>~~OO~~<br>~~TET~~|ns<br>~~OO~~<br>~~TET~~|Fmax= 50 MHz<br>~~OO~~|
|Clock high/low<br>~~a~~|T2/T3<br>~~a~~|(0.45 × T1) – T4<br>~~TET~~<br>~~a~~|(0.55 × T1) – T4<br>~~TET~~<br>~~a~~|ns<br>~~TET~~<br>~~a~~|–<br>~~a~~|
|Clock rise/fall time<br>~~GG~~<br>~~ee~~|T4/T5<br>~~GG~~<br>~~ee~~|–<br>~~GG~~<br>~~es~~|2.5<br>~~GG~~<br>~~es~~|ns<br>~~GG~~<br>~~es~~|–<br>~~GG~~|
|Input setup time<br>~~ee~~<br>~~ee~~|T6<br>~~ee~~<br>~~ee~~|5.0<br>~~es~~<br>~~es~~|–<br>~~es~~<br>~~ee~~|ns<br>~~es~~<br>~~ed~~|Setup time, SIMO valid to SPI_CLK active<br>edge|
|Input hold time<br>~~ee ~~<br>~~ee~~<br>~~ee~~|T7<br> ~~ee~~<br>~~ee~~<br>~~ee~~|5.0<br>~~es~~<br>~~es~~<br>~~es ee~~|–<br>~~es~~<br>~~ee~~<br>~~ee~~|ns<br>~~es~~<br>~~ed~~<br>~~ed~~|Hold time, SPI_CLK active edge to SIMO<br>invalid|
|Output setup time<br>~~ee ~~<br>~~ee~~<br>~~ee~~|T8<br> ~~ee~~<br>~~ee~~<br>~~ee~~|5.0<br>~~es~~<br>~~es ee~~<br>~~es~~|–<br>~~ee ~~<br>~~ee~~<br>~~ee~~|ns<br> ~~ed~~<br>~~ed~~<br>~~es~~|Setup time, SOMI valid before SPI_CLK<br>rising|
|Output hold time<br>~~ee~~<br>~~ee~~|T9<br>~~ee~~<br>~~ee~~|5.0<br>~~es ee~~<br>~~es~~|–<br>~~ee ~~<br>~~ee~~|ns<br> ~~ed~~<br>~~es~~|Hold time, SPI_CLK active edge to SOMI<br>invalid|
|CSX to clock[58]<br>~~ee ~~<br>~~a~~|–<br> ~~ee~~<br>~~a~~|7.86<br>~~es~~<br>~~a~~|–<br>~~ee ~~<br>~~a~~|ns<br> ~~es~~<br>~~a~~|CSX fall to 1st rising edge<br>~~a~~|
|Clock to CSX[58]<br>~~SO~~|–<br>~~SO~~|–<br>~~SO~~|–<br>~~SO~~|ns<br>~~SO~~|Last falling edge to CSX high<br>~~SO~~|
|**Note**<br>58. SPI_CSx remains active for entire duration of gSPI read/write/write_read transaction (that is, overall words for multiple word transaction)<br>~~SO~~||||||



## **18.4  JTAG Timing** 

|**Signal Name**<br>~~FCUMrs—S~~|**Period**<br>~~FCUMrs—S~~|**Output**<br>**Maximum**<br>~~FCUMrs—S~~|**Output**<br>**Minimum**<br>~~FCUMrs—S~~|**Setup**<br>~~FCUMrs—S~~|**Hold**<br>~~FCUMrs—S~~|
|---|---|---|---|---|---|
|TCK<br>~~a~~|125 ns<br>~~a~~|–<br>~~a~~|–<br>~~a~~|–<br>~~a~~|–<br>~~a~~|
|TDI<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|20 ns<br>~~a~~<br>~~a~~|0 ns<br>~~a~~<br>~~a~~|
|TMS<br>~~a~~|–<br>~~a~~|–<br>~~a~~|–<br>~~a~~|20 ns<br>~~a~~|0 ns<br>~~a~~|
|TDO<br>~~a~~<br>~~a~~<br>~~Se~~|–<br>~~a~~<br>~~a~~|100 ns<br>~~a~~<br>~~a~~|0 ns<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|
|JTAG_TRST<br>~~Se~~|250 ns|–|–|–|–|



Document Number: 002-30348 Rev. *D 

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**CYW43439** 

## **19.  Power-Up Sequence and Timing** 

## **19.1  Sequencing of Reset and Regulator Control Signals** 

The CYW43439 has two signals that allow the host to control power consumption by enabling or disabling the Bluetooth, WLAN, and internal regulator blocks. These signals are described below. Additionally, diagrams are provided to indicate proper sequencing of the signals for various operational states (see Figure 32 through Figure 35). The timing values indicated are minimum required values; longer delays are also acceptable. 

## **Note:** 

- The WL_REG_ON and BT_REG_ON signals are OR’ed in the CYW43439. The diagrams show both signals going high at the same time (as would be the case if both REG signals were controlled by a single host GPIO). If two independent host GPIOs are used (one for WL_REG_ON and one for BT_REG_ON), then only one of the two signals needs to be high to enable the CYW43439 regulators. 

- The CYW43439 has an internal power-on reset (POR) circuit. The device will be held in reset for a maximum of 110 ms after VDDC and VDDIO have both passed the POR threshold (see Table 23). Wait at least 150 ms after VDDC and VDDIO are available before initiating SDIO accesses. 

- VBAT and VDDIO should not rise faster than 40 µs. VBAT should be up before or at the same time as VDDIO. VDDIO should not be present first or be held high before VBAT is high. 

## _19.1.1  Description of Control Signals_ 

- **WL_REG_ON** : Used by the PMU to power up the WLAN section. It is also OR-gated with the BT_REG_ON input to control the internal CYW43439 regulators. When this pin is high, the regulators are enabled and the WLAN section is out of reset. When this pin is low the WLAN section is in reset. If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled. 

- **BT_REG_ON** : Used by the PMU (OR-gated with WL_REG_ON) to power up the internal CYW43439 regulators. If both the BT_REG_ON and WL_REG_ON pins are low, the regulators are disabled. When this pin is low and WL_REG_ON is high, the BT section is in reset. 

**Note:** For both the WL_REG_ON and BT_REG_ON pins, there should be at least a 10 ms time delay between consecutive toggles (where both signals have been driven low). This is to allow time for the CBUCK regulator to discharge. If this delay is not followed, then there may be a VDDIO in-rush current on the order of 36 mA during the next PMU cold start. 

Document Number: 002-30348 Rev. *D 

Page 79 of 87 

**CYW43439** 

## _19.1.2  Control Signal Timing Diagrams_ 

**Figure 32. WLAN = ON, Bluetooth = ON** 

**==> picture [145 x 157] intentionally omitted <==**

**----- Start of picture text -----**<br>
32.678 kHz<br>Sleep Clock<br>VBAT<br>90% of VH<br>VDDIO<br>~ 2 Sleep cycles<br>WL_REG_ON<br>BT_REG_ON<br>**----- End of picture text -----**<br>


**Figure 33. WLAN = OFF, Bluetooth = OFF** 

**==> picture [52 x 173] intentionally omitted <==**

**----- Start of picture text -----**<br>
32.678 kHz<br>Sleep Clock<br>VBAT<br>VDDIO<br>WL_REG_ON<br>BT_REG_ON<br>**----- End of picture text -----**<br>


Document Number: 002-30348 Rev. *D 

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**CYW43439** 

**==> picture [329 x 195] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 34. WLAN = ON, Bluetooth = OFF<br>32.678 kHz<br>Sleep Clock<br>VBAT<br>90% of VH<br>VDDIO<br>~ 2 Sleep cycles<br>WL_REG_ON<br>BT_REG_ON<br>**----- End of picture text -----**<br>


**Figure 35. WLAN = OFF, Bluetooth = ON** 

**==> picture [145 x 179] intentionally omitted <==**

**----- Start of picture text -----**<br>
32.678 kHz<br>Sleep Clock<br>VBAT<br>90% of VH<br>VDDIO<br>~ 2 Sleep cycles<br>WL_REG_ON<br>BT_REG_ON<br>**----- End of picture text -----**<br>


Document Number: 002-30348 Rev. *D 

Page 81 of 87 

**CYW43439** 

## **20.  Package Information** 

## **20.1  Package Thermal Characteristics** 

**Table 44. Package Thermal Characteristics[[59]]** 

|**Characteristic**|**Value in Still Air**|
|---|---|
|JA(°C/W)|54.75|
|JB(°C/W)|15.38|
|JC(°C/W)|7.16|
|JT(°C/W)|0.04|
|JB(°C/W)|14.21|
|Maximum Junction Temperature Tj (°C)[60]|125|
|Maximum Power Dissipation (W)|1.2|



**Notes** 

59. No heat sink, TA = 70°C. This is an estimate based on a 4-layer PCB that conforms to EIA/JESD51–7 (101.6 mm x 114.3 mm x 1.6 mm) and P = 1.2W continuous dissipation. 

60. Absolute junction temperature limits maintained through active thermal monitoring and dynamic TX duty cycle limiting. 

## _20.1.1  Junction Temperature Estimation and PSI Versus Thetajc_ 

Package thermal characterization parameter PSI-JT (JT) yields a better estimation of actual junction temperature (TJ) versus using the junction-to-case thermal resistance parameter Theta-JC (JC). The reason for this is JC assumes that all the power is dissipated through the top surface of the package case. In actual applications, some of the power is dissipated through the bottom and sides of the package. JT takes into account power dissipated through the top, bottom, and sides of the package. The equation for calculating the device junction temperature is as follows: 

## TJ = TT + P JT 

Where: 

- TJ = junction temperature at steady-state condition, °C 

- TT = package case top center temperature at steady-state condition, °C 

- P = device power dissipation, Watts 

- JT = package thermal characteristics (no airflow), °C/W 

Document Number: 002-30348 Rev. *D 

Page 82 of 87 

**CYW43439** 

## **21.  Mechanical Information** 

Figure 36 shows the mechanical drawing for the CYW43439 WLBGA package. 

## **Figure 36. 63-Ball WLBGA Mechanical Information** 

Document Number: 002-30348 Rev. *D 

Page 83 of 87 

**CYW43439** 

**Figure 37. WLBGA Package Keep-Out Areas—Top View with the Bumps Facing Down** 

Document Number: 002-30348 Rev. *D 

Page 84 of 87 

**CYW43439** 

## **22.  Ordering Information** 

**Table 45. Part Ordering Information** 

|**Part Number[61]**|**Package**|**Description**|**Operating Ambi-**<br>**ent Temperature**|
|---|---|---|---|
|CYW43439KUBG|63-ball WLBGA halogen-free package<br>(4.87 mm x 2.87 mm, 0.40 pitch)|2.4 GHz single-band WLAN<br>IEEE 802.11n + BT 5.2 compliance|–30°C to +70°C|



**Note** 

61. Add “T” to the end of the part number to specify “Tape and Reel.” 

## **26. Additional Information** 

## **26.1  Acronyms and Abbreviations** 

In most cases, acronyms and abbreviations are defined upon first use. For a more complete list of acronyms and other terms used in Cypress documents, go to: http://www.cypress.com/glossary. 

## **26.2  IoT Resources** 

Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software updates. Customers can acquire technical documentation and software from the Cypress Support Community website (http://community.cypress.com/). 

Document Number: 002-30348 Rev. *D 

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**CYW43439** 

## **Document History** 

**Document Title: CYW43439 Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio with Integrated Bluetooth 5.2 Compliance Document Number: 002-30348** 

|**Document Title: CYW43439 Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio with Integrated Bluetooth 5.2 Compliance**<br>**Document Number: 002-30348**|**Document Title: CYW43439 Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio with Integrated Bluetooth 5.2 Compliance**<br>**Document Number: 002-30348**|**Document Title: CYW43439 Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio with Integrated Bluetooth 5.2 Compliance**<br>**Document Number: 002-30348**|**Document Title: CYW43439 Single-Chip IEEE 802.11 b/g/n MAC/Baseband/Radio with Integrated Bluetooth 5.2 Compliance**<br>**Document Number: 002-30348**|
|---|---|---|---|
|**Revision**|**ECN**|**Submission**<br>**Date**|**Description of Change**|
|**|6889096|05/29/2020|New datasheet|
|*A|6975106|11/03/2020|UpdatedTable 25andTable 38.<br>Removed TurboQAM fromTable 2,Table 25andTable 26.<br>Updated Bluetooth 5.0 to Bluetooth 5.2 throughout the document.<br>Removed 5.1 MAC Features section.|
|*B|7108629|03/19/2021|UpdatedFeaturessection.|
|*C|7835932|11/28/2022|Obsolete document.<br>Completing sunset review.|
|*D|7894589|17/04/2023|Reactivating the datasheet.|



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**CYW43439** 

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Document Number: 002-30348 Rev. *D 

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Revised April 17, 2023