Image not available
Illustrative purposes only
CYW20829B0LKMLTXUMA1
Bluetooth Module, Bluetooth LE 5.4, 2 Mbps, -95 dBm, 1.7 to 3.6 V Supply, -30 °C to 85 °C
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: INFINEON
- Product type: Bluetooth Modules & Adaptors
- SVHC: No SVHC (25-Jun-2025)
- Interfaces: I2C, SPI, UART
- Product Range: AIROC Series
- Certifications: -
- Bluetooth Class: -
- Bluetooth Version: Bluetooth LE 5.4
- Supply Voltage Range: 1.7 V to 3.6 V
- Receiver Sensitivity Rx: -95 dBm
- Operating Temperature Range: -30 °C to 85 °C
| Delivery and price | |
|---|---|
| Units per pack | 500 |
| Price | 1.61 € |
| Current stock | 1000+ |
| Lead time | 30 days |
Datasheet
## **CYW20829** A **AIROC™ Bluetooth® LE 5.4 MCU General description** AIROC™ CYW20829 is a high-performance, ultra-low-power and “Secure” MCU + Bluetooth® LE platform, purpose-built for IoT applications. It combines a high-performance microcontroller with Bluetooth® LE (5.4) connectivity, high-performance analog-to-digital conversion audio input, I[2] S/PCM, CAN, LIN for automotive use cases and other standard communication and timing peripherals. CYW20829 employs high level of integration to minimize external components, reducing the device footprint and costs associated with implementing Bluetooth® Low Energy solutions. AIROC™ CYW20829 is the optimal solution for wireless input devices, remotes, keyboards, joysticks, Bluetooth® Mesh, automotive, asset tracking, and Bluetooth® LE IoT applications that need 10 dBm RF output power such as lighting and home automation. ## **Features** ## • **32-bit application core subsystem** - 96-MHz Arm® Cortex®-M33 CPU with single-cycle multiply and memory protection unit (MPU) - ARMv8-M architecture - CMOS 40-nm process - User-selectable core logic operation at either 1.1 V or 1.0 V - Active CPU current slope with 1.1 V core operation - Cortex®-M33: 40 µA/MHz - Active CPU current slope with 1.0 V core operation - Cortex®-M33: 22 µA/MHz - Datawire (DMA) controller with 16 channels - 32-KB cache for greater XIP performance with lower power ## • **Memory subsystem** - 256-KB SRAM with power and data retention control - OTP eFuse array for security provisioning ## • **Bluetooth® Low Energy subsystem** - 2.4-GHz RF transceiver with 50- Ω antenna drive - Digital PHY - Link layer engine supporting master and slave modes - Programmable TX power: up to 10 dBm - RX sensitivity: - LE-1 Mbps: -98 dBm - LE-2 Mbps: -95 dBm - Coded PHY 500 kbps (LE-LR): –101 dBm - Coded PHY 125 kbps (LE-LR): –106 dBm - 5.2-mA TX (0 dBm), 17.2 mA TX (10 dBm), and 5.6 mA RX (LE 1 Mbps) current with 3.0 V supply and using internal buck converter - Link layer engine supports up to 16 connections simultaneously, four are peripheral ## • **Low-power 1.7 V to 3.6 V operation** - Six power modes for fine-grained power management - Deep Sleep mode current of 4.5 µA with 64 KB SRAM retention - On-chip DC-DC buck converter Please read the Important Notice and Warnings at the end of this document page 1 Datasheet www.infineon.com 002-31976 Rev. *F 2023-09-26 **AIROC™ Bluetooth® LE 5.4 MCU** ## Features ## • **Flexible clocking options** - 8-MHz internal main oscillator (IMO) with ±2% accuracy - Ultra-low-power 32-kHz internal low-speed oscillator (ILO) - Two oscillators: High-frequency (24-MHz) for radio PLL and low-frequency (32-kHz watch crystal) for LPO - 48-MHz low power IHO (internal oscillator) - Frequency-locked loop (FLL) for multiplying IMO frequency - Integer and fractional peripheral clock dividers ## • **Quad SPI (QSPI)/serial memory interface (SMIF)** - eXecute-In-Place (XIP) from external quad SPI flash - On-the-fly encryption and decryption - Support for DDR - Supports single, dual, and quad interfaces with throughput up to 384-Mbps ## • **Serial Communication** - Three run-time configurable Serial Communication Blocks (SCBs) - First SCB: Configurable as SPI or I[2] C - Second SCB: Configurable as SPI or UART - Third SCB: Configurable as I[2] C or UART ## • **Audio subsystem** - Two pulse density modulation (PDM) channels and one I[2] S channel with time division multiplexed (TDM) mode ## • **Timing and pulse-width modulation** - Seven 16-bit and two 32-bit Timer/Counter Pulse-Width Modulator (TCPWM) blocks, for MCU. Multiple PWMs needed for color LEDs. - PWM supports center-aligned, edge, and pseudo-random modes ## • **ADC and MIC** - Sigma-delta switched cap ADC for audio and DC measurements ## • **Up to 32 programmable GPIOs** - One I/O port (8 I/Os) enables Boolean operations on GPIO pins; available during system Deep Sleep - Programmable drive modes, strengths, and slew rates - Two overvoltage-tolerant (OVT) pins - Up to six, used for SMIF ## • **Security built into platform architecture** - ROM-based root of trust via uninterruptible “Secure Boot” - Step-wise authentication of execution images - Secure execution of code in execute-only mode for protected routines - All debug and test ingress paths can be disabled - Up to four protection contexts (One available for customer code) - Secure debug support via authenticated debug token - Encrypted image support for external SMIF memory ## • **Cryptography hardware** - Hardware Acceleration for symmetric cryptographic methods and hash functions - True Random Number Generation (TRNG) function ## • **Packages** - 56-QFN 6 mm 6 mm Datasheet 002-31976 Rev. *F 2 2023-09-26 **AIROC™ Bluetooth® LE 5.4 MCU** Eclipse IDE for Modustoolbox™ software ## **Eclipse IDE for Modustoolbox™ software** **Modustoolbox™ software** is Infineon’s comprehensive collection of multi-platform tools and software libraries that enable an immersive development experience for creating converged MCU and wireless systems. It is: - Comprehensive - it has the resources you need - Flexible - you can use the resources in your own workflow - Atomic - you can get just the resources you want Infineon provides a large collection of code **repositories on GitHub** . This includes: - Board support packages (BSPs) aligned with Infineon kits - Low-level resources, including a hardware abstraction layer (HAL) and peripheral driver library (PDL) - Middleware enabling industry-leading features such as Bluetooth® Low Energy, and mesh networks - An extensive set of thoroughly tested **code example applications** **Note** The HAL provides a high-level, simplified interface to configure and use the hardware blocks on Infineon MCUs and SoCs. It is a generic interface that can be used across multiple product families. You can leverage the HAL’s simpler and more generic interface for most of an application, even if one portion requires fine-grained control. ModusToolbox™ software is IDE-neutral and easily adaptable to your workflow and preferred development environment. It includes a Project Creator, a Library Manager, a BSP Assistant, peripheral and library configurators, as well as the optional Eclipse IDE for the ModusToolbox™, as **Figure 1** shows. For information on using Infineon tools, refer to the documentation delivered with ModusToolbox™ software. **Figure 1 ModusToolbox™ software tools** Datasheet 002-31976 Rev. *F 2023-09-26 3 ## **AIROC™ Bluetooth® LE 5.4 MCU** Table of contents ## **Table of contents** **General description ...........................................................................................................................1 Features ...........................................................................................................................................1 Eclipse IDE for Modustoolbox™ software..............................................................................................3 Table of contents...............................................................................................................................4 1 Block diagram ................................................................................................................................5 2 Functional description ....................................................................................................................6** 2.1 CPU and memory subsystem .................................................................................................................................6 **3 System resources..........................................................................................................................10** 3.1 Power system........................................................................................................................................................10 3.2 Bluetooth® LE radio and subsystem ....................................................................................................................14 3.3 Programmable analog-to-digital converter (ADC)..............................................................................................15 3.4 Programmable digital...........................................................................................................................................15 3.5 Fixed-function digital............................................................................................................................................15 3.6 GPIO.......................................................................................................................................................................17 3.7 Special-function peripherals................................................................................................................................18 **4 Power supply considerations.........................................................................................................28 5 Electrical specifications.................................................................................................................29** 5.1 Absolute maximum ratings ..................................................................................................................................29 5.2 Operating conditions............................................................................................................................................30 5.3 Analog peripherals................................................................................................................................................36 5.4 Digital peripherals.................................................................................................................................................38 5.5 Audio subsystem...................................................................................................................................................41 5.6 System resources..................................................................................................................................................44 5.7 Bluetooth® LE........................................................................................................................................................49 **6 Ordering information....................................................................................................................56 7 Packaging ....................................................................................................................................57 8 Acronyms.....................................................................................................................................59 9 Document conventions..................................................................................................................62** 9.1 Units of measure...................................................................................................................................................62 **Revision history ..............................................................................................................................63** Datasheet 002-31976 Rev. *F 4 2023-09-26 **AIROC™ Bluetooth® LE 5.4 MCU** Block diagram ## **1 Block diagram** **Figure 2** shows the major subsystems and a simplified view of their interconnections. The color coding shows the lowest power mode where a block is still functional. For example, the SRAM is functional down to DS-RAM mode. It should also be noted that six SMIF IOs are in addition to the 26 GPIOs listed in **Figure 2** . **==> picture [482 x 225] intentionally omitted <==** **----- Start of picture text -----**<br> CYW20829 SYSCPUSS CPU Subsystem Bluetooth® Low Energy Subsystem<br>M33X1-Bluetooth® LE SWJ, ITM, CTI SWJ, CTI<br>5.4<br>ROM SRAM0 DW ROM SRAM0<br>Cortex [®] -M33 64 KB 256 KB 16 Ch Cortex [®] -M33 448 KB 96 KB<br>System Resources 24-96 MHz 24-48 MHz<br>Sleep Control Power I$,WIC Controller Controller Controller WIC Controller Controller<br>POR BOD<br>REF<br>OVPActive LDOLVD Interconnect (AHB) Bluetooth® LE Interconnect (AHB)<br>Buck<br>RF LDO<br>PA LDO<br>Clock<br>ILOClock ControlWCO MAC<br>IMO WDT Bluetooth® LE 5.4<br>IHO FLL<br>ALTHF<br>Reset<br>Reset Control<br>TestMode Entry<br>Digital DFT Test Modem<br>Analog DFT Bluetooth® LE 5.4<br>SCAN/LBIST<br>MBIST<br>I/O Matrix, Boundary Scan RF/PA<br>Low Power Active/Sleep Power Modes Active/Sleep 1x Smart IO32x GPIOs Bluetooth®/ Bluetooth® LEIncludes ECO<br>DeepSleep<br>Hibernate IO Subsystem<br>IPC IPC<br>GPIO 9x TCPWM 2x SCB I2C,SPI,UART I2C,SPI Keyscan 20x8 1x TDM 2x PDM EFUSE 1024 bit 1x LIN 1x CAN-FD GCI (SECI) for Wi-Fi CoEx UART, 4-wire<br>TIMER,CTR,QD, PWM 1x SCB (DeepSleep) ADC-Microphone MXCRYPTOLITE (XSPI w OTF Encryption) Test & Debug<br>1x SERIAL MEMORY I/F<br>**----- End of picture text -----**<br> **Figure 2 Functional block diagram** AIROC™ CYW20829 devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware. All device interfaces can be permanently disabled (device security) for applications concerned about attacks due to a maliciously reprogrammed device. All programming, debug, and test interfaces are disabled when maximum device security is enabled. The security level is settable by the user. Complete debug-on-chip functionality enables full device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required to fully support debug. The Eclipse IDE for ModusToolbox™ and Integrated Development Environment (IDE) provide fully integrated programming and debug support for these devices. The SWJ (SWD and JTAG) interface is fully compatible with industry-standard third party probes. With the ability to disable debug features, with very robust flash protection, and by allowing customer-proprietary functionality to be implemented in on-chip programmable blocks, CYW20829 provides a very high level of security. Datasheet 002-31976 Rev. *F 5 2023-09-26 **AIROC™ Bluetooth® LE 5.4 MCU** Functional description ## **2 Functional description** The following sections provide an overview of the features, capabilities and operation of each functional block identified in the block diagram in **Figure 2** . For more detailed information, refer to the following documentation: ## • **Board Support Package (BSP) documentation** BSPs are available on **GitHub** . They are aligned with Infineon kits and provide files for basic device functionality such as hardware configuration files, startup code, and linker files. The BSP also includes other libraries that are required to support a kit. Each BSP has its own documentation, but typically includes an API reference such as the example **here** . This **search link** finds all currently available BSPs on the Infineon **GitHub** site. ## • **Hardware Abstraction Layer(HAL) API reference manual** The Infineon HAL provides a high-level interface to configure and use hardware blocks on Infineon MCUs. It is a generic interface that can be used across multiple product families. You can leverage the HAL’s simpler and more generic interface for most of an application, even if one portion requires finer-grained control. The **HAL API Reference** provides complete details. Example applications that use the HAL download it automatically from the GitHub repository. ## **2.1 CPU and memory subsystem** AIROC™ CYW20829 has multiple bus masters, as **Figure 2** shows. They are: CPU, datawire, QSPI, and a Crypto block. Generally, all memory and peripherals can be accessed and shared by all bus masters through multi-layer Arm® AMBA high-performance bus (AHB) arbitration. An interprocessor communication block (IPC) provides communication between the CPU and the Bluetooth® LE sub-system. ## **2.1.1 CPU** The Cortex®-M33 has single-cycle multiply and a memory protection unit (MPU). It can run at up to 96 MHz in LP mode and 48 MHz in ULP mode. This is the main CPU, designed for a short interrupt response time, high code density, and high throughput. Cortex®-M33 implements a version of the Thumb instruction set based on Thumb-2 technology (defined in the **Armv8-M architecture reference manual** ). The main MCU also implements device-level security, safety, and protection features. Cortex®-M33 provides a secure, interruptible boot function. This guarantees that post boot, system integrity is checked and memory and peripheral access privileges are enforced. The CPU has the following power draw, at VDDD = 3.0 V and using the internal buck regulator. ## **Table 1 Active current slope at VDDD = 3.0 V using the internal buck regulator** **System power mode** ULP LP CPU 22 µA/MHz 40 µA/MHz ~~I eee eee~~ The CPU can be selectively placed in Sleep and Deep Sleep power modes as defined by Arm®. The CPU also implements a Deep Sleep RAM (DS-RAM) mode in which almost all the circuits except RAM are powered OFF. Data in RAM is retained to maintain state. Upon exit, the CPU goes through a reset but can use the data in RAM to skip software initialization. The CPU also has nested vectored interrupt controllers (NVIC) for rapid and deterministic interrupt response, and wakeup interrupt controllers (WIC) for CPU wakeup from Deep Sleep power mode. CYW20829 has a debug access port (DAP) that acts as the interface for device programming and debug. An external programmer or debugger (the “host”) communicates with the DAP through the device serial wire debug (SWD) or Joint Test Action Group (JTAG) interface pins. Through the DAP (and subject to device security restrictions), the host can access the device memory and peripherals as well as the registers in the CPU. CPU debug and trace features are as follows: - Six hardware breakpoints and four watchpoints, serial wire viewer (SWV), and printf()-style debugging through the single wire output (SWO) pin. Datasheet 002-31976 Rev. *F 2023-09-26 6 **AIROC™ Bluetooth® LE 5.4 MCU** Functional description ## **2.1.2 Interrupts** The CPU has interrupt request lines (IRQ), with the interrupt source ‘n’ directly connected to IRQn. Each interrupt supports eight configurable priority levels. One system interrupt can be mapped to the CPU non-maskable interrupts (NMI). Multiple interrupt sources are capable of waking the device from Deep Sleep power mode using the WIC. ## **2.1.3 Datawire** Datawire is a light weight DMA controller with 16 channels, which support CPU-independent accesses to memory and peripherals. The descriptors for the channels are in SRAM and the number of descriptors is limited only by the size of the memory. Each descriptor can transfer data in two nested loops with configurable address increments to the source and destination. ## **2.1.4 Cryptography accelerator (Cryptolite)** A combination of HW and SW is able to support several cryptographic functions. Specifically it supports the following functions: - Encryption/decryption - AES-128 hardware accelerator with following supported modes: - Electronic Code Book (ECB) - Cipher Block Chaining (CBC) - Cipher Feedback (CFB) - Output Feedback (OFB) - Counter (CTR) - Hashing - Secure Hash Algorithm (SHA-256) hardware accelerator - Message Authentication Functions (MAC) - Hashed Message Authentication Code (HMAC) acceleration using SHA-256 hardware - True Random Number Generator (TRNG) - Vector unit hardware accelerator - Digital Signature Verification using RSA - Digital Signature Verification using ECDSA ## **2.1.5 Protection units** CYW20829 has multiple types of protection to control erroneous or unauthorized access to memory and peripheral registers. Protection units support memory and peripheral access attributes including address range, read/write, code/data, privilege level, secure/non-secure, and protection context. Protection units are configured at “Secure Boot” to control access privileges and rights for bus masters and peripherals. Up to eight protection contexts (“Secure Boot” is in protection context 0) allow access privileges for memory and system resources to be set by the “Secure Boot” process per protection context by bus master and code privilege level. Multiple protection contexts are available. ## **2.1.6 AES-128** AES-128 component to accelerate block cipher functionality. This functionality supports forward encryption of a single 128 bit block with a 128 bit key. SHA-256 component to accelerate hash functionality. This component supports message schedule calculation for a 512-bit message chunk and processing of a 512-bit message chunk. Datasheet 002-31976 Rev. *F 7 2023-09-26 **AIROC™ Bluetooth® LE 5.4 MCU** Functional description ## **2.1.7 Vector unit (VU)** VU component to accelerate asymmetric key cryptography (for example, RSA and ECC). This component supports large integer multiplication, addition, and so on. TRNG component based on a set of ring oscillators. The TRNG includes a HW health monitor. ## **2.1.8 Controller area network flexible data-rate (CAN FD)** CYW20829 supports the CAN FD controller that supports one CAN FD channel. All CAN FD controllers are compliant with the ISO 11898-1:2015 standard; an ISO 16845:2015 certificate is available. It also implements the time-triggered CAN (TTCAN) protocol specified in ISO 11898-4 (TTCAN protocol levels 1 and 2) completely in hardware. All functions concerning the handling of messages are implemented by the RX and TX handlers. The RX handler manages message acceptance filtering, transfer of received messages from the CAN core to a message RAM, and provides receive-message status. The TX handler is responsible for the transfer of transmit messages from the message RAM to the CAN core, and provides transmit-message status. ## **2.1.9 Local interconnect network (LIN)** CYW20829 contains a LIN channel. Each channel supports transmission/reception of data following the LIN protocol according to ISO standard 17987. Each LIN channel connects to an external transceiver through a 3-pin interface (including an enable function) and supports master and slave functionality. Each block also supports classic and enhanced checksum, along with break detection during message reception and wake-up signaling. Break detection, sync field, checksum calculations, and error interrupts are handled in hardware. ## **2.1.10 Real time clock (RTC)** - Year/Month/Date, Day-of-week, Hour:Minute:Second fields - 12- and 24-hour formats - Automatic leap-year correction ## **2.1.11 Memory** CYW20829 contains the SRAM, ROM, and eFuse memory blocks. - **SRAM** : CYW20829 has 256-KB of SRAM. Power control and retention granularity is 64-KB blocks allowing the user to control the amount of memory retained in Deep Sleep. Memory is not retained in Hibernate mode. - **ROM** : The 64-KB ROM, also referred to as the supervisory ROM (SROM), provides code (ROM Boot) for several system functions. The ROM contains, primarily device initialization and security. ROM code is executed, in protection context 0. - **eFuse** : A one-time programmable (OTP) eFuse array consists of 1024 bits, which are reserved for system use such as Die ID, Device ID, initial trim settings, device life cycle, and security settings. Some of the bits are available for storing security key information and hash values and can be programmed by the user for device security. Each fuse is individually programmed; once programmed (or “blown”), its state cannot be changed. Blowing a fuse transitions it from the default state of ‘0’ to ‘1’. To program an eFuse, VDDIO1 must be at 2.5 V ±5%. Because blowing an eFuse is an irreversible process, programming is recommended only in mass production under controlled factory conditions by Infineon provided provisioning tools. Datasheet 002-31976 Rev. *F 8 2023-09-26 **AIROC™ Bluetooth® LE 5.4 MCU** Functional description ## **2.1.12 Boot code** On a device reset, the boot code in ROM is the first code to execute. This code performs the following: - Device trim setting (calibration) - Setting the device protection units - Setting device access restrictions for secure life cycle states - Configures the Debug Access Port - In secure life cycle supports secure debug via authenticated debug token - Configures the SMIF for external flash access - In secure life cycle validates first user code in external flash by checking its digital signature. Supports OTF decryption of encrypted images in external flash - Copies the application bootstrap from the external flash to SRAM and jumps to the ROM. It cannot be changed and acts as the Root of Trust in a secure system. It should also be noted that the ROM code sets the system clock to 48 MHz IHO source. ## **2.1.13 Memory map** The 32-bit (4 GB) address space is divided into the regions shown in **Table 3** . Note that code can be executed from the Code, and Internal RAM or External flash. |**Table 2**<br>**Address map**||| |---|---|---| |**Address range**|**Name**<br>~~ee~~|**Use**| |0x0000 0000 – 0x1FFF FFFF|Code<br>~~OO~~|Program code region. It includes the exception vector<br>table, which starts at address 0.| |0x2000 0000 – 0x3FFF FFFF|SRAM<br>~~Po~~|Data region| |0x4000 0000 – 0x5FFF FFFF|Peripheral<br>~~—~~|All peripheral registers. Code cannot be executed from<br>this region. Bit-band in this region is not supported.| |0x6000 0000 – 0x8FFF FFFF<br>~~PF~~|External NVM<br>~~ee~~<br>~~PF~~|SMIF/Quad SPI, (see the **“QSPI interface serial**<br>**memory interface (SMIF)”**on page 16 section). Code<br>can be executed from this region.| |0xA000 0000 – 0xDFFF FFFF<br>~~PF~~|External Device<br>~~PF~~|Not used| |0xE000 0000 – 0xE00F FFFF<br>~~PF~~|Private Peripheral Bus<br>~~PF—~~|Provides access to peripheral registers within the CPU<br>core.| |0xE010 0A000 – 0xFFFF FFFF|Device<br>~~ee~~|Device-specific system registers| The device memory map is shown in **Table 3** . |**Table 3**<br>**Internal memory address map**||| |---|---|---| |**Address range**|**Memory type**|**Size**| |0x0000 0000 – 0x0001 0000|ROM|64 KB| |0x2000 0000 - 0x 2004 0000|SRAM|Up to 256 KB| Datasheet 002-31976 Rev. *F 9 2023-09-26 **AIROC™ Bluetooth® LE 5.4 MCU** System resources ## **3 System resources** ## **3.1 Power system** The power system provides assurance that voltage levels are as required for each respective mode and will either delay mode entry (on power-on reset (POR), for example) until voltage levels are as required for proper function or generate resets (brown-out detect (BOD)) when the power supply drops below specified levels. The design guarantees safe chip operation between power supply voltage dropping below specified levels (for example, below 1.7 V) and the reset occurring. There are no voltage sequencing requirements. The VDDD supply (1.7 to 3.6 V) powers an on-chip buck regulator which offers a selectable (1.0Vor 1.16 V) core operating voltage (VCCD). The selection lets users choose between two system power modes: - System Low Power (LP) operates VCCD at 1.1 V and offers high performance, with no restrictions on device configuration. - System Ultra Low Power (ULP) operates VCCD at 1.0 V for exceptional low power, but imposes limitations on clock speeds. The Bluetooth® radio requires 1.1 V for operation. Bluetooth® system may override user core voltage selection when the radio is turned on. System voltage will return to the user selected value automatically once Bluetooth® radio activity is completed. Refer to **“Power supply considerations”** on page 28 for more details. ## **3.1.1 Power modes** CYW20829 can operate in four system and three CPU power modes. These modes are intended to minimize the average power consumption in an application. For more details on power modes and other power-saving configuration options, see the relevant application note, Power modes supported by CYW20829, in the order of decreasing power consumption, are: - System Low Power (LP) - All peripherals and CPU power modes are available at maximum speed - System Ultra Low Power (ULP) - All peripherals and CPU power modes are available, but with limited speed - CPU Active - CPU is executing code in system LP or ULP mode - CPU Sleep - CPU code execution is halted in system LP or ULP mode - CPU Deep Sleep - CPU code execution is halted and system Deep Sleep is requested in system LP or ULP mode - System Deep Sleep - Only low-frequency peripherals are available after both CPUs enter CPU Deep Sleep mode - System Hibernate - Device and I/O states are frozen and the device resets on wakeup - Deep Sleep RAM - only RAM and IO states are retained. All system activity except for select low power peripherals ceases until system exits from this state. The CPU resets upon exit but can skip software initialization since RAM is retained. CPU Active, Sleep, and Deep Sleep are standard Arm®-defined power modes supported by the Arm® CPU instruction set architecture (ISA). System LP, ULP, Deep Sleep, Deep Sleep RAM and Hibernate modes are additional low-power modes supported by the CYW20829. Datasheet 002-31976 Rev. *F 2023-09-26 10 ## **AIROC™ Bluetooth® LE 5.4 MCU** System resources ## **3.1.2 CYW20829 clock system** CYW20829 clock system consists of a combination of oscillators, external clock, and frequency-locked loop. Specifically, the following: - Internal main oscillator (IMO) - Internal low-speed oscillator (ILO) - Watch crystal oscillator (WCO) - System 24-MHz crystal oscillator - External clock input - One frequency-locked loop (FLL) - Internal high-speed oscillator (IHO) Clocks may be buffered and brought out to a pin on a smart I/O port. **Table 4** shows the mapping of port and associated clock group mapped to peripherals. ## **Table 4 Mapping of clock groups to peripherals** |**PCLK**<br>**group**|**Root clock**<br>**(clk_hf)**<br>~~||~~|**Peripherals**<br>~~|TT~~|**Frequency**<br>~~TT~~|**Frequency**<br>~~TT~~|**Description**| |---|---|---|---|---|---| ||||**LP**<br>**(1.1 V Typ)**<br>~~TT~~<br>~~ff~~|**ULP**<br>**(1.0 V Typ)**<br>~~TT~~<br>~~ff~~|| |0|clk_hf0<br>~~| |~~<br>~~a ~~|CPU Trace<br>~~|~~<br>|24 MHz<br>|24 MHz<br>|–| |1|clk_hf1<br>|SCB<br> ~~_~~|96 MHz|48 MHz|Async peripherals: Strobe signals are driven<br>through dividers; Interface clock is<br>generated inside the peripheral with the<br>main group clock.| |||TCPWM|||| |||LIN<br>~~——~~|||| |||CANFD<br>~~_~~|||| |||SMARTIO<br>~~_~~|||| |2|clk_hf0<br>~~a~~|SMIF<br>~~_~~|96 MHz<br>~~ee~~|48 MHz<br>~~ee~~|Direct connection pass through from clk_hf.<br>This clock is not used for interface clock,<br>rather it is used for the MMIO clocks of SMIF,<br>BTSS and CRYPTO. BTSS uses this clock for<br>Master and Slave AHB/MMIO transactions,<br>and SMIF also uses this clock for FAST/SLOW<br>clocks.| |||BTSS|||| |||CRYPTO<br>~~eee~~|||| |3|clk_hf1<br>~~a~~<br>~~—~~<br>~~a~~|PDM<br>~~eee~~<br>~~—~~|96 MHz<br>~~ee~~|48 MHz<br>~~ee~~|Uses PERI ACLK with default div by 2 option,<br>required interface frequencies are obtained<br>by further division inside the peripheral.| |||TDM<br>~~eee~~<br>~~—~~|||| |4|clk_hf2<br>~~a ~~<br>~~—~~<br>~~a~~|BTSS<br> ~~eee~~<br>~~—~~|48 MHz<br>~~ee~~|48 MHz<br>~~ee~~|RPU clock for BTSS| |5|clk_hf3|ADCMIC|24 MHz|24 MHz|Direct connection for ADCMIC, main source of<br>clk_hf3 is clk_althf which is the BTSS ECO<br>clock.| |6|clk_hf1|SMIF|96 MHz|48 MHz|Direct connection for SMIF and SMARTIO<br>peripherals. This clock is an interface clocks<br>for these peripherals.| Datasheet 002-31976 Rev. *F 11 2023-09-26 **AIROC™ Bluetooth® LE 5.4 MCU** System resources ## **3.1.3 Internal main oscillator (IMO)** The IMO is the primary source of internal clocking. It is trimmed during testing to achieve the specified accuracy. The IMO default frequency is 8 MHz and tolerance is ±2%. ## **3.1.4 Internal low-speed oscillator (ILO)** The ILO is a very low power oscillator, nominally 32 kHz, which operates in all power modes. The ILO can be calibrated against a higher accuracy clock for better accuracy. **==> picture [423 x 442] intentionally omitted <==** **----- Start of picture text -----**<br> Primary mux Path mux Root mux<br>(FLL/PLL)<br>FLL CSV_HF0<br>(optional)<br>clk_ext (optional) Predivider clk_hf0<br>clk_path0 (1/2/4/8) dsi_in0<br>io_clk_hf_out[0]<br>clk_path<P+1><br>clk_althf<br>(optional) CSV_HF1<br>(optional)<br>... (D+P) ... (D) Predivider clk_hf1<br>(1/2/4/8) dsi_in1<br>clk_path<P+D> io_clk_hf_out[1]<br>IHO ... (R)<br>clk_ref_hf CSV_HF<R-1><br>(optional)<br>Predivider clk_hf<R-1><br>(1/2/4/8) dsi_in<R-1><br>io_clk_hf_out[R-1]<br>Active domain<br>DeepSleep domain<br>IMO clk_imo<br>-<br>MF<br>a Prescaler clk_mf(see ver note)<br>clk_lf<br>J<br>LEGEND<br>Active<br>DeepSleep domain LS LS<br>Backup/Hibernate/ DeepSleep<br>HV domain 0 Hibernate/HV<br>ILO0<br>clk_ilo0_hv<br>WCO<br>- clk_wco_hv j — clk_bak_hv<br>(optional)<br>PILO<br>_ clk_pilo<br>(optional)<br>Yellow muxes are glitch safe, white ones are combinational. D = # of direct select paths (>0)P = # of PLLs (>=0) By default, all clocks are off except the IMO path through clk_path0 to clk_hf0. The predivider is<br>Intermediate clock signals (inputs to muxes) are are provided for asynchronous use in other R = # of clock roots (>0) bypassed.<br>peripherals. Use muxed output clocks for It is assumed that P<=R, since it does not make During XRES:SAFE* modes, clk_hf0 is<br>ee general logic. ee sense to have more PLLs than clock roots bypassed to clk_ext (not shown in pic).<br>**----- End of picture text -----**<br> ## **Figure 3 CYW20829 clocking diagram with corresponding oscillators** **Note** : Using PILO as the ILO clock source will result in longer boot time. Datasheet 002-31976 Rev. *F 2023-09-26 12 **AIROC™ Bluetooth® LE 5.4 MCU** System resources ## **3.1.5 External crystal oscillators (ECO)** **Figure 4** shows all of the external crystal oscillator circuits for CYW20829. The component values shown are typical; check the ECO specifications for the crystal values, and the crystal datasheet for the load capacitor values. The ECO and WCO require balanced external load capacitors. For more information, see the HW design guidelines. Note that its performance is affected by GPIO switching noise. **==> picture [282 x 213] intentionally omitted <==** **----- Start of picture text -----**<br> CYW20829<br>BT_XTALI BT_XTALO P5.1/WCO_IN P5.0/WCO_OUT<br>32.768 kHz<br>24 MHz XTAL XTAL<br>CL / 2 CL / 2 CL / 2 CL / 2<br>ae<br>**----- End of picture text -----**<br> **Figure 4** ## **External oscillator** ## **3.1.6 Watchdog timers (WDT, MCWDT)** CYW20829 has one WDT and two multi-counter WDTs (MCWDTs). The WDT has a 16-bit free-running counter. Each MCWDT has two 16-bit counters and one 32-bit counter, with multiple operating modes. All of the 16-bit counters can generate a watchdog device reset. All of the counters can generate an interrupt on a match event. The WDT is clocked by the ILO. It can do interrupt/wakeup generation in system LP/ULP, Deep Sleep, and Hibernate power modes. The MCWDTs are clocked by LFCLK (ILO or WCO). It can do periodic interrupt/wakeup generation in system LP/ULP and Deep Sleep power modes. ## **3.1.7 Clock dividers** Integer and fractional clock dividers are provided for peripheral use and timing purposes. There are one or more: - 8-bit clock dividers - 16-bit integer clock dividers - 16.5-bit fractional clock dividers - 24.5-bit fractional clock divider ## **3.1.8 Trigger routing** CYW20829 contains a trigger multiplexer block. This is a collection of digital multiplexers and switches that are used for routing trigger signals between peripheral blocks and between GPIOs and peripheral blocks. There are two types of trigger routing. Trigger multiplexers have reconfigurability in the source and destination. There are also hardwired switches called “one-to-one triggers”, which connect a specific source to a destination. The user can enable or disable the route. Datasheet 002-31976 Rev. *F 2023-09-26 13 **AIROC™ Bluetooth® LE 5.4 MCU** System resources ## **3.1.9 Reset** CYW20829 can be reset from a variety of sources: - Power-on reset (POR) to hold the device in reset while the power supply ramps up to the level required for the device to function properly. POR activates automatically at power-up. - Brown-out detect (BOD) reset to monitor the digital voltage supply VDDD and generate a reset if VDDD falls below the minimum required logic operating voltage. - External reset dedicated pin (XRES) to reset the device using an external source. The XRES pin is active LOW. It can be connected either to a pull-up resistor to VDDD, or to an active drive circuit, as **Figure 5** shows. If a pull-up resistor is used, select its value to minimize current draw when the pin is pulled LOW; 10 kΩ is typical. **==> picture [178 x 118] intentionally omitted <==** **----- Start of picture text -----**<br> 1.7 to 3.6 V<br>CYW20829<br>VDDD<br>10 kΩ typ.<br>XRES<br>XRES<br>drive<br>**----- End of picture text -----**<br> ## **Figure 5 XRES connection diagram** - Watchdog Timer (WDT or MCWDT) to reset the device if firmware fails to service it within a specified timeout period. - Software-initiated reset to reset the device on demand using firmware. - Logic-protection fault can trigger an interrupt or reset the device if unauthorized operating conditions occur; for example, reaching a debug breakpoint while executing privileged code. - Hibernate wakeup reset to bring the device out of the system Hibernate low-power mode. Reset events are asynchronous and guarantee reversion to a known state. Some of the reset sources are recorded in a register, which is retained through reset and allows software to determine the cause of the reset. ## **3.2 Bluetooth® LE radio and subsystem** CYW20829 incorporates a Bluetooth® 5.4 LE subsystem (BLESS) that contains the physical layer (PHY) and link layer (LL) engines with an embedded security engine. The Bluetooth® LE SS supports all Bluetooth® LE 5.4 features including LE 2 Mbps, LE Long Range, LE Advertising Extensions, LE Isochronous Channels, Periodic Advertising with Responses (PAwR), Encrypted Advertising Data, LE GATT Security Levels Characteristic and Advertising Coding Selection. Infineon also provides extensive driver library and middleware support for Bluetooth® LE; see **“Eclipse IDE for Modustoolbox™ software”** on page 3. The physical layer consists of the digital PHY and the RF transceiver that transmits and receives Gaussian frequency shift keying (GFSK) packets at 1 or 2 Mbps over a 2.4 GHz ISM band, The device also supports Bluetooth® LE long range, both 500 and 125 kbps speeds. The baseband controller is a composite hardware and firmware implementation that supports both master and slave modes. Key protocol elements, such as HCI and link control, are implemented in firmware. Time-critical functional blocks, such as encryption, CRC, data whitening, and access code correlation, are implemented in hardware (in the LL engine). Datasheet 002-31976 Rev. *F 2023-09-26 14 **AIROC™ Bluetooth® LE 5.4 MCU** System resources The RF transceiver contains an integrated balun, which provides a single-ended RF port pin to drive a 50 Ω antenna via a matching/filtering network. In the receive direction, this block converts the RF signal from the antenna to a digital bit stream after performing GFSK demodulation. In the transmit direction, this block performs GFSK modulation and then converts a digital baseband signal to a radio frequency before transmitting it through the antenna. ## **3.3 Programmable analog-to-digital converter (ADC)** ## **3.3.1 Sigma delta ADC** The ADC block is a single switched-cap Σ-Δ ADC core for audio and DC measurement. It operates at the 12-MHz clock rate and has 32 DC input channels, including eight GPIO inputs. The internal bandgap reference has ±5% accuracy without calibration. Different calibration and digital correction schemes can be applied to reduce ADC absolute error and improve measurement accuracy in DC. One of three internal references may be used for the ADC reference voltage: VDDA, VDDA/2, and an analog reference (AREF). AREF is nominally 1.2 V, trimmed to ±1%. ## **3.4 Programmable digital** - System Deep Sleep operation - Asynchronous or synchronous (clocked) operation - Can be synchronous or asynchronous ## **3.5 Fixed-function digital** ## **3.5.1 Timer/counter/pulse-width modulator (TCPWM) block** - The TCPWM supports the following operational modes: - Timer-counter with compare - Timer-counter with capture - Quadrature decoding - Pulse width modulation (PWM) - Pseudo-random PWM - PWM with dead time - Up, down, and up/down counting modes - Clock pre-scaling (division by 1, 2, 4, ... 64, 128) - Double buffering of compare/capture and period values - Underflow, overflow, and capture/compare output signals - Supports interrupt on: - Terminal count - Depends on the mode; typically occurs on overflow or underflow - Capture/compare - The count is captured to the capture register or the counter value equals the value in the compare register - Complementary output for PWMs - Selectable start, reload, stop, count, and capture event signals for each TCPWM; with rising edge, falling edge, both edges, and level trigger options. The TCPWM has a Kill input to force outputs to a predetermined state. - In this device there are: - Two 32-bit TCPWMs - Seven 16-bit TCPWMs Datasheet 002-31976 Rev. *F 15 2023-09-26 **AIROC™ Bluetooth® LE 5.4 MCU** System resources ## **3.5.2 Serial communication blocks (SCB)** - This product line has three SCBs: - First SCB: Configurable as SPI or I[2] C - Second SCB: Configurable as SPI or UART - Third SCB: Configurable as I[2] C or UART - One SCB (SCB #0) can operate in system Deep Sleep mode with an external clock; this SCB can be either SPI slave or I[2] C slave. - **I[2] C mode** : The SCB can implement a full multi-master and slave interface (it is capable of multimaster arbitration). This block can operate at speeds of up to 1 Mbps (Fast Mode Plus). It also supports EZI2C, which creates a mailbox address range and effectively reduces I[2] C communication to reading from and writing to an array in the memory. The SCB supports a 256-byte FIFO for receive and transmit. The I[2] C peripheral is compatible with I[2] C standard-mode, Fast Mode, and Fast Mode Plus devices. The I[2] C bus I/O is implemented with GPIO in open-drain modes. - **UART mode** : This is a full-feature UART operating at up to 8 Mbps. It supports automotive single-wire interface (LIN), infrared interface (IrDA), and SmartCard (ISO 7816) protocols, all of which are minor variants of the basic UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows the addressing of peripherals connected over common Rx and Tx lines. Common UART functions such as parity error, break detect, and frame error are supported. A 256-byte FIFO allows much greater CPU service latencies to be tolerated. - **SPI mode** : The SPI mode supports full SPI, Secure Simple Pairing (SSP) (essentially adds a start pulse that is used to synchronize SPI Codecs), and Microwire (half-duplex form of SPI). The SPI block supports an EZSPI mode in which the data interchange is reduced to reading and writing an array in memory. The SPI interface operates with a 4-MHz clock. ## **3.5.3 QSPI interface serial memory interface (SMIF)** A serial memory interface is provided, running at up to 48 MHz. It supports single, dual and quad SPI configurations, and supports up to four external memory devices. It supports two modes of operation: - Memory-mapped I/O (MMIO), a command mode interface that provides data access via the SMIF registers and FIFOs - Execute-in-Place (XIP), in which AHB reads and writes are directly translated to SPI read and write transfers. In XIP mode, the external memory is mapped into the CYW20829 internal address space, enabling code execution directly from the external memory. To improve performance, a 32 KB cache is included. XIP mode also supports AES-128 based on-the-fly encryption and decryption, enabling secure storage and access of code and data in the external memory. Datasheet 002-31976 Rev. *F 2023-09-26 16 ## **AIROC™ Bluetooth® LE 5.4 MCU** System resources ## **3.6 GPIO** CYW20829 has up to 32 GPIOs, which implement: - Eight drive strength modes: - Analog input mode (input and output buffers disabled) on some IOs - Input only - Weak pull-up with strong pull-down - Strong pull-up with weak pull-down - Open drain with strong pull-down - Open drain with strong pull-up - Strong pull-up with strong pull-down - Weak pull-up with weak pull-down - Hold mode for latching previous state (used for retaining the I/O state in system Hibernate and deep sleep mode) - Selectable slew rates for dV/dt-related noise control to improve EMI The pins are organized in logical entities called ports, which are up to eight pins in width. Data output and pin state registers store, respectively, the values to be driven on the pins and the input states of the pins. Every pin can generate an interrupt if enabled; each port has an interrupt request (IRQ) associated with it. The port 4 pins are capable of overvoltage-tolerant (OVT) operation, where the input voltage may be higher than VDDD. OVT pins are commonly used with I[2] C, to allow powering the chip OFF while maintaining a physical connection to an operating I[2] C bus without affecting its functionality. GPIO pins can be ganged to source or sink higher values of current. GPIO pins, including OVT pins, may not be pulled up higher than the absolute maximum; see **“Electrical specifications”** on page 29. During power-on and reset, the pins are forced to the analog input drive mode, with input and output buffers disabled, so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network known as the high-speed I/O matrix (HSIOM) is used to multiplex between various peripheral and analog signals that may connect to an I/O pin. In order to get the best performance, the following frequency and drive mode constraints may be applied. The DRIVE_SEL values (refer to **Table 5** ) represent drive strengths. ## **Table 5 DRIVE_SEL values** |**Ports**|**Maximum frequency**|**Drive strength for VDDD 2.7 V**|**Drive strength for VDDD > 2.7 V**| |---|---|---|---| |Ports 0, 1|8 MHz|DRIVE_SEL 2|DRIVE_SEL 3| |Ports 2 to 5|16 MHz; 24 MHz for SPI|DRIVE_SEL 2|DRIVE_SEL 3| Datasheet 002-31976 Rev. *F 17 2023-09-26 **AIROC™ Bluetooth® LE 5.4 MCU** System resources ## **3.7 Special-function peripherals** ## **3.7.1 Audio subsystem** This subsystem consists of the following hardware blocks: - One inter-IC sound (I[2] S) interface - Two pulse-density modulation (PDM) to pulse-code modulation (PCM) decoder channels The I[2] S interface implements two independent hardware FIFO buffers - TX and RX, which can operate in master or slave mode. The following features are supported: - Multiple data formats - I[2] S, left-justified, Time Division Multiplexed (TDM) mode A, and TDM mode B - Programmable channel/word lengths - 8/16/18/20/24/32 bits - Internal/external clock operation. Up to 192 ksps - Interrupt mask events - trigger, not empty, full, overflow, underflow, watchdog - Configurable FIFO trigger level with datawire support The I[2] S interface is commonly used to connect with audio codecs, simple DACs, and digital microphones. The PDM-to-PCM decoder implements a single hardware Rx FIFO that decodes a stereo or mono 1-bit PDM input stream to PCM data output. The following features are supported: - Programmable data output word length - 16/18/20/24 bits - Configurable PDM clock generation. Range from 384 kHz to 3.072 MHz - Droop correction and configurable decimation rate for sampling; up to 48 ksps - Programmable high-pass filter gain - Interrupt mask events - not empty, overflow, trigger, underflow - Configurable FIFO trigger level with DMA support The PDM-to-PCM decoder is commonly used to connect to digital PDM microphones. Up to two microphones can be connected to the same PDM data line. Datasheet 002-31976 Rev. *F 2023-09-26 18 ## **AIROC™ Bluetooth® LE 5.4 MCU** System resources ## **Pinouts** |**Pinouts**|**Pinouts**|| |---|---|---| |**Table 6**<br>**Packages and pin information**||| |**Pin name**<br>**Pin number I/O**<br>**Power domain**<br>**Description**<br>**QFN-56**<br>~~ST~~||| |Microphone||| |MIC_P<br>54<br>I<br>VDDA<br>MIC_N<br>55<br>MIC_BIAS<br>53<br>O<br>Onboard switchingregulator and LDOs<br>VDDQ<br>15<br>I<br>–<br>VCC_BUCK<br>17<br>–<br>LX_BUCK<br>16<br>O<br>–<br>VCCD<br>18<br>–<br>VCCI<br>19<br>I<br>–<br>~~—==~~||Microphone positive input<br>Microphone negative input<br>Microphone bias supply<br>External supply to PMU analog<br>External supply to switchingregulator<br>Switchingregulator output<br>Digital LDO output<br>RF and digital LDO input| |Baseband supply||| |VDDIO_0<br>42<br>I<br>VDDIO_0<br>Supply for GPIO ports<br>VDDIO_1<br>52<br>VDDIO_1<br>Supply for GPIO ports and eFuse programming.<br>See**Table 9**for eFuse programmingrequirements.<br>VDDIO_A<br>7<br>VDDIO_A<br>Supply for analogGPIO ports<br>VDDA<br>56<br>VDDA<br>Analogpower supply voltage<br>~~==>>—~~||| |RF power supply||| |VCCRF<br>20<br>O|–|RFLDO output| |VDDD<br>22<br>I|–|PALDO and sub-system resources supply| |VCCPA_0<br>21<br>O|–|PALDO output| |BT_VCOVDD<br>28<br>I<br>BT_VCOVDD<br>BT_LNAVDD<br>26<br>BT_LNAVDD<br>BT_IFVDD<br>27<br>BT_IFVDD<br>BT_PLLVDD<br>29<br>BT_PLLVDD<br>BT_PAVDD<br>24<br>BT_PAVDD<br>~~==~~||VCO supply<br>LNA supply<br>IFPLL power supply<br>RFPLL and crystal oscillator supply<br>Internal PA supply| |Radio I/O||| |BT_RF<br>25<br>I/O|BT_RF|RF antenna port| |Crystal||| |BT_XTALI<br>30<br>I<br>BT_PLLVDD<br>Crystal oscillator input. Two external load capacitors<br>are required to work with the crystal oscillator. The<br>selection of the load capacitors is XTAL-dependent.<br>BT_XTALO<br>31<br>O<br>Crystal oscillator output<br>~~—}tf~~<br>~~|}.~~||| Datasheet 002-31976 Rev. *F 19 2023-09-26 ## **AIROC™ Bluetooth® LE 5.4 MCU** System resources |**Pin name**|**Pin number **<br>~~|—~~|**I/O**<br>~~—~~<br>~~|~~<br>~~ee~~|**Power domain**<br>~~—~~<br>~~|~~|**Description**| |---|---|---|---|---| ||<br>**QFN-56**<br>~~—~~<br>~~sd~~|||| |GPIO|~~ee~~<br>~~sd~~|~~|~~<br>~~ee~~<br>~~ee~~|~~|~~<br>~~ee~~|| |P0.0|32<br>~~ee~~<br>~~sd~~|I/O<br>~~ee~~<br>~~ee~~|VDDIO<br>~~ee~~|General input and output port.<br>See**Table 7**for alternate functions.| |P0.1|33<br>~~sd~~<br>~~sd~~|||| |P0.2|34<br>~~sd~~|||| |P0.3|35<br>~~sd~~|||| |P0.4|36<br>~~sd~~|||| |P0.5|37<br>~~sd~~<br>~~sd~~|||| |P1.0|38<br>~~sd~~|||| |P1.1|39<br>~~sd~~|||| |P1.2|40<br>~~sd~~|||| |P1.3|41<br>~~sd~~<br>~~sd~~|||| |P1.4|43<br>~~sd~~|||| |P1.5|44<br>~~sd~~|||| |P1.6|45<br>~~sd~~|||| |P2.0|46<br>~~sd~~|||| |P2.1|47<br>~~sd~~|||| |P2.2|48<br>~~sd~~|||| |P2.3|49<br>~~sd~~|||| |P2.4|50<br>~~sd~~|||| |P2.5|51<br>~~sd~~|||| |P3.0|1<br>~~sd~~|||| |P3.1|2<br>~~sd~~|||| |P3.2|3<br>~~sd~~|||| |P3.3|4<br>~~sd~~|||| |P3.4<br>~~—~~|5<br>~~sd~~<br>~~—~~|||| |P3.5<br>~~—~~|6<br>~~—~~|||| |P3.6<br>~~—~~|8<br>~~—sd~~|||| |P3.7|9<br>~~sd~~|||| |P4.0|13<br>~~sd~~|||| |P4.1|14<br>~~sd~~|||| |P5.0/<br>WCO_OUT|10<br>~~|~~|||| |P5.1/WCO_IN|11<br>~~sd~~|||| |P5.2|12<br>~~sd~~|||| |XRES|23<br>~~|~~|I<br>~~|~~||Active-low system reset without internal pull-up<br>resistor| Datasheet 002-31976 Rev. *F 20 2023-09-26 **AIROC™ Bluetooth® LE 5.4 MCU** System resources **==> picture [459 x 302] intentionally omitted <==** **----- Start of picture text -----**<br> 56 55 54 53 52 51 50 49 48 47 46 45 44 43<br>P3.0 | 1 42 VDDIO_0<br>P3.1 | 2 41 | P1.3<br>P3.2 3 40 P1.2<br>P3.3 | 4 39 | P1.1<br>P3.4 5 38 P1.0<br>P3.5 | 6 37 | P0.5<br>VDDIO_A 7 36 P0.4<br>P3.6 | 8 35 | P0.3<br>P3.7 9 34 P0.2<br>P5.0/WCO_OUT | 10 33 | P0.1<br>P5.1/WCO_IN 11 32 P0.0<br>P5.2 I 12 31 I BT_XTALO<br>P4.0 13 30 BT_XTALI<br>P4.1 | 14 29 | BT_PLLVDD<br>15 16 17 18 19 20 21 22 23 24 25 26 27 28<br>**----- End of picture text -----**<br> **Figure 6 Device pinout for 56-QFN package** Datasheet 002-31976 Rev. *F 21 2023-09-26 ## Each port pin has multiple alternate functions. These are defined in **Table 7** . **==> picture [7 x 10] intentionally omitted <==** **==> picture [686 x 382] intentionally omitted <==** **----- Start of picture text -----**<br> |||||||||||||||||||||| |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| |Table 7|Multiple alternate functions|[[1]]| |Port/|Ana-|ACT|ACT|ACT|ACT|ACT|ACT|ACT|ACT|ACT|ACT|ACT|ACT|ACT|ACT|DS|DS| |Pin|log|#0|#1|#4|#5|#6|#7|#8|#9|#10|#11|#12|#13|#14|#15|DS #2|#3|DS #5|#6|DS #7| |P0.0|tcpw|tcpw|pdm|tdm.t|tdm.t|keysc|scb[0| |m[0].l|m[0].l|.|dm_t|dm_r|an.ks|].spi_| |ine_c|ine_c|pdm|x_mc|x_mc|_|selec| |ompl|ompl[|_clk[|k[0]:0|k[0]:0|col[2]|t1:0| |[0]:3|262]:0|1]:0| |P0.1|tcpw|tcpw|pdm|tdm.t|keysc|scb[0| |m[0].l|m[0].l|.|dm_t|an.ks|].spi_| |ine[1]|ine[25|pdm|x_sck|_|selec| |:3|6]:1|_dat|[0]:0|col[3]|t2:0| |a[1]:| |0| |P0.2|tcpw|tcpw|peri.tr|tdm.t|keysc|scb[0|scb[0| |m[0].l|m[0].l|_io_|dm_t|an.ks|].i2c_|].spi_| |ine_c|ine_c|input[|x_fsy|_|scl:0|mosi:| |ompl|ompl[|4]:0|nc[0]:|col[11|0| |[1]:3|256]:1|0|]| |P0.3|tcpw|tcpw|scb[1].|tdm.t|keysc|scb[0|scb[0| |m[0].l|m[0].l|spi_se|dm_t|an.ks|].i2c_|].spi_| |ine[0]|ine[25|lect3:|x_sd[|_|sda:0|miso:| |:4|7]:1|0|0]:0|col[12|0| |]| |P0.4|tcpw|tcpw|srss.e|cpus|scb[1].|peri.tr|tdm.t|keysc|scb[0| |m[0].l|m[0].l|xt_cl|s.|spi_se|_io_|dm_r|an.ks|].spi_| |ine_c|ine_c|k:0|trace|lect2:|input[|x_sck|_|clk:0| |ompl|ompl[|_|0|0]:0|[0]:0|row[0| |[0]:4|257]:1|data[|]| |3]:1| **----- End of picture text -----**<br> ## **Note** 1. The notation for a signal is of the form IPName[x].signal_name[u]:y. IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are more than one signals for a particular signal name, y = Designates copies of the signal name. For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximize utilization of on-chip resources. **Multiple alternate functions**[[1]] _(continued)_ |**Port/**<br>**Pin**|**Ana-**<br>**log**<br>~~CECE~~|**ACT**<br>**#0**<br>~~CECE~~|**ACT**<br>**#1**<br>~~CECE~~|**ACT**<br>**#4**<br>~~CECE~~|**ACT**<br>**#5**<br>~~CECE~~|**ACT**<br>**#6**<br>~~CECE~~|**ACT**<br>**#7**<br>~~CECE~~|**ACT**<br>**#8**<br>~~CECE~~|**ACT**<br>**#9**<br>~~CECE~~|**ACT**<br>**#10**<br>~~CECE~~|**ACT**<br>**#11**<br>~~CECE~~|**ACT**<br>**#12**<br>~~CECE~~|**ACT**<br>**#13**<br>~~CECE~~|**ACT**<br>**#14**<br>~~CECE~~|**ACT**<br>**#15**<br>~~CECE~~|**DS #2**<br>~~CECE~~|**DS**<br>**#3**<br>~~CECE~~|**DS #5**<br>~~CECE~~|**DS**<br>**#6**<br>~~CECE~~|**DS #7**| |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| |P0.5|~~CECE~~|tcpw<br>m[0].l<br>ine[1]<br>:4<br>~~CECE~~|tcpw<br>m[0].l<br>ine[25<br>8]:1<br>~~CECE~~|~~CECE~~|cpus<br>s.<br>trace<br>_<br>data[<br>2]:1<br>~~CECE~~|~~CECE~~|~~CECE~~|scb[1].<br>spi_se<br>lect1:<br>0<br>~~CECE~~|~~CECE~~|peri.tr<br>_io_<br>input[<br>1]:0<br>~~CECE~~|~~CECE~~|tdm.t<br>dm_r<br>x_fsy<br>nc[0]:<br>0<br>~~CECE~~|~~CECE~~|~~CECE~~|smif.<br>spihb<br>_sele<br>ct1<br>~~CECE~~|keysc<br>an.ks<br>_<br>row[1<br>]<br>~~CECE~~|~~CECE~~|~~CECE~~|scb[0<br>].spi_<br>selec<br>t0:0<br>~~CECE~~|| |P1.0|~~CECE~~|tcpw<br>m[0].l<br>ine_c<br>ompl<br>[1]:4<br>~~CECE~~|tcpw<br>m[0].l<br>ine_c<br>ompl[<br>258]:1<br>~~CECE~~|~~CECE~~|cpus<br>s.<br>trace<br>_<br>data[<br>1]:1<br>~~CECE~~|scb[1<br>].<br>uart_<br>cts:0<br>~~CECE~~|~~CECE~~|scb[1].<br>spi_se<br>lect0:<br>0<br>~~CECE~~|~~CECE~~|~~CECE~~|peri.t<br>r_io_<br>outp<br>ut[0]:<br>0<br>~~CECE~~|tdm.t<br>dm_r<br>x_sd[<br>0]:0<br>~~CECE~~|~~CECE~~|~~CECE~~|~~CECE~~|keysc<br>an.ks<br>_<br>row[2<br>]<br>~~CECE~~|~~CECE~~|cpuss<br>.swj_<br>swo_<br>tdo<br>~~CECE~~|~~CECE~~|| |P1.1||tcpw<br>m[0].l<br>ine[0]<br>:5|tcpw<br>m[0].l<br>ine[25<br>9]:1||cpus<br>s.<br>trace<br>_<br>data[<br>0]:1|scb[1<br>].<br>uart_<br>rts:0||scb[1].<br>spi_cl<br>k:0|||peri.t<br>r_io_<br>outp<br>ut[1]:<br>0|||||keysc<br>an.ks<br>_<br>row[3<br>]||cpuss<br>.swj_<br>swdo<br>e_<br>tdi||| |P1.2||tcpw<br>m[0].l<br>ine_c<br>ompl<br>[0]:5|tcpw<br>m[0].l<br>ine_c<br>ompl[<br>259]:1||cpus<br>s.<br>trace<br>_<br>clock<br>:1|scb[1<br>].uart<br>_rx:0|scb[2<br>].i2c_<br>scl:1|scb[1].<br>spi_m<br>osi:0||peri.tr<br>_io_<br>input[<br>2]:0||||||keysc<br>an.ks<br>_<br>row[4<br>]||cpuss<br>.swj_<br>swdi<br>o_tm<br>s||| |P1.3|~~CECE~~|tcpw<br>m[0].l<br>ine[1]<br>:5<br>~~CECE~~|tcpw<br>m[0].l<br>ine[26<br>0]:1<br>~~CECE~~|~~CECE~~|~~CECE~~|scb[1<br>].uart<br>_tx:0<br>~~CECE~~|scb[2<br>].i2c_<br>sda:1<br>~~CECE~~|scb[1].<br>spi_m<br>iso:0<br>~~CECE ~~||peri.tr<br>_io_<br>input[<br>3]:0<br> ~~EEE~~|~~EEE~~|~~EEE~~|~~EEE~~|~~EEE~~|~~EEE~~|keysc<br>an.ks<br>_<br>row[5<br>]<br>~~EEE~~|~~EEE~~|cpuss<br>.clk_s<br>wj_s<br>wclk<br>_tclk<br>~~EEE~~|~~EEE~~|| |P1.4|CPOPEECPEPLCEILEILET|tcpw<br>m[0].l<br>ine_c<br>ompl<br>[1]:5<br>CPOPEECPEPLCEILEILET|tcpw<br>m[0].l<br>ine_c<br>ompl[<br>260]:1<br>CPOPEECPEPLCEILEILET|CPOPEECPEPLCEILEILET|CPOPEECPEPLCEILEILET|CPOPEECPEPLCEILEILET|CPOPEECPEPLCEILEILET|CPOPEECPEPLCEILEILET|CPOPEECPEPLCEILEILET|CPOPEECPEPLCEILEILET|lin[0]<br>.lin_<br>en[1]<br>:0<br>CPOPEECPEPLCEILEILET|CPOPEECPEPLCEILEILET|CPOPEECPEPLCEILEILET|CPOPEECPEPLCEILEILET|CPOPEECPEPLCEILEILET|keysc<br>an.ks<br>_<br>col[4]<br>CPOPEECPEPLCEILEILET|CPOPEECPEPLCEILEILET|CPOPEECPEPLCEILEILET|CPOPEECPEPLCEILEILET|| |**Port/**<br>**Pin**|**Ana-**<br>**log**<br>~~|~~|**ACT**<br>**#0**<br>~~PP~~|**ACT**<br>**#1**<br>~~PP~~|**ACT**<br>**#4**<br>~~PPet~~|**ACT**<br>**#5**<br>~~et~~|**ACT**<br>**#6**<br>~~ettT~~|**ACT**<br>**#7**<br>~~tT~~<br>~~TTP~~|**ACT**<br>**#8**<br>~~tTPT~~<br>~~TTP~~|**ACT**<br>**#9**<br>~~PT~~<br>~~TTP~~|**ACT**<br>**#10**<br>~~PT~~<br>~~TTPTT~~|**ACT**<br>**#11**<br>~~TT~~|**ACT**<br>**#12**<br>~~TTTy~~|**ACT**<br>**#13**<br>~~Ty~~|**ACT**<br>**#14**<br>~~Ty~~|**ACT**<br>**#15**|**DS #2**|**DS**<br>**#3**|**DS #5**|**DS**<br>**#6**|**DS #7**| |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| |P1.5|~~| ~~<br>~~LUTTE~~|tcpw<br>m[0].l<br>ine[0]<br>:6<br> ~~PP~~<br>~~LUTTE~~|tcpw<br>m[0].l<br>ine[26<br>1]:1<br>~~PP~~<br>~~LUTTE~~|~~PP et~~<br>~~LUTTE~~|~~et~~<br>~~LUTTE~~|~~et tT~~<br>~~LUTTE~~|~~tT~~<br>~~LUTTE~~<br>~~TTP~~|~~tT PT~~<br>~~LUTTE~~<br>~~TTP~~|~~PT~~<br>~~LUTTE~~<br>~~TTP~~|~~PT~~<br>~~LUTTE~~<br>~~TTPTT~~|lin[0]<br>.lin_r<br>x[1]:<br>0<br>~~LUTTE~~<br>~~TT~~|~~LUTTE~~<br>~~TTTy~~|~~LUTTE~~<br>~~Ty~~|~~LUTTE~~<br>~~Ty~~|~~LUTTE~~|keysc<br>an.ks<br>_<br>col[5]<br>~~LUTTE~~|~~LUTTE~~|~~LUTTE~~|~~LUTTE~~|| |P1.6|~~LUTTE~~<br>~~TE~~<br>~~LTT~~|tcpw<br>m[0].l<br>ine_c<br>ompl<br>[0]:6<br>~~LUTTE~~<br>~~TE~~<br>~~LTT~~|tcpw<br>m[0].l<br>ine_c<br>ompl[<br>261]:1<br>~~LUTTE~~<br>~~TE~~<br>~~LTT~~|~~LUTTE~~<br>~~TE~~<br>~~LTTEET~~|~~LUTTE~~<br>~~TE~~<br>~~EET~~|~~LUTTE~~<br>~~TE~~<br>~~EET~~|~~LUTTE~~<br>~~TTP~~<br>~~TE~~<br>~~TTT~~|~~LUTTE~~<br>~~TTP~~<br>~~TE~~<br>~~TTT~~|~~LUTTE~~<br>~~TTP~~<br>~~TE~~<br>~~TTT~~|~~LUTTE~~<br>~~TTP TT~~<br>~~TE~~<br>~~TTTTT~~|lin[0]<br>.lin_t<br>x[1]:<br>0<br>~~LUTTE~~<br>~~TT~~<br>~~TE~~<br>~~TT~~|~~LUTTE~~<br>~~TT Ty~~<br>~~TE~~<br>~~TTTy~~|~~LUTTE~~<br>~~Ty~~<br>~~TE~~<br>~~Ty~~|~~LUTTE~~<br>~~Ty~~<br>~~TE~~<br>~~Ty~~|~~LUTTE~~<br>~~TE~~|keysc<br>an.ks<br>_<br>col[6]<br>~~LUTTE~~<br>~~TE~~|srss.<br>cal_<br>wave<br>~~LUTTE~~<br>~~TE~~|~~LUTTE~~<br>~~TE~~|~~LUTTE~~<br>~~TE~~|| |P2.0|~~LTT~~<br>~~LTT~~|~~LTT~~<br>~~LTT~~|~~LTT~~<br>~~LTT~~|~~LTTEET~~<br>~~LTTEET~~|~~EET~~<br>~~EET~~|~~EET~~<br>~~EET~~|~~TTT~~<br>~~TTT~~|~~TTT~~<br>~~TTT~~|~~TTT~~<br>~~TTT~~|~~TTTTT~~<br>~~TTTTT~~|~~TT~~<br>~~TT~~|~~TTTy~~<br>~~TTTy~~|~~Ty~~<br>~~Ty~~|~~Ty~~<br>~~Ty~~|smif.<br>spihb<br>_sele<br>ct0|||||| |P2.1|~~LTT~~<br>~~LTT~~|~~LTT~~<br>~~LTT~~|~~LTT~~<br>~~LTT~~|~~LTT EET~~<br>~~LTTEET~~|~~EET~~<br>~~EET~~|~~EET ~~<br>~~EET~~|~~TTT~~<br>~~TTT~~<br>~~TTP~~|~~TTT~~<br>~~TTT~~<br>~~TTP~~|~~TTT~~<br>~~TTT~~<br>~~TTP~~|~~TTT TT~~<br>~~TTTTT~~<br>~~TTPTT~~|~~TT~~<br>~~TT~~<br>~~TT~~|~~TT Ty~~<br>~~TTTy~~<br>~~TTTy~~|~~Ty~~<br>~~Ty~~<br>~~Ty~~|~~Ty~~<br>~~Ty~~<br>~~Ty~~|smif.<br>spihb<br>_dat<br>a3|||||| |P2.2|~~LTT~~<br>~~LUTTE~~<br>~~LTT~~|~~LTT~~<br>~~LUTTE~~<br>~~LTT~~|~~LTT~~<br>~~LUTTE~~<br>~~LTT~~|~~LTT EET~~<br>~~LUTTE~~<br>~~LTT~~|~~EET~~<br>~~LUTTE~~<br>|~~EET ~~<br>~~LUTTE~~<br>|~~TTT~~<br>~~LUTTE~~<br>~~TTP~~<br>~~TTP~~<br>|~~TTT~~<br>~~LUTTE~~<br>~~TTP~~<br>~~TTP~~<br>|~~TTT~~<br>~~LUTTE~~<br>~~TTP~~<br>~~TTP~~<br>|~~TTT TT~~<br>~~LUTTE~~<br>~~TTPTT~~<br>~~TTPTT~~<br>|~~TT~~<br>~~LUTTE~~<br>~~TT~~<br>~~TT~~<br>|~~TT Ty~~<br>~~LUTTE~~<br>~~TTTy~~<br>~~TTTy~~<br>|~~Ty~~<br>~~LUTTE~~<br>~~Ty~~<br>~~Ty~~<br>|~~Ty~~<br>~~LUTTE~~<br>~~Ty~~<br>~~Ty~~<br>|smif.<br>spihb<br>_dat<br>a2<br>~~LUTTE~~<br>|~~LUTTE~~<br>|~~LUTTE~~<br>|~~LUTTE~~<br>|~~LUTTE~~<br>|| |P2.3|~~LUTTE~~<br>~~LTT~~<br>~~PTET~~|~~LUTTE~~<br>~~LTT~~<br>~~PTET~~|~~LUTTE~~<br>~~LTT~~<br>~~PTET~~|~~LUTTE~~<br>~~LTTEET~~<br>~~PTET~~|~~LUTTE~~<br>~~EET~~|~~LUTTE~~<br>~~EET~~|~~TTP~~<br>~~LUTTE~~<br>~~TTP~~<br>~~EET~~|~~TTP~~<br>~~LUTTE~~<br>~~TTP~~<br>|~~TTP~~<br>~~LUTTE~~<br>~~TTP~~<br>|~~TTP TT~~<br>~~LUTTE~~<br>~~TTPTT~~<br>|~~TT~~<br>~~LUTTE~~<br>~~TT~~<br>|~~TT Ty~~<br>~~LUTTE~~<br>~~TTTy~~<br>|~~Ty~~<br>~~LUTTE~~<br>~~Ty~~<br>|~~Ty~~<br>~~LUTTE~~<br>~~Ty~~<br>|smif.<br>spihb<br>_dat<br>a1<br>~~LUTTE~~<br>|~~LUTTE~~<br>|~~LUTTE~~<br><br>~~EE~~|~~LUTTE~~<br><br>~~EE~~|~~LUTTE~~<br><br>~~EE~~|| |P2.4|~~LTT~~<br>~~PTET~~|~~LTT~~<br>~~PTET~~|~~LTT~~<br>~~PTET~~|~~LTTEET~~<br>~~PTET~~<br>TT|~~EET~~<br>TT|~~EET~~<br>TTTT|~~TTP~~<br>~~EETTTT~~<br>TT|~~TTP~~<br>~~TTT~~<br>TTTE|~~TTP~~<br>~~TTT~~<br>TE|~~TTPTT~~<br>~~TTT~~<br>TEPT|~~TT~~<br>~~TTT~~<br>PT|~~TTTy~~<br>~~TTT~~<br>PTEE|~~Ty~~<br>~~TTT~~<br>EE|~~Ty~~<br>~~TTT~~<br>EE|smif.<br>spihb<br>_dat<br>a0<br>~~TTT~~<br>ET|~~TTT~~<br>ET|~~TTT~~<br>~~EE~~<br>ET|~~TTT~~<br>~~EE~~|~~TTT~~<br>~~EE~~|| |P2.5|~~LTT~~<br>~~PTET~~|~~LTT~~<br>~~PTET~~|~~LTT~~<br>~~PTET~~|~~LTT EET~~<br>~~PTET~~<br>TT|~~EET~~<br>TT|~~EET~~<br>TTTT|~~TTP~~<br>~~EET~~<br>TT|~~TTP~~<br><br>TTTE|~~TTP~~<br><br>TE|~~TTP TT~~<br><br>TEPT|~~TT~~<br><br>PT|~~TT Ty~~<br><br>PTEE|~~Ty~~<br><br>EE|~~Ty~~<br><br>EE|smif.<br>spihb<br>_clk<br><br>ET|ET|~~EE~~<br>ET|~~EE~~|~~EE~~|| **Multiple alternate functions**[[1]] _(continued)_ |**Port/**<br>**Pin**|**Ana-**<br>**log**<br>~~CECE~~|**ACT**<br>**#0**<br>~~CECE~~|**ACT**<br>**#1**<br>~~CECE~~|**ACT**<br>**#4**<br>~~CECE~~|**ACT**<br>**#5**<br>~~CECE~~|**ACT**<br>**#6**<br>~~CECE~~|**ACT**<br>**#7**<br>~~CECE~~|**ACT**<br>**#8**<br>~~CECE~~|**ACT**<br>**#9**<br>~~CECE~~|**ACT**<br>**#10**<br>~~CECE~~|**ACT**<br>**#11**<br>~~CECE~~|**ACT**<br>**#12**<br>~~CECE~~|**ACT**<br>**#13**<br>~~CECE~~|**ACT**<br>**#14**<br>~~CECE~~|**ACT**<br>**#15**<br>~~CECE~~|**DS #2**<br>~~CECE~~|**DS**<br>**#3**<br>~~CECE~~|**DS #5**<br>~~CECE~~|**DS**<br>**#6**<br>~~CECE~~|**DS #7**| |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| |P3.0|adcm<br>ic.gpi<br>o_ad<br>c_in[<br>0]<br>~~CECE~~|tcpw<br>m[0].l<br>ine[0]<br>:0<br>~~CECE~~|tcpw<br>m[0].l<br>ine[25<br>6]:0<br>~~CECE~~|~~CECE~~|cpus<br>s.<br>trace<br>_<br>data[<br>3]:0<br>~~CECE~~|scb[2<br>].uart<br>_cts:0<br>~~CECE~~|~~CECE~~|scb[1].<br>spi_se<br>lect0:<br>1<br>~~CECE~~|~~CECE~~|~~CECE~~|~~CECE~~|~~CECE~~|~~CECE~~|btss.<br>uart_<br>cts:0<br>~~CECE~~|~~CECE~~|keysc<br>an.ks<br>_<br>col[13<br>]<br>~~CECE~~|~~CECE~~|~~CECE~~|~~CECE~~|| |P3.1|adcm<br>ic.gpi<br>o_ad<br>c_in[<br>1]<br>~~CECE~~|tcpw<br>m[0].l<br>ine_c<br>ompl<br>[0]:0<br>~~CECE~~|tcpw<br>m[0].l<br>ine_o<br>mpl[2<br>56]:0<br>~~CECE~~|~~CECE~~|cpus<br>s.<br>trace<br>_<br>data[<br>2]:0<br>~~CECE~~|scb[2<br>].uart<br>_rts:0<br>~~CECE~~|~~CECE~~|scb[1].<br>spi_cl<br>k:1<br>~~CECE~~|~~CECE~~|~~CECE~~|lin[0]<br>.lin_<br>en[0]<br>:0<br>~~CECE~~|~~CECE~~|~~CECE~~|btss.<br>uart_<br>rts:0<br>~~CECE~~|~~CECE~~|keysc<br>an.ks<br>_<br>col[14<br>]<br>~~CECE~~|~~CECE~~|cpuss<br>.rst_s<br>wj_tr<br>stn<br>~~CECE~~|~~CECE~~|| |P3.2|adcm<br>ic.gpi<br>o_ad<br>c_in[<br>2]|tcpw<br>m[0].l<br>ine[1]<br>:0|tcpw<br>m[0].l<br>ine[25<br>7]:0||cpus<br>s.<br>trace<br>_<br>data[<br>1]:0|scb[2<br>].uart<br>_rx:0|scb[2<br>].i2c_<br>scl:0|scb[1].<br>spi_m<br>osi:1|pdm<br>.<br>pdm<br>_clk[<br>0]:0|peri.tr<br>_io_<br>input[<br>6]:0|lin[0]<br>.lin_r<br>x[0]:<br>0|canfd<br>[0].ttc<br>an_rx<br>[0]|adcm<br>ic.clk<br>_pdm<br>:0|btss.<br>uart_<br>rxd:0||keysc<br>an.ks<br>_<br>col[15<br>]||||| |P3.3|adcm<br>ic.gpi<br>o_ad<br>c_in[<br>3]|tcpw<br>m[0].l<br>ine_c<br>ompl<br>[1]:0|tcpw<br>m[0].l<br>ine_o<br>mpl[2<br>57]:0||cpus<br>s.tra<br>ce_d<br>ata[0<br>]:0|scb[2<br>].uart<br>_tx:0|scb[2<br>].i2c_<br>sda:0|scb[1].<br>spi_m<br>iso:1|pdm<br>.<br>pdm<br>_dat<br>a[0]:<br>0|peri.tr<br>_io_i<br>nput[7<br>]:0|lin[0]<br>.lin_t<br>x[0]:<br>0|canfd<br>[0].ttc<br>an_tx<br>[0]|adcm<br>ic.pd<br>m_da<br>ta:0|btss.<br>uart_<br>txd:0||keysc<br>an.ks<br>_<br>col[16<br>]||||| |P3.4|adcm<br>ic.gpi<br>o_ad<br>c_in[<br>4]<br>~~CECE~~|tcpw<br>m[0].l<br>ine[0]<br>:1<br>~~CECE~~|tcpw<br>m[0].l<br>ine[25<br>8]:0<br>~~CECE~~|~~CECE~~|cpus<br>s.<br>trace<br>_cloc<br>k:0<br>~~CECE~~|~~CECE~~|~~CECE~~|scb[1].<br>spi_se<br>lect3:<br>1<br>~~CECE ~~||~~EEE~~|~~EEE~~|~~EEE~~|~~EEE~~|~~EEE~~|~~EEE~~|keysc<br>an.ks<br>_<br>col[7]<br>~~EEE~~|~~EEE~~|~~EEE~~|~~EEE~~|| |P3.5|adcm<br>ic.gpi<br>o_ad<br>c_in[<br>5]<br>CPOPEECPEPLCEILEILET|tcpw<br>m[0].l<br>ine_c<br>ompl<br>[0]:1<br>CPOPEECPEPLCEILEILET|tcpw<br>m[0].l<br>ine_o<br>mpl[2<br>58]:0<br>CPOPEECPEPLCEILEILET|CPOPEECPEPLCEILEILET|CPOPEECPEPLCEILEILET|CPOPEECPEPLCEILEILET|CPOPEECPEPLCEILEILET|scb[1].<br>spi_se<br>lect2:<br>1<br>CPOPEECPEPLCEILEILET|CPOPEECPEPLCEILEILET|CPOPEECPEPLCEILEILET|CPOPEECPEPLCEILEILET|CPOPEECPEPLCEILEILET|CPOPEECPEPLCEILEILET|CPOPEECPEPLCEILEILET|CPOPEECPEPLCEILEILET|keysc<br>an.ks<br>_<br>col[8]<br>CPOPEECPEPLCEILEILET|CPOPEECPEPLCEILEILET|CPOPEECPEPLCEILEILET|CPOPEECPEPLCEILEILET|| **Multiple alternate functions**[[1]] _(continued)_ |**Port/**<br>**Pin**|**Ana-**<br>**log**<br>~~Pee~~|**ACT**<br>**#0**<br>~~Pee~~|**ACT**<br>**#1**<br>~~Pee~~|**ACT**<br>**#4**<br>~~Pee~~|**ACT**<br>**#5**<br>~~Pee~~|**ACT**<br>**#6**<br>~~Pee~~|**ACT**<br>**#7**<br>~~Pee~~|**ACT**<br>**#8**<br>~~Pee~~|**ACT**<br>**#9**<br>~~Pee~~|**ACT**<br>**#10**<br>~~Pee~~|**ACT**<br>**#11**<br>~~Pee~~|**ACT**<br>**#12**<br>~~Pee~~|**ACT**<br>**#13**<br>~~Pee~~|**ACT**<br>**#14**<br>~~Pee~~|**ACT**<br>**#15**<br>~~Pee~~|**DS #2**<br>~~Pee~~|**DS**<br>**#3**<br>~~Pee~~|**DS #5**<br>~~Pee~~|**DS**<br>**#6**<br>~~Pee~~|**DS #7**| |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| |P3.6|adcm<br>ic.gpi<br>o_ad<br>c_in[<br>6]<br>~~EEE~~|tcpw<br>m[0].l<br>ine[1]<br>:1<br>~~EEE~~|tcpw<br>m[0].l<br>ine[25<br>9]:0<br>~~EEE~~|~~EEE~~|~~EEE~~|~~EEE~~|~~EEE~~|scb[1].<br>spi_se<br>lect1:<br>1<br>~~EEE~~|~~EEE~~|~~EEE~~|~~EEE~~|~~EEE~~|~~EEE~~|~~EEE~~|~~EEE~~|keysc<br>an.ks<br>_<br>col[9]<br>~~EEE~~|~~EEE~~|~~EEE~~|~~EEE~~|| |P3.7|adcm<br>ic.gpi<br>o_ad<br>c_in[<br>7]<br>~~EEE~~<br>~~ETE~~|tcpw<br>m[0].l<br>ine_c<br>ompl<br>[1]:1<br>~~EEE~~<br>~~ETE~~|tcpw<br>m[0].l<br>ine_o<br>mpl[2<br>59]:0<br>~~EEE~~<br>~~ETE~~|~~EEE~~<br>~~ETE~~|~~EEE~~<br>~~ETE~~|~~EEE~~<br>~~ETE~~|~~EEE~~<br>~~ETE~~|~~EEE~~<br>~~ETE~~|~~EEE~~<br>~~ETE~~|~~EEE~~<br>~~ETE~~|~~EEE~~<br>~~ETE~~|~~EEE~~<br>~~ETE~~|~~EEE~~<br>~~ETE~~|~~EEE~~<br>~~ETE~~|~~EEE~~<br>~~ETE~~|keysc<br>an.ks<br>_<br>col[10<br>]<br>~~EEE~~<br>~~ETE~~|~~EEE~~<br>~~ETE~~|~~EEE~~<br>~~ETE~~|~~EEE~~<br>~~ETE~~|| |P4.0|~~ETE~~|tcpw<br>m[0].l<br>ine_c<br>ompl<br>[1]:2<br>~~ETE~~|tcpw<br>m[0].l<br>ine_o<br>mpl[2<br>61]:0<br>~~ETE~~|~~ETE~~|~~ETE~~|~~ETE~~|~~ETE~~|~~ETE~~|~~ETE~~|~~ETE~~|~~ETE~~|~~ETE~~|~~ETE~~|~~ETE~~|~~ETE~~|keysc<br>an.ks<br>_<br>row[6<br>]<br>~~ETE~~|scb[0<br>].i2c_<br>scl:1<br>~~ETE~~|~~ETE~~|scb[0<br>].spi_<br>mosi:<br>1<br>~~ETE~~|| |P4.1|~~ETE~~|tcpw<br>m[0].l<br>ine[0]<br>:3<br>~~ETE~~|tcpw<br>m[0].l<br>ine[26<br>2]:0<br>~~ETE~~|~~ETE~~|~~ETE~~|~~ETE~~|~~ETE~~|~~ETE~~|~~ETE~~|~~ETE~~|~~ETE~~|~~ETE~~|~~ETE~~|~~ETE~~|~~ETE~~|keysc<br>an.ks<br>_<br>row[7<br>]<br>~~ETE~~|scb[0<br>].i2c_<br>sda:1<br>~~ETE~~|~~ETE~~|scb[0<br>].spi_<br>miso:<br>1<br>~~ETE~~|| |P5.0/<br>WCO<br>_OUT|PLEETE|tcpw<br>m[0].l<br>ine[0]<br>:2<br>PLEETE|tcpw<br>m[0].l<br>ine[26<br>0]:0<br>PLEETE|srss.e<br>xt_cl<br>k:1<br>PLEETE|PLEETE|scb[2<br>].<br>uart_<br>cts:1<br>PLEETE|~~EEE~~|scb[1].<br>spi_se<br>lect0:<br>2<br>~~EEE~~|pdm<br>.<br>pdm<br>_clk[<br>0]:1<br>~~EEE~~|~~EEE~~|~~EEE~~|~~EEE~~|adcm<br>ic.clk<br>_pdm<br>:1<br>~~EEE~~|btss.<br>uart_<br>cts:1<br>~~EEE~~|~~EEE~~|keysc<br>an.ks<br>_<br>col[17<br>]<br>~~EEE~~|~~EEE~~|~~EEE~~|~~EEE~~|| ## **Note** 1. The notation for a signal is of the form IPName[x].signal_name[u]:y. IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are more than one signals for a particular signal name, y = Designates copies of the signal name. For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximize utilization of on-chip resources. **Table 7 Multiple alternate functions**[[1]] _(continued)_ **Port/ AnaACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT ACT DS DS Pin log #0 #1 #4 #5 #6 #7 #8 #9 #10 #11 #12 #13 #14 #15 DS #2 #3 DS #5 #6 DS #7** P5.1/ tcpw tcpw pdm adcm keysc WCO m[0].l m[0].l . ic.pd an.ks _IN ine_c ine_o pdm m_da _ ompl mpl[2 _dat ta:1 col[0] [0]:2 60]:0 a[0]: 1 ~~ATT~~ P5.2 tcpw tcpw keysc m[0].l m[0].l an.ks ine[1] ine[26 _ :2 1]:0 col[1] **Note** ~~PL~~[EELELLELELELELLEL] 1. The notation for a signal is of the form IPName[x].signal_name[u]:y. IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are more than one signals for a particular signal name, y = Designates copies of the signal name. For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the fourth occurrence (copy) of the signal. Signal copies are provided to allow flexibility in routing and to maximize utilization of on-chip resources. **AIROC™ Bluetooth® LE 5.4 MCU** Power supply considerations ## **4 Power supply considerations** **Figure 7** shows the typical connections for power pins for all supported packages. In the QFN packages, all internal grounds are routed to the metal pad (epad) in the package. This pad must be grounded on the PCB. **Figure 7** refers to 10 dBm PA configuration. For 0 dBm, connect BT_PAVDD to VCCRF. **==> picture [310 x 389] intentionally omitted <==** **----- Start of picture text -----**<br> vbat<br>VDDQ VCCPA_0<br>e y ma 1.0 µF<br>x X] VCC_BUCK<br>+/-30%<br>\/A VDDD<br>VCCRF<br>VDDIO_0 1.0 µF<br>+/-30%<br>VDDIO_1<br>VDDIO_A LX_BUCK<br>VDDA<br>4.7 µH<br>xX] +/-30%<br>10 µF VCCI x]<br>4.7 µF<br>+/-20%<br>SC VSS VCCD x ]<br>0.1 µF<br>2.2 µF<br>+/-30%<br>BT_LNAVDD xX]<br>0.1 µF +/-30%<br>BT_IFVDD xX]<br>0.1 µF +/-30%<br>BT_VCOVDD |<br>0.1 µF +/-30%<br>BT_PLLVDD |<br>0.1 µF +/-30%<br>BT_PAVDD xX]<br>0.1 µF +/-30%<br>**----- End of picture text -----**<br> **Figure 7 CYW20829 power topology** Datasheet 002-31976 Rev. *F 28 2023-09-26 **AIROC™ Bluetooth® LE 5.4 MCU** Electrical specifications ## **5 Electrical specifications** All specifications are valid for -30°C < TA < 85°C and for 1.71 V to 3.6 V except where noted. |**Spec ID# **|**Parameter**<br>~~es~~|**Description**<br>~~st~~|**Min**<br>~~st~~|**Typ**<br>~~st~~|**Max**<br>~~st~~|**Unit **<br>~~st~~|**Details / conditions**| |---|---|---|---|---|---|---|---| |SID1|VDD_ABS<br>~~es~~<br>~~es~~|Analog or digital supply relative to<br>VSS(VSSD= VSSA)<br>~~st~~|–0.5<br>~~st~~|–<br>~~st~~<br>~~e~~e<br>|4<br>~~st~~|V<br>~~st~~<br>~~—|~~|–| |SID2|VCCD_ABS<br>~~es~~<br>~~es~~|Direct digital core voltage input<br>relative to VSSD|–0.5||1.2||Absolute maximum| |SID3|VGPIO_ABS<br>~~es~~<br>~~es~~<br>~~**ee**~~|GPIO voltage; VDDDor VDDA<br>~~ee~~|–0.5||VDD+<br>0.5<br>~~—|~~||| |SID4|IGPIO_ABS<br>~~es~~<br>~~**ee**~~<br>~~es~~|Current per GPIO<br>~~ee~~<br>~~en~~|–25<br>~~ene~~||25<br>~~—|~~|mA<br>~~—|~~<br>~~a~~|| |SID5|IGPIO_injection <br>~~**ee**~~<br>~~es~~<br>~~es~~|GPIO injection current per pin<br>~~ee~~<br>~~en~~<br>~~ee~~|–0.5<br>~~ene~~<br>||0.5<br>~~—|~~<br>~~a~~||| |SID3A|ESD_HBM<br>~~**ee**~~<br>~~es~~<br>~~es~~|Electrostatic discharge human<br>body model<br>~~ee~~<br>~~en~~<br>~~ee~~|2200<br>~~ene~~<br>||–<br>~~—|~~<br>~~a~~|V<br>~~—|~~<br>~~a~~|| |SID4A|ESD_CDM<br>~~es~~<br>~~es~~|Electrostatic discharge charged<br>device model<br><br>~~ee~~|500<br>~~e~~<br>||||| |SID5A|LU<br>~~es~~<br>~~a~~<br>~~**e**s~~|Pin current for latchup-free<br>operation<br>~~ee ~~|–100<br>||100<br> ~~a~~<br>~~="~~|mA<br>~~a~~<br>~~="~~|| |SIDWA8|Vundershoot<br>~~**e**s~~|Maximum undershoot voltage for<br>I/O|–||–0.5<br>~~="~~|V<br>~~="~~<br>~~FL~~|Duration not to<br>exceed 25% of the<br>duty cycle| |SIDWA9|Vovershoot<br>~~**e**s~~<br>~~ee~~|Maximum overshoot voltage for<br>I/O<br>~~s~~|||VDDIO +<br>0.5<br>~~="~~<br>~~FL~~||| |SIDWA10|Tj<br>~~ee~~|Maximum junction temperature|||125<br>~~FL~~|°C<br>~~FL~~|–| ## **Note** > 2. Usage above the absolute maximum conditions listed in **Table 8** may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods of time may affect device reliability. The maximum storage temperature is 150°C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification. Datasheet 002-31976 Rev. *F 2023-09-26 29 **AIROC™ Bluetooth® LE 5.4 MCU** Electrical specifications |SID6|VDDD<br>~~ee~~<br>~~|~~|Internal regulator<br>~~ee~~<br>~~|~~|1.7<br>~~ee~~<br>~~|~~<br>~~ee~~<br>~~|~~|–<br>~~|~~<br>~~|I~~|3.6<br>~~|~~<br>~~I~~|V<br>~~|~~|–| |---|---|---|---|---|---|---|---| |SID7|VDDA<br>~~ee~~<br>~~|~~<br>~~ee~~|Analog power supply voltage.<br>Shorted to VDDIOA on PCB.<br>~~ee~~<br>~~|~~<br>~~ee~~|||||Internally unregulated<br>supply| |SID7M|VDDM<br>~~|~~<br>~~ee~~<br>~~—~~|Microphone supply voltage<br>~~|~~<br>~~ee~~<br>~~—~~|||||| |SID7R|VDDRF<br>~~ee~~<br>~~———~~<br>~~—~~|RF LDO input. Connect to<br>output of internal buck<br>~~ee~~<br>~~———~~<br>~~—~~|–<br>~~ee~~<br>~~———~~<br>~~|~~|1.16<br>~~———~~<br>~~|I~~|–<br>~~———~~<br>~~I~~|–<br>~~———~~|–| |SID7C|VDDC<br>~~———~~<br>~~—~~|Digital LDO input. Connect to<br>output of internal buck<br>~~———~~<br>~~—~~|||||| |SID7P|VDDD<br>~~—~~<br>~~es~~|PA LDO input<br>~~—~~<br>~~ee~~|2.75<br>~~|~~<br>~~ee~~|–<br>~~| I~~<br>~~ee~~<br>~~ee~~|3.6<br>~~I~~<br>~~ee~~|V|| |SID7B|VDDIO_0<br>~~—~~<br>~~ee~~<br>~~es~~|GPIO supply for ports<br>~~—~~<br>~~ee~~<br>~~ee~~|1.7<br>~~|~~<br>~~ee~~<br>~~ee~~||3.6<br>~~I~~<br>~~ee~~<br>~~ee~~||| |SID7E|VDDIO_1<br>~~es~~|Supply when programming<br>eFuse<br>~~ee~~|2.38<br>~~ee~~|2.5<br>~~ee~~|2.62<br>~~ee~~||eFuse programming<br>voltage| |SID7A|VDDIO_A<br>~~es~~<br>~~i~~|GPIO supply for analog ports.<br>Short to VDDAon PCB.<br>~~ee~~<br>~~i~~|1.7<br>~~ee~~<br>~~i~~|–<br>~~ee~~<br>~~i~~|3.6<br>~~ee~~<br>~~i~~|~~i~~|–| |SID8|VCCD(LP)<br>~~I~~|Output voltage<br>(for core logic bypass)<br>~~I~~|–<br>~~I~~<br>~~TO~~|1.1<br>~~I~~|–<br>~~I~~|V<br>~~I~~|High speed mode| |SID9|VCCD(ULP)<br>~~I~~<br>~~TO~~|Output voltage<br>(for core logic bypass)<br>~~I~~<br>~~TO~~||1.0<br>~~I~~<br>~~TO~~|||ULP mode.<br>Valid for –20 to 85°C.| |SID10|CEFC<br>~~Tr~~|External regulator voltage<br>(VCCD) bypass<br>~~Tr~~|3.8<br>~~Tr~~|4.7<br>~~Tr~~|5.6<br>~~Tr~~|µF<br>~~Tr~~|X5R ceramic or better.<br>Value for 0.8 to 1.2 V.| |SID11|CEXC<br>~~Tr~~|Power supply decoupling<br>capacitor<br>~~Tr~~|–<br>~~Tr~~<br>~~eee~~<br>~~YL~~|10<br>~~Tr~~|–<br>~~Tr~~<br>~~YL~~||X5R ceramic or better| |SID12|VCCRF<br>~~a~~<br>~~YL~~|Output voltage (for radio)<br>~~YL~~||1.1<br>ee<br>~~YL~~||V<br>~~.~~|–| |SID13|VCCPA<br>~~a~~<br>~~es~~<br>~~YL~~|Output voltage (for PA)<br>~~eee~~<br>~~YL~~||2.5<br>~~ee~~<br>~~YL~~|||| |SID14|VCCM<br>~~es~~<br>~~YL~~|Output voltage (for MIC)<br>~~eee~~<br>~~YL~~||2.5<br>~~YL~~|||| |SID523|VDDQ<br>~~es~~<br>~~YL~~|External supply to PMU analog<br>~~eee~~<br>~~YL~~|1.7<br>~~eee~~<br>~~YL~~<br>~~=————~~|–<br>~~YL~~<br>~~|~~|3.6<br>~~YL~~<br>~~|~~||| |SID524|VCC_BUCK<br>~~YL~~<br>~~=————~~|External supply to switching<br>regulator<br>~~YL~~<br>~~=————~~|||||| |SID525<br>~~po~~|BT_PAVDD<br>~~YL~~<br>~~=————~~<br>~~po~~|Internal PA supply<br>~~YL~~<br>~~=————~~|1<br>~~YL~~<br>~~=————~~<br>~~ee~~||2.75<br>~~YL~~<br>~~|~~<br>-||| |SID526<br>~~po~~|BT_RF<br>~~YL~~<br>~~=————~~<br>~~po~~|RF power supply<br>~~YL~~<br>~~=————~~|||1.2<br>~~YL~~<br>~~|~~<br>-||| |SID527<br>~~po~~|BT_LNAVDD<br>~~YL~~<br>~~=————~~<br>~~po~~<br>~~ee~~<br>~~ee~~|LNA supply<br>~~YL~~<br>~~=————~~<br>~~ee~~<br>~~ee~~|||||| |SID528<br>~~po~~|BT_IFVDD<br>~~YL~~<br>~~=————~~<br>~~po~~<br>~~ee~~|IFPLL power supply<br>~~YL~~<br>~~=————~~<br>~~ee~~|||||| |SID529<br>~~po~~|BT_VCOVDD<br>~~YL~~<br>~~=————~~<br>~~po~~<br>~~ee~~<br>~~ee~~|VCO supply<br>~~YL~~<br>~~=————~~<br>~~ee~~<br>~~ee~~|||||| ## **Note** > 3. Usage above the absolute maximum conditions listed in **Table 8** may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods of time may affect device reliability. The maximum storage temperature is 150°C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification. Datasheet 002-31976 Rev. *F 30 2023-09-26 ## **AIROC™ Bluetooth® LE 5.4 MCU** Electrical specifications |**Table 9**<br>**Power supply range, CPU current, and transition time specifications**_(continued)_|**Table 9**<br>**Power supply range, CPU current, and transition time specifications**_(continued)_|**Table 9**<br>**Power supply range, CPU current, and transition time specifications**_(continued)_|**Table 9**<br>**Power supply range, CPU current, and transition time specifications**_(continued)_|**Table 9**<br>**Power supply range, CPU current, and transition time specifications**_(continued)_| |---|---|---|---|---| |SIDC2<br>IDD4<br>Execute from cache; CM33<br>Active 96 MHz. FLL. Dhrystone<br>–<br>4.8<br>5.8<br>mA<br>7.4<br>8.4<br>SIDC3<br>IDD5<br>Execute from cache; CM33<br>Active 48 MHz. IHO. Dhrystone<br>–<br>2.4<br>3.4<br>mA<br>3.7<br>4.1<br>**Spec ID#**<br>**Parameter**<br>**Description**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit **<br>~~espf Le~~<br>~~-~~<br>~~pf yee~~<br>~~-~~||||VDDD= 3.0 V, Buck ON,<br>Max at 60°C<br>VDDD= 1.8 V, Buck ON,<br>Max at 60°C<br>VDDD= 3.0 V, Buck ON,<br>Max at 60°C<br>VDDD= 1.8 V, Buck ON,<br>Max at 60°C<br> **Details / conditions**| |SIDC4<br>IDD6<br>Execute from cache; CM33<br>Active 8 MHz. IHO. Dhrystone<br>~~fy ~~||0.90<br>1.5<br>1.27<br>1.75<br> ~~er~~<br>~~-~~||VDDD= 3.0 V, Buck ON,<br>Max at 60°C<br>VDDD= 1.8 V, Buck ON,<br>Max at 60°C| |SIDS1<br>IDD11<br>CM33 Sleep 96 MHz with FLL<br>~~fy ~~||1.5<br>2.2<br>2.2<br>2.7<br> ~~ee~~<br>~~-~~||VDDD= 3.0 V, Buck ON,<br>Max at 60°C<br>VDDD= 1.8 V, Buck ON,<br>Max at 60°C| |SIDS2<br>IDD12<br>CM33 Sleep 48 MHz with IHO.<br>~~fy ~~||1.2<br>1.9<br>1.7<br>2.2<br> ~~er~~<br>~~-~~||VDDD= 3.0 V, Buck ON,<br>Max at 60°C<br>VDDD= 1.8 V, Buck ON,<br>Max at 60°C| |SIDS3<br>IDD13<br>CM33 Sleep 8 MHz with IHO<br>~~| ~~||0.7<br>1.3<br>0.96<br>1.5<br> ~~Lee~~<br>~~-~~||VDDD= 3.0 V, Buck ON,<br>Max at 60°C<br>VDDD= 1.8 V, Buck ON,<br>Max at 60°C| |Deep Sleep mode||||| |SIDDS1_B<br>IDD33A_B<br>With internal Buck enabled<br>and 64K SRAM retention||5.7||At 25°C (with typical<br>Silicon)| |SIDDS2_B<br>IDD33B_B<br>With internal Buck enabled<br>and 128K SRAM retention||6.2||At 25°C (with typical<br>Silicon)| |SIDDS5_B<br>IDD33E_B<br>With internal Buck enabled<br>and 256K SRAM retention||7.5||At 25°C (with typical<br>Silicon)| |SIDDS3_B<br>IDD33C_B<br>With internal Buck enabled<br>and 64K SRAM retention<br>DS-RAM|–|4.5|µA|At 25°C (with typical<br>Silicon)| |SIDDS4_B<br>IDD33D_B<br>With internal Buck enabled<br>and 128K SRAM retention<br>DS-RAM||5||At 25°C (with typical<br>Silicon)| |SIDDS6_B<br>IDD33F_B<br>With internal Buck enabled<br>and 256K SRAM retention<br>DS-RAM||6<br>–||At 25°C (with typical<br>Silicon)| |Hibernate mode||||| ## **Note** > 3. Usage above the absolute maximum conditions listed in **Table 8** may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods of time may affect device reliability. The maximum storage temperature is 150°C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification. Datasheet 002-31976 Rev. *F 31 2023-09-26 **AIROC™ Bluetooth® LE 5.4 MCU** Electrical specifications **Table 9 Power supply range, CPU current, and transition time specifications** _(continued)_ |SID13A|TDS_ACT|Deep Sleep to Active transition<br>time. Guaranteed by design.|–|45|60|µs|DS to Active with 1.0 V<br>operation, with upper<br>inrush current limit| |---|---|---|---|---|---|---|---| |SID13B|TDS_ACTLP|Deep Sleep to Active LP<br>transition time.<br>Guaranteed by design.||20|35||DS to Active LP with 0.9 V<br>operation| |SID13C|TDSR_ACT|Deep Sleep-RAM to Active<br>transition time.<br>Guaranteed by design.||–|800||DS to Active with 1.0 V<br>operation, with upper<br>inrush current limit| |SID13D|TDSR_ACTLP|Deep Sleep-RAM to Active LP<br>transition time.<br>Guaranteed by Design.||–|800||DS-RAM to Active LP with<br>0.9 V operation| |SID14|THIB_ACT|Hibernate to Active transition<br>time||2000|–||Hibernate to Active with<br>1.0 V operation, with<br>upper inrush current limit| |SID14A|THIB_ACTLP|Hibernate to Active LP<br>transition time||2000|||Hibernate to Active with<br>0.9 V operation, with<br>upper inrush current limit| ## **Note** 3. Usage above the absolute maximum conditions listed in **Table 8** may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods of time may affect device reliability. The maximum storage temperature is 150°C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification. Datasheet 002-31976 Rev. *F 32 2023-09-26 ## **AIROC™ Bluetooth® LE 5.4 MCU** Electrical specifications ## **5.2.1 XRES** |**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---| |TXRES_IDD|IDD when XRES asserted|–|300|–|nA| |TXRES_IDD_1|||800||| |VIH|Input voltage high<br>threshold|0.7 × VDD|–||V| |VIL|Input voltage low threshold|–||0.3 × VDD|| |CIN|Input capacitance||3|–|pF| |VHYSXRES|Input voltage hysteresis||100||mV| |IDIODE|Current through protection<br>diode to VDD/VSS||–|100|µA| |**Table 11**|**XRES AC specifications**|**XRES AC specifications**|||||| |---|---|---|---|---|---|---|---| |**Spec ID#**|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details / conditions**| |SID15|TXRES_ACT|POR or XRES release to Active<br>transition time|–|1000|–|µs|Normal mode,<br>96 MHz M33,<br>upper inrush current| |SID16|TXRES_PW|XRES pulse width|5|–|||–| Datasheet 002-31976 Rev. *F 33 2023-09-26 **AIROC™ Bluetooth® LE 5.4 MCU** Electrical specifications |**Spec ID#**|**Parameter**<br>~~**e**e~~|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details /**<br>**conditions**| |---|---|---|---|---|---|---|---| |SID57|VIH<br>~~**e**e~~|Input voltage HIGH threshold <br>~~e~~|0.7 × VDD<br>~~e~~|–<br>~~ae~~<br>~~tL~~|–|V|CMOS input| |SID57A|IIHS<br>~~**e**e~~<br>~~7~~|Input current when Pad ><br>VDDIOfor OVT inputs<br>~~7~~|–<br>~~7~~<br>||10|µA|Per I2C spec| |SID58|VIL<br>~~7~~<br>~~i~~|Input voltage LOW threshold<br>~~7~~<br>|||0.3 ×<br>VDD|V|CMOS input| |SID241|VIH<br>~~ee~~|LVTTL input, VDD< 2.7 V<br>~~ee~~|0.7 × VDD<br>~~ee~~||–||–| |SID242|VIL<br>~~ee~~<br>~~_~~||–<br>~~ee~~<br>~~ae~~||0.3 ×<br>VDD<br>~~ae~~||| |SID243<br>~~|~~|VIH<br>~~——~~<br>~~|~~|LVTTL input, VDD> 2.7 V<br>~~——~~|2.0<br>~~——~~<br>~~|~~||–<br>~~tL~~||| |SID244<br>~~|~~|VIL<br>~~——~~<br>~~|~~||–<br>~~——~~<br>~~|~~||0.8<br>~~tL~~||| |SID59<br>~~|~~|VOH<br>~~|~~<br>~~a~~|Output voltage high level|VDD– 0.5<br>~~|~~||–<br>~~tL~~||IOH= 8 mA| |SID62A|VOL<br>~~a~~<br>~~a~~|Output voltage low level|–||0.4||IOL= 8 mA| |SID63|RPULLUP|Pull-up resistor|3.5|5.6|8.5|kΩ|–| |SID64|RPULLDOWN|Pull-down resistor|||||| |SID65|IIL<br>~~i~~<br>~~ee~~|Input leakage current<br>(absolute value)<br>~~ee~~|–|–<br>~~_~~|2<br>~~_|~~|nA|25°C, VDD= 3.0 V| |SID66|CIN<br>~~ee~~|Input capacitance<br>~~ee~~|||5<br>~~_|~~|pF|–| |SID67|VHYSTTL<br>~~ee~~<br>~~i~~<br>~~ee~~|Input hysteresis LVTTL<br>VDD> 2.7 V<br>~~ee~~<br>~~ee~~<br>~~ee~~|100<br>~~ee~~<br>~~ee~~|0<br>~~_~~<br>~~ee~~<br>~~ee~~|–<br>~~_ |~~<br>~~ee~~<br>~~es~~|mV<br>~~ee~~<br>~~es~~|| |SID68|VHYSCMOS<br>~~i ~~<br>~~ee~~<br>~~es~~|Input hysteresis CMOS<br> ~~ee~~<br>~~ee~~<br>~~es~~|0.05 × VDD<br>~~ee~~<br>~~ee~~<br>~~es~~|–<br>~~ee~~<br>~~ee~~<br>~~es~~|||| |SID69|IDIODE<br>~~ee~~<br>~~es~~|Current through protection<br>diode to VDD/VSS<br>~~ee~~<br>~~es~~|–<br>~~ee~~<br>~~es~~||100<br>~~es~~|µA<br>~~es~~|| |SID69A|ITOT_GPIO<br>~~es~~<br>~~i~~|Maximum total source or sink<br>chip current<br>~~es~~|||200<br>~~es~~|mA<br>~~es~~|| Datasheet 002-31976 Rev. *F 34 2023-09-26 ## **AIROC™ Bluetooth® LE 5.4 MCU** Electrical specifications ## **Table 13 GPIO AC specifications** |**Spec ID#**|**Parameter **|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details / conditions**| |---|---|---|---|---|---|---|---| |SID70|TRISEF|Rise time in Fast Strong mode.<br>10% to 90% of VDD.|–|3.5|–|ns|CLOAD= 15 pF,<br>8 mA drive strength,<br>VDDIO> 2.7V| |SID70A|TRISEF_1|||5.5|||CLOAD= 15pF,<br>VDDIO< 2.7 V,<br>max slew and drive<br>strength| |SID71|TFALLF|Fall time in Fast Strong mode.<br>10% to 90% of VDD.||3.5|||CLOAD= 15 pF,<br>8 mA drive strength,<br>VDDIO> 2.7 V| |SID71A|TFALLF_1|||5.5|||CLOAD= 15pF,<br>VDDIO< 2.7 V,<br>max slew and drive<br>strength| |SID72|TRISES_1|Rise time in Slow Strong mode.<br>10% to 90% of VDD.|52|–|142||CLOAD= 15 pF,<br>8 mA drive strength,<br>VDD 2.7 V| |SID72A|TRISES_2||48||102||CLOAD= 15 pF,<br>8 mA drive strength,<br>2.7 V < VDD 3.6| |SID73|TFALLS_1<br>~~Pf~~|Fall time in Slow Strong mode.<br>10% to 90% of VDD.<br>~~Pf~~|44<br>~~Pf~~||211||CLOAD= 15 pF,<br>8 mA drive strength,<br>VDD 2.7 V| |SID74|FGPIOUT1<br>~~ee~~|GPIO Fout; Fast Strongmode.<br>~~ee~~|–<br>~~ee~~||100<br>~~|~~|MHz|90/10%, 15 pF load,<br>60/40 duty cycle| |SID75|FGPIOUT2<br>~~ee~~<br>~~ee~~|GPIO Fout; Slow Strongmode.<br>~~ee~~<br>~~ee~~|||1.5<br>~~|~~<br>~~|~~||| |SID76|FGPIOUT3<br>~~ee~~<br>~~ee~~|GPIO Fout; Fast Strongmode.<br>~~ee~~<br>~~ee~~|||100<br>~~|~~<br>~~|~~||| |SID245|FGPIOUT4<br>~~ee~~|GPIO Fout; Slow Strongmode.<br>~~ee~~|||1.3<br>~~|~~||| |SID246|FGPIOIN<br>~~i ~~|GPIO input operating<br>frequency; 1.71 VVDD 3.6 V<br> ~~ee~~|||100||90/10% VIO| Datasheet 002-31976 Rev. *F 35 2023-09-26 ## **AIROC™ Bluetooth® LE 5.4 MCU** Electrical specifications |DM.4|–<br>~~Po~~|Audio/Mic supply -<br>Mic_avdd<br>~~ee~~|1.8<br>~~ee~~|–<br>~~ee~~|3.3<br>~~ee~~|V<br>~~ee~~|–| |---|---|---|---|---|---|---|---| |DM.5||Current consumption<br>~~Tee~~|–<br>~~Tee~~<br>~~a~~|1.5<br>~~Tee~~|–<br>~~Tee~~<br>~~a~~|mA<br>~~Tee~~|25°C, Mic_avdd = 3 V,<br>excludes MIC bias loading<br>current| |DM.6||Power down current<br>~~Tee~~<br>~~a~~||0.1<br>~~Tee~~<br>~~a~~||µA<br>~~Tee~~<br>~~a~~|25°C, Mic_avdd = 3 V| |DM.21||MIC PGAgain range<br>~~a~~<br>~~———~~|0<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~|42<br>~~a~~<br>~~a~~|dB<br>~~a~~<br>~~a~~|–| |DM.22||MIC PGAgain step<br>~~a~~<br>~~———~~|–<br>~~a~~<br> ~~a~~<br>~~**P**e~~<br> ~~ee~~<br>~~LE~~<br>~~ee~~|1<br>~~a~~<br>~~a~~|–<br>~~a~~<br>~~a~~||| |DM.23||MIC PGAgain error<br>~~——— ~~||1<br>~~a~~|||| |DM.24||PGA input referred noise<br>~~**P**~~<br>~~o~~||–<br>~~e~~<br>~~ee~~|4<br>~~e~~<br>~~|~~|µV<br>~~e~~<br>~~|~~|@ 42 dB PGA gain<br>A-weighted| |DM.25||Passbandgain flatness<br>~~**P**~~<br>~~o~~<br>~~ee~~|||–<br>~~e~~<br>~~|~~<br>~~ee~~|dB<br>~~e~~<br>~~|~~<br>~~ee~~|PGA + ADC, 100-4 kHz| |DM.26||MIC bias output voltage -<br>Micvdd * 0.75 * 1.12<br>~~o~~<br>~~ee ~~<br>~~Po~~||2.52<br>~~ee~~||V<br>~~|~~<br>~~ee~~<br>~~||~~|Micvdd = 3| |DM.27||MIC bias loadingcurrent<br>~~Po~~<br>~~|~~||–<br>~~LE~~<br>~~ee~~|3<br>~~LE~~|mA<br>~~||~~<br>~~LE~~|–| |DM.28||MIC bias noise<br>~~Po~~<br>~~|~~||||µV<br>~~||~~<br>~~LE~~|Referred to PGA input,<br>20-8 kHz, A-weighted| |DM.29||MIC bias PSRR<br>~~| ~~<br>~~ee~~|40<br> ~~LE~~<br>~~ee~~<br>~~ee~~||–<br>~~LE~~|dB<br>~~LE~~|1 kHz| Datasheet 002-31976 Rev. *F 36 2023-09-26 ## **AIROC™ Bluetooth® LE 5.4 MCU** Electrical specifications ||||~~ee~~||||| |---|---|---|---|---|---|---|---| |**Spec ID# **|**Parameter **<br>~~a ee~~|**Description**<br>~~ee~~|**Min**<br>~~ee~~<br>~~ee~~<br>~~ee~~|**Typ**<br>~~ee~~<br>~~ee~~|**Max**<br>~~ee~~<br>~~ee~~|**Unit**<br>~~ee~~<br>~~ee~~|**Details / conditions**<br>~~ee~~| |DM.2|–<br>~~a ee~~|Analog supply voltage - VDDA<br>~~ee~~<br>~~ee~~|1.7<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~<br>~~ee~~|3.6<br>~~ee~~<br>~~ee~~<br>~~ee~~|V<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~ee~~| |DM.5||Active current consumption -<br>VDDC<br>~~ee~~<br>~~PE~~|–<br>~~ee~~<br>~~ee ~~<br>~~PE~~<br> <br>~~ee~~|2<br>~~ee~~<br> ~~ee ~~<br>~~PE~~|–<br>~~ee~~<br> ~~ee~~|mA<br>~~ee~~<br>~~ee~~|25°C<br>~~ee~~| |DM.5a||Active current consumption -<br>VDDA<br>~~———j~~||0.5<br>~~=~~|||25°C, VDDA= 3 V| |DM.6||Power down current - VDDA<br>~~———j ~~<br>~~po~~||0.1<br> ~~=~~||µA<br>~~_~~|25°C - ADC disabled with<br>device in Active mode| |DM.6a||Power down current - VDDC<br>~~po~~||1|||| |DM.8||Absolute error - Includes gain<br>error, offset and distortion<br>~~po~~<br>~~ee~~||–<br>~~ee~~|5<br>~~ee~~|%<br>~~_~~<br>~~ee~~|–| |DM.10||ENOB - Audio application<br>~~ee~~||12<br>~~ee~~|–<br>~~ee~~|Bit<br>~~ee~~|| |DM.11||ENOB - Static application||11|||| |DM.12||ADC input full scale -<br>Audio application<br>~~a~~||1.6||Vpp|| |DM.13||ADC input full scale -<br>Static application<br>~~a~~<br>~~rr~~|0<br>~~rr~~|–<br>~~rr~~|VDDA<br>~~rr~~||| |DM.14||Conversion rate -<br>Audio application<br>~~ee~~|16<br>~~ee~~|48<br>~~ee~~|–<br>~~ee~~|kHz<br>~~ee~~|| |DM.15||Conversion rate -<br>Static application<br>~~ee~~<br>~~re~~|50<br>~~ee~~<br>~~re~~|100<br>~~ee~~<br>~~re~~|–<br>~~ee~~<br>~~re~~||| |DM.16||Signal bandwidth -<br>Audio application<br>~~ee~~|20<br>~~ee~~|–<br>~~ee~~|8000<br>~~ee~~|Hz<br>~~ee~~|| |DM.17||Signal bandwidth -<br>Static application<br>~~ee~~<br>~~OT~~|–<br>~~ee~~|DC<br>~~ee~~|–<br>~~ee~~<br>||| |DM.18||Startup time -<br>Audio application<br>~~re~~||10||ms|| |DM.19||Startup time -<br>Static application<br>~~re~~||20||µs|| |DM.30||ADC SNR<br>~~——~~|78<br>~~——~~|–<br>~~—— ~~<br>~~ee~~||dB<br>~~7~~|0 dB PGA gain,<br>A-weighted| |DM.31||ADC THD+N<br>~~——~~<br>~~——~~<br>|74<br>~~——~~<br>~~——~~<br>~~ee~~||||–3 dB FS input,<br>0 dB PGAgain| |DM.33||GPIO source impedance<br>~~——~~<br>~~ee~~|–<br>~~——~~<br>~~eeee~~||1k<br>|W<br> ~~7~~|10 µs measurement time| Datasheet 002-31976 Rev. *F 37 2023-09-26 **AIROC™ Bluetooth® LE 5.4 MCU** Electrical specifications ## **5.4 Digital peripherals** ||~~es~~|~~es Ge~~|~~Ge~~|~~ee~~|~~en~~||| |---|---|---|---|---|---|---|---| |**Spec ID#**|**Parameter**<br>~~es~~|**Description**<br>~~es Ge~~|**Min**<br>~~Ge~~|**Typ **<br>~~ee~~|**Max**<br>~~en~~|**Unit **|**Details / conditions**| |SID.TCPWM.1<br>~~Pe~~|ITCPWM1<br>~~es~~<br>~~Ff~~<br>~~Pe~~|Block current<br>consumption at 8 MHz<br>~~es Ge~~<br>~~Ff~~|–<br>~~Ge~~<br> |<br>~~TP~~|–<br>~~ee ~~<br>| <br>|70<br> ~~en~~<br>~~7~~<br>~~7~~|µA|All modes (TCPWM)| |SID.TCPWM.2<br>~~Pe~~|ITCPWM2<br>~~Ff~~<br>~~Pe~~<br>~~J~~|Block current<br>consumption at 24 MHz<br>~~Ff~~<br>~~J~~|||180<br>~~7~~<br>~~7~~<br>~~F~~||| |SID.TCPWM.2A<br>~~Pe~~|ITCPWM3<br>~~Pe~~<br>~~J~~|Block current<br>consumption at 50 MHz<br>~~J~~|||270<br>~~7~~<br>~~F~~||| |SID.TCPWM.2B|ITCPWM4<br>~~J~~|Block current<br>consumption at<br>100 MHz<br>~~J~~|||540<br>~~F~~||| |SID.TCPWM.3|TCPWMFREQ<br>~~J~~<br>~~TP~~|Operating frequency<br>~~J ~~<br>~~TP~~|||100<br> ~~F~~<br>nn|MHz<br>nn|Fc max = Fcpu<br>Maximum = 100 MHz| |SID.TCPWM.4|TPWMENEXT<br>~~TP~~|Input trigger pulse<br>width for all trigger<br>events<br>~~TP~~|2 / Fc<br>~~TP~~||–<br> nn|ns<br>nn|Trigger events can be Stop,<br>Start, Reload, Count,<br>Capture, or Kill depending<br>on which mode of<br>operation is selected.| |SID.TCPWM.5|TPWMEXT|Output trigger pulse<br>widths|1.5 / Fc||||Minimum possible width of<br>Overflow, Underflow, and<br>CC (Counter equals<br>Compare value) trigger<br>outputs| |SID.TCPWM.5A|TCRES<br>~~pf~~|Resolution of counter<br>~~pf~~|1 / Fc<br>~~pf~~||||Minimum time between<br>successive counts| |SID.TCPWM.5B|PWMRES<br>~~pf~~|PWM resolution<br>~~pf~~|||||Minimum pulse width of<br>PWM output| |SID.TCPWM.5C|QRES<br>~~Pf~~|Quadrature inputs<br>resolution<br>~~Pf~~|2 / Fc<br>~~Pf~~||||Minimum pulse width<br>between Quadrature phase<br>inputs. Delays from pins<br>should be similar.| Datasheet 002-31976 Rev. *F 38 2023-09-26 **AIROC™ Bluetooth® LE 5.4 MCU** Electrical specifications |**Table 18**<br>**Serial communication block (SCB) specifications**|**Table 18**<br>**Serial communication block (SCB) specifications**|**Table 18**<br>**Serial communication block (SCB) specifications**|**Table 18**<br>**Serial communication block (SCB) specifications**|**Table 18**<br>**Serial communication block (SCB) specifications**||| |---|---|---|---|---|---|---| |**Spec ID#**<br>**Parameter**|**Description**|**Min **|**Typ **|**Max**|**Unit**|**Details / conditions**| |I2C DC specifications||||||| |SID149<br>II2C1|Block current consumption<br>at 100 kHz|||30||| |SID150<br>II2C2|Block current consumption<br>at 400 kHz|||80||–| |SID151<br>II2C3|Block current consumption<br>at 1 Mbps|–|–|180|µA|| |SID152<br>II2C4|I2C enabled in Deep Sleep<br>mode|||1.7||At 60°C| |I2C AC specifications||||||| |SID153<br>FI2C1|Bit rate|–|–|1|Mbps|–| |UART DC specifications||||||| |SID160<br>IUART1<br>Block current consumption<br>at 100 kbps<br>–<br>–<br>30<br>µA<br>–<br>SID161<br>IUART2<br>Block current consumption<br>at 1000 kbps<br>180<br>UART AC specifications<br>SID162A<br>FUART1<br>Bit rate<br>–<br>–<br>3<br>Mbps ULP mode<br>SID162B<br>FUART2<br>8<br>LP mode<br>SPI DC specifications<br>~~ee~~<br>~~——~~||||||| |SID163<br>ISPI1|Block current consumption<br>at 1 Mbps|||220||| |SID164<br>ISPI2<br>SID165<br>ISPI3|Block current consumption<br>at 4 Mbps<br>Block current consumption<br>at 8 Mbps|–|–|340<br>360|µA|–| |SID165A<br>ISP14|Block current consumption<br>at 25 Mbps|||800||| |SPI AC specifications for LP mode (1.1 V) unless noted otherwise.||||||| ||SPI operating frequency|||||| |SID166<br>FSPI|Master and externally|||24||–| ||clocked Slave|||||| |SID166B<br>FSPI_EXT|SPI operating frequency<br>Master (Fscb is SPI clock)|–|–|Fscb/4|MHz|Fscb max is 96 MHz in LP<br>mode, 24 MHz in ULP<br>mode.| |SID166A<br>FSPI_IC|SPI Slave internally clocked|||24||–| |SPI Master mode AC specifications for LP mode (1.1 V) unless noted otherwise.||||||| |SID167<br>TDMO<br>MOSI valid after SClock<br>drivingedge<br>–<br>12<br>12<br>ns<br>20 ns max. for ULP (0.9 V)<br>mode.<br>SID168<br>TDSI<br>MISO valid before SClock<br>capturingedge<br>20<br>–<br>–<br>Full clock, late MISO<br>sampling<br>SID169<br>THMO<br>MOSI data hold time<br>0<br>5<br>Referred to Slave<br>capturingedge.<br>~~———~~||||||| Datasheet 002-31976 Rev. *F 2023-09-26 39 ## **AIROC™ Bluetooth® LE 5.4 MCU** Electrical specifications **Table 18 Serial communication block (SCB) specifications** _(continued)_ |SID170|TDMI|MOSI valid before Sclock<br>capturingedge|5|–|–|ns|–| |---|---|---|---|---|---|---|---| |SID170A|SPI_FREQ|For LP mode|48|||MHz|| |SID171A|TDSO_EXT|MISO valid after Sclock<br>driving edge in Ext. Clk.<br>mode|–||20|ns|35 ns max. for ULP (1.0 V)<br>mode| |SID171|TDSO|MISO valid after Sclock<br>driving edge in Internally<br>Clk. Mode|||TDSO_EXT<br>+ 3*Tscb||Tscb is Serial<br>Communication Block<br>clock period.| |SID171B|TDSO|MISO valid after Sclock<br>driving edge in Internally<br>Clk. Mode with median<br>filter enabled.|||TDSO_EXT<br>+ 4*Tscb||Tscb is Serial<br>Communication Block<br>clock period.| |SID172|THSO|Previous MISO data hold<br>time|5.5||–||–| |SID172C|THIS|SPI MOSI hold from SCLK|||||| Datasheet 002-31976 Rev. *F 40 2023-09-26 ## **AIROC™ Bluetooth® LE 5.4 MCU** Electrical specifications ## **5.5 Audio subsystem** ## **Table 19 Audio subsystem specifications** |SID400P|Fmax_clk_sys|Clock frequency for<br>clk_sys|–|96|–|MHz|PVT18<br>ss, 0.90 V, –40°C, scl40<br>library, minimum<br>parameters| |---|---|---|---|---|---|---|---| |SID401|Fmax_clk_if_srss|Clock frequency for<br>audio clock reference<br>clk_if_srss||48|||PVT18<br>ss, 0.90 V, –40°C, scl40<br>library, minimum<br>parameters| |SID402|Idyn_act_typ|Typical dynamic<br>current when cell is<br>active. See the DC<br>spec table for related<br>static current spec, if<br>applicable.||–|110|µA/<br>MHz|PVT16<br>tt, 1.1 V, 25°C, scl40<br>library, typical<br>parameters<br>clk_audio: 49.152MHz<br>clk_sys: 50MHz| |SID403|Idyn_act_max|Maximum dynamic<br>active current. See<br>the DC spec table for<br>related static current<br>spec, if applicable.|||132||PVT20<br>ff, 1.21 V, 150°C, scl40<br>library, maximum<br>parameters<br>clk_audio: 49.152MHz<br>clk_sys: 50MHz| |SID403A|Idyn_slp_typ|Typical dynamic<br>current when cell is<br>idle. See the DC spec<br>table for related<br>static current spec, if<br>applicable.|||80||PVT16<br>tt, 1.1 V, 25°C, scl40<br>library, typical<br>parameters, clocks<br>toggling<br>clk_audio: 49.152MHz<br>clk_sys: 50MHz| |SID403B|T_SETUP|Receiver setup|||10|ns|PVT18<br>ss, 0.90 V, –40°C, scl40<br>library, minimum<br>parameters| |SID403C|PDM_HOLD|Data input hold time<br>to PDM_CLK edge|10||–||PVT18<br>ss, 0.90 V, –40°C, scl40<br>library, minimum<br>parameters| |SID404A|CPDM<br>~~a~~|Load<br>~~a~~|–<br>~~a~~|10<br>~~a~~|–<br>~~a~~|pF<br>~~a~~|–| |SID404<br>~~SS~~|PDM_OUT<br>~~a~~<br>~~SS~~|Audio sample rate<br>~~a~~<br>~~a~~<br>|8<br>~~a~~<br>~~a~~<br>|–<br>~~a~~<br>|48<br>~~a~~<br>|ksps<br>~~a~~<br>|| |SID405<br>~~SS~~|PDM_WL<br>~~SS~~|Word length<br>~~a~~<br>|16<br>~~a~~<br>||24<br>|bits<br>|| |SID412<br>~~SS~~|PDM_ST<br>~~SSA~~|Startup time<br>~~a~~<br>~~A~~|–<br>~~a~~<br>~~A~~|48<br>~~A~~|–<br>~~A~~|~~A~~|WS (Word Select) cycles| I[2] S specifications. The same for LP and ULP modes unless stated otherwise. ## **Note** 4. TMCLK_SOC is the internal I2S master clock period. Datasheet 002-31976 Rev. *F 41 2023-09-26 ## **AIROC™ Bluetooth® LE 5.4 MCU** Electrical specifications **Table 19 Audio subsystem specifications** _(continued)_ |**Spec ID#**|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit **|**Details / conditions**| |---|---|---|---|---|---|---|---| |SID413|I2S_WORD|Length of I2S word|8|–|32|bits|–| |SID414B|I2S_BCK_F<br>|Bit Clock frequency in<br>LP mode<br>~~ee~~|–<br>~~ee~~<br>~~a~~||12.28<br>8|MHz|| |SID414BU|I2S_BCK_F_U<br>~~es~~|Bit Clock frequency in<br>ULP mode<br>~~esee~~|||3.072||| |SID414BP|I2S_BCK_P<br>~~es~~<br>~~a~~<br>~~ee~~|Bit Clock period<br>~~esee~~<br>~~a~~<br>~~ee~~||1/I2S_B<br>CK_F<br>~~a~~|–<br>~~a~~|ns<br>~~a~~|| |SID414BP<br>U|I2S_BCK_P_U<br>~~a~~<br>~~ee~~|Bit Clock period in<br>ULP mode<br>~~a~~<br>~~ee~~||1/I2S_B<br>CK_F_U<br>~~a~~|||| |SID414|I2S_WS_FREQ<br>~~ee ~~<br>~~—~~|Word clock frequency<br>in LP mode<br> ~~ee~~<br>~~—~~||–|192|kHz|| |SID414M|I2S_WS_FREQ_U <br>~~ee~~|Word clock frequency<br>in ULP mode<br>~~ee~~|||48||| |SID435L|I2S_BCK_TL<br>~~ee~~<br>~~Ff~~|Bit clock low period in<br>LP Mode<br>~~ee~~<br>~~Ff~~|0.35*I2<br>S_BCK_<br>P<br>~~Ff~~||–|ns|| |SID415IL|I2S_MCKI_TL<br>~~oo~~|Master clock IN low<br>period in LP (or) ULP<br>mode<br>~~oo~~|0.45*tM<br>CLK<br>~~oo~~||||| |SID415IH|I2S_MCKI_TH<br>~~oo~~|Master clock IN high<br>period in LP (or) ULP<br>Mode<br>~~oo~~|||||| |SID415OL|I2S_MCKO_TL<br>~~a~~|Master clock Out low<br>period in LP (or) ULP<br>mode<br>~~a~~|0.35*tM<br>CLK<br>~~a~~|0.45*t<br>MCLK<br>to<br>0.4*tMC<br>LK<br>~~a~~|||Typ spec 0.45*tMCLK to<br>0.4*tMCLK| |SID415OH|I2S_MCKO_TH<br>~~a~~|Master clock Out high<br>period in LP (or) ULP<br>mode<br>~~a~~||0.45*t<br>MCLK<br>to<br>0.4*tMC<br>LK<br>~~a~~|||| |SID416|TDM_OUTPUT_L<br>OAD_MAX<br>~~es~~|Capacitive load<br>~~es~~|10<br>~~es~~|–<br>~~es~~||pF|–| ## **Note** 4. TMCLK_SOC is the internal I2S master clock period. Datasheet 002-31976 Rev. *F 42 2023-09-26 ## **AIROC™ Bluetooth® LE 5.4 MCU** Electrical specifications **Table 19 Audio subsystem specifications** _(continued)_ |**Spec ID#**|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit **|**Details / conditions**| |---|---|---|---|---|---|---|---| |||WS Hold time after|||||| |||the first edge|||||| |SID430A|I2S_S_TH_WS|following the driving|0||–||| |||edge of bit clock, LP|||||| |||or ULP mode|||||| |SID432|I2S_S_SDO|SDO Propagation<br>delay from driving<br>edge of bit clock for<br>LP mode|0.3 *<br>I2S_BC<br>K_P|–|0.2 *<br>I2S_B<br>CK_P|ns|–| |SID432U|I2S_S_SDO_U|SDO Propagation<br>delay from driving<br>edge of bit clock for<br>ULP mode|0.3 *<br>I2S_BC<br>K_P_U||0.2 *<br>I2S_B<br>CK_P<br>_U||| |I2S Master mode|||||||| |SID437|I2S_M_WS|WS propagation<br>delay from driving<br>edge of bit clock for<br>LP mode|||0.2 *<br>I2S_B<br>CK_P||| |||WS propagation|||0.2 *||| |SID437_U|I2S_M_WS_U|delay from driving<br>edge of bit clock for|||I2S_B<br>CK_P||–| |||ULP mode|0|–|_U|ns|| |SID438|I2S_M_SDO|SDO Propagation<br>delay from driving<br>edge of bit clock for<br>LP mode|||0.2 *<br>I2S_B<br>CK_P||| |SID438U|I2S_M_SDO_U|SDO Propagation<br>delay from driving<br>edge of bit clock for<br>ULP mode|||0.2 *<br>I2S_B<br>CK_P<br>_U||Associated clock edge<br>depends on selected<br>polarity| ## **Note** 4. TMCLK_SOC is the internal I2S master clock period. Datasheet 002-31976 Rev. *F 43 2023-09-26 ## **AIROC™ Bluetooth® LE 5.4 MCU** Electrical specifications ## **5.6 System resources** ## **5.6.1 Power-on reset** |**5.6.1**<br>**Power-on reset**|**5.6.1**<br>**Power-on reset**|**5.6.1**<br>**Power-on reset**|**5.6.1**<br>**Power-on reset**|**5.6.1**<br>**Power-on reset**|**5.6.1**<br>**Power-on reset**|**5.6.1**<br>**Power-on reset**| |---|---|---|---|---|---|---| |**Table 20**<br>**Power-on reset (POR) with brown-out detect (BOD) DC specifications**||||||| |**Spec ID# Parameter**<br>**Description**<br>Precise POR (PPOR)<br>~~— [ff~~||**Min**|**Typ**|**Max**|**Unit**|**Details / conditions**| |SID190<br>VFALLPPOR|BOD trip voltage in Active and<br>Sleep modes. VDDD.|1.54||–|V|BOD Reset guaranteed<br>for VDDDlevels below<br>1.54 V.| |SID192<br>VFALLDPSLP|BOD trip voltage in Deep<br>Sleep. VDDD.|1.54|–|||–| |SID192A<br>VDDRAMP|Maximum power supply ramp<br>rate (any supply)|–||100|mV/<br>µs|Active mode| |**Table 21**<br>**POR with BOD AC specifications**||||||| |**Spec ID# Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details / conditions**| |SID194A<br>VDDRAMP_DS|Maximum power supply ramp<br>rate (any supply) in system<br>Deep Sleep mode|–|–|10|mV/<br>µs|BOD operation<br>guaranteed| ## **5.6.2 Voltage monitors** **Table 22 Voltage monitors DC specifications** |**Spec**<br>**ID#**|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details / conditions**| |---|---|---|---|---|---|---|---| |SID195|VHVDI1|–|1.38|1.43|1.47|V|–| |SID196|VHVDI2||1.57|1.63|1.68||| |SID197|VHVDI3||1.76|1.83|1.89||| |SID198|VHVDI4||1.95|2.03|2.10||| |SID199|VHVDI5||2.05|2.13|2.2||| |SID200|VHVDI6||2.15|2.23|2.3||| |SID201|VHVDI7||2.24|2.33|2.41||| |SID202|VHVDI8||2.34|2.43|2.51||| |SID203|VHVDI9||2.44|2.53|2.61||| |SID204|VHVDI10||2.53|2.63|2.72||| |SID205|VHVDI11||2.63|2.73|2.82||| |SID206|VHVDI12||2.73|2.83|2.92||| |SID207|VHVDI13||2.82|2.93|3.03||| |SID208|VHVDI14||2.92|3.03|3.13||| |SID209|VHVDI15||3.02|3.13|3.23||| |SID211|LVI_IDD|Block current|–|5|15|µA|| **Table 23 Voltage monitors AC specifications Spec ID# Parameter Description Min Typ Max Unit Details / conditions** ~~ee~~ SID212 TMONTRIP Voltage monitor trip time – – 170 ns – Datasheet 002-31976 Rev. *F 2023-09-26 44 **AIROC™ Bluetooth® LE 5.4 MCU** Electrical specifications ## **5.6.3 SWD and trace interface** ## **Table 24 SWD and trace specifications** |**Spec ID# **|**Parameter**|**Description**|**Min**|**Typ**|**Max**|**Unit**|**Details / conditions**| |---|---|---|---|---|---|---|---| |SID214|F_SWDCLK2|1.7VVDDD 3.6V|–|–|25|MHz|LP mode; VCCD= 1.1 V| |SID214L|F_SWDCLK2L||||12||ULP mode;<br>VCCD= 1.0 V.| |SID215|T_SWDI_SETUP|T = 1/f SWDCLK|0.25 * T||–|ns|For both LP and ULP<br>modes| |SID216|T_SWDI_HOLD||||||| |SID217|T_SWDO_VALID||–||0.5 * T||–| |SID217A|T_SWDO_HOLD||1||–||| |SID214T|F_TRCLK_LP1|With trace data setup/hold<br>times of 2/1 ns respectively|–||48|MHz|LP mode, VDD= 1.1 V.| |SID215T|F_TRCLK_LP2|With trace data setup/hold<br>times of 3/2 ns respectively|||48||| |SID216T|F_TRCLK_ULP||||24||ULP mode, VDD= 1.0 V.| |**5.6.4**|**Internal main oscillator**|**Internal main oscillator**||||||||| |---|---|---|---|---|---|---|---|---|---|---| |**Table 25**|**IMO DC specifications**|||||||||| |**Spec ID# Parameter**<br>**Description**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**<br>**Details /**<br>**conditions**<br>SID218<br>IIMO1<br>IMO operatingcurrent at 8 MHz<br>–<br>9<br>15<br>µA<br>–<br>~~———EE~~||||||||||| |**Table 26**|**IMO AC specifications**|||||||||| |**Spec ID# Parameter**<br>**Description**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**<br>**Details /**<br>**conditions**<br>SID223<br>FIMOTOL1<br>Frequency variation centered on<br>8 MHz<br>–<br>–<br>2<br>%<br>–<br>SID227<br>TJITR<br>Cycle-to-cycle and period jitter<br>–<br>250<br>–<br>µs<br>~~See~~||||||||||| |**5.6.5**|**Internal low-speed oscillator**|||||||||| |**Table 27**|**ILO DC specifications**|||||||||| |**Spec ID# Parameter**<br>**Description**<br>SID231<br>IILO2<br>ILO operating current at<br>32 kHz<br>**Table 28**<br>**ILO AC specifications**<br>~~oe~~|||**Min**<br>–|**Typ**<br>0.3||**Max**<br>0.7||**Unit**<br>µA||**Details /**<br>**conditions**<br>–| |**Spec ID# **|**Parameter**|**Description**|**Min**|**Typ**|**Max**||**Unit**||**Details /**<br>**conditions**|| ||||||||||Startup time to|| ||||–|–|7||µs||80% of final|| |SID234|TSTARTILO1|ILO startup time|||||||frequency<br>Startup time to|| ||||–|–|35||µs||95% of final|| ||||||||||frequency|| |SID236|TLIODUTY|ILO duty cycle|45|50|55||%||–|| |SID237|FILOTRIM1|32 kHz trimmed frequency|28.8|32|35.2||kHz||± 10% variations|| Datasheet 002-31976 Rev. *F 45 2023-09-26 ## **AIROC™ Bluetooth® LE 5.4 MCU** Electrical specifications ## **5.6.6 FLL** **Table 29 Frequency locked loop (FLL) specifications** **==> picture [502 x 245] intentionally omitted <==** **----- Start of picture text -----**<br> ||||||||| |---|---|---|---|---|---|---|---| |Spec ID#|Parameter|Description|Min|Typ|Max|Unit|Details / conditions| |Upper limit is for| |SID450|FLL_RANGE|Input frequency range.|0.040| |External input.| |96.00| |Output frequency range.| |SID451|FLL_OUT_DIV2|MHz| |VCCD = 1.1 V.|Output range of FLL| |24.00| |Output frequency range.|divided-by-2 output| |SID451A|FLL_OUT_DIV2|48.00| |VCCD = 0.9 V.| |SID452|FLL_DUTY_DIV2|[Divided-by-2 output; ]|47.00|53.00|%|–| |High or Low| |–|With IMO input, less| |Time from stable input clock|than 10°C change in| |SID454|FLL_WAKEUP|to 1% of final value on deep|11.00|µs|temperature while in| |sleep wakeup|Deep Sleep, and Fout| |–||50 MHz.| |Period jitter| |SID455|FLL_JITTER|18.00|ps| |(1 sigma at 100 MHz)| |–| |µA/| |SID456|FLL_CURRENT|CCO + logic current|5.50| |MHz| **----- End of picture text -----**<br> ## **5.6.7 Crystal oscillator** **==> picture [509 x 265] intentionally omitted <==** **----- Start of picture text -----**<br> ||||||||| |---|---|---|---|---|---|---|---| |Table 30|ECO specifications| |Details /| |Spec ID#|Parameter|Description|Min|Typ|Max|Unit| |conditions| |es| |MHz ECO DC specifications| |SID316|IDD_MHZ|Block operating current with Cload up to 18 pF|–|1200|–|µA|Type 24 MHz| |ee| |MHz ECO AC specifications| |SID317|F_MHz|Crystal frequency range|–|24|–|MHz|–| |kHz ECO DC specifications| |Block operating current with| |SID318|IDD_kHz|0.38|1|µA| |32-kHz crystal| |–|–| |SID321E|ESR32K|Equivalent series resistance|80|–|kΩ| |SID322E|PD32K|Drive level|–|0.5|µW| |kHz ECO AC specifications| |SID319|F_kHz|32-kHz trimmed frequency|32.8|–|kHz| |SID320|Ton_kHz|Startup time|–|–|1000|ms|–| |=e|SID320E|FTOL32K|Frequency tolerance|50|250|ppm| **----- End of picture text -----**<br> Datasheet 002-31976 Rev. *F 46 2023-09-26 ## **AIROC™ Bluetooth® LE 5.4 MCU** Electrical specifications ## **5.6.8 Clock source switching time Table 31 Clock source switching time specifications** |**Spec ID# **|**Parameter**|**Parameter**|**Description**|**Min**||**Typ**|**Max**||**Unit**|**Details /**<br>**conditions**| |---|---|---|---|---|---|---|---|---|---|---| ||||Clock switching from one CLK_HF||||4 clk1|||| |SID262|TCLKSWITCH||to another CLK_HF in clock<br>periods[5]|–||–|+ 3<br>clk2||periods|–| |**5.6.9**||**QSPI**||||||||| |**Table 32**||**QSPI specifications**||||||||| |**Spec ID#**||**Parameter**|**Description**|**Min**||**Typ**|**Max**||**Unit**|**Details /**<br>**conditions**| |SMIF QSPI specifications. All specs with 15-pF load.||||||||||| |**5.6.10**<br>**Smart I/O**<br>SID390Q<br>Fsmifclock<br>SMIF QSPI output clock frequency<br>–<br>–<br>48<br>MHz<br>LP mode (1.1 V)<br>SID390QU Fsmifclocku<br>SMIF QSPI output clock frequency<br>24<br>ULP mode (1.0 V)<br>SID397Q<br>Idd_qspi<br>Block current in LP mode (1.0 V)<br>1900<br>µA<br>LP mode (1.1 V)<br>SID398Q<br>Idd_qspi_u<br>Block current in ULP mode<br>(0.9 V)<br>590<br>ULP mode (1.0 V)<br>SID399A<br>SDR_TCSH0<br>CS# active hold to CK<br>4<br>–<br>ns<br>–<br>SID399B<br>SDR_TOUT_<br>SETUP_LF<br>Output setup time of DQ[3:0] to CK<br>high<br>5.1<br>SID399C<br>SDR_TOUT_<br>HOLD_LF<br>Output hold time of DQ[3:0] to CK<br>high<br>SID399D<br>SDR_TIN_V<br>CK low to DQ[3:0] input valid time<br>–<br>6.7<br>SID399E<br>SDR_TIN_HO CK low to DQ[3:0] input hold time<br>1<br>–<br>~~=n~~||||||||||| |**Table 33**<br>**Smart I/O specifications**<br>**Spec ID#**<br>**Parameter**<br>**Description**<br>**Min**<br>SID420<br>SMIO_BYP<br>Smart I/O Bypass delay<br>–<br>SID421<br>SMIO_LUT<br>Smart I/O LUT prop delay<br>~~——~~||||**Typ**<br>–||**Max**<br>2|**Unit**<br>ns||**Details / conditions**<br>–|| ## **Note** > 5. As an example, if the clk_path[1] source is changed from the IMO to the FLL (see **Figure 3** ) then clk1 is the IMO and clk2 is the FLL. Datasheet 002-31976 Rev. *F 47 2023-09-26 ## **AIROC™ Bluetooth® LE 5.4 MCU** Electrical specifications ## **5.6.11 JTAG boundary scan** |**5.6.11**|**JTAG boundary scan**|**JTAG boundary scan**|||||| |---|---|---|---|---|---|---|---| |**Table 34**|**JTAG boundary scan**||||||| |**Spec ID#**||**Parameter**|**Min**|**Typ **|**Max **|**Unit**|**Description**| |JTAG boundary scan parameters|||||||| |SID460|TCKLOW|TCK LOW minimum|34|–|–|ns|–| |SID461|TCKHIGH|TCK HIGH|10||||| |SID462|TCK_TDO|TDO clock-to-out (max) from|–||22||| |||fallingTCK|||||| |SID463|TSU_TCK|TDI, TMS Setup time before|12||–||| |||risingTCK|||||| |SID464|TCk_THD|TDI, TMS Hold time after|10||||| |||risingTCK|||||| |SID465|TCK_TDOV|TCK to TDO data valid|22||||| |||(High-Z to active)|||||| |SID466|TCK_TDOZ|TCK to TDO data valid|||||| |||(Active to High-Z).|||||| |JTAG boundary scan parameters for 1.1 V (LP) mode operation|||||||| |SID468|TCKLOW|TCK low|52|–|–|ns|–| |SID469|TCKHIGH|TCK high|10||||| |SID469A|TCKPERIOD|CLK_JTAG_PERIOD,|–|62|||| |||30 pF load|||||| |SID470|TCK_TDO|TCK falling edge to output||–|40||| |||valid|||||| |SID471|TSU_TCK|Input valid to TCK risingedge|12||–||| |SID472|TCk_THD|Input hold time to TCK rising|10||||| |||edge|||||| |SID473|TCK_TDOV|TCK falling edge to output|40||||| |||valid (High-Z to active).|||||| |JTAG boundary scan p for 1.0 V (ULP) mode operation|||||||| |SID468A|TCKLOW|TCK low|102|–|–|ns|–| |SID469A|TCKHIGH|TCK high|20||||| |SID470A|TCK_TDO|TCK falling edge to output|–||80||| |||valid|||||| |SID471A|TSU_TCK|Input valid to TCK risingedge|22||–||| |SID472A|TCk_THD|Input hold time to TCK rising|20|–|–|ns|–| |||edge|||||| |SID473A|TCK_TDOV|TCK falling edge to output|80||||| |||valid (High-Z to active).|||||| |SID474A|TCK_TDOZ|TCK fallingedgetooutput|||||| |||valid (Active to high-Z).|||||| Datasheet 002-31976 Rev. *F 48 2023-09-26 ## **AIROC™ Bluetooth® LE 5.4 MCU** Electrical specifications |SID317R[6]|RXS, IDLE|RX sensitivity with ideal<br>transmitter|–|–98|–|dBm|Across RF operating<br>frequency range| |---|---|---|---|---|---|---|---| |SID318R[7]||||–96.5|||| |SID319R|PRXMAX|Maximum received signal<br>strength at < 30.8% PER||–5|||RF-PHY specification<br>(RCV-LE/CA/06/C)| |SID320R|CI1|Co-channel interference,<br>Wanted Signal at –67 dBm<br>and Interferer at FRX||9|21|dB|RF-PHY specification<br>(RCV-LE/CA/03/C)| |SID321R|CI2|Adjacent channel<br>interference<br>Wanted Signal at –67 dBm<br>and Interferer at FRX ± 1 MHz||–3|15||| |SID322R|CI3|Adjacent channel<br>interference<br>Wanted Signal at –67 dBm<br>and Interferer at FRX ± 2 MHz||–45|–17||| |SID323R|CI4|Adjacent channel<br>interference<br>Wanted Signal at –67 dBm<br>and Interferer at ≥ FRX ± 3<br>MHz||–49|–27||| |SID324R|CI5|Adjacent channel<br>interference<br>Wanted Signal at –67 dBm<br>and Interferer at image<br>frequency (FIMAGE)||–31|–9||| |SID325R|CI6|Adjacent channel<br>interference<br>Wanted Signal at –67dBm<br>and Interferer at image<br>frequency (FIMAGE ± 1 MHz)||–35|–15||| ## **Note** 6. Coherent demodulator enabled with stable modulation index. 7. Coherent demodulator enabled with standard modulation index. Datasheet 002-31976 Rev. *F 49 2023-09-26 **AIROC™ Bluetooth® LE 5.4 MCU** Electrical specifications **Table 35 Bluetooth® LE subsystem specifications** _(continued)_ |SID326[6]|RXS, IDLE|RX sensitivity with ideal<br>transmitter|–|–95|–|dBm|Across RF operating<br>frequency range| |---|---|---|---|---|---|---|---| |SID327[7]||||–93.5|||| |SID328R|PRXMAX|Maximum received signal<br>strength at < 30.8% PER||–5|||RF-PHY specification<br>(RCV-LE/CA/06/C)| |SID329R|CI1|Co-channel interference,<br>Wanted Signal at –67 dBm<br>and Interferer at FRX||7|21|dB|RF-PHY specification<br>(RCV-LE/CA/03/C)| |SID330|CI2|Adjacent channel<br>interference Wanted Signal<br>at –67 dBm and Interferer at<br>FRX ± 2 MHz||–2|15||| |SID331|CI3|Adjacent channel<br>interference Wanted Signal<br>at –67 dBm and Interferer at<br>FRX ± 4 MHz||–42|–15||| |SID332|CI4|Adjacent channel<br>interference Wanted Signal<br>at –67 dBm and Interferer at<br>FRX ± 6 MHz||–42|–27||| |SID333|CI5|Adjacent channel<br>interference Wanted Signal<br>at –67 dBm and Interferer at<br>Image frequency<br>(FIMAGE)||–29|–9||| |SID334|CI6|Adjacent channel<br>interference Wanted Signal<br>at –67 dBm and Interferer at<br>Image frequency<br>(FIMAGE ± 2 MHz)||–40|–15||| ## **Note** 6. Coherent demodulator enabled with stable modulation index. 7. Coherent demodulator enabled with standard modulation index. Datasheet 002-31976 Rev. *F 50 2023-09-26 **AIROC™ Bluetooth® LE 5.4 MCU** Electrical specifications **Table 35 Bluetooth® LE subsystem specifications** _(continued)_ |SID501|RXS, IDLE|RX sensitivity with Ideal<br>Transmitter, Standard Mod<br>Index Rx|–|–101|–|dBm|Across RF operating<br>frequency range| |---|---|---|---|---|---|---|---| |SID506|CI1|Co-channel interference,<br>Wanted Signal at –72 dBm<br>and Interferer at FRX|–|3|17|dB|RF-PHY specification<br>(RCV-LE/CA/28/C)| |SID507|CI2|Adjacent channel<br>interference Wanted Signal<br>at –72 dBm and Interferer at<br>FRX ± 1MHz||–11|11||| |SID508|CI3|Adjacent channel<br>interference Wanted Signal<br>at –72 dBm and Interferer at<br>FRX ± 2 MHz||–50|–21||| |SID509|CI4|Adjacent channel<br>interference Wanted Signal<br>at –72 dBm and Interferer at<br>FRX ± 3 MHz||–53|–31||| |SID510|CI5|Adjacent channel<br>interference Wanted Signal<br>at –72 dBm and Interferer at<br>image frequency<br>(FIMAGE)||–37|–13||| |SID511|CI6|Adjacent channel<br>interference Wanted Signal<br>at –72 dBm and Interferer at<br>image frequency<br>(FIMAGE ± 1MHz)||–42|–19||| ## **Note** 6. Coherent demodulator enabled with stable modulation index. 7. Coherent demodulator enabled with standard modulation index. Datasheet 002-31976 Rev. *F 51 2023-09-26 **AIROC™ Bluetooth® LE 5.4 MCU** Electrical specifications **Table 35 Bluetooth® LE subsystem specifications** _(continued)_ |SID512|RXS, IDLE|RX sensitivity with Ideal<br>Transmitter[7]|–|–106|–|dBm|Across RF operating<br>frequency range| |---|---|---|---|---|---|---|---| |SID517|CI1|Co-channel interference,<br>Wanted Signal at –79 dBm<br>and Interferer at FRX||6|12|dB|RF-PHY specification<br>(RCV-LE/CA/29/C)| |SID518|CI2|Adjacent channel<br>interference Wanted Signal<br>at –79 dBm and Interferer at<br>FRX ± 1MHz||–18|6|–|| |SID519|CI3|Adjacent channel<br>interference Wanted Signal<br>at –79 dBm and Interferer at<br>FRX ± 2 MHz||–52|–26||| |SID520|CI4|Adjacent channel<br>interference Wanted Signal<br>at –79 dBm and Interferer at<br>FRX ± 3 MHz||–51|36||| |SID521|CI5|Adjacent channel<br>interference Wanted Signal<br>at –79 dBm and Interferer at<br>Image frequency (FIMAGE)||–40|–18||| |SID522|CI6|Adjacent channel<br>interference Wanted Signal<br>at –79 dBm and Interferer at<br>Image frequency<br>(FIMAGE ± 1MHz)||–47|–24||| ## **Note** 6. Coherent demodulator enabled with stable modulation index. 7. Coherent demodulator enabled with standard modulation index. Datasheet 002-31976 Rev. *F 52 2023-09-26 ## **AIROC™ Bluetooth® LE 5.4 MCU** Electrical specifications **Table 35 Bluetooth® LE subsystem specifications** _(continued)_ |SID338|OBB1|Out of Band Blocking<br>Wanted Signal at –67 dBm<br>and Interferer at F = 30 –2000<br>MHz|–30|TBD|–|dBm|RF-PHY specification<br>(RCV-LE/CA/04/C)| |---|---|---|---|---|---|---|---| |SID339|OBB2|Out of Band Blocking<br>Wanted Signal at –67 dBm<br>and Interferer at<br>F = 2003 - 2399 MHz|–35|TBD|–|dBm|RF-PHY specification<br>(RCV-LE/CA/04/C)| |SID340|OBB3|Out of Band Blocking,<br>Wanted Signal at –67 dBm<br>and Interferer at<br>F = 2484 - 2997 MHz|||||| |SID341|OBB4|Out of Band Blocking<br>Wanted Signal at -67 dBm<br>and Interferer at<br>F = 3000 - 12750 MHz|–30||||RF-PHY specification<br>(RCV-LE/CA/04/C)| |SID342|IMD|Intermodulation<br>Performance Wanted Signal<br>at –64 dBm and 1 Mbps<br>Bluetooth® LE, 3rd, 4th and<br>5th offset channel|–50|–|||RF-PHY specification<br>(RCV-LE/CA/05/C)| |SID343|RXSE1|Receiver Spurious emission<br>30 MHz to 1.0 GHz|–||–57||100 kHz measurement<br>bandwidth<br>ETSI EN300 328 V2.1.1| |SID344|RXSE2|Receiver Spurious emission<br>1.0 GHz to 12.75 GHz|||–53||1 MHz measurement<br>bandwidth<br>ETSI EN300 328 V2.1.1| ## **Note** 6. Coherent demodulator enabled with stable modulation index. 7. Coherent demodulator enabled with standard modulation index. Datasheet 002-31976 Rev. *F 53 2023-09-26 **AIROC™ Bluetooth® LE 5.4 MCU** Electrical specifications |SID345|TXP, ACC<br>~~es~~<br>~~ES~~|RF power accuracy<br>~~en~~<br>~~ES~~|–2<br>~~n~~<br>~~ES~~|–<br>~~n~~<br>~~ES~~|2<br>~~n~~<br>~~ES~~|dB<br>~~ES~~|–| |---|---|---|---|---|---|---|---| |SID346|TX0<br>~~es~~<br>~~ES~~|Power range<br>~~en~~<br>~~ES~~<br>~~ee~~|–<br>~~n~~<br>~~ES~~<br>~~eee~~<br>~~ee~~<br>|23<br>~~n~~<br>~~ES~~|–<br>~~n~~<br>~~ES~~<br>~~eee~~||–24 dBm to 0 dBm| ||TX10<br>~~ES~~<br>~~a~~|||33<br>~~ES~~<br>~~ee~~|||–24 dBm to 10 dBm| |SID347|TXP, 0dBm<br>~~a~~|Output power, 0 dB power<br>setting<br>~~ee~~||0<br>~~ee~~||dBm|For TX10 mode,<br>BT_PAVDDconnected<br>to VCCPA. The<br>minimum supply<br>voltage VDDPA is 2.6 V.| |SID348|TXP, MAX<br>~~a~~<br>~~a ~~|Output power,<br>10 dBm power setting<br>~~ee~~<br> ~~eee~~||10<br>~~ee~~<br>~~eee~~|||| |SID349<br>~~SF~~|TXP, MIN<br>~~a~~<br>~~SF~~|Output power,<br>minimum power setting<br>~~ee~~<br>||–20<br>~~ee~~|||| |SID350<br>~~SF~~|F2Max<br>~~a~~<br>~~SF~~|Average frequency deviation<br>for 10101010 pattern<br>~~ee~~<br>|185<br>~~ee~~<br>|–<br>~~ee~~<br>~~eee~~||kHz<br>~~eee~~|RF-PHY specification<br>(TRM-LE/CA/05/C)| |SID350R<br>~~SF~~|F2Max_2M<br>~~SFPf~~|Average frequency deviation<br>for 10101010 pattern for<br>2 Mbps<br>~~Pf~~|370<br>~~Pf~~||||| |SID350LR|F1Max_S8<br>~~Pf~~<br>~~ee~~|Average frequency deviation<br>for 10101010 pattern for<br>125 bps<br>~~Pf~~<br>~~eee~~|185<br>~~Pf~~<br>~~eee~~||||RF-PHY specification<br>(TRM-LE/CA/13/C)| |SID351|F1AVG<br>~~ee~~|Average frequency deviation<br>for 11110000 pattern<br>~~eee~~|225<br>~~eee~~|250<br>~~eee~~|275<br>~~eee~~||RF-PHY specification<br>(TRM-LE/CA/05/C)| |SID351R|F1AVG_2M<br>~~ee~~<br>~~Pf~~|Average frequency deviation<br>for 11110000 pattern for<br>2 Mbps<br>~~eee~~<br>~~Pf~~|450<br>~~eee~~<br>~~Pf~~|500<br>~~eee~~<br>~~Pf~~|550<br>~~eee~~<br>~~Pf~~||RF-PHY specification<br>(TRM-LE/CA/05/C)| |SID351R|F1AVG_S8<br>~~Pf~~<br>~~ee~~|Average frequency deviation<br>for 11110000 pattern for<br>125 kbps<br>~~Pf~~<br>~~ee~~|225<br>~~Pf~~<br>~~ee~~|250<br>~~Pf~~|275<br>~~Pf~~<br>~~eee~~||RF-PHY specification<br>(TRM-LE/CA/13/C)| |SID352|EO<br>~~ee~~<br>~~ee~~|Eye opening =<br>∆F2AVG/∆F1AVG<br>~~ee~~<br>~~eee~~|0.8<br>~~ee~~<br>~~eee~~|–<br>~~eee~~<br>~~eee~~<br>~~HE~~<br>~~Lt~~<br>~~ae~~<br>~~|~~|–<br>~~eee~~<br>~~eee~~|–<br>~~eee~~|RF-PHY specification<br>(TRM-LE/CA/05/C)| |SID353|FTX,ACC<br>~~ee~~<br>~~ee~~<br>~~ee~~|Frequency accuracy<br>~~ee~~<br>~~eee~~<br>~~eee~~|–150<br>~~ee~~<br>~~eee~~<br>~~eee~~||150<br>~~eee~~<br>~~eee~~<br>~~eee~~|kHz<br>~~eee~~|RF-PHY specification<br>(TRM-LE/CA/06/C)| |SID354|FTX,MAXDR<br>~~ee~~<br>~~ee~~|Maximum frequency drift<br>~~eee~~<br>~~eee~~|–50<br>~~eee~~<br>~~eee~~||50<br>~~eee~~<br>~~eee~~||RF-PHY specification<br>(TRM-LE/CA/06/C)| |SID355|FTX, INITDR<br>~~ee~~<br>~~HE~~<br>~~oe~~|Initial frequency drift<br>~~eee~~<br>~~HE~~|–20<br>~~eee~~<br>~~HE~~<br>~~—}~~||20<br>~~eee~~<br>~~HE~~<br>~~Lt~~||RF-PHY specification<br>(TRM-LE/CA/06/C)| |SID355LR|FTX, INITDR,<br>S8<br>~~HE~~<br>~~oe~~||–19.2<br>~~HE~~<br>~~—}~~||19.2<br>~~HE~~<br>~~Lt~~||RF-PHY specification<br>(TRM-LE/CA/14/C)| |SID356|FTX, DR<br>~~oe~~<br>~~—~~|Maximum drift rate<br>~~ae~~|–20<br>~~—}~~<br>~~ae~~<br>~~|~~||20<br>~~Lt~~<br>~~ae~~<br>~~|~~|kHz/<br>50 µs<br>~~ae~~|RF-PHY specification<br>(TRM-LE/CA/06/C)| ||FTX, DR, S8<br>~~—~~||–19.2<br>~~ae~~<br>~~|~~||19.2<br>~~ae~~<br>~~|~~||RF-PHY specification<br>(TRM-LE/CA/14/C)| ## **Note** 6. Coherent demodulator enabled with stable modulation index. 7. Coherent demodulator enabled with standard modulation index. Datasheet 002-31976 Rev. *F 54 2023-09-26 ## **AIROC™ Bluetooth® LE 5.4 MCU** Electrical specifications **Table 35 Bluetooth® LE subsystem specifications** _(continued)_ **==> picture [508 x 631] intentionally omitted <==** **----- Start of picture text -----**<br> ||||||||| |---|---|---|---|---|---|---|---| |Spec ID#|Parameter|Description|Min|Typ|Max|Unit|Details / conditions| |SID357|IBSE1|In Band Spurious Emission at|–|–|–20|dBm|RF-PHY specification| |2 MHz offset (1 Mbps)|(TRM-LE/CA/03/C)| |In Band Spurious Emission at| |4 MHz offset (2 Mbps)| |SID358|IBSE2|In Band Spurious Emission at|–30| |> 3 MHz offset (1 Mbps)| |In Band Spurious Emission at| |> 6 MHz offset (2 Mbps)| |SID359|TXSE1|Transmitter Spurious|–|–|–55.5|FCC-15.247| |Emissions (Averaging), < 1.0| |GHz| |SID360|TXSE2|Transmitter Spurious|–41.5| |Emissions (Averaging), > 1.0| |GHz| |RF Current specifications| |SID361|IRX1_wb|Receive current (LE 1 Mbps)|–|5.6|–|mA|Measured with| |VCC_BUCK = 3.0 V.| |SID362|ITX1_0dBm|TX current at 0 dBm setting|5.2| |In all cases, VCCI = 1.16| |(LE 1 Mbps)| |V and VCCRF = 1.1 V.| |SID365R|ITX1_10dBm|TX current at 10 dBm setting|17.2|For TX0,| |(LE 1 Mbps)|BT_PAVDD = VCCRF.| |For TX10,| |BT_PAVDD = VCCPA =| |2.5 V| |EES| |General RF specifications| |SID373|FREQ|RF operating frequency|2400|–|2482|MHz|–| |SID374|CHBW|Channel spacing|–|2|–| |SID375|DR1|On-air data rate (1 Mbps)|1000|kbps| |SID376|DR2|On-air data rate (2 Mbps)|2000| |=e| |RSSI specifications| |SID379|RSSI, ACC|RSSI accuracy|–4|–|4|dB|–95 dBm to –20 dBm| |measurement range| |SID381|RSSI, PER|RSSI sample period|–|6|–|µs|–| |re| |System-level Bluetooth® LE specifications| |SID433R|Adv_Pwr|Advertising power, 1.28s|–|44.5|–|µW|Connectible| |advertising interval,|advertising,| |31 bytes, TX 0 dBm|VBAT = 3.0 V| |SID434R|Conn_Pwr_30|Connection power, 300ms|64.6|VBAT = 3.0V| |0|connection interval, 0 bytes,| |TX 0 dBm| |SID435R|Conn_Pwr_1S|Connection power, 1000ms|29.5| |connection interval, 0 bytes,| |TX 0 dBm| |SB| |Note| |6.|Coherent demodulator enabled with stable modulation index.| **----- End of picture text -----**<br> 7. Coherent demodulator enabled with standard modulation index. Datasheet 002-31976 Rev. *F 2023-09-26 55 **AIROC™ Bluetooth® LE 5.4 MCU** Ordering information ## **6 Ordering information** **Table 36** lists the CYW20829 part numbers and features. **Table 36 Ordering part numbers Part number Package Ambient operating temperature** CYW20829B0LKML/CYW20829B0LKMLT[[8]] 6 6 0.9 mm 56-QFN –30°C to 85°C ~~>~~ **Note** 8. T and R device with “T”. Datasheet 002-31976 Rev. *F 56 2023-09-26 **AIROC™ Bluetooth® LE 5.4 MCU** Packaging ## **7 Packaging** This product line is offered in 56-QFN package. |This product line is offered in 56-QFN package.|| |---|---| |**Table 37**<br>**Package dimensions**|| |**Spec ID#**<br>**Package**<br>**Description**<br>PKG_2<br>56-QFN<br>56-QFN, 660.9 mm height with 0.35-mm pitch<br>~~———~~|**Package drawing number**<br>002-31757| |**Table 38**|**Package characteristics**|||| |---|---|---|---|---| |**Parameter**|**Description**<br>**Conditions**<br>**Min**<br>**Typ**||**Max**|**Unit**| |TA|Operatingambient<br>–|–30<br>25|85|°C| |TJ|Operating junction|–|100|| |TJA|PackageJA(56-QFN)|–<br>13.8|–|°C/watt| |TJC|PackageJC(56-QFN)|4.8||| |**Table 39**|**Solder reflow peak temperature**|||| |**Package**<br>56-QFN<br>~~——~~|**Maximum peak temperature**<br>**Maximum time at peak**<br>**temperature**<br>260°C<br>30 seconds|||| |**Table 40**|**Package moisture sensitivity level (MSL), IPC/JEDEC J-STD-2**|||| |**Package**<br>**MSL**<br>56-QFN<br>MSL-3<br>~~———————————————~~||||| Datasheet 002-31976 Rev. *F 57 2023-09-26 **AIROC™ Bluetooth® LE 5.4 MCU** ## Packaging **==> picture [455 x 181] intentionally omitted <==** **----- Start of picture text -----**<br> NOTES:<br>DIMENSIONS<br>SYMBOL 1. ALL DIMENSIONS ARE IN MILLIMETERS.<br>MIN. NOM. MAX.<br>2. N IS THE TOTAL NUMBER OF TERMINALS.<br>e 0.35 BSC AN 3 DIMENSION "b" APPLIES TO METALLIZED TERMINAL AND IS MEASURED<br>N 56<br>BETWEEN 0.15 AND 0.30mm FROM TERMINAL TIP. IF THE TERMINAL HAS<br>ND 14<br> THE OPTIONAL RADIUS ON THE OTHER END OF THE TERMINAL, THE<br>L 0.30 0.40 0.50<br>DIMENSION "b" SHOULD NOT BE MEASURED IN THAT RADIUS AREA.<br>b 0.11 0.16 0.21<br>L\ 4 ND REFERS TO THE NUMBER OF TERMINALS ON D SIDE.<br>D2 4.50 4.60 4.70<br>LN 5 PIN #1 ID ON TOP WILL BE LOCATED WITHIN THE INDICATED ZONE.<br>E2 4.50 4.60 4.70<br>L\ 6 COPLANARITY ZONE APPLIES TO THE EXPOSED HEAT SINK<br>D 6.00 BSC<br>SLUG AS WELL AS THE TERMINALS.<br>E 6.00 BSC<br>7. JEDEC SPECIFICATION NO. REF. : N/A.<br>A - - 0.90<br>A1 0.00 - 0.05<br>A3 0.203 REF<br>R 0.20 TYP<br>K 0.30 MIN 002-31757 Rev. **<br>**----- End of picture text -----**<br> **Figure 8 Package outline, 56-lead QFN 6.0** **6.0** **0.9 mm LT56F 4.60** **4.60 mm E-Pad (SAWN) (PG-VQFN-56)** Datasheet 002-31976 Rev. *F 2023-09-26 58 ## **AIROC™ Bluetooth® LE 5.4 MCU** Acronyms |**Table 41**|**Acronyms used in this document**| |---|---| |**Acronym**|**Description**| |3DES|triple DES (data encryption standard)| |ADC|analog-to-digital converter| |AES|advanced encryption standard| |AHB|AMBA<br>(advanced microcontroller bus architecture) high-performance bus, an Arm® data transfer bus| |API|application programminginterface| |Arm®|advanced RISC machine, a CPU architecture| |BOD|brown-out detect| |BTSS|Bluetooth® sub system| |CAD|computer aided design| |CBC|cipher block chaining| |CFB|cipher feedback| |CCO|current controlled oscillator| |CM0+|Cortex®-M0+, an Arm® CPU| |CM4|Cortex®-M4, an Arm® CPU| |CMOS|complementary metal-oxide-semiconductor, a process technology for IC fabrication| |CPU|central processingunit| |CRC|cyclic redundancy check, an error-checkingprotocol| |CSD|CAPSENSE™ sigma-delta| |CTR|Counter| |DAC|digital-to-analogconverter, see also IDAC, VDAC| |DAP|debugaccess port| |DES|data encryption standard| |DMA|direct memory access, see also TD| |DNL|differential nonlinearity, see also INL| |DSI|digital system interconnect| |ECB|electronic code book| |ECC|elliptic curve cryptography| |ECDSA|elliptic curve digital signature algorithm| |ECO|external crystal oscillator| |EMI|electromagnetic interference| |ESD|electrostatic discharge| |FIFO|first-in, first-out| |FLL|frequency locked loop| |FS|full-speed| |GND|Ground| |GPIO|general-purpose input/output| |HMAC|hash-based message authentication code| Datasheet 002-31976 Rev. *F 59 2023-09-26 ## **AIROC™ Bluetooth® LE 5.4 MCU** Acronyms |**Table 41**|**Acronyms used in this document**_(continued)_| |---|---| |**Acronym**|**Description**| |HSIOM|high-speed I/O matrix| |I/O|input/output, see also GPIO, DIO, SIO, USBIO| |I2C, or IIC|Inter-Integrated Circuit, a communications protocol| |I2S|inter-IC sound| |IC|integrated circuit| |IDAC|current DAC, see also DAC, VDAC| |IDE|integrated development environment| |ILO|internal low-speed oscillator, see also IMO| |IMO|internal main oscillator, see also ILO| |INL|integral nonlinearity, see also DNL| |IoT|internet of things| |IPC|inter-processor communication| |IRQ|interrupt request| |JTAG|Joint Test Action Group| |LIN|Local Interconnect Network, a communications protocol| |LP|low power| |LS|low-speed| |LUT|lookup table| |LVD|low-voltage detect, see also LVI| |LVTTL|low-voltage transistor-transistor logic| |MAC|multiply-accumulate| |MCU|microcontroller unit| |MCWDT|multi-counter watchdogtimer| |MISO|master-in slave-out| |MMIO|memory-mapped input output| |MOSI|master-out slave-in| |MPU|memory protection unit| |MSL|moisture sensitivity level| |NMI|nonmaskable interrupt| |NVIC|nested vectored interrupt controller| |OFB|output feedback| |OTP|one-time programmable| |OVT|overvoltage tolerant| |PCB|printed circuit board| |PCM|pulse code modulation| |PDM|pulse density modulation| |PHY|physical layer| |PLL|phase-locked loop| |POR|power-on reset| |PRNG|pseudo random numbergenerator| Datasheet 002-31976 Rev. *F 60 2023-09-26 ## **AIROC™ Bluetooth® LE 5.4 MCU** Acronyms |**Table 41**|**Acronyms used in this document**_(continued)_| |---|---| |**Acronym**|**Description**| |PSRR|power supply rejection ratio| |PWM|pulse-width modulator| |QD|quadrature decoder| |QSPI|quad serial peripheral interface| |RAM|random-access memory| |RISC|reduced-instruction-set computing| |ROM|read-only memory| |RTC|real-time clock| |RX|receive| |SAR|successive approximation register| |SARMUX|SAR ADC multiplexer bus| |SCB|serial communication block| |SHA|secure hash algorithm| |SMIF|serial media interface| |SNR|signal-to-noise ration| |SPI|Serial Peripheral Interface, a communications protocol| |SRAM|static random access memory| |SROM|supervisory read-only memory| |SWD|serial wire debug, a test protocol| |SWJ|serial wire JTAG| |SWO|single wire output| |SWV|serial-wire viewer| |TCPWM|timer, counter, pulse-width modulator| |TDM|time division multiplexed| |TRM|technical reference manual| |TRNG|true random numbergenerator| |TX|transmit| |UART|Universal Asynchronous Transmitter Receiver, a communications protocol| |ULP|ultra-low power| |WCO|watch crystal oscillator| |WDT|watchdog timer| |WIC|wakeup interrupt controller| |XIP|execute-in-place| |XRES|external reset input pin| Datasheet 002-31976 Rev. *F 61 2023-09-26 ## **AIROC™ Bluetooth® LE 5.4 MCU** Document conventions |**9**|**Document conventions**| |---|---| |**9.1**|**Units of measure**| |**Table 42**|**Units of measure**| |**Symbol**|**Unit of measure**| |°C|degrees Celsius| |dB|decibel| |fF|femto farad| |Hz|hertz| |KB|1024 bytes| |kbps|kilobits per second| |khr|kilohour| |kHz|kilohertz| |k|kilo ohm| |ksps|kilosamples per second| |LSb|least significant bit| |Mbps|megabits per second| |MHz|megahertz| |M|mega-ohm| |Msps|megasamples per second| |µA|microampere| |µF|microfarad| |µH|microhenry| |µs|microsecond| |µV|microvolt| |µW|microwatt| |mA|milliampere| |ms|millisecond| |mV|millivolt| |nA|nanoampere| |ns|nanosecond| |nV|nanovolt| |W|ohm| |pF|picofarad| |ppm|parts per million| |ps|picosecond| |s|second| |sps|samples per second| |sqrtHz|square root of hertz| |V|volt| Datasheet 002-31976 Rev. *F 62 2023-09-26 ## **AIROC™ Bluetooth® LE 5.4 MCU** Revision history ## **Revision history** |**Document**<br>**revision**|**Date**<br>~~oe~~|**Description of changes**| |---|---|---| |**|2021-04-27<br>~~oe~~<br>~~OO~~|New datasheet for new device family.| |*A|2022-03-30<br>~~OO~~|Migrated to Infineon template.<br>Refer to MEMO# KHMU-70 for more details.| |*B|2023-02-02|Updated template.<br>Updated**“Block diagram”**on page 5.<br>Updated**Figure 4**,**Figure 6**, and**Figure 7**.<br>Updated**“CPU”**on page 6,**“Cryptography accelerator (Cryptolite)”**on<br>page 7,**“Power system”**on page 10.<br>Updated**Table 6**:<br>Deleted 40-QFN pin number.<br>Added pin number for BT_XTALI and BT_XTALO.<br>Added sections:**“AES-128”**on page 7,**“Vector unit (VU)”**on page 8,<br>**“Controller area network flexible data-rate (CAN FD)”**on page 8,**“Local**<br>**interconnect network (LIN)”**on page 8,**“Real time clock (RTC)”**on<br>page 8.<br>Added BT_RF pin details.<br>Deleted 40-QFN pinout diagram.<br>Updated**Table 7**:Removed columns ACT #2 and ACT #3.<br>Updated**Table 9**: Added SID523 through SID529. Added Deep Sleep mode<br>parameters.<br>Updated Typ. and Max. values for SID13A and SID13B.<br>Updated**Table 19**: Updated Min. values for SID432 and SID 432U.<br>Updated**Table 31**: Updated Description.<br>Updated**Table 33**: Updated Max. value for SID420 and SID421.<br>Updated**Table 35**:<br>Added notes for SID317R, SID326, and SID512.<br>Updated Typ. value for SID326, SID348, SID433R, SID434R, and SID435R.<br>Added TXO and TX1 parameters for SID346.<br>Added SID501, SID506 through SID512, and SID517 through SID522.<br>Added Description for SID347 through SID349.<br>Updated Description for SID361 through SID365R.<br>Updated**“Packaging”**on page 57: Deleted 40-QFN details.<br>Updated**“Revision history”**on page 63: Replaced A0 instances with B0.<br>Updated**“Ordering information”**on page 56: Deleted 40-QFN package<br>diagram (002-31756).<br>Updated**Table 41**.<br>Deleted references to AoA/AoD in the entire document.| |*C|2023-04-18|Deleted Preliminary status.<br>Deleted External clock specifications section.<br>Updated**Features**and**Cryptography accelerator (Cryptolite)**.<br>Updated**Figure 2**,**Figure 4**,**Figure 6**, and**Figure 7**.<br>Updated**Table 6**,**Table 7**,**Table 9**, and**Table 35**.<br>Release to web.| |*D|2023-05-10|Reverted the datasheet to “Preliminary” status.<br>Updated the**Revision history**section.<br>Updated**Figure 7**.| Datasheet 002-31976 Rev. *F 63 2023-09-26 ## **AIROC™ Bluetooth® LE 5.4 MCU** Revision history |**Document**<br>**revision**|**Date**|**Description of changes**| |---|---|---| |*E|2023-09-01<br>~~_~~|Updated**Features**.<br>Updated “RF current specifications” in**Table 35**.<br>Added a note in**“Internal low-speed oscillator (ILO)”**on page 12.<br>Updated “Max” value for Deep Sleep parameters in**Table 9**.<br>Updated**Table 28**and**Table 35**.<br>Removed the Errata section.| |*F|2023-09-26|Updated**Table 9**.| |||Updated**Table 2**,**Table 3**, and**“Memory map”**on page 9.| |||Updated “System-level Bluetooth® LE specifications” in**Table 35**.| |||Datasheet is moved from “Preliminary” to “Final” status.| Datasheet 002-31976 Rev. *F 2023-09-26 64 ## **Trademarks** All referenced product or service names and trademarks are the property of their respective owners. The Bluetooth® word mark and logos are registered trademarks owned by Bluetooth SIG, Inc., and any use of such marks by Infineon is under license. ||**IMPORTANT NOTICE**|**WARNINGS**| |---|---|---| |**Edition 2023-09-26**|The information given in this document shall in no|Due to technical requirements products may contain| |**Published by**|event be regarded as a guarantee of conditions or<br>characteristics (“Beschaffenheitsgarantie”).|dangerous substances. For information on the types<br>in question please contact your nearest Infineon| |||Technologies office.| |**Infineon Technologies AG**<br>**81726 Munich, Germany**|With respect to any examples, hints or any typical<br>values stated herein and/or any information<br>regarding the application of the product, Infineon|Except as otherwise explicitly approved by Infineon<br>Technologies in a written document signed by| ||Technologies<br>hereby<br>disclaims<br>any<br>and<br>all|authorized<br>representatives<br>of<br>Infineon| ||warranties and liabilities of any kind, including|Technologies, Infineon Technologies’ products may| ||without limitation warranties of non-infringement of|not be used in any applications where a failure of the| |**© 2023 Infineon Technologies AG.**<br>**All Rights Reserved.**|intellectual property rights of any third party.<br>In addition, any information given in this document|product or any consequences of the use thereof can<br>reasonably be expected to result in personal injury.| ||is subject to customer’s compliance with its|| |**Do you have a question about this**<br>**document?**<br>**Email:**|obligations stated in this document and any<br>applicable legal requirements, norms and standards<br>concerning customer’s products and any use of the<br>product of Infineon Technologies in customer’s|| |**erratum@infineon.com**|applications.|| ||The data contained in this document is exclusively|| |**Document reference**|intended for technically trained staff. It is the|| |**002-31976 Rev. *F**|responsibility of customer’s technical departments<br>to evaluate the suitability of the product for the|| ||intended application and the completeness of the|| ||product information given in this document with|| ||respect to such application.||
Updated at April 28, 2026
Infineon Technologies is a globally recognized leader in semiconductor solutions, renowned for driving innovation in power management, energy efficiency, and modern mobility. With a strong legacy of engineering excellence, the company provides highly reliable components designed to meet the rigorous demands of industrial, automotive, and advanced commercial applications. The core of our Infineon portfolio is centered on their industry-leading discrete semiconductors. We offer an extensive selection of single and dual MOSFETs, alongside a robust range of single IGBTs and advanced IGBT modules. These flagship power transistors are essential for high-efficiency power conversion and motor control, providing engineers with superior thermal performance and minimized switching losses. Beyond advanced field-effect transistors, the selection includes a comprehensive array of diodes and rectifiers, heavily featuring Schottky diodes, as well as fast-recovery and RF/PIN diodes. This power foundation is further supported by bipolar transistors, intelligent power modules, and thyristor SCR modules, delivering the critical building blocks required for complex power system designs. To support broader system integration, the portfolio also encompasses specialized solutions such as solid-state relays, AC/DC LED driver ICs, and Bluetooth communications modules. From high-power industrial rectifiers to wireless connectivity adapters, Infineon equips designers with the precision components needed to build efficient, scalable, and fully connected electronic systems.
About Novapart
Novapart is a B2B electronic component broker specialising in stock shortages and cost reduction. We source hard-to-find parts and identify compliant alternatives across a catalogue of 410,000+ components from 500+ manufacturers.
Learn more →Stock Shortage Specialist
When a component is unavailable, discontinued or has an unacceptable lead time, we tap into our network of vetted European and Asian distributors to source what you need — without compromising on quality or traceability.
Request a quote →Compliant Alternatives
We identify pin-to-pin, electrically equivalent substitutes that meet the same certifications (RoHS, AEC-Q100, REACH) as your original specification — validated against datasheets, not just part numbers. Often at a lower cost.
BOM Analysis service →