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CYW20820A1KFBG
Bluetooth Module, LE 5.2 Version, 3Mbps, -94.5dBm, 2.375 to 2.625 V Supply, -30 °C to 85 °C
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- Manufacturer: INFINEON
- Product type: Bluetooth Modules & Adaptors
- SVHC: No SVHC (25-Jun-2025)
- Product Range: -
- Bluetooth Class: Class 1
- Bluetooth Version: Bluetooth LE 5.2
- Supply Voltage Range: 2.375 V to 2.625 V
- Receiver Sensitivity Rx: -94.5 dBm
- Operating Temperature Range: -30 °C to 85 °C
| Delivery and price | |
|---|---|
| Units per pack | 500 |
| Price | 2.6 € |
| Current stock | 1000+ |
| Lead time | 7 days |
Datasheet
## **CYW20820** - A/™“| q **AIROC™ Bluetooth® and Bluetooth® LE system on chip** The CYW20820 is a Bluetooth® 5.2 core spec compliant single-chip solution targeted for Internet of Things (IoT) applications. The CYW20820 is a highly integrated device which delivers up to 11.5 dBm transmit output power in LE and BR modes and up to 2.5 dBm in EDR mode, allowing device makers to reduce product footprints and decrease overall system costs associated with implementing Bluetooth® solutions. The CYW20820 integrates ultra-low-power (ULP) Bluetooth® LE along with the capability to add Bluetooth® classic functionality to enhance the user experience for fitness wearables and trackers. It also provides best-in-class receiver sensitivity for both Bluetooth® basic rate (BR) and enhanced date rate (EDR). Using advanced design techniques and process technology to reduce active and idle power, the CYW20820 addresses the needs of a diverse class of low power Bluetooth® enabled devices that require minimal power consumption and compact size. The device is intended for use in home automation, sensors (medical, home, security and industrial), lighting, Bluetooth® Mesh or any Bluetooth® connected IoT application. The datasheet provides details of the functional, operational, and electrical characteristics of the CYW20820 device. It is intended for hardware, design, application, and original equipment manufacturer (OEM) engineers. ## **Features** - Bluetooth® sub-system - Complies with Bluetooth® core specification version 5.2 - Includes support for basic data rate (BR), EDR 2 Mbps and 3 Mbps, extended synchronous connection-oriented (eSCO), Bluetooth® LE, and LE 2 Mbps. - Programmable basic data rate (BDR) TX power up to 11.5 dBm - Excellent receiver sensitivity (-94.5 dBm for Bluetooth® LE 1 Mbps) - Microcontroller - Powerful Arm® Cortex®-M4 core with a maximum speed of 96 MHz - Bluetooth® stack in ROM allowing standalone operation without any external MCU - 256-KB on-chip flash - 176-KB on-chip RAM - Bluetooth® stack, peripheral drivers, security functions built into ROM (1 MB) allowing application to efficiently use on-chip flash - AES-128 and true random number generator (TRNG) - Security functions in ROM including elliptic curve digital signature algorithm (ECDSA) signature verification - Over-the-air (OTA) firmware updates - Peripherals - Up to 22 GPIOs - I2C, I2S, UART, and PCM interfaces - Two Quad-SPI interfaces - Auxiliary ADC with up to 28 analog channels - Programmable key scan 20 8 matrix - Three-axis quadrature signal decoder - General-purpose timers and pulse width modulation (PWM) - Real-time clock (RTC) and watchdog timer (WDT) - Power management - On-chip power-on reset (POR) - Integrated buck (DC-DC) and low drop out (LDO) regulators - On-chip software controlled power management unit - On-chip 32 kHz low power oscillator (LPO) with optional external 32 kHz crystal oscillator support Preliminary Datasheet Please read the Important Notice and Warnings at the end of this document www.infineon.com 002-24743 Rev. *G 2022-09-26 page 1 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Functional block diagram - Wi-Fi coexistence - Global coexistence interface (GCI) for Infineon Wi-Fi parts - Serial enhanced coexistence interface (SECI) - Supported in ModusToolbox™ software - Package types - 62-pin FPBGA - RoHS compliant - Applications - Fitness bands - Home automation - Blood pressure monitors and other medical applications - Proximity sensors - Key fobs - Thermostats and thermometers - Toys - Industrial ## **Functional block diagram** **==> picture [509 x 408] intentionally omitted <==** **----- Start of picture text -----**<br> Bluetooth® Core Microcontroller Subsystem<br>Cache Secure Flash<br>8KB 256KB<br>BT5.0 BT5.0<br>PA RF<br>PHY MAC<br>RAM<br>160KB<br>TL<br>Arm® ROM<br>Clocks 1MB<br>Cortex® M4 Patch<br>XTAL OSC 96MHz Control<br>24MHz Patch RAM<br>16KB<br>HP-LPO<br>32kHz Debug UART/JTAG<br>XTAL OSC<br>32kHz<br>LP-LPO Watchdog<br>16/32/128kHz<br>Peripherals<br>Power Management<br>Core DC-DC ADC TRNG GPIOs (40)<br>RF LDO IR Timer I2C Master I/<br>O<br>Digital LDO PWM 3-Axis Quad. I2C Slave<br>M<br>U<br>PA LDO Keyscan PCM UART (x2) X<br>Q-SPI (x2)<br>Coexistence Interface (GCI)<br>= [25]<br>Preliminary Datasheet 2 002-24743 Rev. *G<br>2022-09-26<br>AHB Bus Matrix<br>**----- End of picture text -----**<br> **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Table of contents ## **Table of contents** **==> picture [510 x 658] intentionally omitted <==** **----- Start of picture text -----**<br> ||| |---|---| |Features ...........................................................................................................................................1| |Functional block diagram...................................................................................................................2| |Table of contents...............................................................................................................................3| |1 Bluetooth® baseband core ...............................................................................................................5| |1.1 BQB and regulatory testing support......................................................................................................................5| |1.2 Wi-Fi coexistence support ......................................................................................................................................6| |2 Microprocessor unit ........................................................................................................................7| |2.1 Main crystal oscillator.............................................................................................................................................7| |2.2 32 kHz crystal oscillator..........................................................................................................................................8| |2.3 Low-frequency clock sources.................................................................................................................................8| |2.4 Power modes ........................................................................................................................................................10| |2.5 Watchdog timer.....................................................................................................................................................10| |2.6 Lockout functionality............................................................................................................................................10| |2.7 True random number generator (TRNG) .............................................................................................................10| |3 Power on and external reset ..........................................................................................................11| |4 Power management unit (PMU) .....................................................................................................12| |5 Power configurations....................................................................................................................13| |5.1 Configuration 1 - VBAT and VDDIO.......................................................................................................................13| |5.2 Configuration 2 - External supplies......................................................................................................................14| |5.3 Configuration 3 - LDOs and VDDIO.......................................................................................................................15| |6 Integrated radio transceiver..........................................................................................................16| |6.1 Transmitter path...................................................................................................................................................16| |6.2 Receiver path ........................................................................................................................................................16| |6.3 Local oscillator (LO)..............................................................................................................................................16| |7 Peripherals|..................................................................................................................................17| |7.1 I2C compatible master .........................................................................................................................................17| |7.2 Serial peripheral interface (SPI)...........................................................................................................................17| |7.3 HCI UART interface................................................................................................................................................17| |7.4 Peripheral UART interface....................................................................................................................................17| |7.5 GPIO ports .............................................................................................................................................................18| |7.6 Keyboard scanner.................................................................................................................................................18| |7.7 Mouse quadrature signal decoder .......................................................................................................................18| |7.8 ADC ........................................................................................................................................................................18| |7.9 PWM.......................................................................................................................................................................18| |7.10 Pulse density modulation (PDM) microphone ..................................................................................................19| |7.11 I2S interface ........................................................................................................................................................20| |7.12 PCM interface ......................................................................................................................................................20| |8 Firmware .....................................................................................................................................22| |9 Pin assignments and GPIOs............................................................................................................23| |9.1 62-pin FBGA pin assignments...............................................................................................................................23| |9.2 I/O states ...............................................................................................................................................................32| |10 Ball maps ...................................................................................................................................33| |10.1 62-pin FBGA pin map ..........................................................................................................................................33| |11 Specifications.............................................................................................................................34| |11.1 Electrical characteristics ....................................................................................................................................34| |11.2 Brown out............................................................................................................................................................35| |11.3 Core buck regulator ............................................................................................................................................36| |11.4 Recommended component ...............................................................................................................................36| |11.5 Digital LDO...........................................................................................................................................................37| |11.6 Recommended component ...............................................................................................................................37| |11.7 RF LDO .................................................................................................................................................................38| **----- End of picture text -----**<br> Preliminary Datasheet 002-24743 Rev. *G 3 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Table of contents 11.8 PALDO..................................................................................................................................................................39 11.9 Digital I/O characteristics ...................................................................................................................................40 11.10 ADC electrical characteristics...........................................................................................................................41 11.11 Current consumption .......................................................................................................................................42 11.12 RF specifications ...............................................................................................................................................43 11.13 Timing and AC characteristics..........................................................................................................................46 **12 Packaging diagrams ....................................................................................................................51** 12.1 62-pin FBGA package..........................................................................................................................................51 12.2 Tape reel and packaging specifications ............................................................................................................52 **13 Ordering information ..................................................................................................................53 14 Acronyms ...................................................................................................................................54 Revision history ..............................................................................................................................57** Preliminary Datasheet 002-24743 Rev. *G 2022-09-26 4 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Bluetooth® baseband core ## **1 Bluetooth® baseband core** The Bluetooth® baseband core (BBC) implements all of the time-critical functions required for high-performance Bluetooth® operation. The BBC manages the buffering, segmentation, and routing of data for all asynchronous connection-less (ACL), SCO, eSCO, Bluetooth® LE, and 2 Mbps Bluetooth® LE connections. It prioritizes and schedules all RX/TX activities including adv, paging, scanning, and servicing of connections. In addition to these functions, it independently handles the host controller interface (HCI) including all commands, events, and data flowing over HCI. The core also handles symbol timing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC), authentication, data encryption/decryption, and data whitening/dewhitening. **Table 1** lists key Bluetooth® features supported by the CYW20820. ## **Table 1 Key Bluetooth® features supported by CYW20820** |**Table 1**lists key Bluetooth® features supported by the CYW20820.<br>**Table 1**<br>**Key Bluetooth® features supported by CYW20820**|**Table 1**lists key Bluetooth® features supported by the CYW20820.<br>**Table 1**<br>**Key Bluetooth® features supported by CYW20820**|**Table 1**lists key Bluetooth® features supported by the CYW20820.<br>**Table 1**<br>**Key Bluetooth® features supported by CYW20820**| |---|---|---| |**Bluetooth® features**||| |**Bluetooth® 1.0**<br>~~tt~~|**Bluetooth® 1.2**<br>~~tt~~|**Bluetooth® 2.0**| |Basic rate<br>~~tt~~|Interlaced scans<br>~~tt~~|EDR 2 Mbps and 3 Mbps| |SCO<br>~~——~~|Adaptive frequency hopping<br>~~——~~|–| |Pagingand inquiry<br>~~———~~|eSCO<br>~~———~~|–| |Page and inquiry scan<br>~~———~~|–<br>~~———~~|–| |Sniff<br>~~—~~|–<br>~~—~~|–| |**Bluetooth® 2.1**<br>~~——~~|**Bluetooth® 3.0**<br>~~——~~|**Bluetooth® 4.0**| |Secure simple pairing<br>~~———~~|Unicast connectionless data<br>~~———~~|Bluetooth® Low Energy| |Enhanced inquiry response<br>~~———~~|Enhanced power control<br>~~———~~|–| |Sniff subrating<br>~~—~~|eSCO<br>~~—~~|–| |**Bluetooth® 4.1**<br>~~——~~|**Bluetooth® 4.2**<br>~~——~~|**Bluetooth® 5.0**| |Low duty cycle advertising<br>~~———~~|Data packet length extension<br>~~———~~|Bluetooth® LE 2 Mbps| |Dual mode<br>~~———~~|Bluetooth® LE secure connection<br>~~———~~|Slot availability mask| |Bluetooth® LE link layer topology<br>~~—TT~~|Link layer privacy<br>~~—TT~~|High duty cycle advertising| ## **1.1 BQB and regulatory testing support** The CYW20820 fully supports Bluetooth® Test mode as described in Part I:1 of the specification of the Bluetooth® system version 3.0. This includes the transmitter tests, normal and delayed loop back tests, and reduced hopping sequence. In addition to the standard Bluetooth® Test mode, the CYW20820 also supports enhanced testing features to simplify RF debugging and qualification. These features include: - Fixed frequency carrier wave (unmodulated) transmission - Simplifies some type-approval measurements (Japan) - Aids in transmitter performance analysis - Fixed frequency constant receiver mode - Receiver output directed to I/O pin - Allows for direct bit error rate (BER) measurements using standard RF test equipment - Facilitates spurious emissions testing for receive mode - Fixed frequency constant transmission - 8-bit fixed pattern or PRBS-9 - Enables modulated signal measurements with standard RF test equipment Preliminary Datasheet 002-24743 Rev. *G 5 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Bluetooth® baseband core ## **1.2 Wi-Fi coexistence support** The CYW20820 includes support for: - Global coexistence interface for use with Infineon Wi-Fi parts - Serial enhanced coexistence interface (SECI) for use with SECI compatible Wi-Fi parts Preliminary Datasheet 002-24743 Rev. *G 6 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Microprocessor unit ## **2 Microprocessor unit** The CYW20820 includes a Cotrex®-M4 processor with 1 MB of program ROM, 176 K RAM, and 256 KB of flash. The CM4 has a maximum speed of 96 MHz. The 256 KB of flash is supported by an 8 KB cache allowing direct code execution from flash at near maximum speed and low power consumption. The CM4 runs all the Bluetooth® layers as well as application code. The ROM includes LMAC, HCI, L2CAP, GATT, as well as other stack layers freeing up most of the flash for application usage. A standard serial wire debug (SWD) interface provides debugging support. See the **“Firmware”** on page 22 for details on the architecture and layers that are included in the ROM. ## **2.1 Main crystal oscillator** The CYW20820 uses a 24 MHz crystal oscillator (XTAL). The XTAL must have an accuracy of ±20 ppm as defined by the Bluetooth® specification. Two external load capacitors are required to work with the crystal oscillator. The selection of the load capacitors is XTAL-dependent (see **Figure 1** ). **==> picture [179 x 79] intentionally omitted <==** **----- Start of picture text -----**<br> CL1<br>XIN<br>Crystal<br>XOUT<br>CL2<br>**----- End of picture text -----**<br> ## **Figure 1 Recommended oscillator configuration** ## **Table 2** ## **Reference crystal electrical specifications** |**Parameter**<br>~~ee~~|**Conditions**<br>~~ee~~|**Min**<br>~~ee~~|**Typ**<br>~~ee~~|**Max**<br>~~ee~~|**Unit**| |---|---|---|---|---|---| |Nominal frequency<br>~~ee~~|–<br>~~ee~~|–<br>~~ee~~|24.000<br>~~ee~~|–<br>~~ee~~|MHz| |Oscillation mode<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|Fundamental<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|||–| |Frequency accuracy<br>~~ee~~<br>~~ee~~|Includes operating temperature<br>range and aging<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~<br>~~eee~~|–<br>~~ee~~<br>~~ee~~<br>~~eee~~|±20<br>~~ee~~<br>~~ee~~<br>~~eee~~|ppm| |Equivalent series resistance<br>~~a~~|–<br>~~a~~|–<br>~~eee~~<br>~~a~~|–<br>~~eee~~<br>~~a~~|60<br>~~eee~~<br>~~a~~|W| |Load capacitance<br>~~ee~~|–<br>~~ee~~|–<br>~~ee~~|8<br>~~ee~~|–<br>~~ee~~|pF| |Drive level<br>~~ee~~|–<br>~~ee~~|–<br>~~ee~~|–<br>~~ee~~|200<br>~~ee~~|μW| |Shunt capacitance<br>~~ee~~<br>~~oT~~|–<br>~~ee~~<br>~~oT~~|–<br>~~ee~~<br>~~oT~~|–<br>~~ee~~<br>~~oT~~|2<br>~~ee~~<br>~~oT~~|pF| Preliminary Datasheet 002-24743 Rev. *G 7 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Microprocessor unit ## **2.2 32 kHz crystal oscillator** |**2.2**<br>**32 kHz crystal oscillator**|**2.2**<br>**32 kHz crystal oscillator**| |---|---| |The CYW20820 includes a 32 kHz oscillator to provide accurate timing during low power operations.**Figure 2**|| |shows the 32-kHz XTAL oscillator with external components and**Table 3**lists the oscillator’s characteristics. This|| |oscillator can be operated with a 32 kHz or 32.768 kHz crystal oscillator or be driven with a clock input at similar|| |frequency. The XTAL must have an accuracy of ±250 ppm or better per the Bluetooth® spec over temperature and|| |including aging. The default component values are: R1 = 10 MΩ and C1 = C2 = ~6 pF. The values of C1 and C2 are|including aging. The default component values are: R1 = 10 MΩ and C1 = C2 = ~6 pF. The values of C1 and C2 are| |used to fine-tune the oscillator.<br>**Figure 2**<br>**32 kHz oscillator block diagram**<br>C 2<br>C 1<br>R 1<br>32.7 68 kH z<br>X T A L<br>~~=~~|| |**Table 3**<br>**XTAL oscillator characteristics**|| |**Parameter**<br>**Symbol**<br>**Conditions**<br>**Min**<br>**Typ**<br>**Max**|**Unit**| |Output frequency<br>Foscout<br>–<br>–<br>32.768<br>–|kHz| |Frequency tolerance<br>–<br>Over temperature and aging<br>–<br>–<br>250|ppm| |XTAL drive level<br>Pdrv<br>For crystal selection<br>–<br>–<br>0.5|μW| |XTAL series resistance<br>Rseries<br>For crystal selection<br>–<br>–<br>70|kΩ| |XTAL shunt capacitance<br>Cshunt<br>For crystal selection<br>–<br>–<br>2.2|pF| ## **2.3 Low-frequency clock sources** The 32 kHz low-frequency clock (LPO_32K on **Figure 3** ) can be obtained from multiple sources. There are two internal low-power oscillators (LPOs), called the LP-LPO and HP-LPO, as well as external crystal connections (OSC32K). The firmware determines the clock source to use among the available LPOs depending on the accuracy and power requirements. The preferred source is the external LPO (OSC32K) because it has good accuracy with the lowest current consumption. Internal LP-LPO has low current consumption and low accuracy whereas HP-LPO has higher accuracy and higher current consumption. The firmware assumes the external LPO has less than 250 PPM error with little or no jitter. Preliminary Datasheet 002-24743 Rev. *G 2022-09-26 8 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Microprocessor unit **==> picture [437 x 541] intentionally omitted <==** **----- Start of picture text -----**<br> Variable<br>Frequency<br>rd<br>Fixed DIV N 48/96 M HCLK CPU<br>Frequency<br>Block<br>DIV N 1 M Timers<br>— ore<br>XTAL 24M ADPLL 96M<br>SPI2<br>SPI1<br>DIV N 48M PTU PUART<br>2 4 M<br>rl, 7<br>HCI UART<br>ADC I2C<br>2 4M<br>(12M)<br>bole<br>24M DIV N 1M<br>ACLK0<br>24M<br>R iaj eee<br>ACLK1<br>HH<br>PWM(0‐5)<br>OSC32K<br>LPO<br>HP-LPO LPO_32K<br>LPO LHL<br>=<br>LP-LPO<br>LPO<br>RTC<br>= —<br>==) HH<br>Figure 3 Simplified clock source<br>**----- End of picture text -----**<br> Preliminary Datasheet 002-24743 Rev. *G 2022-09-26 9 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Microprocessor unit ## **2.4** ## **Power modes** The CYW20820 supports the following HW power modes: - Active mode: Normal operating mode in which all peripherals are available and CPU is active. - Idle mode - CPU is paused: In this mode, the CPU is in wait for interrupt (WFI) and the HCLK, which is the high frequency clock derived from the main crystal oscillator, is running at a lower clock speed. Other clocks are active and the state of the entire chip is retained. - Sleep mode: All systems clocks idle except for the LPO. The chip can wake up either after a programmed period of time has expired or if an external event is received via one of the GPIOs. In this mode, CPU is in WFI and the HCLK is not running. The PMU determines if the other clocks can be turned off and does accordingly. State of the entire chip is retained, the internal LDOs run at a lower voltage (voltage is managed by the PMU), and SRAM is retained. - Power Down Sleep (PDS) mode: Radio powered down and digital core mostly powered down except for RAM, registers, and some core logic. CYW20820 can wake up either after a programmed period of time has expired or if an external event is received via one of the GPIOs. - extended PDS (ePDS) mode: This is an extension of the PDS mode. In this mode, only the main RAM and ePDS control circuitry retains power. As in other modes, the CYW20820 can wake up either after a programmed period or upon receiving an external event. - HID-OFF (Deep Sleep) mode: Core, radio, and regulators powered down. Only the LHL IO domain is powered. In this mode, the CYW20820 can be woken up either by an event on one of the GPIOs or after a certain amount of time has expired. After wakeup, the part will go through full FW initialization although it will retain enough information to determine that it came out of HID-OFF and the event that caused the wake up. LPO and RTC are turned off in this mode. Either an internal LPO or an external input would provide a measure of time. Transition between power modes is handled by the on-chip firmware with host/application involvement. In general ePDS is the most power efficient mode for most active use cases. HID-OFF generally works for non-connectable beacon type use cases with long advertisement intervals. See the **“Firmware”** on page 22 for more details. ## **2.5** ## **Watchdog timer** CYW20820 includes an onboard WDT with a period of approximately 4 seconds. The WDT generates an interrupt to the FW after 2 seconds of inactivity and resets the parts after 4 seconds. ## **2.6 Lockout functionality** The CYW20820 powers up with SWD access to flash and RAM is disabled. After reset, FW checks on chip flash (OCF) for the presence of a security lockout field. If present, FW leaves JTAG and SWD flash and RAM access disabled and also blocks any HCI commands from reading the raw contents of the RAM or flash. The security field can be programmed in the factory after all programming and testing has been done. See the **ModusToolbox™** documentation for details on how to enable this feature. This provides an effective way of protecting against any tampering, dumping, probing or reverse engineering of OCF resident user application. The only FW upgrade path in this scenario is the secure OTA update. ## **2.7 True random number generator (TRNG)** The CYW20820 includes a hardware TRNG. Applications can access the random number generator via the firmware driver. See the **ModusToolbox™** documentation for details. Preliminary Datasheet 002-24743 Rev. *G 10 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Power on and external reset ## **3 Power on and external reset** **Figure 4** shows power on and reset timing of the CYW20820. After VBAT is applied and reset is inactive, the internal buck turns on, followed by the RF and digital low drop outs (LDOs). Once the LDO outputs have stabilized, the PMU allows the digital core to come out of reset. As shown in **Figure 4** , external reset can be applied at any time subsequent to power up. **Figure 4 Reset timing** Preliminary Datasheet 002-24743 Rev. *G 2022-09-26 11 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Power management unit (PMU) ## **4 Power management unit (PMU)** **Figure 5** shows the CYW20820 PMU block diagram. The CYW20820 includes an integrated buck regulator, a digital LDO for the digital core, and an RF LDO for the radio. The PMU also includes a brownout detector which places the part in shutdown when input voltage is below a certain threshold. **==> picture [365 x 307] intentionally omitted <==** **----- Start of picture text -----**<br> CYW20820 PMU<br>PMU_AVDD Brownout Reset<br>Detector<br>SRPVDD SR_VLX Buck Output<br>Buck<br>|<br>DIGLDO_VDDOUT<br>DIGLDO_VDDIN<br>Digital LDO<br>I<br>RFLDO_VDDIN RFLDO_VDDOUT<br>RF LDO<br>|<br>PALDO_VDDIN<br>PALDO_VDDOUT<br>PA LDO<br>**----- End of picture text -----**<br> **Figure 5 Power management unit** Preliminary Datasheet 002-24743 Rev. *G 12 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Power configurations ## **5** ## **Power configurations** CYW20820 supports three power configurations as described in **Table 4** . ## **Table 4 Power configuration** |**Configuration**|**Description**| |---|---| |VBAT and VDDIO|VBAT and VDDIO are supplied externally and are used to generate all other supplies on the<br>device. Reset may be left floating as it has an internal pull-up, may be connected to an<br>external RC, or may be driven externally.| |External supplies|PMU is disabled and on-chip regulators are not used. All supplies are provided externally.<br>Reset is driven from the outside.| |LDOs and VDDIO|On-chip LDOs are used to generate internal supplies but the on-chip buck is not used.<br>Reset is driven externally.| ## **5.1 Configuration 1 - VBAT and VDDIO** In this configuration, the device is provided with two supplies (which can also be tied together). RST_N is either left floating and relies on the internal pull-up to VDDIO to bring the device out of reset or tied to an external RC, or driven externally. All other required supplies are generated on-chip (see **Figure 6** ). Note that VDDIO must be supplied at the same time or before VBAT is supplied. RST_N needs to be held low for additional 4ms after VDDIO reaches high state. The device may require an external reset when any supply voltages drop below 1 V. POR operation not guaranteed below 1 V. **Figure 6 Configuration 1 - VBAT and VDDIO** Preliminary Datasheet 002-24743 Rev. *G 2022-09-26 13 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Power configurations ## **5.2 Configuration 2 - External supplies** In this configuration, the internal regulators are not used and VBAT is not supplied. VDDIO is supplied along with externally generated core and radio supplies. This is shown in the **Figure 7** . **==> picture [330 x 234] intentionally omitted <==** **----- Start of picture text -----**<br> 20820<br>PALDO_VDDIN PA LDO PALDO_VDDOUT<br>PMU_AVDD<br>SR_PVDD BUCK<br>SR_VLX<br>RFLDO_VDDIN RF LDO RFLDO_VDDOUT<br>DIGLDO_VDDIN DIG LDO DIGLDO_VDDOUT<br>VDDC<br>VDDC<br>External<br>RST_N<br>Radio VDDRF<br>IFVDD<br>VDDIO<br>VDDIO<br>PLLVDD<br>VDDIO<br>VCOVDD<br>MICAVDD<br>ADC_AVDDBAT PAVDD<br>VDDPA<br>**----- End of picture text -----**<br> ## **Figure 7 Configuration 2 - External supplies** Note that VDDIO must be provided simultaneously or before the rest of the supplies and the device must be held in reset until all supplies are within normal operating ranges. The device may require a reset if any supply goes outside the normal operating range. Preliminary Datasheet 002-24743 Rev. *G 14 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Power configurations ## **5.3 Configuration 3 - LDOs and VDDIO** In this configuration, the internal buck regulator is not used. Instead, power is supplied to the internal LDOs which are responsible for supplying the rest of the device. **==> picture [284 x 225] intentionally omitted <==** **----- Start of picture text -----**<br> 20820<br>PA Supply<br>PALDO_VDDIN PA LDO PALDO_VDDOUT<br>PMU_AVDD<br>SR_PVDD BUCK<br>SR_VLX<br>RF Supply<br>RFLDO_VDDIN RF LDO RFLDO_VDDOUT<br>DIGLDO_VDDIN DIG LDO DIGLDO_VDDOUT<br>DIG Supply<br>VDDC<br>External<br>RST_N<br>Radio<br>IFVDD<br>VDDIO<br>VDDIO<br>PLLVDD<br>VDDIO<br>VCOVDD<br>MIC_AVDD<br>ADC_AVDDBAT PAVDD<br>**----- End of picture text -----**<br> ## **Figure 8 Configuration 3 - LDOs and VDDIO** Note that VDDIO must be provided simultaneously or before the rest of the supplies and the device must be held in reset until all supplies are within normal operating ranges. The internal LDOs have a small turn-on time (specified later in the datasheet) which should be accounted for before releasing reset. RST_N must be held for additional 4ms after VDDIO reaches high state. The device may require a reset if any supply goes outside the normal operating range. Preliminary Datasheet 002-24743 Rev. *G 15 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Integrated radio transceiver ## **6 Integrated radio transceiver** The CYW20820 has an integrated radio transceiver that has been designed to provide low power operation in the globally available 2.4 GHz unlicensed ISM band. It is fully compliant with Bluetooth® Radio Specification 3.0 and meets or exceeds the requirements to provide the highest communication link quality of service. ## **6.1 Transmitter path** The CYW20820 features a fully integrated transmitter. The baseband transmit data is GFSK modulated in the 2.4 GHz ISM band. ## **6.1.1 Digital modulator** The digital modulator performs the data modulation and filtering required for the GFSK signal. The fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted signal. ## **6.1.2 Power amplifier (PA)** The CYW20820 has an integrated PA that can transmit up to +11.5 dBm for class 1 operation. ## **6.2 Receiver path** The receiver path uses a low IF scheme to down-convert the received signal for demodulation in the digital demodulator and bit synchronizer. The receiver path provides a high degree of linearity, and an extended dynamic range to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology, which has built-in out-of-band attenuation, enables the CYW20820 to be used in most applications without off-chip filtering. ## **6.2.1 Digital demodulator and bit synchronizer** The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit synchronization algorithm. ## **6.2.2 Receiver signal strength indicator (RSSI)** The radio portion of the CYW20820 provides a RSSI to the baseband. This enables the controller to take part in a Bluetooth® power-controlled link by providing a metric of its own receiver signal strength to determine whether the transmitter should increase or decrease its output power. ## **6.3 Local oscillator (LO)** The LO provides fast frequency hopping (1600 hops/second) across the band. The CYW20820 uses an internal loop filter. Preliminary Datasheet 002-24743 Rev. *G 16 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Peripherals ## **7 Peripherals** ## **7.1 I[2] C compatible master** The CYW20820 provides a 2-pin I[2] C compatible master interface to communicate with I[2] C compatible peripherals. The I _[2]_ C compatible master supports the following clock speeds: - 100 kHz - 400 kHz - 800 kHz (Not a standard I[2] C-compatible speed.) - 1 MHz (Compatibility with high-speed I[2] C-compatible devices is not guaranteed.) The I[2] C compatible master is capable for doing read, write, write followed by read, and read followed by write operations where read/write can be up to 64 bytes. SCL and SDA lines can be routed to any of the P0–P39 GPIOs allowing for flexible system configuration. When used as SCL/SDA the GPIOs go into open drain mode and require an external pull-up for proper operation. I[2] C does not support multimaster capability or flexible wait-state insertion by either master or slave devices. ## **7.2 Serial peripheral interface (SPI)** The CYW20820 has two independent SPI interfaces. Both interfaces support single, dual, and Quad mode SPI operations. Either interface can be a master or a slave. Each interface has a 64-byte transmit buffer and a 64-byte receive buffer. To support more flexibility for user applications, the CYW20820 has optional I/O ports that can be configured individually and separately for each functional pin. SPI IO voltage depends on VDDO/VDDM. ## **7.3 HCI UART interface** The CYW20820 includes a UART interface for factory programming as well as when operating as a Bluetooth® HCI device in a system with an external host. The UART physical interface is a standard, 4-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from 115200 bps to 3 Mbps. Typical rates are 115200, 921600, 1500000, and 3,000,000 bps although intermediate speeds are also available. Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command. The CYW20820 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is within ±5%. The UART interface CYW20820 has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced data rates. The interface supports the Bluetooth® UART HCI (H4) specification. The default baud rate for H4 is 115.2 kbaud. During HCI mode, the DEV_WAKE signal can be programmed to wake up the CYW20820 or allow the CYW20820 to sleep when radio activities permit. The CYW20820 can also wake up the host as needed or allow the host to sleep via the HOST_WAKE signal. Combined, the two signals allow the host and the CYW20820 to optimize system power consumption by allowing independent control of low power modes. DEV_WAKE and HOST_WAKE signals can be enabled via a vendor specific command. The FW UART driver allows applications to select different baud rates. ## **7.4 Peripheral UART interface** The CYW20820 has a second UART that may be used to interface to peripherals. Functionally, the peripheral UART is the same as the HCI UART except for 256 byte TX/RX FIFOs. The peripheral UART is accessed through the I/O ports, which can be configured individually and separately for each functional pin. The CYW20820 can map the peripheral UART to any GPIO. Preliminary Datasheet 002-24743 Rev. *G 17 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Peripherals ## **7.5 GPIO ports** The CYW20820 has 22 general purpose IOs labeled P0-P39. All GPIOs support the following: - Programmable pull-up/down of approx 45 k - Input disable, allowing pins to be left floating or analog signals connected without risk of leakage - Source/sink 8 mA at 3.0 V and 4 mA at 1.8 V - P26/P27/P28/P29 sink/source 16 mA at 3.0 V and 8 mA at 1.8 V Most peripheral functions can be assigned to any GPIO. For details, see **Table 6** and **Table 7** . ## **7.6 Keyboard scanner** The CYW20820 includes a HW key scanner that supports a maximum matrix size of 20x8. The scanner has 8 inputs (also referred to as rows) and 20 outputs (also referred to as columns). Keys are detected by driving the columns down sequentially and sampling the rows. The HW scanner includes support for ghost key detection and debouncing. The scanner can also operate in Sleep and PDS modes allowing low power operation while continuing to detect/store all key strokes, up or down. In other low power modes, the scanner can continue to monitor the matrix and initiate exit to Active mode upon detecting a change of state. The application can access the key scanner via the associated firmware driver. See the **“Firmware”** on page 22 for more details. ## **7.7 Mouse quadrature signal decoder** The CYW20820 includes one double-axis and one single axis quadrature decoders. There are two input lines for each axis and a programmable control signal that can be active HIGH or LOW. The application can access the quadrature interface via the driver included in the firmware. ## **7.8 ADC** The CYW20820 includes a Σ-Δ ADC designed for audio and DC measurements. The ADC can measure the voltage on 15 GPIOs (P0, P1, P8–P15, P17, P28, P29, P32, and P37). When used for analog inputs, the GPIOs must be placed in digital input disable mode to disconnect the digital circuit from the pin and avoid leakage. The internal bandgap reference has ±5% accuracy without calibration. Calibration and digital correction schemes can be applied to reduce ADC absolute error and improve measurement accuracy in Direct Current (DC) mode. The application can access the ADC through the ADC driver included in the firmware. ## **7.9 PWM** The CYW20820 has six internal PWMs, labeled PWM0-5. - Each of the six PWM channels contains the following registers: - 16-bit initial value register (read/write) - 16-bit toggle register (read/write) - 16-bit PWM counter value register (read) - PWM configuration register is shared among PWM0–5 (read/write). This 18-bit register is used: - To enable/disable each PWM channel - To select the clock of each PWM channel - To invert the output of each PWM channel. The application can access the PWM module through the FW driver. Preliminary Datasheet 002-24743 Rev. *G 2022-09-26 18 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Peripherals **Figure 9** shows the structure of one PWM channel. **==> picture [395 x 281] intentionally omitted <==** **----- Start of picture text -----**<br> pwm_cfg_adr register pwm#_init_val_adr register pwm#_togg_val_adr register<br>16 16<br>pwm#_cntr_adr<br>16<br>cntr value is ARM readable pwm_out<br>Example: PWM cntr w/ pwm#_init_val = 0 (dashed line)<br> PWM cntr w/ pwm#_init_val = x (solid line)<br>16'HFFFF<br>pwm_togg_val_adr<br>16'Hx<br>16'H000<br>pwm_out<br>o_flip clk_sel enable<br>**----- End of picture text -----**<br> **Figure 9 PWM block diagram** ## **7.10 Pulse density modulation (PDM) microphone** The CYW20820 accepts a ΣΔ-based one-bit PDM input stream and outputs filtered samples at either 8 kHz or 16 kHz sampling rates. The PDM signal derives from an external kit that can process analog microphone signals and generate digital signals. The PDM inputs share the filter path with the aux ADC. Two types of data rates can be supported: - 8 kHz - 16 kHz The external digital microphone takes in a 2.4 MHz clock generated by the CYW20820 and outputs a PDM signal which is registered by the PDM interface with either the rising or falling edge of the 2.4 MHz clock selectable through a programmable control bit. The design can accommodate two simultaneous PDM input channels, so stereo voice is possible. Preliminary Datasheet 002-24743 Rev. *G 19 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Peripherals ## **7.11** ## **I[2] S interface** The CYW20820 supports a single I2S digital audio port with both master and slave modes. The I[2] S signals are: - I[2] S clock: I[2] S SCK - I[2] S word select: I[2] S WS - I[2] S data out: I[2] S DO - I[2] S data in: I[2] S DI I[2] S SCK and I[2] S WS become outputs in master mode and inputs in slave mode, while I[2] S DO always stays as an output. The channel word length is 16 bits and the data is justified so that the MSB of the left-channel data is aligned with the MSB of the I[2] S bus, per I[2] S Specifications. The MSB of each data word is transmitted one bit clock cycle after the I[2] S WS transition, synchronous with the falling edge of bit clock. Left channel data is transmitted when I[2] S WS is low, and right-channel data is transmitted when I[2] S WS is high. Data bits sent by the CYW20820 are synchronized with the falling edge of I[2] S SCK and should be sampled by the receiver on the rising edge of the I[2] S SCK. The clock rate in master mode is as follows: - 16 kHz × 16 bits per frame = 256 kHz The master clock is generated from the reference clock using an N/M clock divider. In the slave mode, any clock rate is supported up to a maximum of 3.072 MHz. ## **7.12 PCM interface** The CYW20820 includes a PCM interface that can connect to linear PCM codec devices in master or slave mode. In master mode, the CYW20820 generates the PCM_CLK and PCM_SYNC signals. In slave mode, these signals are provided by another master on the PCM interface and are inputs to the CYW20820. The configuration of the PCM interface may be adjusted by the host through the use of vendor-specific HCI commands. **Note** The PCM interface shares HW with the I2S interface and only one can be used at any time. Only audio source (other than SCO) use cases are supported on CYW20820. ## **7.12.1 Slot mapping** The CYW20820 supports up to three simultaneous full-duplex channels through the PCM Interface. These three channels are time-multiplexed onto the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate (128 kHz, 512 kHz, or 1024 kHz). The corresponding number of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to allow other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCM clock during the last bit of the slot. ## **7.12.2 Frame synchronization** The CYW20820 supports both short- and long-frame synchronization in both master and slave modes. In short frame synchronization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge of the bit clock and expects the first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident with the first bit of the first slot. Preliminary Datasheet 002-24743 Rev. *G 20 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Peripherals ## **7.12.3 Data formatting** The CYW20820 may be configured to generate and accept several different data formats. For conventional narrow band speech mode, the CYW20820 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit, or a programmed value on the output. The default format is 13-bit 2’s complement data, left justified, and clocked MSB first. Preliminary Datasheet 002-24743 Rev. *G 21 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Firmware ## **8 Firmware** The CYW20820 ROM firmware runs on a real time operating system and handles the programming and configuration of all on-chip hardware functions as well as the Bluetooth®/LE baseband, LMAC, HCI, GATT, ATT, L2CAP, and SDP layers. The ROM also includes drivers for on-chip peripherals as well as handling on-chip power management functions including transitions between different power modes. The ROM also supports OTA firmware update and acts as a root of trust. The CYW20820 is fully supported by the Infineon ModusToolbox™. ModusToolbox™ releases provide the latest ROM patches, drivers, and sample applications allowing customized applications using the CYW20820 to be built quickly and efficiently. See the **ModusToolbox™** documentation for details on the software and how to write applications/profiles using the CYW20820. Preliminary Datasheet 002-24743 Rev. *G 22 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Pin assignments and GPIOs ## **9 Pin assignments and GPIOs** This section addresses both 62-pin FBGA pin assignments and GPIOs for the CYW20820 device. ## **9.1 62-pin FBGA pin assignments** |**Table 5**|**62-pin FBGA pin assignments**|**62-pin FBGA pin assignments**|**62-pin FBGA pin assignments**|||| |---|---|---|---|---|---|---| |**Pin name**||**Pin number**<br>**FBGA-62**||**I/O**|**Power**<br>**domain**|**Description**| |**Baseband supply**||||||| |VDDO1||B8||I|VDDO|I/O pad power supply| |VDDO2||D1||I|VDDO|I/O pad power supply| |VDDC||C8, E1||I/O|VDDC|Baseband core power supply| |**RF power supply**||||||| |IFVDD||F6||I|IFVDD|IFPLL power supply| |PLLVDD||G8||I|PLLVDD|RFPLL and crystal oscillator supply| |PAVDD||H5||I|PAVDD|PA supply| |VCOVDD||H8||I|VCOVDD|VCO supply| |**Onboard LDO’s**||||||| |PALDO_VDDIN||F5||I|–|PA LDO input| |PALDO_VDDOUT||G5||O|–|PA LDO output| |DIGLDO_VDDOUT||G4||O|–|Internal digital LDO output| |RFLDO_VDDOUT||H4||O|–|RF LDO output| |RFLDO_DIGLDO_VDDIN||E5||I|–|Internal digital LDO and RF LDO input| |SR_PVDD||H3||I|–|Core buck input| |SR_VLX||H2||O|–|Core buck output| |PMU_AVDD||G3||I|–|PMU supply| |**Ground pins**||||||| |VSSC||C3, C6, E3||I|VSS|Ground| |ADC_AVSS||A8||I|AVSS|Analog ground| |PMU_AVSS||F4||I|VSS|PMUground| |PLLVSS||F7||I|VSS|Ground| |PAVSS||G6||I|VSS|Ground| |VCOVSS||G7||I|VSS|Ground| |SR_PVSS||H1||I|VSS|Ground| |IFVSS||H7||I|VSS|Ground| |**UART**||||||| |UART_CTS_N||C7||I, PU|VDDO|Clear to send (CTS) for HCI UART interface.| |||||||Leave unconnected if not used.| |UART_RTS_N||E6||O, PU|VDDO|Request to send (RTS) for HCI UART| |||||||interface.| |||||||Leave unconnected if not used.| |UART_RXD||D7||I|VDDO|UART serial input. Serial data input for the| |||||||HCI UART interface.| Preliminary Datasheet 002-24743 Rev. *G 23 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Pin assignments and GPIOs |**Table 5**|**62-pin FBGA pin assignments**_(continued)_|**62-pin FBGA pin assignments**_(continued)_|**62-pin FBGA pin assignments**_(continued)_|**62-pin FBGA pin assignments**_(continued)_|| |---|---|---|---|---|---| |UART_TXD<br>D6<br>O, PU<br>VDDO<br>UART serial output. Serial data output for<br>the HCI UART interface.<br>**Pin name**<br>**Pin number**<br>**I/O**<br>**Power**<br>**domain**<br>**Description**<br>**FBGA-62**<br>~~——~~|||||| |**Crystal**|||||| |XTALI||F8|I|PLLVDD|Crystal oscillator input. See**“Main crystal**| ||||||**oscillator”**on page 7 “The XTAL must| ||||||have an accuracy of ±20 ppm as defined| ||||||by the Bluetooth® specification. Two| ||||||external load capacitors are required to| ||||||work with the crystal oscillator. The| ||||||selection of the load capacitors is| ||||||XTAL-dependent (see**Figure 1**)” for| ||||||options.| |XTALO||E8|O|PLLVDD|Crystal oscillator output| |XTALI_32K||B7|I|VDDO|Low-power oscillator input| |XTALO_32K||A7|O|VDDO|Low-power oscillator output| |**Other**|||||| |RF<br>H6<br>–<br>–<br>RF antenna port<br>RST_N<br>G1<br>I<br>VDDO<br>Active-low system reset with internal<br>pull-up resistor.<br>JTAG_SEL<br>G2<br>–<br>–<br>Arm® JTAG debug mode control. Connect<br>to GND for all applications.<br>~~—————~~|||||| |**GPIOs**|||||| |HOST_WAKE||D8|O|VDDO|A signal from the CYW20820 device to the| ||||||host indicating that the Bluetooth® device| ||||||requires attention.| |DEV_WAKE||E7|I|VDDO|A signal from the host to the CYW20820| ||||||indicating that the host requires| ||||||attention.| |P0||D2|I/O|VDDO|Recommended functions for P0| ||||||• Keyboard scan input (row): KSI0| ||||||• A/D converter input 29| ||||||• Peripheral UART: puart_tx| ||||||• SPI_1: MOSI (master only)| ||||||• UART1_TXD| ||||||P0 can also be remapped using Supermux| ||||||I/O functions as defined in**Table 6**and| ||||||**Table 7**.| Preliminary Datasheet 002-24743 Rev. *G 2022-09-26 24 ## **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Pin assignments and GPIOs |**Pin name**|**Pin number**|**I/O**|**Power**<br>**domain**|**Description**| |---|---|---|---|---| ||**FBGA-62**|||| |P1|C1|I/O|VDDO|Recommended functions for P1<br>• Keyboard scan input (row): KSI1<br>• A/D converter input 28<br>• Peripheral UART: puart_rts<br>• SPI_1: MISO (slave only)<br>• UART1_RXD<br>• Can also be remapped using Supermux<br>I/O functions as defined in**Table 6**and<br>**Table 7**.| |P2|B5|I/O|VDDO|Recommended functions for P2<br>• Keyboard scan input (row): KSI2<br>• Quadrature: QDX0<br>• SPI_1: MOSI (master only)<br>• UART1_RTS_N<br>P2 can also be remapped using Supermux<br>I/O functions as defined in**Table 6**and<br>**Table 7**.| |P3|A5|I/O|VDDO|Recommended functions for P3<br>• Keyboard scan input (row): KSI3<br>• Quadrature: QDX1<br>• UART1_CTS_N<br>• SPI_1: SPI_CLK (master only)<br>P3 can also be remapped using Supermux<br>I/O functions as defined in**Table 6**and<br>**Table 7**.| |P4|C5|I/O|VDDO|Recommended functions for P4<br>• Keyboard scan input (row): KSI4<br>• Quadrature: QDY0<br>• SPI_1: MOSI (master only)<br>P4 can also be remapped using Supermux<br>I/O functions as defined in**Table 6**and<br>**Table 7**.| Preliminary Datasheet 002-24743 Rev. *G 2022-09-26 25 ## **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Pin assignments and GPIOs |**Pin name**|**Pin number**|**I/O**|**Power**<br>**domain**|**Description**| |---|---|---|---|---| ||**FBGA-62**|||| |P5|B4|I/O|VDDO|Recommended functions for P5<br>• Keyboard scan input (row): KSI5<br>• Quadrature: QDY1<br>• Peripheral UART: puart_tx<br>• SPI_1: MISO (slave only)<br>• I2C: SDA<br>P5 can also be remapped using Supermux<br>I/O functions as defined in**Table 6**and<br>**Table 7**.| |P6|A4|I/O|VDDO|Recommended functions for P6<br>• Keyboard scan input (row): KSI6<br>• Quadrature: QDZ0<br>• Peripheral UART: puart_rts<br>• PWM2<br>P6 can also be remapped using Supermux<br>I/O functions as defined in**Table 6**and<br>**Table 7**.| |P8|A6|I/O|VDDO|Recommended functions for P8<br>• Keyboard scan output (column): KSO0<br>• A/D converter input 27<br>• External T/R switch control: ~tx_pd<br>P8 can also be remapped using Supermux<br>I/O functions as defined in**Table 6**and<br>**Table 7**.| |P9|A2|I/O|VDDO|Recommended functions for P9<br>• Keyboard scan output (column): KSO1<br>• A/D converter input 26<br>• External T/R switc0h control: tx_pd<br>P9 can also be remapped using Supermux<br>I/O functions as defined in**Table 6**and<br>**Table 7**.| |P10|C2|I/O|VDDO|Recommended functions for P10<br>• Keyboard scan output (column): KSO2<br>• A/D converter input 25<br>• External PA ramp control: PA_Ramp<br>P10 can also be remapped using<br>Supermux I/O functions as defined in<br>**Table 6**and**Table 7**.| Preliminary Datasheet 002-24743 Rev. *G 26 2022-09-26 ## **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Pin assignments and GPIOs ## **Table 5 62-pin FBGA pin assignments** _(continued)_ |**Pin name**|**Pin number**|**I/O**|**Power**<br>**domain**|**Description**| |---|---|---|---|---| ||**FBGA-62**|||| |P11|B2|I/O|VDDO|Recommended functions for P11<br>• Keyboard scan output (column): KSO3<br>• A/D converter input 24<br>P11 can also be remapped using<br>Supermux I/O functions as defined in<br>**Table 6**and**Table 7**.| |P12|A1|I/O|VDDO|Recommended functions for P12<br>• Keyboard scan output (column): KSO4<br>• A/D converter input 23<br>P12 can also be remapped using<br>Supermux I/O functions as defined in<br>**Table 6**and**Table 7**.| |P13|B1|I/O|VDDO|Recommended functions for P13<br>• Keyboard scan output (column): KSO5<br>• A/D converter input 22<br>• PWM3<br>P13 can also be remapped using<br>Supermux I/O functions as defined in<br>**Table 6**and**Table 7**.| |P14|B3|I/O|VDDO|Recommended functions for P14<br>• Keyboard scan output (column): KSO6<br>• A/D converter input 21<br>• PWM2<br>P14 can also be remapped using<br>Supermux I/O functions as defined in<br>**Table 6**and**Table 7**.| |P15|B6|I/O|VDDO|Recommended functions for P15<br>• Keyboard scan output (column): KSO7<br>• A/D converter input 20<br>P15 can also be remapped using<br>Supermux I/O functions as defined in<br>**Table 6**and**Table 7**.| |P17|A3|I/O|VDDO|Recommended functions for P17<br>• Keyboard scan output (column): KSO9<br>• A/D converter input 18<br>P17 can also be remapped using<br>Supermux I/O functions as defined in<br>**Table 6**and**Table 7**.| Preliminary Datasheet 002-24743 Rev. *G 27 2022-09-26 ## **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Pin assignments and GPIOs |**Pin name**|**Pin number**|**I/O**|**Power**<br>**domain**|**Description**| |---|---|---|---|---| ||**FBGA-62**|||| |P26|D4|I/O|VDDO|Recommended functions for P26<br>• Keyboard scan output (column): KSO18<br>• PWM0<br>• SPI_1: SPI_CS (slave only)<br>• Optical control output: QOC0<br>• Current: 16 mA sink<br>P26 can also be remapped using<br>Supermux I/O functions as defined in<br>**Table 6**and**Table 7**.| |P27|F1|I/O|VDDO|Recommended functions for P27<br>• Keyboard scan output (column): KSO19<br>• PWM1<br>• SPI_1: MOSI (master only)<br>• Optical control output: QOC1<br>• Current: 16 mA sink<br>P27 can also be remapped using<br>Supermux I/O functions as defined in<br>**Table 6**and**Table 7**.| |P28|C4|I/O|VDDO|Recommended functions for P28<br>• PWM2<br>• SCL3 (master and slave)<br>• Optical control output: QOC2<br>• A/D converter input 11<br>• Current: 16 mA sink<br>P28 can also be remapped using<br>Supermux I/O functions as defined in<br>**Table 6**and**Table 7**.| |P29|D3|I/O|VDDO|Recommended functions for P29<br>• PWM3<br>• SDA3 (master and slave)<br>• Optical control output: QOC3<br>• A/D converter input 10<br>• Current: 16 mA sink<br>P29 can also be remapped using<br>Supermux I/O functions as defined in<br>**Table 6**and**Table 7**.| Preliminary Datasheet 002-24743 Rev. *G 28 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Pin assignments and GPIOs ## **Table 5 62-pin FBGA pin assignments** _(continued)_ |**Pin name**|**Pin number**|**I/O**|**Power**<br>**domain**|**Description**| |---|---|---|---|---| ||**FBGA-62**|||| |P32|F2|I/O|VDDO|Recommended functions P32<br>• A/D converter input 7<br>• Quadrature: QDX0<br>• Auxiliary clock output: ACLK0<br>• Peripheral UART: puart_tx<br>P32 Can also be remapped using<br>Supermux I/O functions as defined in<br>**Table 6**and**Table 7**.| |P37|E2|I/O|VDDO|Recommended functions for P37<br>• A/D converter input 2<br>• Quadrature: QDZ1<br>• SPI_1: MISO (slave only)<br>• Auxiliary clock output: ACLK1<br>• I2C: SCL<br>P37 can also be remapped using<br>Supermux I/O functions as defined in<br>**Table 6**and**Table 7**.| Preliminary Datasheet 002-24743 Rev. *G 29 2022-09-26 ## **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Pin assignments and GPIOs ## **Table 6 GPIO supermux input functions** **Input** SWDCK SWDIO SPI1_CLK SPI1_CS SPI1_MOSI SPI1_MISO SPI1_IO2 SPI1_IO3 SPI1_INT SPI2_CLK SPI2_CS SPI2_MOSI SPI2_MISO SPI2_IO2 SPI2_IO3 SPI2_INT puart_rx puart_cts_n SCL SDA SCL2 SDA2 PCM_IN PCM_CLK PCM_SYNC I2S_DI I2S_WS I2S_CLK PDM_IN_Ch_1 PDM_IN_Ch 2 Preliminary Datasheet 002-24743 Rev. *G 30 2022-09-26 ## **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Pin assignments and GPIOs ## **Table 7 GPIO Supermux output functions** **Output** do_P# (data out of GPIO. For example: P0) do_PCM_IN do_PCM_OUT do_PCM_CLK do_PCM_SYNC do_I2S_DO do_I2S_DI do_I2S_WS do_I2S_CLK do_CLK_REQ IR_TX kso0 kso1 kso2 kso3 kso4 kso5 kso6 kso7 kso8 kso9 kso10 kso11 kso12 kso13 kso14 kso15 kso16 kso17 kso18 kso19 do_P# pwm0 do_P# pwm1 do_P# pwm2 do_P# pwm3 do_P# pwm4 do_P# pwm5 aclk0 aclk1 Preliminary Datasheet 002-24743 Rev. *G 31 2022-09-26 ## **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Pin assignments and GPIOs |**Table 7**|**GPIO Supermux output functions**_(continued)_| |---|---| |**Output**|| |HID_OFF|| |pa_ramp|| |tx_pd|| |~tx_pd|| |SWDIO|| |SDA2|| |SCL2|| |puart_tx (uart2_tx)|| |puart_rts_n (uart2_rts_n)|puart_rts_n (uart2_rts_n)| |SPI1_CLK|| |SPI1_CS|| |SPI1_MOSI|| |SPI1_MISO|| |SPI1_IO2|| |SPI1_IO3|| |SPI2_CLK|| |SPI2_CS|| |SPI2_MOSI|| |SPI2_MISO|| |SPI2_IO2|| |SPI2_IO3|| ## **9.2** ## **I/O states** When RST_N = 0 (during reset), all GPIOs (P0 to P39) are input-pins, no pull-up/pull-down and input-disabled. In auto-baud (RST_N = 1 and no FW programming), all GPIOs (P0 to P39) are input-pins and no pull-up/pull-down. Input signals are allowed to pass. Preliminary Datasheet 002-24743 Rev. *G 32 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Ball maps ## **10 Ball maps** ## **10.1 62-pin FBGA pin map** The CYW20820 62-pin FBGA package is shown in **Figure 10** . |1<br>2<br>3<br>4<br>5<br>6<br>7<br>8|| |---|---| |P8<br>P3<br>P6<br>P17<br>P9<br>P12<br>ADC_AVSS<br>XTALO_32K<br>eeeeeeee|A| |P15<br>P2<br>P5<br>P14<br>P11<br>P13<br>VDDO1<br>XTALI_32K<br>Seeeeeeee|B| |VSSC<br>P4<br>P28<br>VSSC<br>P10<br>P1<br>UART_TXD<br>P26<br>P29<br>P0<br>VDDO2<br>UART_RTS<br>_N<br>RFLDO_<br>DIGLDO_<br>VDDIN<br>PMU_LDO<br>_ONLY<br>_STRAP<br>VSSC<br>P37<br>VDDC<br>VDDC<br>UART_CTS<br>_N<br>HOST_<br>WAKE<br>UART_RXD<br>XTALO<br>DEV_WAKE<br>OOOO<br>O00<br>OOO _OOOO<br>Seeeeeeee|C<br>D<br>E| |IFVDD<br>PALDO_VDD<br>IN<br>PMU_AVSS<br>P32<br>P27<br>PAVSS<br>PALDO_VDD<br>OUT<br>DIGLDO<br>_VDDOUT<br>PMU_AVDD<br>JTAG_SEL<br>RST_N<br>XTALI<br>PLLVSS<br>PLLVDD<br>VCOVSS<br>OOOO _OO<br>eeeceeeee|F<br>G| |RF<br>PAVDD<br>RFLDO<br>_VDDOUT<br>SR_PVDD<br>SR_VLX<br>SR_PVSS<br>VCOVDD<br>IFVSS<br>OOOOOU0U)|H| ## **Figure 10 62-pin FBGA ball map** Preliminary Datasheet 002-24743 Rev. *G 2022-09-26 33 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Specifications ## **11 Specifications** ## **11.1 Electrical characteristics** **Caution!** The absolute maximum ratings in **Table 8** indicate levels where permanent damage to the device can occur, even if these limits are exceeded for only a brief duration. Functional operation is not guaranteed under these conditions. Operation at absolute maximum conditions for extended periods can adversely affect long-term reliability of the device. |**Table 8**<br>**Absolute maximum ratings**||||| |---|---|---|---|---| |**Requirement parameter**|**Specification**<br>~~Ct~—SSSY~~|||**Unit**| ||**Min**<br>~~Ct~—SSSY~~<br>~~_.~~|**Nom**<br>~~Ct~—SSSY~~<br>~~_.~~|**Max**<br>~~Ct~—SSSY~~<br>~~_.~~|| |Maximum junction temperature|–<br>~~|.~~|–<br>~~|. ~~|125<br> ~~f~~|°C| |VDDO1/VDDO2|–0.5<br>~~ff~~|–<br>~~ff~~|3.45<br>~~ff~~|V<br>~~ee~~| |IFVDD/PLLVDD/VCOVDD/VDDC|–0.5<br>~~fT~~<br>~~ee~~|–<br>~~fT~~<br>~~ee~~|1.38<br>~~fT~~<br>~~ee~~|| |PMUAVDD/SR_PVDD|–0.5<br>~~fT~~<br>~~ee~~|–<br>~~fT~~<br>~~ee~~|3.45<br>~~fT~~<br>~~ee~~|| |DIGLDO_VDDIN|–0.5<br>~~ee~~<br>~~ff~~|–<br>~~ee ~~<br>~~ff~~|1.65<br> ~~ee~~<br>~~ff~~|| |RFLDO_VDDIN|–0.5<br>~~ff~~|–<br>~~ff~~|1.65<br>~~ff~~|| |PALDO_VDDIN|–0.5<br>~~fo~~|–<br>~~fo~~|3.45<br>~~fo~~|| |PAVDD|–0.5<br>~~ff~~|2.5<br>~~ff~~|2.75<br>~~ff~~|| |**Table 9**<br>**ESD/latch-up**||| |---|---|---| |**Requirement Parameter**|**Specification**<br>**Min**<br>**Nom**<br>**Max**<br>~~Ct~—SSSY~~<br>~~_.~~|**Unit**| |ESD tolerance HBM|–2000<br>–<br>2000<br>~~|. f~~|V| |ESD tolerance CDM|–500<br>–<br>500<br>~~ff~~|| |Latch-up|–<br>200<br>–<br>~~fC~~|mA| |**Table 10**<br>**Environmental ratings**||| |**Characteristic**|**Value**|**Unit**| |Operatingtemperature|–30 to +85|°C| |Storage temperature|–40 to +150|| Preliminary Datasheet 002-24743 Rev. *G 2022-09-26 34 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Specifications |**Table 11**<br>**Recommended operating conditions**||||| |---|---|---|---|---| |**Parameter**|**Specification**<br>~~Ct™~—SSY~~|||**Unit**| ||**Min**<br>~~Ct™~—SSY~~<br>~~dd~~|**Typ**<br>~~Ct™~—SSY~~<br>~~dd~~|**Max**<br>~~Ct™~—SSY~~<br>~~dd~~|| |VDDC|1.045[1]<br>~~dd~~<br>~~ee~~|1.2<br>~~dd~~<br>~~ee~~|1.26<br>~~dd~~<br>~~ee~~|V<br>~~ee~~<br>~~ee~~| |IFVDD[3]|1.14<br>~~ff~~|1.2<br>~~ff~~|1.26<br>~~ff~~|| |PLLVDD[3]|1.14<br>~~ff~~|1.2<br>~~ff~~|1.26<br>~~ff~~|| |VCOVDD[3]|1.14<br>~~fT~~<br>~~ee~~|1.2<br>~~fT~~<br>~~ee~~|1.26<br>~~fT~~<br>~~ee~~|| |PAVDD[3]|2.375<br>~~fT~~<br>~~ee~~|2.5<br>~~fT~~<br>~~ee~~|2.625<br>~~fT~~<br>~~ee~~|| |VDDO1[2]|1.71<br>~~ee~~<br>~~ff~~|3.0<br>~~ee ~~<br>~~ff~~|3.3<br> ~~ee~~<br>~~ff~~|| |VDDO2[2]|1.71<br>~~ff~~|3.0<br>~~ff~~|3.3<br>~~ff~~|| |PMU_AVDD|1.71<br>~~fT~~<br>~~ee~~|3.0<br>~~fT~~<br>~~ee~~|3.3<br>~~fT~~<br>~~ee~~|| |SR_PVDD|1.71<br>~~fT~~<br>~~ee~~|3.0<br>~~fT~~<br>~~ee~~|3.3<br>~~fT~~<br>~~ee~~|| |RFLDO_VDDIN|1.26<br>~~ee~~<br>~~ff~~|1.26<br>~~ee ~~<br>~~ff~~|1.38<br> ~~ee~~<br>~~ff~~|| |DIGLDO_VDDIN|1.26<br>~~ff~~|1.26<br>~~ff~~|1.38<br>~~ff~~|| |PALDO_IN[4]|2.6<br>~~fd~~|3.0<br>~~fd~~|3.3<br>~~fd~~|| ## **Note** 1. 1.14 V for > 48 MHz operation. 2. VDDO1 must be equal to VDDO2. Recommend that these be provided from the same source. 3. IFVDD, PLLVDD, and VCOVDD must all be equal. Recommend providing from the same supply. 4. PAVDD_IN min. must be greater than VOUT + 100 mV under max. load current. ## **11.2 Brown out** The CYW20820 uses an onboard low voltage detector to shut down the part when supply voltage (VDDBAT3V) drops below the operating range. |**Table 12**<br>**Shutdown voltage**||||| |---|---|---|---|---| |**Parameter**|**Specification**|||**Unit**| ||**Min**|**Typ**|**Max**|| |VSHUT|1.5|1.56|1.7|V| Preliminary Datasheet 002-24743 Rev. *G 35 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Specifications ## **11.3 Core buck regulator** ||||~~ee~~||| |---|---|---|---|---|---| |**Parameter**|**Conditions**<br>~~se~~|**Min**<br>~~se~~<br>~~es~~|**Typ**<br>~~se~~<br>~~ee~~|**Max**<br>~~se~~|**Unit**| |Input supply, VBAT|DC range<br>~~es~~|1.71<br>~~es~~<br>~~es~~|3.0<br>~~ee~~<br>~~es~~|3.3<br>~~es~~|V| |Output current|Active mode<br>~~——~~|–<br>~~es~~<br>~~——~~|< 60<br>~~——~~|100<br>~~——~~|mA| ||PDS mode<br>~~——~~|–<br>~~——~~|< 60<br>~~——~~|70<br>~~——~~|| |Output voltage|Active mode<br>~~——~~<br>~~————~~|1.1<br>~~——~~<br>~~————~~|1.26<br>~~——~~<br>~~————~~|1.4<br>~~——~~<br>~~————~~|V| ||PDS mode, 40 mV min regulation window.<br>~~————~~|0.76<br>~~————~~|0.94 Avg<br>~~————~~|1.4<br>~~————~~|| |Output voltage<br>accuracy<br>~~Pe~~|Active mode, includes line and load<br>regulation.<br>Before trim:<br>~~PE~~<br>~~Pe~~|–4<br>~~PE~~<br>|–<br>~~PE~~<br>|+4<br>~~PE~~<br>|%| |Ripple voltage<br>~~Pe~~|Active mode<br>2.2H ± 25% inductor, DCR = 114 m± 20%<br>4.7F ± 10% capacitor, Total ESR < 20 m<br>~~Pe~~|–<br>|3<br>|–<br>|mV| ||PDS mode<br>~~Pe~~|–<br>|–<br>|–<br>|| |Output inductor, L<br>|See the**Recommended component**for<br>more details.<br>~~|!~~|1.6[5]<br>~~|!~~|2.2<br>~~|!~~|–<br>~~|!~~|μH| |Output capacitor, COUT<br>||3.0[5]<br>~~|!~~|4.7<br>~~|!~~|–<br>~~|!~~|μF<br>~~ee~~| |Input capacitor, CIN<br>||4.0[5]<br>~~|!~~<br>~~ee~~|10<br>~~|!~~<br>~~ee~~|–<br>~~|!~~<br>~~ee~~|| |Input supply voltage<br>ramp time|0 to 3.3 V<br>~~ee~~|40<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|μs<br>~~ee~~| ## **Note** 5. Minimum values represent minimums after derating due to tolerance, temperature, and voltage effects. ## **11.4 Recommended component** |**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---| |External inductor, L|2.2 μH ±25%, DCR = 114 mΩ ±20%, ACR < 1 Ω<br>(for frequency < 1 MHz)|1.6|2.2|–|μH| |External output capacitor, COUT|4.7 μF ±10%, 6.3 V, 0603 inch, X5R, MLCC<br>capacitor + board total-ESR < 20 mΩ|3.0|4.7|–|μF| |External input capacitor, CIN|For SR_VDDBAT pin<br>Ceramic, X5R, 0402, ESR < 30 mΩ at 4 MHz,<br>+/-20%, 6.3 V, 10 μF|4|10|–|| Preliminary Datasheet 002-24743 Rev. *G 36 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Specifications |**11.5**<br>**Digital LDO**<br>**Table 15**<br>**Digital LDO**|||||| |---|---|---|---|---|---| |**Parameter**|**Condition**<br>~~a~~|**Min**<br>~~a~~|**Typ**<br>~~a~~|**Max**<br>~~a~~|**Unit**| |Input supply, DIGLDO_VDDIN|Min must be met for correct<br>operation<br>~~a~~|VOUT+ 20 mV<br>~~a~~|1.26<br>~~a~~|1.4<br>~~a~~|V| |Output voltage,<br>DIGLDO_VDDOUT|Range<br>~~—~~|0.9<br>~~—~~|1.2<br>~~—~~|1.275<br>~~—~~|| ||Step<br>~~—~~|–<br>~~—~~|25<br>~~—~~|–<br>~~—~~|mV| ||Accuracy<br>~~—~~<br>~~os~~|–4<br>~~—~~<br>~~os~~|–<br>~~—~~<br>~~os~~|+4<br>~~—~~<br>~~os~~|%| |Dropout voltage|At max load current<br>~~os~~|–<br>~~os~~|–<br>~~os~~|20<br>~~os~~|mV| |Output current|DC Load<br>~~—~~|–<br>~~—~~|30<br>~~—~~|60<br>~~—~~|mA| |Quiescent current|At T ≤ 85°C, VIN= 1.4 V<br>~~—~~<br>~~a~~|–<br>~~—~~<br>~~|~~|–<br>~~—~~<br>~~||~~|50<br>~~—~~<br>~~|~~|μA| |Output load capacitor, COUT|Total trace + cap ESR must be <<br>80 mΩ<br>~~—~~<br>~~pf~~<br>~~a~~|1.55[6]<br>~~—~~<br>~~pf~~<br>~~|~~|2.2<br>~~—~~<br>~~pf~~<br>~~||~~|–<br>~~—~~<br>~~pf~~<br>~~|~~|μF| |Line regulation|1.235 V ≤ VIN≤ 1.4 V<br>~~pf~~<br>~~a~~|–<br>~~pf~~<br>~~|~~<br>~~eee~~|–<br>~~pf~~<br>~~||~~<br>~~eee~~|10<br>~~pf~~<br>~~|~~<br>~~eee~~|mV/V| |Load regulation|VOUT= 1.2 V, VIN= 1.26 V,<br>1 mA ≤ IOUT≤ 25 mA<br>~~pf~~<br>~~a~~|–<br>~~pf~~<br>~~|~~<br>~~eee~~|–<br>~~pf~~<br>~~| |~~<br>~~eee~~|1<br>~~pf~~<br>~~|~~<br>~~eee~~|mV/mA| |Load step error|IOUTstep 1 mA20 mA @ 1 μs<br>rise/fall,<br>COUT= 2.2 μF, VIN= 1.235 V,<br>VOUT= 1.2 V<br>~~CT~~|–24<br>~~eee~~<br>~~CT~~<br>~~ee~~|–<br>~~eee~~<br>~~CT~~<br>~~ee~~|+24<br>~~eee~~<br>~~CT~~<br>~~ee~~|mV| |Leakage current|Power down mode, VIN= 1.4 V,<br>Temp = 25°C<br>~~es~~<br>~~a~~|–<br>~~es~~<br>~~ee~~<br>~~ee~~<br>|–<br>~~es~~<br>~~ee~~<br>~~eee~~<br>|50<br>~~es~~<br>~~ee~~<br>~~eee~~<br>|nA| ||Power down mode, VIN= 1.4 V,<br>Temp = 125°C<br>~~es~~<br>~~ee~~<br>~~a~~<br>~~a~~|–<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|–<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|2<br>~~es~~<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~eee~~|μA| |In-rush current|COUT= 2.2 μF, VIN= 1.4 V,<br>VOUT= 1.2 V<br>~~ee~~<br>~~a ~~<br>~~a~~|–<br>~~ee~~<br>~~ee~~<br> ~~eee~~<br>~~eee~~|–<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>~~eee~~|100<br>~~ee~~<br>~~eee~~<br>~~eee~~<br>~~eee~~|mA| |LDO turn on time|COUT= 2.2 μF, VIN= 1.4 V,<br>VOUT= 1.2 V, IOUT= 20 mA<br> <br>~~a~~|–<br> ~~eee~~<br>~~eee~~|–<br>~~eee~~<br>~~eee~~|120<br>~~eee~~<br>~~eee~~|μs| |PSRR|COUT= 2.2 μF, 1.235 V ≤ VIN≤ 1.4 V,<br>VOUT= 1.2 V, IOUT= 20 mA<br>f = 1 kHz<br>f = 100 kHz<br>~~PT~~|25<br>13<br>~~eee~~<br>~~PT~~|–<br>~~eee~~<br>~~PT~~|–<br>~~eee~~<br>~~PT~~|dB<br>dB| |**Parameter**<br>~~I~~|**Conditions**<br>~~I~~|**Min**<br>~~I~~|**Typ**<br>~~I~~|**Max**<br>~~I~~|**Unit**<br>~~I~~| |---|---|---|---|---|---| |External output capacitor,<br>Cout<br>~~I~~|2.2 μF ±10%, 10 V, 0402 inch, X5R,<br>MLCC capacitor +board total- ESR < 20 mΩ<br>~~I~~|1.55<br>~~I~~|2.2<br>~~I~~|–<br>~~I~~|μF<br>~~I~~| Preliminary Datasheet 002-24743 Rev. *G 37 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Specifications |**Parameter**|**Conditions**<br>~~ooo~~|**Min**<br>~~ooo~~<br>~~—EEE ELL~~<br>~~eee~~|**Typ**<br>~~ooo~~<br>~~ELL~~<br>~~eee~~|**Max**<br>~~ooo~~<br>~~ELL~~<br>~~eee~~|**Unit**| |---|---|---|---|---|---| |Input supply,<br>RFLDO_VDDIN|Min must be met for correct operation<br>~~ee~~|VOUT+ 20 mV<br>~~—EEE ELL~~<br>~~ee~~<br>~~eee~~|1.26<br>~~ELL~~<br>~~ee~~<br>~~eee~~|1.4<br>~~ELL~~<br>~~ee~~<br>~~eee~~|V| |Output voltage,<br>RFLDO_VDDOUT|Range<br>~~SO~~|1.1<br>~~eee ~~<br>~~SO~~|1.2<br> ~~eee~~<br>~~SO~~|1.275<br>~~eee~~<br>~~SO~~|| ||Step<br>~~a~~|–<br>~~a~~|25<br>~~a~~|–<br>~~a~~|mV| ||Accuracy<br>~~a~~<br>~~a~~<br>~~TTT~~|–4<br>~~a~~<br>~~a~~<br>~~OEEE~~|–<br>~~a~~<br>~~a~~<br>~~OEEE~~|+4<br>~~a~~<br>~~a~~<br>~~OEEE~~|%| |Dropout voltage|At max load current<br>~~a~~<br>~~TTT~~|–<br>~~a~~<br>~~OEEE~~|–<br>~~a~~<br>~~OEEE~~|20<br>~~a~~<br>~~OEEE~~|mV| |Output current|DC Load<br>~~TTT ~~<br>~~SO~~|–<br> ~~OEEE~~<br>~~SO~~|20<br>~~OEEE~~<br>~~SO~~|60<br>~~OEEE~~<br>~~SO~~|mA| |Quiescent current|At T ≤ 85°C, VIN= 1.4 V<br>~~SO~~|–<br>~~SO~~|–<br>~~SO~~|50<br>~~SO~~|μA| |Output load capacitor,<br>COUT<br>~~—SOV"Y]??—/s~~|Total trace + cap ESR must be < 80 mΩ<br>~~SO~~<br>~~ee~~<br>~~—SOV"Y]??—/s~~|1.55[7]<br>~~SO~~<br>~~ee~~<br>~~—SOV"Y]??—/s“a>~~|2.2<br>~~SO~~<br>~~ee~~<br>~~“a>~~|–<br>~~SO~~<br>~~ee~~<br>~~“a>~~|μF| |Line regulation<br>~~—SOV"Y]??—/s~~|1.235V ≤ VIN≤ 1.4 V<br>~~—SOV"Y]??—/s~~|–<br>~~—SOV"Y]??—/s“a>~~<br>~~eee~~|–<br>~~“a>~~<br>~~ee~~|10<br>~~“a>~~<br>~~ee~~|mV/V| |Load regulation<br>~~—SOV"Y]??—/s~~|VOUT= 1.2 V, VIN= 1.26 V,<br>1 mA ≤ IOUT≤ 25 mA<br>~~—SOV"Y]??—/s~~<br>~~ee~~|–<br>~~—SOV"Y]??—/s“a>~~<br>~~ee~~<br>~~eee~~<br>~~ee~~|–<br>~~“a>~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|1<br>~~“a>~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|mV/mA| |Load step error|IOUTstep 1 mA20 mA @ 1 μs rise/fall,<br>COUT= 2.2 μF, VIN= 1.235 V, VOUT= 1.2 V<br>~~ee~~|–24<br>~~eee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|+24<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|mV| |Leakage current|Power down mode, VIN= 1.4 V,<br>Temp = 25°C<br>~~ee~~<br>~~oT~~|–<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>|–<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>|50<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>|μA| ||Power down mode, VIN= 1.4 V,<br>Temp = 125°C<br>~~ee~~<br>~~ee~~<br>~~oT EEE~~|–<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~EEE~~|–<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~EEE~~|2<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~<br>~~EEE~~|μA| |In-rush current|COUT= 2.2 μF, VIN= 1.4 V, VOUT= 1.2 V<br>~~ee~~<br>~~oT EEE~~|–<br>~~ee~~<br>~~ee~~<br>~~EEE~~|–<br>~~ee~~<br>~~eee~~<br>~~EEE~~|100<br>~~ee~~<br>~~eee~~<br>~~EEE~~|mA| |LDO turn on time|COUT= 2.2 μF, VIN= 1.4 V, VOUT= 1.2 V,<br>IOUT= 20 mA<br>~~oT EEE~~|–<br>~~ee ~~<br>~~EEE~~|–<br> ~~eee~~<br>~~EEE~~|120<br>~~eee~~<br>~~EEE~~|μs| |PSRR|COUT= 2.2 μF, 1.235 V ≤ VIN≤ 1.4 V,<br>VOUT= 1.2 V, IOUT= 20 mA<br>f = 1 kHz<br>f = 100 kHz|25<br>13|–|–|dB<br>dB| ## **Note** 7. Minimum values represent minimums after derating due to tolerance, temperature, and voltage effects. Preliminary Datasheet 002-24743 Rev. *G 38 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Specifications |**11.8**<br>**PALDO**<br>**Table 18**<br>**PALDO**|||||| |---|---|---|---|---|---| |**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**| |Input supply,<br>PALDO_VDDIN|VDDIN min must be greater than<br>VOUT+ 100 mV under max load current for<br>proper regulation<br>~~Pe~~|2.6<br>~~Pe~~|3.0<br>~~Pe~~|3.3<br>~~Pe~~|V| |Output voltage,<br>PALDO_VDDOUT|Range<br>~~Oo~~|1.5<br>~~Oo~~|2.45<br>~~Oo~~|3.0<br>~~Oo~~|V| ||Step<br>~~eo~~|–<br>~~eo~~<br>~~C~~|100<br>~~eo~~<br>|–<br>~~eo~~<br>|mV| ||Accuracy<br>~~eo~~<br>~~a~~|–4<br>~~eo~~<br>~~a~~<br>~~C~~|–<br>~~eo~~<br>~~a~~<br><br>~~ee~~|+4<br>~~eo~~<br>~~a~~<br>|%| |HTOL output voltage||–<br>~~Cee~~|3.3<br>~~ee~~<br>~~ee~~|–<br>~~ee~~|V| |Dropout voltage|At max load current<br>~~eo~~|–<br>~~eo~~|–<br>~~ee~~<br>~~eo~~|100<br>~~eo~~|mV| |Output current|DC load<br>~~eo~~|0<br>~~eo~~|30<br>~~eo~~|60<br>~~eo~~|mA| |Quiescent current|At T≤ 85°C, VIN= 3.3 V<br>~~eo~~<br>~~TTT~~|–<br>~~eo~~<br>~~TTT~~|–<br>~~eo~~<br>~~TTT~~<br>~~ee~~|110<br>~~eo~~<br>~~TTT~~|μA| |Output load capacitor, COUT||1.2[8]<br>~~ee~~|2.2<br>~~ee~~<br>~~ee~~|–<br>~~ee~~|μF| |Line regulation|2.7 V ≤ VIN≤ 3.3 V, VOUT= 2.5 V<br>~~a~~|–<br>~~a~~|–<br>~~ee~~<br>~~a~~|25<br>~~a~~|mV/V| |Load regulation|VIN= 3.3 V, VOUT= 2.5 V, 0 mA ≤ IOUT≤ 30 mA<br>~~eo~~|–<br>~~eo~~|–<br>~~eo~~|1<br>~~eo~~<br>~~ee~~|mV/mA| |Load step error|IOUTstep 1 mA20 mA @ 1s rise/fall,<br>COUT= 2.2F, VIN= 3.3 V, VOUT= 2.5 V<br>~~eo~~<br>~~ee~~|–25<br>~~eo~~<br>~~ee~~<br>~~eee~~|–<br>~~eo~~<br>~~ee~~<br>~~eee~~|25<br>~~eo~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|mV| |Leakage current|Power-down mode, VIN= 3.6 V,<br>Temp = 25°C<br>~~ee~~|–<br>~~ee~~<br>~~eee~~<br>~~ee~~|–<br>~~ee~~<br>~~eee~~<br>~~eee~~|1.6<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~eee~~|μA| ||Power-down mode, VIN= 3.6 V,<br>Temp = 125°C<br>~~ee~~|–<br>~~eee~~<br>~~ee~~<br>~~ee~~|–<br>~~eee ~~<br>~~ee~~<br>~~eee~~|4.9<br> ~~ee~~<br>~~ee~~<br>~~eee~~|μA| |In-rush current|COUT= 2.2F, VIN= 3.3 V, VOUT= 2.5 V<br>~~eo~~|–<br>~~ee ~~<br>~~eo~~|–<br> ~~eee~~<br>~~eo~~|140<br>~~eee~~<br>~~eo~~|mA| |LDO turn on time|COUT= 2.2F, VIN= 3.3 V, VOUT= 2.5 V,<br>IOUT= 20 mA|–|–|140|μs| |PSRR|COUT= 2.2F, VIN= 3.3 V, VOUT= 2.5 V,<br>IOUT= 20 mA<br>f = 1 kHz<br>f = 100 kHz|45<br>25|–<br>–|–<br>–|dB<br>dB| ## **Note** 8. Minimum values represent minimums after derating due to tolerance, temperature, and voltage effect. Preliminary Datasheet 002-24743 Rev. *G 39 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Specifications ## **11.9 Digital I/O characteristics** |**Table 19**<br>**Digital I/O characteristics**<br>**Characteristics**<br>Input low voltage (VDDO = 3 V)<br>Input high voltage (VDDO = 3 V)<br>Input low voltage (VDDO = 1.8 V)<br>Input high voltage (VDDO = 1.8 V)<br>Output low voltage<br>Output high voltage<br>Input low current<br>Input high current<br>Output low current (VDDO = 3 V, VOL= 0.4 V)<br>Output low current (VDDO = 3 V, VOL= 1.8 V)<br>Output high current (VDDO = 3 V, VOH= 2.6 V)<br>Output high current (VDDO = 1.8 V, VOH= 1.4 V)<br>Input capacitance|**Symbol**<br>VIL<br>VIH<br>VIL<br>VIH<br>VOL<br>VOH<br>IIL<br>IIH<br>IOL<br>IOL<br>IOH<br>IOH<br>CIN<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee ~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|**Min**<br>–<br>2.4<br>–<br>1.4<br>–<br>VDDO – 0.4 V<br>–<br>–<br>–<br>–<br>–<br>–<br>–<br>~~ee ~~<br>~~ee~~<br>~~ee ~~<br>~~ee ~~<br> ~~ee~~<br>~~ee~~<br>~~ee ~~<br>~~ee ~~<br> ~~ee~~<br>~~ee~~<br>~~ee ~~<br>~~ee ~~<br>~~ee ~~|**Typ**<br>–<br>–<br>–<br>–<br>–<br>–<br>–<br>–<br>–<br>–<br>–<br>–<br>–<br> ~~ee~~<br> ~~ee~~<br> ~~ee~~<br> ~~ee~~<br> ~~ee~~<br> ~~ee~~<br> ~~ee~~<br> ~~es~~|**Max**<br>0.8<br>–<br>0.4<br>–<br>0.4<br>–<br>1.0<br>1.0<br>4.0<br>2.0<br>8.0<br>4.0<br>0.4|**Unit**<br>V<br>μA<br>mA<br>pF| |---|---|---|---|---|---| Preliminary Datasheet 002-24743 Rev. *G 40 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Specifications ## **11.10 ADC electrical characteristics** |**Table 20**<br>**Electrical characteristics**|**Table 20**<br>**Electrical characteristics**|**Table 20**<br>**Electrical characteristics**||||| |---|---|---|---|---|---|---| |**Parameter**<br>Current consumption<br>Power down current<br>**ADC core specification**<br>~~——~~|**Symbol**<br>ITOT<br>–|**Conditions/comments**<br>–<br>At room temperature<br>~~es~~|**Min**<br>–<br>–|**Typ**<br>2<br>1|**Max**<br>3<br>–|**Unit**<br>mA<br>μA| |ADC reference voltage|VREF|From BG with ±3% accuracy|–|0.85|–|V| |ADC samplingclock|–|–|–|12|–|MHz| |Absolute error|–|Includes gain error, offset and|–|–|5|%| |||distortion. Without factory||||| |||calibration.||||| |ENOB<br>ADC input full scale<br>Conversion rate|Includes gain error, offset and<br>distortion. After factory<br>calibration.<br>–<br>–<br>2<br>–<br>For audio application<br>12<br>13<br>–<br>For static measurement<br>10<br>–<br>–<br>FS<br>For audio application<br>–<br>1.6<br>–<br>For static measurement<br>1.8<br>–<br>3.3<br>–<br>For audio application<br>8<br>16<br>–<br>~~PE~~<br>~~—=— ==~~<br>~~—~~|||||%<br>Bit<br>kHz| |Signal bandwidth|–<br>For audio application<br>20<br>–<br>8K<br>For static measurement<br>–<br>DC<br>–<br>~~a~~<br>~~———_—~~|||||Hz| |Input impedance|RIN<br>For audio application<br>10<br>–<br>–<br>For static measurement<br>500<br>–<br>–<br>~~a——_—~~|||||kΩ| |Startup time|–<br>For audio application<br>–<br>10<br>–<br>For static measurement<br>–<br>20<br>–<br>~~————~~|||||ms<br>μs| |**MIC bias specifications**||||||| |MIC bias output voltage|–|At 3 V supply, 25°C, default|–|2.4|–|V| |||settings||||| |MIC bias loadingcurrent|–|–|–|–|3|mA| |MIC bias noise|–|Refers to PGA input 20 Hz to|–|–|3|μV| |||8 kHz, A-weighted||||| |MIC bias PSRR|–|at 1 kHz|40|–|–|dB| |ADC SNR|–|A-weighted 0 dB PGA gain,|–|78|–|dB| |||Temperature = 25°C||||| |ADC THD + N|–|–3 dBFS input 0 dB PGA gain,|–|70|–|dB| |||Temperature = 25°C||||| |GPIO input voltage|–|Always lower than avddBAT|–|–|3.3|V| |GPIO source|–|Resistance|–|–|1|kΩ| |impedance[9]||Capacitance|–|–|10|pF| ## **Note** 9. Conditional requirement for the measurement time of 10 μs. Relaxed with longer measurement time for each GPIO. Preliminary Datasheet 002-24743 Rev. *G 41 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Specifications ## **11.11 Current consumption** **Table 21** provides the current consumption measurements taken at input of LDOIN and VDDIO combined (LDOIN = VDDIO = 3.0 V). ## **Table 21 Current consumption** |**Current consumption**|| |---|---| |**Conditions**|**Typical**| |48 MHz with pause|1.3| |48 MHz without pause|2.55| |Continuous RX (BR)<br>Continuous RX (EDR)<br>Continuous RX (Bluetooth® LE)|6.28<br>6.87<br>6.31| |Continuous TX (BR)<br>Continuous TX (EDR)<br>Continuous TX (Bluetooth® LE)|18.58<br>22.48<br>18.76| |–|16.5| |All RAM retained|8.7| |32 kHz XTAL on|1.75| Preliminary Datasheet 002-24743 Rev. *G 2022-09-26 42 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Specifications ## **11.12 RF specifications** **Note Table 22** and **Table 23** apply to single-ended industrial temperatures. Unused inputs are left open. |**Table 22**<br>**BR/EDR - Receiver RF specifications**|**Table 22**<br>**BR/EDR - Receiver RF specifications**||||| |---|---|---|---|---|---| |**Parameter**|**Mode and conditions**|**Min**|**Typ**|**Max**|**Unit**| |Receiver section|||||| |Frequency range|–|2402|–|2480|MHz| |RX sensitivity|GFSK, BDR GFSK 0.1% BER, 1 Mbps|–|–91|–|dBm| ||EDR 2M|–|–94.0|–|dB| ||EDR 3M|–|–87.5|–|| |Maximum input|–|–20|–|–|dBm| |**Interference performance**|||||| |C/I cochannel|GFSK, BDR GFSK 0.1% BER[11]|–|–|11.0|dB| |C/I 1 MHz adjacent channel|GFSK, BDR GFSK 0.1% BER[11]|–|–|–4.0|| |C/I 2 MHz adjacent channel|GFSK, BDR GFSK 0.1% BER[11]|–|–|–31.5|| |C/I3 MHz adjacent channel GFSK, BDR GFSK 0.1% BER|3 MHz adjacent channel GFSK, BDR GFSK 0.1% BER[11]|–|–|–42.5|| |C/I image channel|GFSK, BDR GFSK 0.1% BER[11]|–|–|–24.0|| |C/I 1 MHz adjacent to image|GFSK, BDR GFSK 0.1% BER[11]|–|–|–35.0|| |channel|||||| |**Out-of-band blocking performance (CW)**[12]|||||| |30 MHz to 2000 MHz|BDR GFSK 0.1% BER|–|–10.0|–|dBm| |2000 MHz to 2399 MHz|BDR GFSK 0.1% BER|–|–27|–|| |2498 MHz to 3000 MHz|BDR GFSK 0.1% BER|–|–27|–|| |3000 MHz to 12.75 GHz|BDR GFSK 0.1% BER|–|–10.0|–|| |**Intermodulation performance**[11]|||||| |Bluetooth, interferer signal<br>level<br>**Spurious emissions**<br>~~ee ~~|BDR GFSK 0.1% BER<br> ~~ee~~|–|–|–39.0|dBm| |30 MHz to 1 GHz<br>–<br>–<br>–<br>–57.0<br>dBm<br>1 GHz to 12.75 GHz<br>–<br>–<br>–<br>–47.0<br>~~re~~|||||| |**Notes**|||||| 10.The receiver sensitivity is measured at BER of 0.1% on the device interface with dirty TX Off. 11.Desired signal is 10 dB above the reference sensitivity level (defined as –70 dBm). 12.Desired signal is 3 dB above the reference sensitivity level (defined as –70 dBm). Preliminary Datasheet 002-24743 Rev. *G 43 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Specifications |**Table 23**<br>**BR/EDR - Transmitter RF specifications**||||| |---|---|---|---|---| |**Parameter**|**Min**|**Typ**|**Max**|**Unit**| |**Transmitter section**||||| |Frequency range|2402|–|2480|MHz| |Class 1: BR TX power|–|11.5|–|dBm| |Class 1: EDR 2M TX power|–|2.5|–|| |Class 1: EDR 3M TX power|–|1.5|–|| |20 dB bandwidth|–|930|1000|kHz| |**Adjacent channel power**||||| ||M – N|= 2|–|–|–20|dBm| ||M – N| 3[13]|–|–|–40|| |Out-of-band spurious emission||||| |30 MHz to 1 GHz<br>–<br>–<br>–36.0<br>dBm<br>1 GHz to 12.75 GHz<br>–<br>–<br>–30.0<br>1.8 GHz to 1.9 GHz<br>–<br>–<br>–47.0<br>5.15 GHz to 5.3 GHz<br>–<br>–<br>–47.0<br>~~—<—_—~~||||| |**LO performance**||||| |Initial carrier frequency tolerance|–75|–|+75|kHz| |Frequency drift||||| |DH1 packet|–25|–|+25|kHz| |DH3 packet|–40|–|+40|| |DH5 packet|–40|–|+40|| |Drift rate|–20|–|20|kHz/50 µs| |**Frequency deviation**||||| |Average deviation in payload (sequence used is 00001111)<br>140<br>–<br>175<br>kHz<br>Maximum deviation in payload (sequence used is 10101010)<br>115<br>–<br>–<br>Channel spacing<br>–<br>1<br>–<br>MHz<br>**Note**<br>~~—ee~~||||| |13.Meet SIG specification.||||| Preliminary Datasheet 002-24743 Rev. *G 44 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Specifications ## **Table 24 Bluetooth LE RF specifications** |**Bluetooth LE RF specifications**|||| |---|---|---|---| |**Conditions**|**Min**|**Typ**|**Max**| |N/A|2402|–|2480| |GFSK, BDR GFSK 0.1% BER 0.1% BER,<br>1 Mbps|–|–94.5|–| |N/A|–|11.5|–| |N/A|225|255|275| |N/A|99.9|–|–| |N/A|0.8|–|–| ## **Notes** 14.Dirty TX is off. 15.At least 99.9% of all delta F2 max frequency values recorded over 10 packets must be greater than 185 kHz. **Table 25 BLE2 RF specifications Parameter Conditions Min Typ Max Unit** RX sensitivity[[16]] – – –91.5 – dBm TX power – – 11.5 – ~~a~~ **Notes** 16.255 packet. Preliminary Datasheet 002-24743 Rev. *G 2022-09-26 45 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Specifications ## **11.13 Timing and AC characteristics** In this section, use the numbers listed in the Reference column of each table to interpret the timing diagrams shown in **Figure 11** through **Figure 16** . ## **11.13.1 UART timing** |**11.13.1**<br>**Table 26**|**UART timing**<br>**UART timing specifications**||||| |---|---|---|---|---|---| |**Reference**|**Characteristics**|**Min**|**Typ**|**Max**|**Unit**| |1|Delay time, UART_CTS_N LOW to UART_TXD<br>valid.|–|–|1.50|Bit periods| |2|Setup time, UART_CTS_N HIGH before midpoint<br>of stop bit.|–|–|0.67|| |3|Delay time, midpoint of stop bit to UART_RTS_N<br>HIGH.|–|–|1.33|| **==> picture [466 x 203] intentionally omitted <==** **----- Start of picture text -----**<br> UART_CTS_N<br>2<br>1<br>UART_TXD<br>Midpoint of STOP bit<br>ee Pa Midpoint of STOP bit<br>UART_RXD<br>OK yt<br>3<br>UART_RTS_N<br>**----- End of picture text -----**<br> **Figure 11 UART timing** Preliminary Datasheet 002-24743 Rev. *G 46 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Specifications ## **11.13.2 SPI timing** The SPI interface can be clocked up to 12 MHz. **Table 27** and **Figure 12** show the timing requirements when operating in SPI mode 0 and 2. ## **Table 27 SPI mode 0 and 2** |**Table 27**|**SPI mode 0 and 2**|||| |---|---|---|---|---| |**Reference**|**Characteristics**|**Min**|**Max**|**Unit**| |1|Time from master assert SPI_CSN to first clock edge|45|–|ns| |2|Setup time for MOSI data lines|6|½ SCK|| |3|Idle time between subsequent SPI transactions|1 SCK|–|| **==> picture [425 x 133] intentionally omitted <==** **----- Start of picture text -----**<br> SPI_CSN 3<br>1<br>SPI_CLK (mode 0)<br>SPI_CLK (mode 2)<br>2<br>SPI_MOSI First Bit Second Bit Last Bit<br>SPI_MISO Not Driven First Bit Second Bit Last Bit Not Driven<br>**----- End of picture text -----**<br> **Figure 12 SPI timing, mode 0 and 2** **Table 28** and **Figure 13** show the timing requirements when operating in SPI mode 1 and 3. ## **Table 28 SPI mode 1 and 3** |**Table 28**|**SPI mode 1 and 3**|||| |---|---|---|---|---| |**Reference**|**Characteristics**|**Min**|**Max**|**Unit**| |1|Time from master assert SPI_CSN to first clock edge|45|–|ns| |2|Setup time for MOSI data lines|6|½ SCK|| |3|Idle time between subsequent SPI transactions|1 SCK|–|| **==> picture [440 x 133] intentionally omitted <==** **----- Start of picture text -----**<br> SPI_CSN 3<br>1<br>SPI_CLK (mode 1)<br>SPI_CLK (mode 3) 2<br>SPI_MOSI Invalid bit First Bit Second Bit Last Bit<br>SPI_MISO Not Driven Invalid bit First Bit Second Bit Last Bit Not Driven<br>**----- End of picture text -----**<br> **Figure 13 SPI timing, mode 1 and 3** Preliminary Datasheet 002-24743 Rev. *G 47 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Specifications ## **11.13.3 I[2] C interface timing** The specifications in **Table 29** references **Figure 14** . |**Table 29**|**I2C interface timing specifications (up to 1 MHz)**|||| |---|---|---|---|---| |**Reference**|**Characteristics**|**Min**|**Max**|**Unit**| |1|Clock frequency|–|100|kHz| ||||400|| ||||800|| ||||1000|| |2|START condition setup time|650|–|μs| |3|START condition hold time|280|–|| |4|Clock low time|650|–|| |5|Clock high time|280|–|| |6|Data input hold time[17]|0|–|| |7|Data input setup time|100|–|| |8|STOP condition setup time|280|–|| |9|Output valid from clock|–|400|| |10|Bus free time[18]|650|–|| ## **Notes** 17.As a transmitter, 125 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 18.Time that the CBUS must be free before a new transaction can start. **==> picture [468 x 181] intentionally omitted <==** **----- Start of picture text -----**<br> 1<br>5<br>SCL<br>2<br>4 6 8<br>3 7<br>SDA<br>IN<br>10<br>cy A > Ge GG<br>9<br>SDA<br>OUT<br>a cn<br>**----- End of picture text -----**<br> **Figure 14** **I[2] C interface timing diagram** Preliminary Datasheet 002-24743 Rev. *G 48 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Specifications ## **11.13.4 I2S** **Table 30 Timing for I[2] S transmitters and receivers** **Transmitter Receiver Lower limit Upper limit Lower limit Upper limit Notes Min Max Min Max Min Max Min Max** Clock period T Ttr – – – Tr – – – [19] **Master mode: Clock generated by transmitter or receiver** HIGH tHC 0.35 × Ttr – – – 0.35 × Ttr – – – [20] ~~ee~~ LOWtLC 0.35 × Ttr – – – 0.35 × Ttr – – – [20] **Slave mode: Clock accepted by transmitter or receiver** HIGH tHC – 0.35 × Ttr – – – 0.35 × Ttr – – [19] LOW tLC – 0.35 × Ttr – – – 0.35 × Ttr – – [19] ~~ee~~ Rise time tRC – – 0.15 × Ttr – – – – [20] **Transmitter** Delay tdtr – – – 0.8 × T – – – – [21] ~~EE~~ Hold time thtr 0 – – – – – – – [20] **Receiver** Setup time tsr – – – – 0.2 × Ttr – – – [22] ~~ee~~ Hold time thr – – – ~~ee~~ – 0.2 × T ~~ee~~ tr ~~ee~~ – – – [22] **Notes** 19.The system clock period T must be greater than Ttr and Tr because both the transmitter and receiver have to be able to handle the data transfer rate. 20.At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, tHC and tLC are specified with respect to T. - 21.In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that they can detect the signal. So long as the minimum periods are greater than 0.35Tr, any clock that meets the requirements can be used. - 22.Because the delay (tdtr) and the maximum transmitter speed (defined by Ttr) are related, a fast transmitter driven by a slow clock edge can result in tdtr not exceeding tRC which means thtr becomes zero or negative. Therefore, the transmitter has to guarantee that thtr is greater than or equal to zero, so long as the clock rise-time tRC is not more than tRCmax, where tRCmax is not less than 0.15Ttr. - 23.To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always giving the receiver sufficient setup time. 24.The data setup and hold time must not be less than the specified receiver setup and hold time. Preliminary Datasheet 002-24743 Rev. *G 49 2022-09-26 ## **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Specifications **==> picture [510 x 516] intentionally omitted <==** **----- Start of picture text -----**<br> T<br>tRC*<br>tLC 0.35T tHC 0.35T<br>VH = 2.0V<br>SCK<br>VL = 0.8V<br>thtr 0<br>totr 0.8T<br>SD and WS<br>T = Clock period<br>Ttr = Minimum allowed clock period for transmitter<br>T = Ttr<br>* tRC is only relevant for transmitters in slave mode.<br>=<br>Figure 15 I [2] S transmitter timing<br>T<br>tLC 0.35T tHC 0.35<br>VH = 2.0V<br>SCK<br>VL = 0.8V<br>tsr 0.2T thr 0<br>SD and WS<br>T = Clock period<br>Tr = Minimum allowed clock period for transmitter<br>T > Tr<br>Se<br>Figure 16 I [2] S receiver timing<br>**----- End of picture text -----**<br> Preliminary Datasheet 002-24743 Rev. *G 50 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Packaging diagrams ## **12 Packaging diagrams** ## **12.1 62-pin FBGA package** **==> picture [431 x 482] intentionally omitted <==** **----- Start of picture text -----**<br> 2X an 0.10 C i, E1 7<br>L (datum B)<br>E B A A1 CORNER<br>8 7 6 5 4 3 2 1<br>| pot te G g | | -<br>7 6 A<br>A1 CORNER SD B<br>C<br>D<br>D1<br>D E<br>F (datum A)<br>G<br>H<br>0.10 C 2X eD 6 eE<br>SE<br>TOP VIEW<br>BOTTOM VIEW<br>DETAIL A<br>0.10 C<br>A<br>A 1<br>0.08 C C 62XØb 5<br>Ø0.15 M C A B SIDE VIEW<br>Ø0.05 M C<br>DETAIL A<br>NOTES:<br>PO DIMENSIONS 1. ALL DIMENSIONS ARE IN MILLIMETERS.<br>SYMBOL<br>MIN. NOM. MAX. 2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.<br>——————a<br>A 0.70 0.75 0.80 3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.<br>ee ee ee<br>A1 0.126 0.176 0.226 4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.<br>es ee ee<br>D 4.50 BSC SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.<br>es N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX<br>E 4.50 BSC<br>ee SIZE MD X ME.<br>D1 3.50 BSC<br>eea E1 eeee 3.50 BSC 5. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A<br>PLANE PARALLEL TO DATUM C.<br>MD 8<br>ee ME ee 8 6. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND<br>ee DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW<br>a N ee 62<br>WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW<br>b 0.20 0.25 0.30<br>ee ee "SD" OR "SE" = 0.<br>a eD 0.50 BSC<br>WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW<br>eE 0.50 BSC<br>ee "SD" = eD/2 AND "SE" = eE/2.<br>a SD 0.25 BSC<br>7. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK<br>SE 0.25 BSC<br>ee METALIZED MARK, INDENTATION OR OTHER MEANS.<br>8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER<br>BALLS.<br>9. JEDEC SPECIFICATION NO. REF. : N/A.<br>**----- End of picture text -----**<br> **==> picture [61 x 9] intentionally omitted <==** **----- Start of picture text -----**<br> 002-20916 *A<br>**----- End of picture text -----**<br> **Figure 17 62-ball FBGA (4.5 × 4.5 × 0.8 mm) package outline, 002-20916** Preliminary Datasheet 002-24743 Rev. *G 51 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Packaging diagrams ## **12.2 Tape reel and packaging specifications** **Table 31 CYW20820 62-pin FBGA tape reel specifications** |**Parameter**|**Value**| |---|---| |Quantity per reel|5500 parts| |Reel diameter|13 inches| |Hub diameter|4 inches| |Tape width|12 mm| |Pocket pitch|8 mm| |Sprocket hole pitch|4 mm| The top-left corner of the CYW20820 package is situated near the sprocket holes, as shown in **Figure 18** . Pin 1:[Top left corner of package toward sprocket holes] The direction of unreeling is to the right **Figure 18 Pin 1 orientation** Preliminary Datasheet 002-24743 Rev. *G 2022-09-26 52 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Ordering information ## **13 Ordering information** |**Table 32**|**Table 32**|**Ordering information**|**Ordering information**||| |---|---|---|---|---|---| |~~—~~||**Part number**<br>CYW20820A1KFBG||**Package**<br>4.5 mm ×4.5 mm 62-ball FBGA|**Ambient operating temperature**<br>30°C to 85°C| Preliminary Datasheet 002-24743 Rev. *G 53 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Acronyms |**Acronym**|**Description**| |---|---| |ACL|asynchronous connection-less| |ADC|analog-to-digital converter| |AFH|adaptive frequency hopping| |ARM7TDMI-S™|Acorn RISC Machine 7 Thumb instruction, Debugger, Multiplier, Ice, Synthesizable| |BBC|Bluetooth Baseband Core| |BDR|basic data rate| |BLE|Bluetooth low energy| |BER|bit error rate| |BR|basic data rate| |CMOS|complementary metal oxide semiconductor| |CRC|cyclic redundancy check| |CTS|clear to send| |ECDSA|elliptic curve digital signature algorithm| |ED|erroneous data| |EDR|enhanced data rate| |EIR|extended inquiry response| |ePDS|extended power down sleep| |eSCO|extended synchronous connection-oriented| |EPR|encryption pause resume| |FEC|forward error correction| |FPU|floating point unit| |GAP|generic access profile| |GATT|generic attribute profile| |GCI|global coexistence interface| |GFSK|Gaussian Frequency Shift Keying| |GPIO|general-purpose I/O| |HCI|host control interface| |HEC|header error control| |HID|human-interface device| |I2C|inter-integrated circuit| |I2S|inter-IC sound bus| |IF|intermediate frequency| |JTAG|Joint Test Action Group| |L2CAP|logical link control and adaptation protocol| |LC|link control| |LCU|link control unit| Preliminary Datasheet 002-24743 Rev. *G 54 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Acronyms **Table 33 Acronyms used in this document** _(continued)_ |**Acronym**|**Description**| |---|---| |LDO|low drop out| |LE|low energy| |LED|light emitting diode| |LHL|lean high land| |LMAC|Lower MAC| |LO|local oscillator| |LPO|low power oscillator| |LSTO|link supervision time out| |MOSI|master out slave in| |OEM|original equipment manufacturer| |OTP|one-time programmable| |OCF|on chip flash| |OTA|over-the-air| |PA|power amplifier| |PBF|packet boundary flag| |PCM|pulse code modulation| |PDM|pulse density modulation| |PDS|power down sleep| |PLL|phase locked loop| |PMU|power management unit| |POR|power-on reset| |PWM|pulse width modulation| |QFN|quad flat no-lead| |QoS|quality of service| |RAM|random access memory| |RC oscillator|A resistor-capacitor oscillator is a circuit composed of an amplifier, which provides the<br>output signal, and a resistor-capacitor network, which controls the frequency of the<br>signal.| |RF|radio frequency| |ROM|read-only memory| |RSSI|receiver signal strength indicator| |RTC|real time clock| |RTS|request to send| |RX/TX|receive/transmit| |SCO|synchronous connection-oriented| |SDS|Shut Down Sleep| |SECI|serial enhanced coexistence interface| |SoC|system on chip| |SPI|serial peripheral interface| Preliminary Datasheet 002-24743 Rev. *G 55 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Acronyms **Table 33 Acronyms used in this document** _(continued)_ |**Acronym**|**Description**| |---|---| |SSP|secure simple pairing| |SSR|sniff subrating| |SWD|serial wire debug| |TRNG|True Random Number Generator| |TSSI|transmit signal strength indicator| |UART|universal asynchronous receiver/transmitter| |ULP|ultra-low-power| |WDT|watchdog timer| |WFI|wait for interrupt| Preliminary Datasheet 002-24743 Rev. *G 56 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** Revision history ## **Revision history** |**Document**<br>**revision**|**Date**|**Description of changes**| |---|---|---| |**|2018-08-16|New datasheet.| |*A|2019-02-22|Replaced “WICED” with “ModusToolbox™” in all instances across the<br>document.<br>Updated**“Functional block diagram”**on page 2.<br>Updated**“Peripherals”**on page 17:<br>Updated**“I2S interface”**on page 20:<br>Updated description.<br>Updated**“Pin assignments and GPIOs”**on page 23:<br>Updated 62-pin FBGA and 112-pin FBGA Pin Assignments:<br>Updated**Table 5**.<br>Updated**“Specifications”**on page 34:<br>Updated**“Electrical characteristics”**on page 34:<br>Updated**Table 8**.<br>Updated**“Core buck regulator”**on page 36:<br>Updated**Table 13**.<br>Updated**“Recommended component”**on page 36:<br>Updated**Table 14**.<br>Updated**“Digital LDO”**on page 37:<br>Updated**Table 15**.<br>Updated**“Recommended component”**on page 37:<br>Updated**Table 16**.<br>Updated**“RF LDO”**on page 38:<br>Updated**Table 17**.<br>Removed “Recommended Component”.<br>Added**“PALDO”**on page 39.<br>Added**“ADC electrical characteristics”**on page 41.<br>Updated**“Current consumption”**on page 42:<br>Updated**Table 21**.<br>Updated**“RF specifications”**on page 43:<br>Added footnote in**Table 23**.| |*B|2019-06-13|Updated**“Microprocessor unit”**on page 7:<br>Added**“Low-frequency clock sources”**on page 8.<br>Updated**“Peripherals”**on page 17:<br>Removed “Serial Peripheral Interface”.<br>Updated**“Ball maps”**on page 33:<br>Updated**“62-pin FBGA pin map”**on page 33:<br>Updated**Figure 10**.<br>Updated “112-pin FBGA Pin”.<br>Updated figure “112-pin FBGA Ball Map”.<br>Updated**“Specifications”**on page 34:<br>Updated**“RF specifications”**on page 43:<br>Updated**Table 23**.| |*C|2020-01-16|Added**Power configurations**.<br>Updated**“Specifications”**on page 34:<br>Updated**“Electrical characteristics”**on page 34:<br>Updated**Table 8**.<br>Updated**“Specifications”**on page 34:<br>Updated**“RF specifications”**on page 43:<br>Updated details under “Transmitter section” in**Table 23**.| Preliminary Datasheet 002-24743 Rev. *G 57 2022-09-26 **AIROC™ Bluetooth® and Bluetooth® LE system on chip** ## Revision history |*D|2020-07-15|Updated**“Features”**on page 1:<br>Replaced “Programmable BDR TX Power up to 10.5 dBm” with<br>“Programmable BDR TX Power up to 11.5 dBm”.<br>Updated**“Power configurations”**on page 13:<br>Added external reset information in this section.<br>Updated**“Pin assignments and GPIOs”**on page 23:<br>Updated 62-pin FBGA and 112-pin FBGA Pin Assignments:<br>Updated VDDC pin description in**Table 5**.| |---|---|---| |*E|2021-06-11|Replaced “BLE” with “Bluetooth® LE” in all instances across the document.<br>Replaced “BT” with “Bluetooth®” in all instances across the document.<br>Updated**“Specifications”**on page 34:<br>Updated**“Current consumption”**on page 42:<br>Updated**Table 21**to include BR, EDR, and Bluetooth® LE.| |*F|2022-07-13|Updated**“Peripherals”**on page 17:<br>Updated**“GPIO ports”**on page 18:<br>Updated description.<br>Updated**“Pin assignments and GPIOs”**on page 23:<br>Updated**“62-pin FBGA pin assignments”**on page 23:<br>Updated**Table 5**.<br>Updated**“Ball maps”**on page 33:<br>Removed “112-pin FBGA pin”.<br>Updated**“Packaging diagrams”**on page 51:<br>Removed “112-pin FBGA package”.<br>Updated**“Tape reel and packaging specifications”**on page 52:<br>Removed table “CYW20820 112-pin FBGA Tape Reel Specifications”.<br>Updated**“Ordering information”**on page 53:<br>Updated**Table 32**:<br>Updated part numbers.<br>Updated to Infineon template.| |*G|2022-09-26|Updated**Power configurations**:<br>Updated**Configuration 1 - VBAT and VDDIO**:<br>Updated**Figure 6**.<br>Updated**Peripherals**:<br>Updated**ADC**:<br>Updated description.<br>Updated**Pin assignments and GPIOs**:<br>Updated**62-pin FBGA pin assignments**:<br>Updated**Table 5**.<br>Updated**Specifications**:<br>Updated**RF specifications**:<br>Updated**Table 23**.| Preliminary Datasheet 002-24743 Rev. *G 58 2022-09-26 ## **Trademarks** All referenced product or service names and trademarks are the property of their respective owners. ## **IMPORTANT NOTICE** For further information on the product, technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies office ( **www.infineon.com** ). **Edition 2022-09-26** The information given in this document shall in no For further information on the product, technology, event be regarded as a guarantee of conditions or delivery terms and conditions and prices please **Published by** characteristics (“Beschaffenheitsgarantie”). contact your nearest Infineon Technologies office **Infineon Technologies AG** ( **www.infineon.com** ). **81726 Munich, Germany** With respect to any examples, hints or any typical values stated herein and/or any information **WARNINGS** regarding the application of the product, Infineon Due to technical requirements products may contain Technologies hereby disclaims any and all dangerous substances. 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Except as otherwise explicitly approved by Infineon **Do you have a question about this document?** obligations stated in this document and anyIn addition, any information given in this documentis subject to customer’s compliance with its Technologies in a written document signed byauthorized Technologies, Infineon Technologies’ products mayrepresentatives of Infineon **Go to www.infineon.com/support** applicable legal requirements, norms and standards not be used in any applications where a failure of the concerning customer’s products and any use of the product or any consequences of the use thereof can product of Infineon Technologies in customer’s reasonably be expected to result in personal injury. **Document reference** applications. **002-24743 Rev. *G** The data contained in this document is exclusively intended for technically trained staff. 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Updated at March 6, 2026
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