CYW20736S

**CYW20736S** 

Bluetooth Low Energy S stem-in-Packa e SiP Module y g ( ) 

The CYW20736S is a compact, highly integrated Bluetooth Low Energy (BLE) system-in-package (SiP) module. The CYW20736S SiP includes an embedded BLE antenna, 24 MHz clock, and 512 Kb EEPROM, so only a minimal set of external components is needed to create a standalone BLE device. 

The CYW20736S is designed to accelerate time to market. The Bluetooth stack and several application profiles are built into the module, allowing customers to focus on their core applications. To further reduce application development time, the CYW20736S includes integrated software support, with one-click installation of the complete environment and a one-click compile/build/link/load cycle. All this, coupled with an ultrasmall form factor and support for a wide voltage range, makes the CYW20736S well suited for virtually any Bluetooth Smart application. 

## **Cypress Part Numbering Scheme** 

Cypress is converting the acquired IoT part numbers from Broadcom to the Cypress part numbering scheme. Due to this conversion, there is no change in form, fit, or function as a result of offering the device with Cypress part number marking. The table provides Cypress ordering part number that matches an existing IoT part number. 

**Table 1.  Mapping Table for Part Number between Broadcom and Cypress** 

**Broadcom Part Number Cypress Part Number** BCM20736S CYW20736S ~~|~~ **Features** 

## **Applications** 

The following profiles are supported in CYW20736S ROM: 

- ARM Cortex-M3 microcontroller unit (MCU) 

- Embedded 512 Kb EEPROM 

   - Battery status 

- Broadcom Serial Control (BSC), SPI, and UART interfaces 

   - Blood pressure monitor 

- FCC and CE compliant 

   - Find me 

- RoHS compliant, certified lead- and halogen-free 

   - Heart rate monitor 

- Moisture Sensitivity Level (MSL) 3 compliant 

   - Proximity 

- 6.5 mm × 6.5 mm × 1.2 mm Land Grid Array (LGA) 48-pin package 

- Thermometer 

- Weight scale 

- Time 

- Blood glucose monitor 

Additional profiles that can be supported in CYW20736S RAM include: 

- Blood glucose monitor 

- Temperature alarm 

- Location 

- Other custom profiles 

**Cypress Semiconductor Corporation** Document Number: 002-15224 Rev. *E 

• 198 Champion Court 

San Jose, CA 95134-1709 • 408-943-2600 Revised November 15, 2017 

• 

**CYW20736S** 

**Figure 1.  CYW20736S BLE SiP Block Diagram** 

**==> picture [343 x 225] intentionally omitted <==**

**----- Start of picture text -----**<br>
VBAT/VDDIO<br>CYW20736S<br>Antenna BCM20736S<br>\/<br>Bandpass<br>Filter<br>UART<br>SPI/I [2] C<br>BCM20736 CYW20736S<br>Bluetooth Low Energy Infrared<br>System-on-Chip with<br>ARM  [®]  Cortex™ M3-based ADC<br>24 MHz Microprocessor Core<br>GPIOs<br>XTAL<br>PWM<br>_<br>||<br>32.768 kHz<br>EEPROM<br>Oscillator<br>512 Kb I [2] C<br>(optional)<br>|| =<br>**----- End of picture text -----**<br>


## **IoT Resources** 

Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software updates. Customers can acquire technical documentation and software from the Cypress Support Community website (http://community.cypress.com/). 

Document Number: 002-15224 Rev. *E 

Page 2 of 24 

**CYW20736S** 

## **Contents** 

**1. Functional Description................................................. 4** 1.1 External Reset....................................................... 4 1.2 32.768 kHz Oscillator ............................................ 4 **2. Pin Map and Signal Descriptions................................ 5 3. Electrical Specifications ............................................ 10 4. RF Specifications ....................................................... 11 5. ADC Specifications .................................................... 12 6. Timing and AC Characteristics ................................. 13** 6.1 SPI Timing........................................................... 13 

6.2 BSC Interface Timing .......................................... 14 6.3 UART Timing....................................................... 15 **7. PCB Design and Manufacturing Recommendations 16** 7.1 Pad and Solder Mask Opening Dimensions........ 16 7.2 PCB Stencil ......................................................... 17 **8. Packaging and Storage Information......................... 18 9. Mechanical Information ............................................. 20 10. Ordering Information................................................ 22 Document History.......................................................... 23** 

Document Number: 002-15224 Rev. *E 

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**CYW20736S** 

## **1.  Functional Description** 

## **1.1  External Reset** 

External reset timing for the CYW20736S is illustrated in Figure 2. 

**Figure 2. External Reset Timing** 

**==> picture [373 x 186] intentionally omitted <==**

**----- Start of picture text -----**<br>
Pulse width<br>>20 µs<br>RESET_N<br>Crystal<br>warm‐up<br>delay:<br>~ 5 ms<br>Baseband Reset<br>Start reading EEPROM and<br>firmware boot<br>Crystal Enable<br>**----- End of picture text -----**<br>


## **1.2  32.768 kHz Oscillator** 

The CYW20736S includes a standard Pierce oscillator. The oscillator circuit includes a comparator with hysteresis on the output to create a single-ended digital output. The hysteresis eliminates chatter when the input is near the comparator threshold (~100 mV). The oscillator circuit can is designed for a 32 kHz or 32.768 kHz crystal oscillator, and can also be driven by an external clock input with a similar frequency. Characteristics for a 32 kHz oscillator are defined in Table 2. 

**Table 2. 32 kHz Crystal Oscillator Characteristics** 

|**Parameter**<br>~~po~~<br>~~a~~|**Symbol**|**Conditions**|**Min.**<br>~~GO~~|**Typ.**<br>~~GO~~|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|Output frequency<br>~~po~~<br>~~eS~~<br>~~a~~|Foscout<br>~~eS~~|–<br>~~eS~~|–<br>~~eS~~<br>~~GO~~|32.768<br>~~eS~~<br>~~GO~~|–<br>~~eS~~|kHz<br>~~eS~~|
|Frequency tolerance<br>~~a~~|Ftol<br>~~CC~~|Crystal-dependent<br>~~CC~~|–<br>~~GO~~<br>~~CC~~|100<br>~~GO~~<br>~~CC~~|–<br>~~CC~~|ppm<br>~~CC~~|
|Start-up time<br>~~a~~<br>~~a~~|Tstartup<br>~~CC~~<br>~~GG~~|–<br>~~CC~~<br>~~GG~~|–<br>~~GO~~<br>~~CC~~<br>~~GG~~|–<br>~~GO~~<br>~~CC~~<br>~~GG~~|500<br>~~CC~~<br>~~GG~~|µs<br>~~CC~~<br>~~GG~~|
|Crystal drive level<br>~~a~~|Pdrv<br>~~CC~~|For crystal selection<br>~~CC~~|0.5<br>~~CC~~|–<br>~~CC~~|–<br>~~CC~~|µW<br>~~CC~~|
|Crystal series resistance<br>~~a~~|Rseries<br>~~GG~~|For crystal selection<br>~~GG~~|–<br>~~GG~~|–<br>~~GG~~|70<br>~~GG~~|kΩ<br>~~GG~~|
|Crystal shunt capacitance<br>~~DG~~|Cshunt<br>~~DG~~|For crystal selection<br>~~DG~~|–<br>~~DG~~|–<br>~~DG~~|1.3<br>~~DG~~|pF<br>~~DG~~|



Document Number: 002-15224 Rev. *E 

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**CYW20736S** 

## **2.  Pin Map and Signal Descriptions** 

The CYW20736S pin map is shown in Figure 3. 

**Figure 3. CYW20736S (TOP View)** 

The signal name, type, and description of each pin in the CYW20736S is listed in Table 3 on page 6. The symbols shown under I/O Type indicate pin directions (I/O = bidirectional, I = input, O = output) and the internal pull-up/pull-down characteristics (PU = weak internal pull-up resistor and PD = weak internal pull-down resistor), if any. 

Document Number: 002-15224 Rev. *E 

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**CYW20736S** 

**Table 3. Pin Descriptions** 

|**Pin**<br>~~|~~|**Name**<br>~~|~~|**I/O Type**<br>~~fo~~|**Description**<br>~~fo~~|
|---|---|---|---|
|1<br>~~|~~<br>~~ee~~|GPIO: P27<br>PWM1<br>~~|~~<br>~~es~~|I<br>~~fo~~<br>~~es~~|Default direction: Input.<br>After POR state: Input floating.<br>Drain current: 16 mA<br>Alternate function: MOSI (master and slave) for SPI_2<br>~~fo~~|
|2<br>~~|~~<br>~~ee~~<br>~~ee~~|GND<br>~~| ~~<br>~~es~~<br>~~es~~|GND<br> ~~fo~~<br>~~es~~<br>~~es~~|GND<br>~~fo~~|
|3<br>~~ee ~~<br>~~ee~~<br>~~ee~~|VBAT<br> ~~es~~<br>~~es~~<br>~~es~~|I<br>~~es~~<br>~~es~~<br>~~es~~|Battery supply input.|
|4<br>~~ee ~~<br>~~ee~~<br>~~ee~~|GND<br> ~~es~~<br>~~es~~<br>~~ee Rs~~|GND<br>~~es~~<br>~~es~~<br>~~Rs~~|GND|
|5<br>~~ee ~~<br>~~ee~~<br>~~ee~~|GND<br> ~~es~~<br>~~ee Rs~~<br>~~ee~~|GND<br>~~es~~<br>~~Rs~~|GND|
|6<br>~~ee~~<br>~~ee~~<br>~~ee~~|GND<br>~~ee Rs~~<br>~~ee~~<br>~~ee~~|GND<br>~~Rs~~|GND|
|7<br>~~ee~~<br>~~ee~~<br>~~ee~~|GND<br>~~ee~~<br>~~ee~~<br>~~ee~~|GND|GND|
|8<br>~~ee~~<br>~~ee~~<br>~~ee~~|GND<br>~~ee~~<br>~~ee~~|GND|GND|
|9<br>~~ee~~<br>~~ee~~<br>~~ee~~|GND<br>~~ee~~<br>~~Rs~~|GND<br>~~Rs~~|GND|
|10<br>~~ee~~<br>~~ee~~<br>~~ee~~|Reserved<br>~~Rs~~<br>~~es~~|–<br>~~Rs~~<br>~~es~~|Leave floating|
|11<br>~~ee~~<br>~~ee~~<br>~~ee~~|GND<br>~~Rs~~<br>~~es~~<br>~~es~~|GND<br>~~Rs~~<br>~~es~~<br>~~es~~|GND|
|12<br>~~ee ~~<br>~~ee~~<br>~~ee~~|GND<br> ~~es~~<br>~~es~~<br>~~ee Rs~~|GND<br>~~es~~<br>~~es~~<br>~~Rs~~|GND|
|13<br>~~ee ~~<br>~~ee~~<br>~~ee~~|GND<br> ~~es~~<br>~~ee Rs~~<br>~~ee~~|GND<br>~~es~~<br>~~Rs~~|GND|
|14<br>~~ee~~<br>~~ee~~<br>~~ee~~|GND<br>~~ee Rs~~<br>~~ee~~<br>~~ee~~|GND<br>~~Rs~~|GND|
|15<br>~~ee~~<br>~~ee~~<br>~~ee~~|GND<br>~~ee~~<br>~~ee~~<br>~~ee~~|GND|GND|
|16<br>~~ee~~<br>~~ee~~<br>~~ee~~|GND<br>~~ee~~<br>~~ee~~|GND|GND|
|17<br>~~ee~~<br>~~ee~~<br>~~ee~~|GND<br>~~ee~~<br>~~Rs~~|GND<br>~~Rs~~|GND|
|18<br>~~ee~~<br>~~ee~~<br>~~ee~~|UART_RX<br>~~Rs~~<br>~~es~~|I<br>~~Rs~~<br>~~es~~|UART_RX. This pin is pulled low through an internal 10 kΩ resistor.|
|19<br>~~ee~~<br>~~ee~~<br>~~ee~~|UART_TX<br>~~Rs~~<br>~~es~~<br>~~es~~|O, PU<br>~~Rs~~<br>~~es~~<br>~~es~~|UART_TX|
|20<br>~~ee ~~<br>~~ee~~<br>~~ee~~|GND<br> ~~es~~<br>~~es~~<br>~~ee Rs~~|GND<br>~~es~~<br>~~es~~<br>~~Rs~~|GND|
|21<br>~~ee ~~<br>~~ee~~<br>~~ee~~|SCL<br> ~~es~~<br>~~ee Rs~~<br>~~ee~~|I/O, PU<br>~~es~~<br>~~Rs~~|SCL I/O, PU clock signal for an external I2C device|
|22<br>~~ee~~<br>~~ee~~<br>~~ee~~|SDA<br>~~ee Rs~~<br>~~ee~~<br>~~ee~~|I/O, PU<br>~~Rs~~|SDA I/O, PU data signal for an external I2C device|
|23<br>~~ee~~<br>~~ee~~<br>~~ee~~|GND<br>~~ee~~<br>~~ee~~<br>~~ee~~|GND|GND|
|24<br>~~ee~~<br>~~ee~~|GND<br>~~ee~~<br>~~ee~~|GND|GND|
|25<br>~~ee~~|GPIO: P1<br>~~ee~~|I|Default direction: Input.<br>After POR state: Input floating.<br>This pin is tied to the WP pin of the embedded EEPROM.<br>Requires an external 10K pull-up|
|26<br>~~ee~~|TMC<br>~~en~~|I<br>~~en~~|Test mode control. Pull this pin high to invoke test mode; leave it floating if not used.<br>This pin is connected to GND through an internal 10 kΩ resistor.|
|27<br>~~ee~~|RESET_N<br>~~en~~|I/O PU<br>~~en~~|Active-low system reset with open-drain output|



Document Number: 002-15224 Rev. *E 

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**CYW20736S** 

**Table 3. Pin Descriptions (Cont.)** 

|**Pin**|**Name**|**I/O Type**|**Description**|
|---|---|---|---|
|28|GPIO: P0|I|Default direction: Input.<br>After POR state: Input floating.<br>Alternate functions:<br>■A/D converter input<br>■Peripheral UART TX (PUART_TX)<br>■MOSI (master and slave) for SPI_2<br>■IR_RX<br>■60Hz_main|
|29|GND|GND|GND|
|30|GPIO: P3|I|Default direction: Input.<br>After POR state: Input floating.<br>Alternate functions:<br>■Peripheral UART CTS (PUART_CTS)<br>■SPI_CLK (master and slave) for SPI_2|
|31|GPIO: P2|I|Default direction: Input.<br>After POR state: Input floating.<br>Alternate functions:<br>■Peripheral UART RX (PUART_RX)<br>■SPI_CS (slave only) for SPI_2<br>■SPI_MOSI (master only) for SPI_2|
|32|GPIO: P4|I|Default direction: Input.<br>After POR state: Input floating.<br>Alternate functions:<br>■Peripheral UART RX (PUART_RX)<br>■MOSI (master and slave) for SPI_2.<br>■IR_TX|
|33|GPIO: P8|I|Default direction: Input.<br>After POR state: Input floating.<br>Alternate functions: A/D converter input.|
|34|GPIO: P33|I|Default direction: Input.<br>After POR state: Input floating.<br>Alternate functions:<br>■A/D converter input<br>■MOSI (slave only) for SPI_2<br>■Auxiliary clock output (ACLK1)<br>■Peripheral UART RX (PUART_RX)|



Document Number: 002-15224 Rev. *E 

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**CYW20736S** 

**Table 3. Pin Descriptions (Cont.)** 

|**Pin**|**Name**|**I/O Type**|**Description**|
|---|---|---|---|
|35|GPIO: P32|I|Default direction: Input.<br>After POR state: Input floating.<br>Alternate functions:<br>■A/D converter input<br>■SPI_CS (slave only) for SPI_2.<br>■Auxiliary clock output (ACLK0)<br>■Peripheral UART TX (PUART_TX)|
|36|GPIO: P25|I|Default direction: Input.<br>After POR state: Input floating.<br>Alternate functions:<br>■MISO (master and slave) for SPI_2<br>■Peripheral UART RX (PUART_RX)|
|37|GPIO: P24|I|Default direction: Input.<br>After POR state: Input floating.<br>Alternate functions:<br>■SPI_CLK (master and slave) for SPI_2<br>■Peripheral UART TX (PUART_TX)|
|38|NC|NC|No Connection (N/C).|
|39|GPIO: P13<br>PWM3|I|Default Direction: Input<br>After POR State: Input Floating<br>Drain current: 16 mA<br>Alternate function: A/D converter input|
||GPIO: P28<br>PWM2|I|Default direction: Input.<br>After POR state: Input floating.<br>Drain current: 16 mA<br>Alternate functions:<br>■A/D converter input<br>■LED1<br>■IR_TX|
|40|GPIO: P14<br>PWM2|I|Default direction: Input.<br>After POR state: Input floating.<br>Alternate function: A/D converter input|
||GPIO: P38|I|Default direction: Input.<br>After POR state: Input floating.<br>Alternate functions:<br>■A/D converter input<br>■MOSI (master and slave) for SPI_2<br>■IR_TX|
|41|GPIO: P15|I|Default direction: Input.<br>After POR state: Input floating.<br>Alternate functions:<br>■A/D converter input<br>■IR_RX<br>■60 Hz_main|



Document Number: 002-15224 Rev. *E 

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**CYW20736S** 

**Table 3. Pin Descriptions (Cont.)** 

|**Pin**|**Name**|**I/O Type**|**Description**|
|---|---|---|---|
|42|GPIO: P26<br>PWM0|I|Default direction: Input.<br>After POR state: Input floating.<br>Drain current: 16 mA<br>Alternate function: SPI_CS (slave only) for SPI_2|
|43|GPIO: P12|I|Default direction: Input.<br>After POR state: Input floating.<br>Alternate functions:<br>■A/D converter input<br>■XTALO32K|
||XTALO32K|O|Low-power oscillator (LPO) output.<br>Alternate functions:<br>P12<br>P26|
|44|GPIO: P11|I|Default direction: Input.<br>After POR state: Input floating.<br>Alternate functions:<br>■A/D converter input<br>■XTALI32K|
||XTALI32K|I|Low-power oscillator (LPO) input.<br>Alternate functions:<br>■P11<br>■P27|
|45|GND|GND|GND|
|46|GND|GND|GND|
|47|GND|GND|GND|
|48|GND|GND|GND|



Document Number: 002-15224 Rev. *E 

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**CYW20736S** 

## **3.  Electrical Specifications** 

Absolute maximum ratings are defined in Table 4. 

## **Table 4. Absolute Maximum Ratings** 

|**Parameter**|**Min.**|**Max.**|**Unit**|
|---|---|---|---|
|Supply power|NA|3.63|V|
|Storage temperature|–40|125|°C|
|Voltage ripple|0|±2|%|
|Power supply (VBAT absolute maximum rating)|1.62|3.63|V|



Power for the CYW20736S module is provided by the host through the power pins. 

## **Table 5. Voltage** 

|**Symbol**|**Parameter**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|
|VBAT|Battery voltage|1.62|–|3.63|V|



## **Table 6. Current Consumption** 

|**Operating Mode**|**Condition**|**Nominal**|**Maximum**|**Unit**|
|---|---|---|---|---|
|Receive|Receiver and baseband are both operating, 100%|24|28|mA|
|Transmit|Transmitter and baseband are both operating, 100%|24|28|mA|
|Sleep|Wake in < 5 ms|55|60|µA|
|Deep Sleep|Wake on interrupt|2.0|2.5|µA|



**Note:** All measurements taken at 25°C. 

Based on the current measurements in Table 6 on page 10, CYW20736S peak power values are: 

■ RX: 101.6 mW 

- TX: 101.6 mW 

- Sleep mode: 217.8 µW 

- Deep Sleep mode: 9.1 µW 

Document Number: 002-15224 Rev. *E 

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**CYW20736S** 

## **4.  RF Specifications** 

CYW20736S receiver specifications are defined in Table 7. 

## **Table 7. Receiver Specifications** 

|**Parameter**|**Mode and Conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|
|Frequency range|–|2402|–|2480|MHz|
|RX sensitivity (standard)|Packets: 200<br>Payload: PRBS 9<br>Length: 37 Bytes<br>Dirty Transmitter: off.<br>PER: 30.8%|–|–94|–|dBm|
|Maximum input|–|–10|–|–|dBm|



**Note:** All measurements taken at 3.0V (default voltage). 

RF transmitter specifications are defined in Table 8. 

**Table 8. Transmitter Specifications** 

~~a~~ **Parameter Min. Typ. Max. Unit Transmitter** ~~| a~~ Frequency range[a] 2402 – 2480 MHz ~~GG~~ Output power adjustment range –20 – 4 dBm ~~a~~ Output power – 2 – dBm ~~a~~ Output power variation – 2.5 – dB ~~pT~~ **LO Performance** ~~GG~~ Initial carrier frequency tolerance – – ±150 kHz ~~pT~~ **Frequency Drift** ~~GG~~ Frequency drift – – ±50 kHz ~~a~~ Drift rate – – 20 kHz/50 µs **Frequency Deviation** Average deviation in payload 225 – 275 kHz ~~ee~~ (sequence: 00001111) Average deviation in payload 185 – – kHz (sequence: 10101010) ~~ee GG~~ Channel spacing – 2 – MHz 

a. This parameter is taken from the Bluetooth 4.0 specification. 

Document Number: 002-15224 Rev. *E 

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**CYW20736S** 

## **5.  ADC Specifications** 

CYW20736S ADC specifications are defined in Table 9. 

**Table 9. ADC Specifications** 

|**Parameter**<br>~~OO~~|**Symbol**<br>~~OO~~<br>~~f~~|**Conditions**<br>~~OO~~<br>~~f~~|**Min.**<br>~~OO~~|**Typ.**<br>~~OO~~|**Max.**<br>~~OO~~|**Unit**<br>~~OO~~|
|---|---|---|---|---|---|---|
|Number of input channels<br>~~e~~|–<br>~~e~~<br>~~f~~|–<br>~~e~~~~**e**~~<br>~~f~~|–<br>~~**e**~~|9<br>~~**e**~~|–<br>~~**e**~~|-<br>~~**e**~~|
|Channel switching rate<br>~~e~~<br>~~GG~~|fch<br>~~e~~<br>~~f~~<br>~~GG~~|–<br>~~e~~~~**e**~~<br>~~f~~<br>~~GG~~|–<br>~~**e**~~<br>~~GG~~|–<br>~~**e**~~<br>~~GG~~|133.33<br>~~**e**~~<br>~~GG~~|Kch/s<br>~~**e**~~<br>~~GG~~|
|Input signal range<br>~~GG~~|Vinp<br>~~GG~~|–<br>~~GG~~|0<br>~~GG~~|–<br>~~GG~~|3.63<br>~~GG~~|V<br>~~GG~~|
|Reference settling time<br>~~GG~~<br>~~GG~~|–<br>~~GG~~<br>~~GG~~|Charging refsel<br>~~GG~~<br>~~GG~~|7.5<br>~~GG~~<br>~~GG~~|–<br>~~GG~~<br>~~GG~~|–<br>~~GG~~<br>~~GG~~|µs<br>~~GG~~<br>~~GG~~|
|Input resistance<br>~~GG~~|Rinp<br>~~GG~~|Effective, single-ended<br>~~GG~~|–<br>~~GG~~|500<br>~~GG~~|–<br>~~GG~~|kΩ<br>~~GG~~|
|Input capacitance<br>~~GG~~<br>~~GG~~|Cinp<br>~~GG~~<br>~~GG~~|–<br>~~GG~~<br>~~GG~~|–<br>~~GG~~<br>~~GG~~|–<br>~~GG~~<br>~~GG~~|5<br>~~GG~~<br>~~GG~~|pF<br>~~GG~~<br>~~GG~~|
|Conversion rate<br>~~GG~~|Fc<br>~~GG~~|–<br>~~GG~~|5.859<br>~~GG~~|–<br>~~GG~~|187<br>~~GG~~|kHz<br>~~GG~~|
|Conversion time<br>~~GG~~<br>~~GG~~|Tc<br>~~GG~~<br>~~GG~~|–<br>~~GG~~<br>~~GG~~|5.35<br>~~GG~~<br>~~GG~~|–<br>~~GG~~<br>~~GG~~|170.7<br>~~GG~~<br>~~GG~~|µs<br>~~GG~~<br>~~GG~~|
|Resolution<br>~~GG~~|R<br>~~GG~~<br>~~es ee~~|–<br>~~GG~~<br>~~ee~~|~~GG~~|16<br>~~GG~~|~~GG~~|Bits<br>~~GG~~|
|Absolute voltage measurement error<br>~~GG~~<br>~~ee~~|–<br>~~GG~~<br>~~ee~~<br>~~es ee~~|Using on–chip ADC<br>firmware driver<br>~~GG~~<br>~~ee~~<br>~~ee~~<br>~~Qe~~|–<br>~~GG~~<br>~~ee~~|±2<br>~~GG~~<br>~~ee~~|–<br>~~GG~~<br>~~ee~~|%<br>~~GG~~<br>~~ee~~|
|Current<br>~~eG~~|I<br>~~es ee~~<br>~~eG~~|Iavdd1p2+ Iavdd3p3<br>~~ee~~<br>~~eG~~<br>~~Qe~~|–<br>~~eG~~|–<br>~~eG~~|1<br>~~eG~~|mA<br>~~eG~~|
|Power<br>~~GG~~|P<br>~~GG~~|–<br>~~Qe~~<br>~~GG~~<br>~~Qe~~|–<br>~~GG~~|1.5<br>~~GG~~|–<br>~~GG~~|mW<br>~~GG~~|
|Leakage Current<br>~~eG~~|Ileakage<br>~~eG~~|T = 25°C<br>~~eG~~<br>~~Qe~~|–<br>~~eG~~|–<br>~~eG~~|100<br>~~eG~~|nA<br>~~eG~~|
|Power-up time<br>~~GG~~|Tpowerup<br>~~GG~~<br>~~es~~|–<br>~~Qe~~<br>~~GG~~<br>~~ee~~|–<br>~~GG~~|–<br>~~GG~~|200<br>~~GG~~|µs<br>~~GG~~|
|Integral nonlinearity<br>~~ee~~|INL<br>~~ee~~<br>~~es~~<br>~~es~~|In the guaranteed<br>performance range<br>~~ee~~<br>~~ee~~|–1<br>~~ee~~|–<br>~~ee~~|1<br>~~ee~~|LSBa<br>~~ee~~|
|Differential nonlinearity<br>~~es~~|DNL<br>~~es~~<br>~~es~~<br>~~es~~|In the guaranteed<br>performance range<br>~~ee~~<br>~~es~~|–1<br>~~es~~|–<br>~~es~~|1<br>~~es~~|LSBa<br>~~es~~|



a. LSBs are expressed at the 10-bit level. 

Document Number: 002-15224 Rev. *E 

Page 12 of 24 

**CYW20736S** 

## **6.  Timing and AC Characteristics** 

## **6.1  SPI Timing** 

SPI interface timing is illustrated in Figure 4 and Figure 5 and defined in Table 10 on page 14. 

**Figure 4. SPI Timing—Modes 0 and 2** 

**==> picture [474 x 166] intentionally omitted <==**

**----- Start of picture text -----**<br>
6<br>SPI_CSN rn<br>SPI_CLK 1<br>(Mode 0)<br>SPI_CLK<br>(Mode 2)<br>2 3<br>SPI_MOSI ‐ First Bit Second Bit Last bit ‐<br>4 5<br>SPI_MISO Not Driven First Bit Second Bit Last bit Not Driven<br>**----- End of picture text -----**<br>


**Figure 5. SPI Timing—Modes 1 and 3** 

**==> picture [461 x 152] intentionally omitted <==**

**----- Start of picture text -----**<br>
6<br>SPI_CSN<br>SPI_CLK 1<br>(Mode 1)<br>SPI_CLK<br>(Mode 3)<br>2 3<br>SPI_MOSI ‐ Invalid bit First bit Last bit ‐<br>4 5<br>SPI_MISO Not Driven Invalid bit First bit Last bit Not Driven<br>**----- End of picture text -----**<br>


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**CYW20736S** 

**Table 10. SPI Interface Timing Specifications** 

|**Reference**|**Characteristics**|**Min.**|**Typ.**|**Max.**|
|---|---|---|---|---|
|1|Time from CSN asserted to first clock edge|1 SCK|100|∞|
|2|Master setup time|–|1/2SCK|–|
|3|Master hold time|1/2SCK|-|–|
|4|Slave setup time|–|1/2 SCK|–|
|5|Slave hold time|1/2 SCK|–|–|
|6|Time from last clock edge to CSN deasserted|SCK|10 SCK|100|



## **6.2  BSC Interface Timing** 

BSC interface timing is illustrated in Figure 6 and is defined in Table 11. 

**Figure 6. BSC Interface Timing** 

**Table 11. BSC Interface Timing Specifications** 

|**Reference**<br>~~a~~<br>~~ee~~|**Characteristics**<br>~~ee~~<br>|**Min.**<br>~~ee~~<br>~~es~~<br>|**Max.**<br>~~ee~~<br>|**Unit**<br>~~ee~~<br>|
|---|---|---|---|---|
|1<br>~~ee~~|Clock frequency<br>~~GG~~|–<br>~~es~~<br>~~GG~~|100, 400, 800, 1000<br>~~GG~~|kHz<br>~~GG~~|
|2<br>~~ee~~<br>~~i~~|START condition setup time<br>|650<br>~~es~~<br>|–<br>|ns<br>|
|3<br>~~i~~|START condition hold time<br>~~GG~~|280<br>~~GG~~|–<br>~~GG~~|ns<br>~~GG~~|
|4<br>~~i~~|Clock low time|650|–|ns|
|5<br>~~i~~|Clock high time<br>~~GG~~|280<br>~~GG~~|–<br>~~GG~~|ns<br>~~GG~~|
|6<br>~~i~~|Data input hold time|0|–|ns|
|7<br>~~i~~|Data input setup time<br>~~GG~~|100<br>~~GG~~|–<br>~~GG~~|ns<br>~~GG~~|
|8<br>~~i~~<br>~~es~~|STOP condition setup time|280|–|ns|
|9<br>~~es~~|Output valid from clock|–|400|ns|
|10<br>~~es~~<br>~~a ~~|Bus free time<br> ~~a~~|650<br>~~GG~~|–<br>~~GG~~|ns<br>~~GG~~|



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**CYW20736S** 

## **6.3  UART Timing** 

UART timing is illustrated in Figure 7 and defined in Table 12. 

**==> picture [98 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 7. UART Timing<br>**----- End of picture text -----**<br>


**Table 12. UART Timing Specifications** 

|**Reference**|**Characteristics**|**Min.**|**Max.**|**Unit**|
|---|---|---|---|---|
|1|Delay time, UART_CTS_N low to UART_TXD valid|–|24|Baudout cycles|
|2|Setup time, UART_CTS_N high before midpoint of stop bit|–|10|ns|
|3|Delay time, midpoint of stop bit to UART_RTS_N high|–|2|Baudout cycles|



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**CYW20736S** 

## **7.  PCB Design and Manufacturing Recommendations** 

## **7.1  Pad and Solder Mask Opening Dimensions** 

CYW20736S pad and solder mask opening dimensions are defined in Table 13. 

**Table 13. Pad and Solder Mask Dimensions** 

|**Pad Type**|**Pad Dimensions**|**Solder Mask Opening Dimensions**|**Unit**|
|---|---|---|---|
|Type A|0.6 × 0.25|0.7 × 0.35|mm|
|Type B|0.55 × 0.3|0.65 × 0.4||
|Type C|0.4 × 0.4|0.5 × 0.5||



## _7.1.1  PCB Layout Recommendations_ 

The following layout recommendations are referenced to Figure 8 on page 16. 

- Connect to system ground from side D of the module (pins 13–22). 

- The L-shaped ground plane is required for the embedded BLE antenna. Keep the GND continuous. Do not cut off the GND shape to accommodate trace routes. 

- An L-shaped ground plane is required. If the L-shaped GND plane is located on the top layer of the PCB, do not place components on the ground plane. If this cannot be avoided, move the L-shaped ground plane to another layer. 

- Antenna efficiency of 31–41% can be achieved based on the layout in Figure 8 on page 16 and the dimensions listed below. Following these layout recommendations is expected to yield 50+ meters of usable range; deviating from these recommendations may reduce the range of the antenna. 

- ❐ D: 4.5 mm (typical) 

- ❐ G, H, S: 3 mm (typical) 

- ❐ L: 3 mm (minimum) 

- ❐ W: 0.4 mm (typical) 

- Route signal traces out of the module from side C (between pins 27 and 30) or side D (between pins 16 and 19) of the module. Traces can be overlapped to avoid routing through the keep-out area. 

- Do not route traces from side A or side B. 

**Figure 8. PCB Layout Example** 

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**CYW20736S** 

## **7.2  PCB Stencil** 

The recommended PCB stencil is shown in Figure 9 (all measurements in mm). Use an unsolder mask to set the module footprint. 

**Figure 9. CYW20736S Stencil (Bottom View)** 

## _7.2.1  Solder Reflow_ 

The recommended solder reflow profile for the CYW20736S is defined in Figure 10. 

**Figure 10. Solder Reflow Profile** 

**==> picture [351 x 172] intentionally omitted <==**

**----- Start of picture text -----**<br>
245°C<br>217°C<br>200°C<br>150°C<br>Pre‐Heating: 90~120 sec. Soldering: 60~90 sec.<br>Time<br>Temperature<br>**----- End of picture text -----**<br>


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**CYW20736S** 

## **8.  Packaging and Storage Information** 

The CYW20736S is available in a tape and reel package and is shipped in an ESD-protected moisture-resistant (MSL-3) bag as shown in Figure 11. The storage temperature range is –40°C to +125°C. 

**Figure 11. CYW20736S ESD/Moisture Packaging** 

The moisture sensitivity label on the CYW20736S shipping bag is shown in Figure 12 on page 19. 

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**CYW20736S** 

**Figure 12. CYW20736S Moisture Sensitivity Label** 

Figure 13 shows the location of pin 1 on the CYW20736S relative to its orientation on the tape packaging. 

**Figure 13. CYW20736S Tape and Reel Pin 1 Location** 

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**CYW20736S** 

## **9.  Mechanical Information** 

Package dimensions for the CYW20736S are shown in Figure 14. 

**Figure 14. CYW20736S Package Dimensions** 

Additional CYW20736S package dimensions are shown in Figure 15 on page 21. 

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**CYW20736S** 

**Figure 15. CYW20736S Pin Dimensions (Bottom View)** 

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**CYW20736S** 

## **10.  Ordering Information** 

## **Table 14. Ordering Information** 

|**Part Number**|**Package**|**Operating Temperature**|**Humidity**|
|---|---|---|---|
|CYW20736S|48-pin LGA|–40°C to +85°C|95% max., noncondensing|



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**CYW20736S** 

## **Document History** 

**Document Title: CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module Document Number: 002-15224** 

|**Document Title: CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module**<br>**Document Number: 002-15224**|**Document Title: CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module**<br>**Document Number: 002-15224**|**Document Title: CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module**<br>**Document Number: 002-15224**|**Document Title: CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module**<br>**Document Number: 002-15224**|**Document Title: CYW20736S Bluetooth Low Energy System-in-Package (SiP) Module**<br>**Document Number: 002-15224**|
|---|---|---|---|---|
|**Revision**|**ECN**|**Orig. of**<br>**Change**|**Submission**<br>**Date**|**Description of Change**|
|**|–||04/18/2014|MMP20736E-TRM100-R<br>Initial release.|
|*A|–|–|07/15/2014|MMP20736S-TRM101-R<br>Updated**:**<br>•<br>Pin 33 and pin 38 descriptions; see Table 3: “Pin Descriptions,” on page 7and 8.|
|*B|–|–|09/11/2014|MMP20736S-TRM102-R<br>Updated**:**<br>Table 3: “Pin Descriptions,” on page 8: Pin 37.<br>Removed**:**<br>•<br>Appendix A: “Acronyms and Abbreviations,” on page 28.|
|*C|–|UTSV|04/11/2016|MMP20736S-TRM103-R<br>Updated**:**<br>•<br>Table 6: “Current Consumption,” on page 10.|
|*D|5445386|UTSV|09/23/2016|Updated to Cypress Template.|
|*E|5967849|AESATMP9|11/15/2017|Updated logo and copyright.|



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**CYW20736S** 

## **Sales, Solutions, and Legal Information** 

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## **Technical Support** 

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© Cypress Semiconductor Corporation, 2014-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress").  This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide.  Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights.  If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products.  Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. 

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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. 

Document Number: 002-15224 Rev. *E 

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Revised November 15, 2017