CYBT-353027-02

Bluetooth 5.0 + EDR, 2.3V to 3.6V Supply, EZ-BT WICED Series Range, 3Mbps, -89.5dBm Sensitivity

⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
Manufacturer: INFINEON
Product type: Bluetooth Modules & Adaptors
Bluetooth Version:Bluetooth 5.0 + EDR; Supply Voltage Min:2.3V; Supply Voltage Max:3.6V; Signal Range Max:-; Data Rate:3Mbps; Bluetooth Class:-; Receive Sensitivity:-89.5dBm; Operatin
SVHC: No SVHC (25-Jun-2025)
Interfaces: I2C, SPI, UART
Product Range: EZ-BT WICED Series
Certifications: CE, FCC, ISED, MIC
Bluetooth Class: -
Bluetooth Version: Bluetooth 5.0 + EDR
Supply Voltage Range: 2.3 V to 3.6 V
Receiver Sensitivity Rx: -89.5 dBm
Operating Temperature Range: -30 °C to 85 °C
Delivery and price
Units per pack	250
Price	6.84 €
Current stock	200+
Lead time	30 days
Datasheet
**==> picture [120 x 54] intentionally omitted <==**

## **Please note that Cypress is an Infineon Technologies Company.** 

The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. 

## **Continuity of document content** 

The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. 

## **Continuity of ordering part numbers** 

Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. 

www.infineon.com 

**CYBT-353027-02** 

EZ-BT WICED Module 

## **General Description** 

The CYBT-353027-02 is a fully integrated Bluetooth[] Smart Ready wireless module. The CYBT-353027-02 includes an onboard crystal oscillator, passive components, flash memory, and the Cypress CYW2070x silicon device. 

The CYBT-353027-02 supports peripheral functions (ADC, timers), UART, I[2] C, and SPI communication, and a Bluetooth audio interface. The CYBT-353027-02 includes a royalty-free Bluetooth stack compatible with Bluetooth 5.0 in a 9.0 × 9.0 × 1.75 mm SMT package. 

The CYBT-353027-02 includes 512 KB of onboard serial flash memory and is designed for standalone operation. The CYBT-353027-02 uses an integrated power amplifier to achieve Class I or Class II output power capability. 

The CYBT-353027-02 is fully qualified by Bluetooth SIG and is targeted at space constrained applications. 

## **Features** 

## **Module Description** 

- Module size: 9.00 mm × 9.00 mm × 1.75 mm 

- Bluetooth 5.0 Qualified Smart Ready module 

## **Power Consumption**[[1]] 

- TX average current consumption: 52.5 mA (EDR) at 8 dBm 

- RX average current consumption: 26.4 mA (EDR) 

- Low power mode support 

- ❐ Deep Sleep: 2.69 µA 

## **Functional Capabilities** 

- - ADC for audio (12 bits) and DC measurement (10 bits) 

- Serial communications interface compatible with I[2] C slaves 

- Master Serial Peripheral Interface (SPI) support 

- HCI interface through UART 

- PCM/I2S Audio interface 

- Programmable output power control 

- Supports extended synchronous connections (eSCO), for enhanced voice quality by allowing for retransmission of dropped packets 

- Bluetooth wideband speech support 

## **Benefits** 

- ❐ QDID: D039123 

- ❐ Declaration ID: 109292 

- Certified to FCC, ISED, MIC, and CE regulations 

- Castelated solder pad connections for ease-of-use 

- 512-KB on-module serial flash memory 

- Up to eight GPIOs 

- Temperature range: –30 °C to +85 °C 

- Cortex[®] -M3 32-bit processor 

- Maximum TX output power: 

- ❐ +12 dBm for Bluetooth Classic 

- ❐ +9 dBm for Bluetooth Low Energy 

- RX Receive Sensitivity: 

- ❐ –93.5 dBm for Bluetooth Classic 

- ❐ –96.5 dBm for Bluetooth Low Energy 

CYBT-353027-02 provides all necessary components required to operate Bluetooth LE and/or BR/EDR communication standards. 

- Proven hardware design ready to use 

- Dual-mode operation eliminates the need for multiple modules 

- Cost optimized for applications without space constraints 

- Nonvolatile memory for self-sufficient operation and Over-the-air updates 

- Bluetooth SIG Listed with QDID and Declaration ID 

- Fully certified module eliminates the time needed for design, development and certification processes 

- WICED[] Studio provides an easy-to-use integrated design environment (IDE) to configure, develop, and program a Bluetooth application 

## **Note** 

1. The values in this section were calculated for a 90% efficient DC-DC at 3 V in HCI mode, and based on a Class I configuration bench-marked at Class II. Lower values are expected for a Class II configuration using an external LPO and corresponding PA configuration. 

**Cypress Semiconductor Corporation** • Document Number: 002-23132 Rev. *E 

198 Champion Court 

San Jose, CA 95134-1709 • 408-943-2600 Revised April 2, 2021 

• 

**CYBT-353027-02** 

## **More Information** 

Cypress provides a wealth of data at www.cypress.com to help you to select the right module for your design, and to help you to quickly and effectively integrate the module into your design. 

## **References** 

■ Overview: EZ-BLE/BT Module Portfolio, Module Roadmap 

- Development Kits: 

- ❐ CYBT-353027-EVAL, CYBT-353027-02 Evaluation Board 

- Test and Debug Tools: 

- ❐ CYSmart, Bluetooth[®] LE Test and Debug Tool (Windows) 

- ❐ CYSmart Mobile, Bluetooth[®] LE Test and Debug Tool (Android/iOS Mobile App) 

## ■ Knowledge Base Article 

- ❐ KBA97095 - EZ-BLE™ Module Placement 

- ❐ KBA213976 - FAQ for BLE and Regulatory Certifications with EZ-BLE modules 

- ❐ KBA210802 - Queries on BLE Qualification and Declaration Processes 

- ❐ KBA218122 - 3D Model Fils for EZ-BLE/EZ-BT™ Modules 

## **Development Environments** 

_Wireless Connectivity for Embedded Devices (WICED) Studio Software Development Kit (SDK)_ 

Cypress' WICED (Wireless Connectivity for Embedded Devices) is a full-featured platform with proven Software Development Kits (SDKs) and turnkey hardware solutions from partners to readily enable Wi-Fi and Bluetooth connectivity in system design. 

WICED Studio is the only SDK for the Internet of Things (IoT) that combines Wi-Fi and Bluetooth into a single integrated development environment. In addition to providing WICED APIs and an application framework designed to abstract complexity, WICED Studio also leverages many common industry standards. 

## **Technical Support** 

- Cypress Community: Whether you are a customer, partner, or a developer interested in the latest Cypress innovations, the Cypress Developer Community offers you a place to learn, share and engage with both Cypress experts, and other embedded engineers around the world. 

- Frequently Asked Questions (FAQs): Learn more about our Bluetooth ECO System. 

- Visit our support page and create a technical support case or contact a local sales representatives. If you are in the United States, you can talk to our technical support team by calling our toll-free number: +1-800-541-4736. Select option 2 at the prompt. 

Document Number: 002-23132 Rev. *E 

Page 2 of 47 

**CYBT-353027-02** 

## **Contents** 

**Overview ............................................................................4** Functional Block Diagram ...........................................4 Module Description ......................................................4 **Pad Connection Interface ................................................6 Recommended Host PCB Layout ...................................7 Module Connections ........................................................9 Connections and Optional External Components .......10** Power Connections (VDDIN) .....................................10 External Reset (XRES) ..............................................10 Multiple-Bonded GPIO Connections .........................10 Critical Components List ...........................................12 Antenna Design .........................................................12 **Bluetooth Baseband Core .............................................12** Bluetooth Features ....................................................12 Link Control Layer .....................................................13 Frequency Hopping Generator ..................................13 **Power Management Unit ................................................13** RF Power Management ............................................13 Host Controller Power Management .........................13 BBC Power Management ..........................................13 **Microcontroller Unit .......................................................14** NVRAM Configuration Data and Storage ..................14 External Reset (XRES) ..............................................14 **Integrated Radio Transceiver ........................................16** Transmitter Path ........................................................16 Receiver Path ............................................................16 Local Oscillator Generation .......................................16 Calibration .................................................................16 Internal LDO ..............................................................16 **Collaborative Coexistence .............................................17 Peripheral and Communication Interfaces ..................17** Cypress Serial Communications Interface ................17 HCI UART Interface ..................................................18 Peripheral UART Interface ........................................19 Serial Peripheral Interface .........................................19 PCM Interface ...........................................................19 

Clock Frequencies .....................................................19 ADC Port ...................................................................20 GPIO Port ..................................................................20 **Electrical Characteristics ...............................................21 Chipset RF Specifications .............................................24 Timing and AC Characteristics .....................................27** UART Timing .............................................................27 SPI Timing .................................................................28 BSC Interface Timing ................................................30 PCM Interface Timing ................................................31 I2S Interface Timing ..................................................35 **Environmental Specifications .......................................36** Environmental Compliance .......................................36 RF Certification ..........................................................36 Safety Certification ....................................................36 Environmental Conditions .........................................36 ESD and EMI Protection ...........................................36 **Regulatory Information ..................................................37** FCC ...........................................................................37 ISED ..........................................................................38 European Declaration of Conformity .........................39 MIC Japan .................................................................39 **Packaging ........................................................................40 Ordering Information ......................................................42 Acronyms ........................................................................43 Document Conventions .................................................45** Units of Measure .......................................................45 **Document History Page .................................................46 Sales, Solutions, and Legal Information ......................47** Worldwide Sales and Design Support .......................47 Products ....................................................................47 PSoC® Solutions ......................................................47 Cypress Developer Community .................................47 Technical Support .....................................................47 

Document Number: 002-23132 Rev. *E 

Page 3 of 47 

**CYBT-353027-02** 

## **Overview** 

## **Functional Block Diagram** 

Figure 1 illustrates the CYBT-353027-02 functional block diagram. 

## **Figure 1.  Functional Block Diagram** 

**==> picture [69 x 24] intentionally omitted <==**

**----- Start of picture text -----**<br>
Serial Flash 512KB<br>**----- End of picture text -----**<br>


## **Module Description** 

The CYBT-353027-02 module is a complete module designed to be soldered to the application’s main board. 

## _Module Dimensions and Drawing_ 

Cypress reserves the right to select components from various vendors to achieve the Bluetooth module functionality. Such selections will still guarantee that all mechanical specifications and module certifications are maintained. Designs should be held within the physical dimensions shown in the mechanical drawings in Figure 2 on page 5. All dimensions are in millimeters (mm). 

**Table 1.  Module Design Dimensions** 

|**Dimension Item**|**Dimension Item**|**Specification**|
|---|---|---|
|Module dimensions|Length (X)|9.00 ± 0.15 mm|
||Width (Y)|9.00 ± 0.15 mm|
|Antenna area dimensions|Length (X)|6.00 mm|
||Width (Y)|2.50 mm|
|PCB thickness|Height (H)|0.50 ± 0.10 mm|
|Shield height|Height (H)|1.25-mm typical|
|Maximum component height|Height (H)|1.25-mm typical|
|Total module thickness (bottom of module to highest component)|Height (H)|1.75-mm typical|



Document Number: 002-23132 Rev. *E 

Page 4 of 47 

**CYBT-353027-02** 

See Figure 2 for the mechanical reference drawing for CYBT-353027-02. 

**Figure 2.  Module Mechanical Drawing**[[2]] 

**==> picture [361 x 360] intentionally omitted <==**

**----- Start of picture text -----**<br>
Side View<br>Wi<br>Top View (Seen from Top)<br>|_|. + YP.L75<br>9.904015 _<br>CPCB) a; PADL:GNI<br>\~a— 6,00 PADOGPIO_4<br>PADSPL<br>ANTENNA PADAPY<br>AREA PADSIKRES<br>- 419 PADTSP12_CS_NPAD6:GPIO_5<br> a| PADSGPID_0<br>F 7 PADSGPIC_|<br>TXD<br>5 = PADIQUART.<br>PADLUCLK.<br>= == | s} PADIOUARTPADL3:\VDDINREQRXD<br>—0,82LITT dt Te PADLAGNDPADISIUART RTS<br>| PADIGGPIO. [3]<br>7 14 + PADI7UART CTS<br>+ PADISGPIO.<br>a 6<br>PADISGND<br>Bottom View (Seen from Bottom)<br>**----- End of picture text -----**<br>


## **Note** 

2. No metal should be located beneath or above the antenna area. Only bare PCB material should be located beneath the antenna area. For more information on recommended host PCB layout, see Recommended Host PCB Layout on page 7. 

Document Number: 002-23132 Rev. *E 

Page 5 of 47 

**CYBT-353027-02** 

## **Pad Connection Interface** 

As shown in the bottom view of Figure 2 on page 5, the CYBT-353027-02 connects to the host board via solder pads on the backside of the module. Table 2 and Figure 3 detail the solder pad length, width, and pitch dimensions of the CYBT-353027-02 module. 

**Table 2.  Connection Description** 

|**Name**|**Connections**|**Connection Type**|**Pad Length Dimension**|**Pad Width Dimension**|**Pad Pitch**|
|---|---|---|---|---|---|
|SP|24|Solder Pads|0.71 mm|0.51 mm|1.05 mm|



**Figure 3.  Solder Pad Dimensions (Seen from Bottom** 

To maximize RF performance, the host layout should follow these recommendations: 

1. Antenna Area Keepout: The host board directly below the antenna area of the Cypress module (see Figure 2 on page 5) must contain no ground or signal traces. This keepout area requirement applies to all layers of the host board. 

2. Module Placement: The ideal placement of the Cypress Bluetooth module is in a corner of the host board with the chip antenna located at the far corner. This placement minimizes the additional recommended keep out area stated in item 3 below. Refer to AN96841 for module placement best practices. 

3. Optional Keepout: To maximize RF performance, the area immediately around the Cypress Bluetooth module chip antenna may contain an additional keep out area, where there are no grounding or signal traces. The keepout area applies to all layers of the host board. The recommended dimensions of the host PCB keep out area are shown in Figure 4 (dimensions are in mm). 

## **Figure 4.  Recommended Host PCB Keep Out Area Around the CYBT-353027-02 Antenna** 

Document Number: 002-23132 Rev. *E 

Page 6 of 47 

**CYBT-353027-02** 

## **Recommended Host PCB Layout** 

Figure 5, Figure 6, Figure 7, and Table 3 provide details that can be used for the recommended host PCB layout pattern for the CYBT-353027-02. Dimensions are in millimeters unless otherwise noted. Pad length of 0.96 mm (0.48 mm from center of the pad on either side) shown in Figure 7 is the minimum recommended host pad length. The host PCB layout pattern can be completed using either Figure 5, Figure 6, or Figure 7. It is not necessary to use all figures to complete the host PCB layout pattern. 

**Figure 5.  CYBT-353027-02 Host Layout (Dimensioned)** 

**Figure 6.  CYBT-353027-02 Host Layout (Relative to Origin)** 

**Top View (Seen on Host PCB)** 

**Top View (Seen on Host PCB)** 

Document Number: 002-23132 Rev. *E 

Page 7 of 47 

**CYBT-353027-02** 

Table 3 provides the center location for each solder pad on the CYBT-353027-02. All dimensions are referenced to the center of the solder pad. Refer to Figure 7 for the location of each module solder pad. 

**Figure 7.  Solder Pad Reference Location** 

**Table 3.  Module Solder Pad Location** 

|**Solder Pad**<br>**(Center of Pad)**<br>~~ee ee~~|**Location (X,Y) from**<br>**Orign (mm)**<br>~~ee~~|**Dimension from**<br>**Orign (mils)**|
|---|---|---|
|1<br>~~ee ee~~<br>~~ee~~<br>~~ee~~|(0.23, 2.31)<br>~~ee~~<br>~~ee~~<br>|(9.06, 119.29)|
|2<br>~~ee ee~~<br>~~ee~~<br>~~ee ee~~<br>~~ee~~|(0.23, 3.36)<br>~~ee~~<br>~~ee~~<br>~~ee~~|(9.06, 132.28)<br>~~ee~~|
|3<br>~~ee~~<br>~~ee ee~~<br>~~ee~~|(0.23, 4.41)<br>~~ee~~<br>~~ee~~|(9.06, 201.97)<br>~~ee~~|
|4<br>~~ee ee~~<br>~~ee~~<br>~~ee~~|(0.23, 5.46)<br>~~ee~~<br>~~ee~~<br>~~ee~~|(9.06, 243.31)<br>~~ee~~|
|5<br>~~ee~~<br>~~ee~~<br>~~ee~~<br>~~ee ee~~|(0.23, 6.51)<br>~~ee~~<br>~~ee~~<br>~~ee~~|(9.06, 284.65)<br>~~ee~~<br>~~ee~~|
|6<br>~~ee~~<br>~~ee ee~~<br>~~ee~~|(0.23, 7.56)<br>~~ee~~<br>~~ee~~<br>~~ee~~|(9.06, 297.64)<br>~~ee~~|
|7<br>~~ee ee~~<br>~~ee~~<br>~~ee~~|(0.82,8.77)<br>~~ee~~<br>~~ee~~<br>~~ee~~|(32.28, 345.27)<br>~~ee~~|
|8<br>~~ee ~~<br>~~ee~~|(1.88,8.77)<br> ~~ee~~<br>~~ee~~|(74.02, 345.27)|
|9<br>~~ee~~|(2.93,8.77)<br>~~ee~~|(115.35, 345.27)|
|10|(3.98,8.77)|(156.69, 345.27)|
|11|(5.03,8.77)|(198.03, 345.27)|
|12|(6.08,8.77)|(239.37, 345.27)|
|13<br>~~ee~~|(7.13,8.77)<br>~~ee~~|(280.71, 345.27)|
|14<br>~~ee~~|(8.18,8.77)<br>~~ee~~|(322.05, 345.27)|
|15<br>~~ee~~<br>~~ee~~|(8.77,7.56)<br>~~ee~~<br>~~ee~~|(345.27, 297.64)|
|16<br>~~ee~~|(8.77,6.51)<br>~~ee~~|(345.27,256.30)|
|17<br>~~ee ~~|(8.77,5.46)<br> ~~ee~~|(345.27, 214.96)|
|18|(8.77,4.41)|(345.27, 173.62)|
|19|(8.77,3.36)|(345.27, 132.28)|



## **Top View (Seen on Host PCB)** 

Document Number: 002-23132 Rev. *E 

Page 8 of 47 

**CYBT-353027-02** 

## **Module Connections** 

Table 4 details the solder pad connection definitions and available functions for the pad connections for the CYBT-353027-02 module. Table 4 lists the solder pads on the CYBT-353027-02 module, the silicon device pin, and denotes what functions are available for each solder pad. 

**Table 4.  CYBT-353027-02 Solder Pad Connection Definitions** 

|**Pad**<br>~~ee~~<br>~~a~~|**Pad Name**<br>~~ee~~<br>~~ee~~|**Silicon Port Pin**<br>**Name(s)**<br>~~ee~~<br>~~es~~|**UART**<br>~~ee~~|**SPI**[3]<br>~~ee~~|**I2C**<br>~~ee~~|**ADC**|**CLK/XTAL**|**GPIO**|**Other**|
|---|---|---|---|---|---|---|---|---|---|
|1<br>~~ee~~<br>~~a~~<br>~~fof~~|GND<br>~~ee~~<br>~~ee~~<br>~~fof~~|GND<br>~~ee~~<br>~~es~~<br>~~fof~~|Ground<br>~~ee ee ee~~|||||||
|2<br>~~a~~<br>~~fof~~<br>~~ee~~|GPIO_4<br>~~ee~~<br>~~fof~~<br>~~ee~~|GPIO_4/P1/<br>I2S_CLK/<br>PCM_CLK<br>~~es~~<br>~~fof~~<br>~~ee~~|~~ee~~|SPI1_MISO/<br>P1 (master)<br>~~ee~~|~~es~~|IN28/P1||✓|PCM_CLK<br>I2S_CLK|
|3<br>~~fof~~<br>~~ee~~<br>~~fof~~|P11<br>~~fof~~<br>~~ee~~<br>~~fof~~|P11/I2S_WS/<br>PCM_SYNC<br>~~fof~~<br>~~ee~~<br>~~fofff~~|~~ee~~<br>~~ff~~|~~ee~~<br>~~ffff~~|~~es~~<br>~~ff~~|IN24||✓|PCM_Sync<br>I2S_WS|
|4<br>~~ee~~<br>~~fof~~|P3<br>~~ee~~<br>~~fof~~|P3/I2S_DI/<br>PCM_IN<br>~~ee ~~<br>~~fofff~~|~~ee ~~<br>~~ff~~|SPI1_CLK<br>(master)<br> ~~ee~~<br>~~ffff~~|SDA<br>~~es~~<br>~~ff~~|||✓|PCM_DI<br>I2S_DI|
|5<br>~~fof~~<br>~~ee~~|XRES<br>~~fof~~<br>~~ee~~|RST_N<br>~~fofff~~<br>~~ee es~~|External Reset (Active Low)<br>~~ffff~~<br>~~esee~~<br>~~es~~|||||||
|6<br>~~fof~~<br>~~ee~~<br>~~a~~|GPIO_5<br>~~fof~~<br>~~ee~~<br>~~ee es~~|BT_GPIO_5/<br>P8/P33<br>~~fof ff~~<br>~~ee es~~<br>~~es Me~~|PUART_RX/<br>P33<br>~~ff~~<br>~~es~~<br>~~Me~~|~~ff ff~~<br>~~ee~~<br>~~rs~~|~~ff~~<br>~~es~~<br>~~Is~~|IN27/P8<br>IN6/P33<br>~~I~~|ACK1/P33|✓||
|7<br>~~ee~~<br>~~a~~<br>~~a~~|SPI2_CS_N<br>~~ee~~<br>~~ee es~~|SPI2_CSN[4]<br>~~ee es~~<br>~~es Me~~<br>~~ee~~|~~es ~~<br>~~Me~~<br>~~ee~~|SPI2_CS_N<br> ~~ee~~<br>~~rs~~<br>~~ee~~|~~es~~<br>~~Is~~<br>~~ee~~|~~I~~<br>~~ee~~||||
|8<br>~~a~~<br>~~a~~<br>~~+p~~|GPIO_0<br>~~ee es~~<br>~~+p~~|BT_GPIO_0<br>~~es Me~~<br>~~ee~~<br>~~+p~~|~~Me~~<br>~~ee~~<br>~~ee~~|~~rs ~~<br>~~ee~~<br>~~ee~~|~~Is ~~<br>~~ee~~<br>~~ee~~|~~I~~<br>~~ee~~<br>~~ee~~|~~ee~~|✓<br>(Dev<br>Wake)||
|9<br>~~a~~<br>~~ee~~<br>~~+p~~|GPIO_1<br>~~ee~~<br>~~+p~~|BT_GPIO_1<br>~~ee ~~<br>~~ee~~<br>~~+p~~|~~ee ~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee ~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|✓<br>(Host<br>Wake)<br>~~ee~~|~~ee~~|
|10<br>~~+p~~|UART_TXD<br>~~+p~~|BT_UART_TXD<br>~~+p~~|HCI UART Transmit Data<br>~~eeeeeeee~~|||||||
|11<br>~~+p~~<br>~~a~~|CLK_REQ<br>~~+p~~<br>~~ee~~|BT_CLK_REQ<br>~~+p~~<br>~~es~~|Used for shared-clock applications<br>~~eeeeeeee~~|||||||
|12<br>~~+p~~<br>~~a~~<br>~~a~~|UART_RXD<br>~~+p~~<br>~~ee~~<br>~~ee~~|BT_UART_RXD<br>~~+p~~<br>~~es~~<br>~~es~~|HCI UART Receive Data<br>~~ee ee ee ee~~|||||||
|13<br>~~a~~<br>~~a~~<br>~~a~~|VDDIN<br>~~ee~~<br>~~ee~~<br>~~ee~~|VDDO<br>~~es~~<br>~~es~~<br>~~es~~|VDDIN (2.3 V ~ 3.6 V)|||||||
|14<br>~~a~~<br>~~a~~<br>~~a~~|GND<br>~~ee~~<br>~~ee~~<br>~~ee~~|GND<br>~~es~~<br>~~es~~<br>~~es~~|Ground|||||||
|15<br>~~a~~<br>~~a~~<br>~~ee~~|UART_RTS<br>~~ee~~<br>~~ee~~<br>~~ee~~|BT_UART_RTS_N<br>~~es~~<br>~~es~~<br>~~es~~|HCI UART Request To Send Output<br>~~es es~~<br>~~es~~|||||||
|16<br>~~a~~<br>~~ee~~<br>~~a~~|GPIO_3<br>~~ee~~<br>~~ee~~<br>~~ee~~|BT_GPIO_3/P0<br>~~es~~<br>~~es~~<br>~~es~~|PUART_TX/<br>P0<br>~~es es~~|SPI1_MOSI/<br>P0 (master)<br>~~es~~|~~es~~|IN29/P0||✓||
|17<br>~~ee~~<br>~~a~~<br>~~fof~~|UART_CTS<br>~~ee~~<br>~~ee~~<br>~~fof~~|BT_UART_CTS_N<br>~~es~~<br>~~es~~<br>~~fofft~~|HCI UART Clear To Send Input<br>~~es es~~<br>~~es~~<br>~~ft~~|||||||
|18<br>~~a~~<br>~~fof~~<br>~~a~~|GPIO_6<br>~~ee~~<br>~~fof~~<br>~~a~~|BT_GPIO_6/P9/<br>I2S_DO/<br>PCM_OUT<br>~~es~~<br>~~fofft~~<br>~~es~~|~~ft~~|~~ft~~|SCL|IN26/P9||✓|I2S_DO<br>PCM_Out|
|19<br>~~fof~~<br>~~a~~|GND<br>~~fof~~<br>~~a~~|GND<br>~~fof ft~~<br>~~es~~|Ground<br>~~ft~~|||||||



## **Notes** 

> 3. The CYBT-353027-02 contains a single SPI (SPI1) peripheral supporting master configuration. SPI2 is used for on-module serial memory interface. 

> 4. SPI2_CS_N is internally routed on the module to on-board serial flash memory. SPI2_CS_N is made available on module pad 7 to be used for Recover Mode operation only. 

Document Number: 002-23132 Rev. *E 

Page 9 of 47 

**CYBT-353027-02** 

## **Connections and Optional External Components** 

## **Power Connections (VDDIN)** 

The CYBT-353027-02 contains one power supply connection, VDDIN, which accepts a supply input range of 2.3 V to 3.6 V for CYBT-353027-02. Table 11 provides this specification. The maximum power supply ripple for this power connection is 100 mV, as shown in Table 11. 

It is not required to place any power supply decoupling or noise reduction circuitry on the host PCB. If desired, an external ferrite bead between the supply and the module connection can be included, but is not necessary. If used, the ferrite bead should be positioned as close as possible to the module pin connection and the recommended ferrite bead value is 330 , 100 MHz. 

## _Considerations and Optional Components for Brown Out (BO) Conditions_ 

Power supply design must be completed to ensure that the CYBT-353027-02 module does not encounter a Brown Out condition, which can lead to unexpected functionality, or module lock up. A Brown Out condition may be met if power supply provided to the module during power up or reset is in the following range: 

**==> picture [74 x 11] intentionally omitted <==**

## Refer to Table 12 for the VIL and VIH specifications. 

System design should ensure that the condition above is not encountered when power is removed from the system. In the event that this cannot be guaranteed (that is, battery installation, high-value power capacitors with slow discharge), it is recommended that an external voltage detection device be used to prevent the Brown Out voltage range from occurring during power removal. Refer to Figure 8 for the recommended circuit design when using an external voltage detection IC. 

## **Figure 8.  Reference Circuit Block Diagram for External Voltage Detection IC** 

In the event that the module does encounter a Brown Out condition, and is operating erratically or not responsive, power cycling the module will correct this issue and once reset, the module should operate correctly. Brown Out conditions can potentially cause issues that cannot be corrected, but in general, a power-on-reset operation will correct a Brown Out condition. 

## **External Reset (XRES)** 

The CYBT-353027-02 has an integrated power-on reset circuit, which completely resets all circuits to a known power-on state. This action can also be evoked by an external reset signal, forcing it into a power-on reset state. The XRES signal is an active-low signal, which is an input to the CYBT-353027-02 module (solder pad 5). The CYBT-353027-02 module does not require an external pull-up resistor on the XRES input 

During power-on operation, the XRES connection to the CYBT-353027-02 is required to be held low 50 ms after the VDD power supply input to the module is stable. This can be accomplished in the following ways: 

- The host device should connect a GPIO to the XRES of the Cypress CYBT-353027-02 module and pull XRES low until VDD is stable. XRES is recommended to be released 50 ms after VDDIN is stable. 

- If the XRES connection of the CYBT-353027-02 module is not used in the application, a 10-µF capacitor may be connected to the XRES solder pad of the CYBT-353027-02 in order to delay the XRES release. The capacitor value for this recommended implementation is approximate, and the exact value may differ depending on the VDDIN power supply ramp time of the system. The capacitor value should result in an XRES release timing of 50 ms after VDDIN stability. 

- The XRES release timing may be controlled by a external voltage detection IC. XRES should be released 50 ms after VDD is stable. 

Refer to Figure 11 on page 15 for XRES operating and timing requirements during power-on events. 

## **Multiple-Bonded GPIO Connections** 

The CYBT-353027-02 contains GPIOs, which are multiple-bonded at the silicon level. If any of these dual-bonded GPIOs are used, only the functionality and features for one of these port pins may be used. The desired port pin should be configured in the WICED Studio SDK. For details on the port pins that are multiple-bonded, refer to the GPIO Port section of this document. 

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**CYBT-353027-02** 

Figure 9 illustrates the CYBT-353027-02 schematic. 

**Figure 9.  CYBT-353027-02 Schematic Diagram** 

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**CYBT-353027-02** 

## **Critical Components List** 

Table 5 details the critical components used in the CYBT-353027-02 module. 

**Table 5.  Critical Component List** 

|**Component**|**Reference Designator**|**Description**|
|---|---|---|
|Silicon|U1|36-pin FBGA BT/Bluetooth LE Silicon Device - CYW2070X|
|Silicon|U2|8-pin TDF8N, 512K Serial Flash|
|Crystal|Y1|24.000 MHz, 12PF|



## **Antenna Design** 

Table 6 details trace antenna used in the CYBT-353027-02 module. For more information, see Table 6. 

**Table 6.  Chip Antenna Specifications** 

|**Item**|**Description**|
|---|---|
|FrequencyRange|2400–2500 MHz|
|Peak Gain|–1.0-dBi typical|
|Return Loss|10-dB minimum|



## **Bluetooth Baseband Core** 

The Bluetooth Baseband Core (BBC) implements all of the time-critical functions required for high-performance Bluetooth operation. The BBC manages the buffering, segmentation, and routing of data for all connections. It also buffers data that passes through it, handles data flow control, schedules SCO/ACL and TX/RX transactions, monitors Bluetooth slot usage, optimally segments and packages data into baseband packets, manages connection status indicators, and composes and decodes HCI packets. In addition to these functions, it independently handles HCI event types, and HCI command types. The following transmit and receive functions are also implemented in the BBC hardware to increase reliability and security of the TX/RX data before sending over the air: 

- Symbol timing recovery, data deframing, forward error correction (FEC), header error control (HEC), cyclic redundancy check (CRC), data decryption, and data dewhitening in the receiver. 

- Data framing, FEC generation, HEC generation, CRC generation, key generation, data encryption, and data whitening in the transmitter. 

## **Bluetooth Features** 

CYBT-353027-02 is qualified to the Bluetooth 5.0 specification. CYBT-353027-02 supports all Bluetooth 4.2 and legacy features, with the following benefits: 

- Dual-mode Bluetooth (BT Classic and Bluetooth LE) operation 

- Extended inquiry response (EIR): Shortens the time to retrieve the device name, specific profile, and operating mode. 

- Encryption pause resume (EPR): Enables the use of Bluetooth technology in a much more secure environment. 

- Sniff subrating (SSR): Optimizes power consumption for low duty cycle asymmetric data flow, which subsequently extends battery life. 

- Secure simple pairing (SSP): Reduces the number of steps for connecting two devices, with minimal or no user interaction required. 

- Link supervision time out (LSTO): Additional commands added to HCI and Link Management Protocol (LMP) for improved link timeout supervision. 

- Quality of service (QoS) enhancements: Changes to data traffic control, which results in better link performance. Audio, human interface device (HID), bulk traffic, SCO, and enhanced SCO (eSCO) are improved with the erroneous data (ED) and packet boundary flag (PBF) enhancements. 

- Secure connections (BR/EDR) 

- Fast advertising interval 

- Piconet clock adjust 

- Connectionless broadcast 

- LE privacy v1.1 

- Low duty cycle directed advertising 

- LE dual mode topology 

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**CYBT-353027-02** 

## **Link Control Layer** 

The link control layer is part of the Bluetooth link control functions that are implemented in dedicated logic in the link control unit (LCU). This layer consists of the command controller that takes commands from the software, and other controllers that are activated or configured by the command controller, to perform the link control tasks. Each task is performed in a different state in the LCU. 

## ■ States: 

❐ Standby 

❐ Connection 

- ❐ Page 

❐ Page Scan 

- ❐ Inquiry 

- ❐ Inquiry Scan 

- ❐ Sniff 

- ❐ Advertising 

- ❐ Scanning 

## **Frequency Hopping Generator** 

The frequency hopping sequence generator selects the correct hopping channel number based on the link controller state, Bluetooth clock, and device address. 

## **Power Management Unit** 

The Power Management Unit (PMU) provides power management features that can be invoked by software through power management registers or packet-handling in the baseband core. 

## **RF Power Management** 

The BBC generates power-down control signals for the transmit path, receive path, PLL, and power amplifier to the 2.4-GHz transceiver, which then processes the power-down functions accordingly. 

## **Host Controller Power Management** 

Power is automatically managed by the firmware based on input device activity. As a power-saving task, the firmware controls the disabling of the on-chip regulator when in deep sleep (HIDOFF) mode. 

## **BBC Power Management** 

There are several low-power operations for the BBC: 

■ Physical layer packet handling turns RF on and off dynamically within packet TX and RX. 

- Bluetooth-specified low-power connection mode. While in these low-power connection modes, the CYBT-353027-02 runs on the Low Power Oscillator and wakes up after a predefined time period. 

The CYBT-353027-02 automatically adjusts its power dissipation based on user activity. The following power modes are supported: 

## ■ Active mode 

## ■ Idle mode 

## ■ Sleep mode 

## ■ HIDOFF (Deep Sleep) mode 

The CYBT-353027-02 transitions to the next lower state after a programmable period of user inactivity. Busy mode is immediately entered when user activity resumes. 

In HIDOFF (Deep Sleep) mode, the CYBT-353027-02 baseband and core are powered off by disabling power to LDOOUT. The VDDO domain remains powered up and will turn the remainder of the chip on when it detects user events. This mode minimizes chip power consumption and is intended for long periods of inactivity. 

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**CYBT-353027-02** 

## **Microcontroller Unit** 

The microcontroller unit in CYBT-353027-02 runs software from the link control (LC) layer up to the host controller interface (HCI). The microcontroller is based on the Cortex-M3 32-bit RISC processor with embedded ICE-RT debug and JTAG interface units. The microcontroller also includes 848 KB of ROM memory for program storage and boot ROM, 352 KB of RAM for data scratch-pad, and patch RAM code. 

The internal boot ROM provides flexibility during power-on reset to enable the same device to be used in various configurations. At power-up, the lower layer protocol stack is executed from the internal ROM. 

External patches can be applied to the ROM-based firmware to provide flexibility for bug fixes and features additions. These patches can be downloaded using external NVRAM. The device can also support the integration of user applications and profiles using an external serial flash memory. 

## **NVRAM Configuration Data and Storage** 

NVRAM contains configuration information about the customer application, including the following: 

- Fractional-N information 

- BD_ADDR 

- UART baud rate 

- SDP service record 

- File system information used for code, code patches, or data. The CYBT-353027-02 uses SPI Serial Flash for NVRAM storage. 

## **External Reset (XRES)** 

The CYBT-353027-02 has an integrated power-on reset circuit that completely resets all circuits to a known power-on state. An external active low reset signal, XRES, can be used to put the CYBT-353027-02 in the reset state. The XRES pin has an internal pull-up resistor and, in most applications, it does not require anything to be connected to it. 

## **Figure 10.  External Reset Internal Timing** 

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**CYBT-353027-02** 

## _XRES Recommended External Components and Proper Operation_ 

During a power-on event, the XRES line of the CYBT-353027-02 is required to be held low 50 ms after the VDD power supply input to the module is stable. Refer to Figure 11 for the Power-On XRES timing operation. This power-on operation can be accomplished in the following ways: 

- A host device should connect a GPIO to the XRES of the Cypress CYBT-353027-02 module and pull XRES low until VDD is stable. XRES can be released after VDD is stable. 

- If the XRES connection of the CYBT-353027-02 module is not used in the application, a 10-µF capacitor may be connected to the XRES solder pad of the CYBT-353027-02. 

- The XRES release timing can also be controlled via an external voltage detection circuit. 

**Figure 11.  Power-On External Reset (XRES) Operation** 

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**CYBT-353027-02** 

## **Integrated Radio Transceiver** 

The CYBT-353027-02 has an integrated radio transceiver that has been optimized for use in 2.4-GHz Bluetooth wireless systems. It has been designed to provide low-power, low-cost, robust communications for applications operating in the globally available 2.4-GHz unlicensed ISM band. The CYBT-353027-02 is fully compliant with the Bluetooth Radio Specification and enhanced data rate (EDR) specification and meets or exceeds the requirements to provide the highest communication link quality of service. 

## **Transmitter Path** 

The CYBT-353027-02 a fully integrated zero-IF transmitter. The baseband transmit data is GFSK-modulated in the modem block and upconverted to the 2.4-GHz ISM band in the transmitter path. The transmitter path consists of signal filtering, I/Q upconversion, output power amplifier, and RF filtering. The transmitter path also incorporates /4-DQPSK for 2 Mbps and 8-DPSK for 3 Mbps to support EDR. The transmitter section is compatible with the Bluetooth LE specification. The transmitter PA bias can also be adjusted to provide Bluetooth class 1 or class 2 operation. 

## _Digital Modulator_ 

The digital modulator performs the data modulation and filtering required for the GFSK, 4-DQPSK, and 8-DPSK signal. The fully digital modulator minimizes any frequency drift or anomalies in the modulation characteristics of the transmitted signal and is much more stable than direct VCO modulation schemes. 

## _Power Amplifier_ 

The fully integrated PA supports Class 1 or Class 2 output using a highly linearized, temperature-compensated design. This provides greater flexibility in front-end matching and filtering. Due to the linear nature of the PA combined with some integrated filtering, external filtering is required to meet the Bluetooth and regulatory harmonic and spurious requirements. For integrated mobile handset applications in which Bluetooth is integrated next to the cellular radio, external filtering can be applied to achieve near thermal noise levels for spurious and radiated noise emissions. The transmitter features a sophisticated on-chip transmit signal strength indicator (TSSI) block to keep the absolute output power variation within a tight range across process, voltage, and temperature. 

## **Receiver Path** 

The receiver path uses a low-IF scheme to downconvert the received signal for demodulation in the digital demodulator and bit synchronizer. The receiver path provides a high degree of linearity, an extended dynamic range, and high-order on-chip channel filtering to ensure reliable operation in the noisy 2.4 GHz ISM band. The front-end topology, with built-in out-of-band attenuation, enables the CYBT-353027-02 to be used in most applications with minimal off-chip filtering. For integrated handset operation, in which the Bluetooth function is integrated close to the cellular transmitter, external filtering is required to eliminate the desensitization of the receiver by the cellular transmit signal. 

## _Digital Demodulator and Bit Synchronizer_ 

The digital demodulator and bit synchronizer take the low-IF received signal and perform an optimal frequency tracking and bit synchronization algorithm. 

## _Receiver Signal Strength Indicator_ 

The radio portion of the CYBT-353027-02 provides a receiver signal strength indicator (RSSI) to the baseband. This enables the controller to take part in a Bluetooth power-controlled link by providing a metric of its own receiver signal strength to determine whether the transmitter should increase or decrease its output power. 

## **Local Oscillator Generation** 

The local oscillator (LO) provides fast frequency hopping (1600 hops/second) across the 79 maximum available channels. The LO generation sub-block employs an architecture for high immunity to LO pulling during PA operation. The CYBT-353027-02 uses an internal loop filter. 

## **Calibration** 

The CYBT-353027-02 radio transceiver features an automated calibration scheme that is fully self-contained in the radio. No user interaction is required during normal operation or during manufacturing to provide optimal performance. Calibration tunes the performance of all the major blocks within the radio to within 2% of optimal conditions, including gain and phase characteristics of filters, matching between key components, and key gain blocks. This takes into account process variation and temperature variation. Calibration occurs transparently during normal operation during the settling time of the hops, and calibrates for temperature variations as the device cools and heats during normal operation in its environment. 

## **Internal LDO** 

The microcontroller in CYBT-353027-02 uses two LDOs – one for 1.2 V and the other for 2.5 V. The 1.2-V LDO provides power to the baseband and radio and the 2.5-V LDO powers the PA. 

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**CYBT-353027-02** 

## **Collaborative Coexistence** 

The CYBT-353027-02 provides extensions and collaborative coexistence to the standard Bluetooth AFH for direct communication with WLAN devices. Collaborative coexistence enables WLAN and Bluetooth to operate simultaneously in a single device. The device supports industry-standard coexistence signaling, including 802.15.2, and supports Cypress and third-party WLAN solutions. 

## **Peripheral and Communication Interfaces** 

## **Cypress Serial Communications Interface** 

The CYBT-353027-02 provides a 2-pin master BSC interface, which can be used to retrieve configuration information from an external EEPROM or to communicate with peripherals such as track-ball or touch-pad modules, and motion tracking ICs used in mouse devices. The BSC interface is compatible with I[2] C slave devices. The BSC does not support multimaster capability or flexible wait-state insertion by either master or slave devices. 

The following transfer clock rates are supported by the BSC: 

- 100 kHz 

- 400 kHz 

- 800 kHz (not a standard I[2] C-compatible speed.) 

- 1 MHz (Compatibility with high-speed I[2] C-compatible devices is not guaranteed.) 

- The following transfer types are supported by the BSC: 

- Read (Up to 127 bytes can be read) 

- Write (Up to 127 bytes can be written) 

- Read-then-Write (Up to 127 bytes can be read and up to 127 bytes can be written) 

- Write-then-Read (Up to127 bytes can be written and up to 127 bytes can be read) 

Hardware controls the transfers, requiring minimal firmware setup and supervision. 

The clock pad (I2C_SCL) and data pad 2 (I2C_SDA) are both open-drain I/O pins. Pull-up resistors, external to the CYBT-353027-02, are required on both the SCL and SDA pad for proper operation. 

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**CYBT-353027-02** 

## **HCI UART Interface** 

The UART physical interface is a standard, 2-wire interface (RX, TX, RTS, and CTS) with adjustable baud rates from 38400 bps to 6 Mbps. During initial boot, UART speeds may be limited to 750 kbps. The baud rate may be selected via a vendor-specific UART HCI command. The CYBT-353027-02 has a 1040-byte receive FIFO and a 1040-byte transmit FIFO to support enhanced data rates. The interface supports the Bluetooth UART HCI (H4) specification. The default baud rate for H4 is 115.2 kbaud. 

The UART clock default setting is 24 MHz, and can be configured to run as high as 48 MHz to support up to 6 Mbps. The baud rate of the CYBT-353027-02UART is controlled by two values. The first is a UART clock divisor (set in the DLBR register) that divides the UART clock by an integer multiple of 16. The second is a baud rate adjustment (set in the DHBR register) that is used to specify a number of UART clock cycles to stuff in the first or second half of each bit time. Up to eight UART cycles can be inserted into the first half of each bit time, and up to eight UART clock cycles can be inserted into the end of each bit time. 

Table 7 contains example values to generate common baud rates with a 24-MHz UART clock. 

**Table 7.  Common Baud Rate Examples, 24 MHz Clock** 

|**Baud Rate (bps)**|**Baud Rate Adjustment**<br>~~pO~~<br>~~ee~~<br>~~ee~~|**Baud Rate Adjustment**<br>~~pO~~<br>~~ee~~<br>~~ee~~|**Mode**|**Error (%)**|
|---|---|---|---|---|
||**High Nibble**<br>~~pO~~<br>~~ee~~|**Low Nibble**<br>~~pO~~<br>~~ee~~|||
|3M<br>~~GG~~|0xFF<br>~~ee~~<br>~~GG~~|0xF8<br>~~ee~~<br>~~GG~~|High rate<br>~~GG~~|0.00<br>~~GG~~|
|2M<br>~~GG~~|0XFF<br>~~GG~~|0XF4<br>~~GG~~|High rate<br>~~GG~~|0.00<br>~~GG~~|
|1M<br>~~GG~~<br>~~GG~~|0X44<br>~~GG~~<br>~~GG~~|0XFF<br>~~GG~~<br>~~GG~~|Normal<br>~~GG~~<br>~~GG~~|0.00<br>~~GG~~<br>~~GG~~|
|921600<br>~~GG~~|0x05<br>~~GG~~|0x05<br>~~GG~~|Normal<br>~~GG~~|0.16<br>~~GG~~|
|460800<br>~~GG~~|0x02<br>~~GG~~|0x02<br>~~GG~~|Normal<br>~~GG~~|0.16<br>~~GG~~|
|230400<br>~~GG~~<br>~~GG~~|0x04<br>~~GG~~<br>~~GG~~|0x04<br>~~GG~~<br>~~GG~~|Normal<br>~~GG~~<br>~~GG~~|0.16<br>~~GG~~<br>~~GG~~|
|115200<br>~~GG~~|0x00<br>~~GG~~|0x00<br>~~GG~~|Normal<br>~~GG~~|0.16<br>~~GG~~|
|57600<br>~~GG~~|0x00<br>~~GG~~|0x00<br>~~GG~~|Normal<br>~~GG~~|0.16<br>~~GG~~|
|38400<br>~~GG~~<br>~~GC~~|0x01<br>~~GG~~<br>~~GC~~|0x00<br>~~GG~~<br>~~GC~~|Normal<br>~~GG~~<br>~~GC~~|0.00<br>~~GG~~<br>~~GC~~|



Table 8 contains example values to generate common baud rates with a 48-MHz UART clock. 

**Table 8.  Common Baud Rate Examples, 48 MHz Clock** 

|**Baud Rate (bps)**<br>~~GG~~|**High Rate**<br>~~GG~~|**Low Rate**<br>~~GG~~|**Mode**<br>~~GG~~|**Error (%)**<br>~~GG~~|
|---|---|---|---|---|
|6M<br>~~GG~~<br>~~GG~~|0xFF<br>~~GG~~<br>~~GG~~|0xF8<br>~~GG~~<br>~~GG~~|High rate<br>~~GG~~<br>~~GG~~|0<br>~~GG~~<br>~~GG~~|
|4M<br>~~GG~~|0xFF<br>~~GG~~|0xF4<br>~~GG~~|High rate<br>~~GG~~|0<br>~~GG~~|
|3M<br>~~GG~~|0x0<br>~~GG~~|0xFF<br>~~GG~~|Normal<br>~~GG~~|0<br>~~GG~~|
|2M<br>~~GG~~<br>~~GG~~|0x44<br>~~GG~~<br>~~GG~~|0xFF<br>~~GG~~<br>~~GG~~|Normal<br>~~GG~~<br>~~GG~~|0<br>~~GG~~<br>~~GG~~|
|1.5M<br>~~GG~~|0x0<br>~~GG~~|0xFE<br>~~GG~~|Normal<br>~~GG~~|0<br>~~GG~~|
|1M<br>~~GG~~|0x0<br>~~GG~~|0xFD<br>~~GG~~|Normal<br>~~GG~~|0<br>~~GG~~|
|921600<br>~~GG~~<br>~~GG~~|0x22<br>~~GG~~<br>~~GG~~|0xFD<br>~~GG~~<br>~~GG~~|Normal<br>~~GG~~<br>~~GG~~|0.16<br>~~GG~~<br>~~GG~~|
|230400<br>~~GG~~<br>~~GG~~|0x0<br>~~GG~~<br>~~GG~~|0xF3<br>~~GG~~<br>~~GG~~|Normal<br>~~GG~~<br>~~GG~~|0.16<br>~~GG~~<br>~~GG~~|
|115200<br>~~GG~~|0x1<br>~~GG~~|0xE6<br>~~GG~~|Normal<br>~~GG~~|–0.08<br>~~GG~~|
|57600<br>~~GG~~<br>~~GG~~|0x1<br>~~GG~~<br>~~GG~~|0xCC<br>~~GG~~<br>~~GG~~|Normal<br>~~GG~~<br>~~GG~~|0.04<br>~~GG~~<br>~~GG~~|
|38400<br>~~GG~~<br>~~GC~~|0x11<br>~~GG~~<br>~~GC~~|0xB2<br>~~GG~~<br>~~GC~~|Normal<br>~~GG~~<br>~~GC~~|0<br>~~GG~~<br>~~GC~~|



Normally, the UART baud rate is set by a configuration record downloaded after reset. Support for changing the baud rate during normal HCI UART operation is included through a vendor-specific command that allows the host to adjust the contents of the baud rate registers. 

The CYBT-353027-02 UART operates correctly with the host UART as long as the combined baud rate error of the two devices is within ±2%. 

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**CYBT-353027-02** 

## **Peripheral UART Interface** 

The CYBT-353027-02 has a second UART that may be used to interface to other peripherals. This peripheral UART is accessed through the optional I/O ports, which can be configured individually and separately for each signal as shown in Table 9 The CYBT-353027-02 supports a two-wire UART interface. Flow Control is not supported on this module. 

## **Table 9.  CYBT-353027-02 Peripheral UART** 

|**Signal Name**|**PUART_TX**|**PUART_RX**|**PUART_CTS_N**|**PUART_RTS_N**|
|---|---|---|---|---|
|Configured port name|P0|P33|–|–|



## **Serial Peripheral Interface** 

The CYBT-353027-02 has two independent SPI interfaces. One is a master-only interface (SPI2) and is used for on-module SFLASH interface. The other (SPI1) can be used as a master interface. Each interface has a 64-byte transmit buffer and a 64-byte receive buffer. To support more flexibility for user applications, the CYBT-353027-02 has optional I/O ports that can be configured individually and separately for each functional pin. The CYBT-353027-02 acts as an SPI master device that supports 2.3 V or 3.3 V SPI slaves. The CYBT-353027-02 can also act as an SPI slave device that supports a 2.3 V or 3.3 V SPI master. 

SPI voltage depends on VDD; therefore, it defines the type of devices that can be supported. 

## **PCM Interface** 

The CYBT-353027-02 includes a PCM interface that shares pins with the I[2] S interface. The PCM Interface on the CYBT-353027-02 can connect to linear PCM codec devices in master or slave mode. In master mode, the CYBT-353027-02 generates the PCM_CLK and PCM_SYNC signals. In slave mode, these signals are provided by another master on the PCM interface and are inputs to the CYBT-353027-02. 

## _Slot Mapping_ 

The CYBT-353027-02 supports up to three simultaneous full-duplex SCO or eSCO channels through the PCM interface. These three channels are time-multiplexed on to the single PCM interface by using a time-slotting scheme where the 8 kHz or 16 kHz audio sample interval is divided into as many as 16 slots. The number of slots is dependent on the selected interface rate (128 kHz, 512 kHz, or 1024 kHz). The corresponding number of slots for these interface rate is 1, 2, 4, 8, and 16, respectively. Transmit and receive PCM data from an SCO channel is always mapped to the same slot. The PCM data output driver tristates its output on unused slots to allow other devices to share the same PCM interface signals. The data output driver tristates its output after the falling edge of the PCM clock during the last bit of the slot. 

## _Frame Synchronization_ 

The CYBT-353027-02 supports both short- and long-frame synchronization in both master and slave modes. In short-frame synchronization mode, the frame synchronization signal is an active-high pulse at the audio frame rate that is a single-bit period in width and is synchronized to the rising edge of the bit clock. The PCM slave looks for a high on the falling edge of the bit clock and expects the first bit of the first slot to start at the next rising edge of the clock. In long-frame synchronization mode, the frame synchronization signal is again an active-high pulse at the audio frame rate; however, the duration is three bit periods and the pulse starts coincident with the first bit of the first slot. 

## _Data Formatting_ 

The CYBT-353027-02 may be configured to generate and accept several different data formats. For conventional narrowband speech mode, the CYBT-353027-02 uses 13 of the 16 bits in each PCM frame. The location and order of these 13 bits can be configured to support various data formats on the PCM interface. The remaining three bits are ignored on the input and may be filled with 0s, 1s, a sign bit, or a programmed value on the output. The default format is 13-bit 2’s complement data, left justified, and clocked MSB first. 

## _Burst PCM Mode_ 

In this mode of operation, the PCM bus runs at a significantly higher rate of operation to allow the host to duty cycle its operation and save current. In this mode of operation, the PCM bus can operate at a rate of up to 24 MHz. This mode of operation is initiated with an HCI command from the host. 

## **Clock Frequencies** 

The CYBT-353027-02 has an integrated 24 MHz crystal on the module. There is no need to add an additional crystal oscillator. 

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**CYBT-353027-02** 

## **ADC Port** 

The ADC is a - ADC core designed for audio (12 bits) and DC (10 bits) measurement. There are five solder pad connections that can act as input channels on the CYBT-353027-02 module. 

The following CYBT-353027-02 module solder pads can be used as ADC inputs: 

- Pad 2: P1, ADC Input Channel 28 

- Pad 3: P11, ADC Input Channel 24 

- Pad 6: P8/P33, ADC Input Channels 27/6 respectively (Note: Only one ADC input on this solder pad can be active at a given time). 

- Pad 16: P0, ADC Input Channel 29 

- Pad 18: P9, ADC Input Channel 26 

## **GPIO Port** 

The CYBT-353027-02 has eight GPIOs besides two I[2] C pads. All GPIOs support programmable pull-ups and are capable of driving up to 8 mA at 3.3 V or 4 mA at 1.8 V. 

The following GPIOs are available on the module pads: 

- PAD 2 GPIO_4: GPIO_4/P1/I[2] S_CLK_PCM_CLK (triple bonded; only one of three is available) 

- PAD 3 P11: P11/I[2] S_WS_PCM_SYNC (Dual bonded; only one of two is available) 

- PAD 4 P3: P3/I[2] S_DI_PCM_IN (dual bonded; only one of two is available) 

- PAD 6 GPIO_5: GPIO_5/P8/P33 (triple bonded; only one of three is available) 

- PAD 8 GPIO_0 

- PAD 9 GPIO_1 

- PAD 16 GPIO_3: GPIO_3/P0/LPO_IN (triple bonded; only one of three is available) 

- PAD 18 GPIO_6: GPIO_6/P9/I[2] S_DO_PCM_OUT (triple bonded; only one of three is available) 

Pads 2, 3, 6, 16, and 18 can be programmed as ADC inputs. 

**Note:** SPI2_CS_N is internally routed on the module to on-board serial flash memory. SPI2_CS_N is made available on module pad 7 to be used for Recover Mode operation only. No other functionality should be used with this connection. 

Document Number: 002-23132 Rev. *E 

Page 20 of 47 

**CYBT-353027-02** 

## **Electrical Characteristics** 

Table 10 shows the maximum electrical rating for voltages referenced to VDD pin. 

## **Table 10.  Maximum Electrical Rating** 

|**Rating**|**Symbol**|**Value**|**Unit**|
|---|---|---|---|
|VDDIN|–|3.795|V|
|Voltage on input or output pin|–|VSS– 0.3 to VDD+ 0.3|V|
|Operating ambient temperature range|Topr|–30 to +85|°C|
|Storage temperature range|Tstg|–40 to +85|°C|



Table 11 shows the power supply characteristics for the range TJ = 0 to 125 °C. 

## **Table 11.  Power Supply** 

|**Parameter**|**Description**|**Minimum**[5]|**Typical**|**Maximum**[5]|**Unit**|
|---|---|---|---|---|---|
|VDDIN|Power Supply Input (CYBT-353027-02)|2.3|–|3.6|V|



Table 12 shows the specifications for the digital voltage levels. 

## **Table 12.  Digital Levels** 

|**Characteristics**|**Symbol**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|
|Input low voltage|VIL|–|–|0.8|V|
|Input high voltage|VIH|2.0|–|–|V|
|Output low voltage|VOL|–|–|0.4|V|
|Output high voltage|VOH|VDD– 0.4|–|–|V|
|Input capacitance (VDDMEMdomain)|CIN|–|–|0.4|pF|



## **Note** 

> 5. Overall performance degrades beyond minimum and maximum supply voltages.The voltage range specified is determined by the minimum and maximum operating voltage of the SPI Serial Flash included on the module. 

Document Number: 002-23132 Rev. *E 

Page 21 of 47 

**CYBT-353027-02** 

Table 13 shows the current consumption measurements **Table 13.  Bluetooth, Bluetooth LE, BR and EDR Current Consumption** 

|**Parameter**|**Description**|**Silicon or**<br>**Module**<br>**Parameter**|**Output**<br>**Power**<br>**Level/Class**|**Typ**|**Unit**|
|---|---|---|---|---|---|
|**Bluetooth Classic (BR, EDR)**<br>~~a~~||||||
|3DM5/3DH5<br>~~a~~<br>~~a~~<br>~~eS~~|HCI control mode<br>~~a~~<br>~~a~~|Silicon<br>~~a~~<br>~~a~~|Class 1<br>~~a~~<br>~~a~~|37.1<br>~~a~~<br>~~a~~|mA<br>~~a~~<br>~~a~~|
|DM1/DH1<br>~~eS~~|HCI control mode|Silicon|Class 1|32.2|mA|
|DM3/DH3<br>~~eS~~<br>~~a~~|HCI control mode|Silicon|Class 1|38.2|mA|
|DM5/DH5<br>~~a~~<br>~~a~~|HCI control mode|Silicon|Class 1|38.5|mA|
|RX1M_BR<br>~~a~~|Peak receive (1 Mbps) current level when receiving a<br>basic rate packet (radio only)|Silicon|Class 1|26.4|mA|
|TX1M_BR<br>~~a~~|Peak transmit (1 Mbps) current level when transmitting<br>a basic rate packet (radio only)|Silicon|10 dBm|60.3|mA|
|RX23M_EDR<br>~~a~~|Peak receive (EDR) current level when receiving a 2 or<br>3 Mbps rate packet (radio only)|Silicon|Class 1|26.4|mA|
|TX23M_EDR<br>~~a~~<br>~~eS~~|Peak transmit (EDR) current level when transmitting a<br>2 or 3 Mbps rate packet (radio only)|Silicon|8 dBm|52.5|mA|
|Deep Sleep<br>~~eS~~|Deep Sleep (HIDOFF) current|Module|All|2.69|µA|
|IDLE<br>~~eS~~<br>~~a~~|Module is idle, non-discoverable and non-connectable|Module|Class 1|0.11|mA|
|IScan<br>~~a~~<br>~~a~~<br>~~eS~~|Inquiry Scan (1.28 seconds)|Module|Class 1|0.65|mA|
|PScan<br>~~eS~~|Page scan (1.28 seconds)|Module|Class 1|0.65|mA|
|IScan+PScan<br>~~eS~~<br>~~a~~|Inquiry scan + Page Scan (1.28 seconds)|Module|Class 1|1.2|mA|
|Connected<br>~~a~~<br>~~a~~|Connected with no data transfer|Module|Class 1|2.6|mA|
|Connected + PScan<br>~~a~~|Connected with no data transfer + Page Scan (1.28<br>seconds)|Module|Class 1|3.3|mA|
|Connected + IScan+ PScan<br>~~a~~<br>~~eS~~|Connected with no data transfer + Inquiry Scan(1.28<br>seconds) + Page Scan (1.28 seconds)|Module|Class 1|3.6|mA|
|Connected + SNIFF<br>~~eS~~<br>~~a~~|Connected with no data transfer + SNIFF (500 ms)|Module|Class 1|0.95|mA|
|Connected + SNIFF+ IScan+<br>PScan<br>~~eS~~<br>~~a~~|Connected with no data transfer + SNIFF (500 ms) +<br>Inquiry Scan and Page Scan 1.28 seconds|Module|Class 1|1.9|mA|
|TX_BR<br>~~aa~~<br>~~es~~|Data transfer @ 115200 baud rate|Module|Class 1|22|mA|
|TX+SNIFF_BR<br>~~a~~<br>~~es~~|Data transfer @ 115200 baud rate + Sniff (500 ms)|Module|Class 1|5.5|mA|
|**Bluetooth Low Energy**<br>~~es~~<br>~~a~~||||||
|TXPeak<br>~~SS~~|Peak TX Current<br>~~SS~~|Module|–2.5 dBm<br>+6.5 dBm<br>+9.0 dBm|42<br>54<br>56|mA|
|RXPeak<br>~~SS~~|Peak RX current<br>~~SS~~|Module|–2.5 dBm<br>+6.5 dBm<br>+9.0 dBm|28<br>28<br>28|mA|
|Deep Sleep<br>~~SS~~|Deep Sleep (HIDOFF) current<br>~~SS~~|Module|All|2.69|µA|
|Connection_1s<br>~~SS~~|Connection; 1-second interval<br>~~SS~~|Module|–2.5 dBm<br>+6.5 dBm<br>+9.0 dBm|970<br>980<br>1000|µA|
|Connection_4s<br>~~SS~~|Connection; 4-second interval<br>~~SS~~|Module|–2.5 dBm<br>+6.5 dBm<br>+9.0 dBm|900<br>945<br>950|µA|



Document Number: 002-23132 Rev. *E 

Page 22 of 47 

**CYBT-353027-02** 

**Table 13.  Bluetooth, Bluetooth LE, BR and EDR Current Consumption** (continued) 

|**Parameter**|**Description**|**Silicon or**<br>**Module**<br>**Parameter**|**Output**<br>**Power**<br>**Level/Class**|**Typ**|**Unit**|
|---|---|---|---|---|---|
|Adv_640|Advertisement (low duty cycle); 640 ms|Module|–2.5 dBm<br>+6.5 dBm<br>+9.0 dBm|0.4<br>0.5<br>0.5|mA|
|Adv_30|Advertisement (high duty cycle); 30 ms|Module|–2.5 dBm<br>+6.5 dBm<br>+9.0 dBm|3.8<br>4.2<br>4.3|mA|
|Adv_1s|1-second non-connectable advertisement (Beacon)|Module|–2.5 dBm<br>+6.5 dBm<br>+9.0 dBm|315<br>350<br>350|µA|



**Table 14.  Bluetooth and Bluetooth LE Chipset Current Consumption, Class 2 (0 dBm)** 

|**Mode**|**Remarks**|**Typ.**|**Unit**|
|---|---|---|---|
|**3DH5/3DH5**|–|31.57|mA|
|**Bluetooth LE**||||
|Bluetooth LE ADV|Unconnectable 1.00 sec|174|A|
|Bluetooth LE Scan|No devices present. A 1.28 second interval with a scan window of 11.25 ms|368|A|
|**DMx/DHx**||||
|DM1/DH1|–|27.5|mA|
|DM3/DH3|–|31.34|mA|
|DM5/DH5|–|32.36|mA|



Document Number: 002-23132 Rev. *E 

Page 23 of 47 

**CYBT-353027-02** 

## **Chipset RF Specifications** 

All specifications in Table 15 are for industrial temperatures and are single-ended. Unused inputs are left open. 

**Table 15.  Chipset Receiver RF Specifications** 

|**Parameter**<br>~~Ge~~|**Conditions**<br>~~Ge~~|**Minimum**<br>~~Ge~~|**Typical**[6]<br>~~Ge~~|**Maximum**<br>~~Ge~~|**Unit**<br>~~Ge~~|
|---|---|---|---|---|---|
|**General**<br>~~Ge~~<br>~~Ee~~||||||
|Frequency range<br>~~Ge~~|–<br>~~Ge~~|2402<br>~~Ge~~|–<br>~~Ge~~|2480<br>~~Ge~~|MHz<br>~~Ge~~|
|RX sensitivity[7]|GFSK, 0.1% BER, 1 Mbps<br>~~eG~~|–<br>~~eG~~|–93.5<br>~~eG~~|–<br>~~eG~~|dBm<br>~~eG~~|
||LE GFSK, 0.1% BER, 1 Mbps<br>~~eG~~<br>~~eG~~|–<br>~~eG~~<br>~~eG~~|–96.5<br>~~eG~~<br>~~eG~~|–<br>~~eG~~<br>~~eG~~|dBm<br>~~eG~~<br>~~eG~~|
||/4-DQPSK, 0.01% BER, 2 Mbps<br>~~eG~~|–<br>~~eG~~|–95.5<br>~~eG~~|–<br>~~eG~~|dBm<br>~~eG~~|
||8-DPSK, 0.01% BER, 3 Mbps<br>~~eG~~|–<br>~~eG~~|–89.5<br>~~eG~~|–<br>~~eG~~|dBm<br>~~eG~~|
|Maximum input<br>~~a~~|GFSK, 1 Mbps<br>~~eG~~|–<br>~~eG~~|–<br>~~eG~~|–20<br>~~eG~~|dBm<br>~~eG~~|
|Maximum input<br>~~Ge~~|/4-DQPSK, 8-DPSK, 2/3 Mbps<br>~~Ge~~|–<br>~~Ge~~|–<br>~~Ge~~|–20<br>~~Ge~~|dBm<br>~~Ge~~|
|**Interference Performance**||||||
|C/I cochannel<br>~~a~~|GFSK, 0.1% BER|–|9.5|11|dB|
|C/I 1 MHz adjacent channel<br>~~Ge~~|GFSK, 0.1% BER<br>~~Ge~~|–<br>~~Ge~~|–5<br>~~Ge~~|0<br>~~Ge~~|dB<br>~~Ge~~|
|C/I 2 MHz adjacent channel<br>~~Ge~~|GFSK, 0.1% BER<br>~~Ge~~|–<br>~~Ge~~|–40<br>~~Ge~~|–30.0<br>~~Ge~~|dB<br>~~Ge~~|
|C/I><br> 3 MHz adjacent channel<br>~~Ge~~<br>~~Ge~~|GFSK, 0.1% BER<br>~~Ge~~<br>~~Ge~~|–<br>~~Ge~~<br>~~Ge~~|–49<br>~~Ge~~<br>~~Ge~~|–40.0<br>~~Ge~~<br>~~Ge~~|dB<br>~~Ge~~<br>~~Ge~~|
|C/I image channel<br>~~Ge~~|GFSK, 0.1% BER<br>~~Ge~~|–<br>~~Ge~~|–27<br>~~Ge~~|–9.0<br>~~Ge~~|dB<br>~~Ge~~|
|C/I 1 MHz adjacent to image channel<br>~~Ge~~|GFSK, 0.1% BER<br>~~Ge~~|–<br>~~Ge~~|–37<br>~~Ge~~|–20.0<br>~~Ge~~|dB<br>~~Ge~~|
|C/I cochannel<br>~~Ge~~<br>~~a~~|/4-DQPSK, 0.1% BER<br>~~Ge~~|–<br>~~Ge~~|11<br>~~Ge~~|13<br>~~Ge~~|dB<br>~~Ge~~|
|C/I 1 MHz adjacent channel<br>~~Ge~~|/4-DQPSK, 0.1% BER<br>~~Ge~~|–<br>~~Ge~~|–8<br>~~Ge~~|0<br>~~Ge~~|dB<br>~~Ge~~|
|C/I 2 MHz adjacent channel<br>~~Ge~~|/4-DQPSK, 0.1% BER<br>~~Ge~~|–<br>~~Ge~~|–40<br>~~Ge~~|–30.0<br>~~Ge~~|dB<br>~~Ge~~|
|C/I><br> 3 MHz adjacent channel<br>~~Ge~~<br>~~Ge~~|8-DPSK, 0.1% BER<br>~~Ge~~<br>~~Ge~~|–<br>~~Ge~~<br>~~Ge~~|–50<br>~~Ge~~<br>~~Ge~~|–40.0<br>~~Ge~~<br>~~Ge~~|dB<br>~~Ge~~<br>~~Ge~~|
|C/I image channel<br>~~Ge~~|/4-DQPSK, 0.1% BER<br>~~Ge~~|–<br>~~Ge~~|–27<br>~~Ge~~|–7.0<br>~~Ge~~|dB<br>~~Ge~~|
|C/I 1 MHz adjacent to image channel<br>~~Ge~~|/4-DQPSK, 0.1% BER<br>~~Ge~~|–<br>~~Ge~~|–40<br>~~Ge~~|–20.0<br>~~Ge~~|dB<br>~~Ge~~|
|C/I cochannel<br>~~Ge~~<br>~~a~~|8-DPSK, 0.1% BER<br>~~Ge~~|–<br>~~Ge~~|17<br>~~Ge~~|21<br>~~Ge~~|dB<br>~~Ge~~|
|C/I 1 MHz adjacent channel<br>~~Ge~~|8-DPSK, 0.1% BER<br>~~Ge~~|–<br>~~Ge~~|–5<br>~~Ge~~|5<br>~~Ge~~|dB<br>~~Ge~~|
|C/I 2 MHz adjacent channel<br>~~Ge~~|8-DPSK, 0.1% BER<br>~~Ge~~|–<br>~~Ge~~|–40<br>~~Ge~~|–25.0<br>~~Ge~~|dB<br>~~Ge~~|
|C/I><br>3 MHz adjacent channel<br>~~Ge~~<br>~~a~~|8-DPSK, 0.1% BER<br>~~Ge~~|–<br>~~Ge~~|–47<br>~~Ge~~|–33.0<br>~~Ge~~|dB<br>~~Ge~~|
|C/I Image channel<br>~~Ge~~|8-DPSK, 0.1% BER<br>~~Ge~~|–<br>~~Ge~~|–20<br>~~Ge~~|0<br>~~Ge~~|dB<br>~~Ge~~|
|C/I 1 MHz adjacent to image channel<br>~~Ga~~|8-DPSK, 0.1% BER<br>~~Ga~~|–<br>~~Ga~~|–35<br>~~Ga~~|–13.0<br>~~Ga~~|dB<br>~~Ga~~|



## **Notes** 

> 6. Typical operating conditions are 1.22-V operating voltage and 25 °C ambient temperature. 

> 7. The receiver sensitivity is measured at BER of 0.1% on the device interface. 

Document Number: 002-23132 Rev. *E 

Page 24 of 47 

**CYBT-353027-02** 

**Table 15.  Chipset Receiver RF Specifications** (continued) 

|**Parameter**<br>~~ts~~|**Conditions**<br>~~PD~~|**Minimum**<br>~~I~~|**Typical**[6]<br>~~(~~|**Maximum**|**Unit**|
|---|---|---|---|---|---|
|**Out-of-Band Blocking Performance (CW)**[8]<br>~~tsPD I (~~<br>~~ee~~||||||
|30 MHz–2000 MHz<br>~~es~~<br>~~rs~~|0.1% BER<br>~~es~~<br>~~nS~~|–<br>~~es~~<br>~~(~~|–10.0<br>~~es~~<br>~~(~~|–<br>~~es~~|dBm<br>~~es~~|
|2000–2399 MHz<br>~~es~~<br>~~rs~~<br>~~rs~~|0.1% BER<br>~~es~~<br>~~nS~~<br>~~ns~~|–<br>~~es~~<br>~~(~~|–27<br>~~es~~<br>~~(~~|–<br>~~es~~|dBm<br>~~es~~|
|2498–3000 MHz<br>~~rs~~<br>~~rs~~|0.1% BER<br>~~nS~~<br>~~ns~~|–<br>~~(~~|–27<br>~~(~~|–|dBm|
|3000 MHz–12.75 GHz<br>~~rs~~<br>~~ey~~<br>~~Cn~~|0.1% BER<br>~~ns~~<br>~~ey~~<br>|–<br>~~ey~~<br>|–10.0<br>~~ey~~<br>|–<br>~~ey~~<br>|dBm<br>~~ey~~<br>|
|**Out-of-Band Blocking Performance, Modulated Interferer**<br>~~ey~~<br>~~Cn~~<br>~~nt~~<br>~~(~~<br>~~(~~||||||
|776–764 MHz<br>~~Cnrs~~|CDMA<br>~~rs~~<br>~~nt~~|–<br>~~rs~~<br>~~(~~|–10[9]<br>~~rs~~<br>~~(~~|–<br>~~rs~~|dBm<br>~~rs~~|
|824–849 MHz<br>~~rs~~<br>~~rs~~|CDMA<br>~~nt~~<br>~~rs~~<br>~~nS~~|–<br>~~(~~<br>~~rs~~<br>~~(~~|–10[9]<br>~~(~~<br>~~rs~~<br>~~(~~|–<br>~~rs~~|dBm<br>~~rs~~|
|1850–1910 MHz<br>~~rs~~<br>~~rs~~<br>~~rs~~|CDMA<br>~~rs~~<br>~~nS~~<br>~~ns~~|–<br>~~rs~~<br>~~(~~|–23[9]<br>~~rs~~<br>~~(~~|–<br>~~rs~~|dBm<br>~~rs~~|
|824–849 MHz<br>~~rs~~<br>~~rs~~|EDGE/GSM<br>~~nS~~<br>~~ns~~|–<br>~~(~~|–10[9]<br>~~(~~|–|dBm|
|880–915 MHz<br>~~rs~~<br>~~rs~~<br>~~rs~~|EDGE/GSM<br>~~ns~~<br>~~rs~~<br>~~nS~~|–<br>~~rs~~<br>~~(~~|–10[9]<br>~~rs~~<br>~~(~~|–<br>~~rs~~|dBm<br>~~rs~~|
|1710–1785 MHz<br>~~rs~~<br>~~rs~~<br>~~rs~~|EDGE/GSM<br>~~rs~~<br>~~nS~~<br>~~ns~~|–<br>~~rs~~<br>~~(~~|–23[9]<br>~~rs~~<br>~~(~~|–<br>~~rs~~|dBm<br>~~rs~~|
|1850–1910 MHz<br>~~rs~~<br>~~rs~~|EDGE/GSM<br>~~nS~~<br>~~ns~~|–<br>~~(~~|–23[9]<br>~~(~~|–|dBm|
|1850–1910 MHz<br>~~rs~~<br>~~rs~~<br>~~ts~~|WCDMA<br>~~ns~~<br>~~rs~~<br>~~GD~~|–<br>~~rs~~<br>~~(~~|–23[9]<br>~~rs~~<br>~~(~~|–<br>~~rs~~|dBm<br>~~rs~~|
|1920–1980 MHz<br>~~rs~~<br>~~ts~~|WCDMA<br>~~rs~~<br>~~GD~~|–<br>~~rs~~<br>~~(~~|–23[9]<br>~~rs~~<br>~~(~~|–<br>~~rs~~|dBm<br>~~rs~~|
|**Intermodulation Performance**[10]<br>~~tsGD~~<br>~~(~~<br>~~ee~~<br>~~Pn~~||||||
|BT, Df = 5 MHz<br>~~rs~~|–<br>~~rs~~<br>~~Pn~~|–39.0<br>~~rs~~|–<br>~~rs~~|–<br>~~rs~~|dBm<br>~~rs~~|
|**Spurious Emissions**[11]<br>~~rs~~<br>~~Pn~~<br>~~Ce~~<br>~~rs ts~~<br>~~(~~||||||
|30 MHz to 1 GHz<br>~~rs ts~~|–<br>~~ts~~|–<br>~~(~~|–<br>~~(~~|–62|dBm|
|1 GHz to 12.75 GHz<br>~~rs ts~~<br>~~rs~~<br>~~rs nD~~|–<br>~~ts~~<br>~~rs~~<br>~~nD~~|–<br>~~(~~<br>~~rs~~<br>~~(~~|–<br>~~(~~<br>~~rs~~<br>~~(~~|–47<br>~~rs~~|dBm<br>~~rs~~|
|65 MHz to 108 MHz<br>~~rs~~<br>~~rs nD~~<br>~~rs~~|FM Rx<br>~~rs~~<br>~~nD~~<br>~~GD~~|–<br>~~rs~~<br>~~(~~|–147<br>~~rs~~<br>~~(~~|–<br>~~rs~~|dBm/Hz<br>~~rs~~|
|746 MHz to 764 MHz<br>~~rs nD~~<br>~~rs~~|CDMA<br>~~nD~~<br>~~GD~~|–<br>~~(~~|–147<br>~~(~~|–|dBm/Hz|
|851–894 MHz<br>~~rs~~<br>~~rs~~<br>~~rs nD~~|CDMA<br>~~GD~~<br>~~rs~~<br>~~nD~~|–<br>~~rs~~<br>~~(~~|–147<br>~~rs~~<br>~~(~~|–<br>~~rs~~|dBm/Hz<br>~~rs~~|
|925–960 MHz<br>~~rs~~<br>~~rs nD~~<br>~~rs~~|EDGE/GSM<br>~~rs~~<br>~~nD~~<br>~~GD~~|–<br>~~rs~~<br>~~(~~|–147<br>~~rs~~<br>~~(~~|–<br>~~rs~~|dBm/Hz<br>~~rs~~|
|1805–1880 MHz<br>~~rs nD~~<br>~~rs~~|EDGE/GSM<br>~~nD~~<br>~~GD~~|–<br>~~(~~|–147<br>~~(~~|–|dBm/Hz|
|1930–1990 MHz<br>~~rs~~<br>~~rs~~<br>~~ts~~|PCS<br>~~GD~~<br>~~rs~~<br>~~nS~~|–<br>~~rs~~<br>~~(OU~~|–147<br>~~rs~~<br>~~(~~|–<br>~~rs~~|dBm/Hz<br>~~rs~~|
|2110–2170 MHz<br>~~rs~~<br>~~ts~~|WCDMA<br>~~rs~~<br>~~nS~~|–<br>~~rs~~<br>~~(OU~~|–147<br>~~rs~~<br>~~(~~|–<br>~~rs~~|dBm/Hz<br>~~rs~~|



## **Notes** 

8. Meets this specification using front-end band pass filter. 

> 9. Numbers are referred to the pin output with an external BPF filter. 

> 10. f0 = -64 dBm Bluetooth-modulated signal, f1 = –39 dBm sine wave, f2 = –39 dBm Bluetooth-modulated signal, f0 = 2f1 – f2, and |f2 – f1| = n*1 MHz, where n is 3, 4, or 5. For the typical case, n = 4. 11. Includes baseband radiated emissions. 

Document Number: 002-23132 Rev. *E 

Page 25 of 47 

**CYBT-353027-02** 

**Table 16.  Chipset Transmitter RF Specifications** 

|**Parameter**<br>~~Ge~~|**Conditions**<br>~~Ge~~|**Minimum**<br>~~Ge~~|**Typical**<br>~~Ge~~|**Maximum**<br>~~Ge~~|**Unit**<br>~~Ge~~|
|---|---|---|---|---|---|
|**General**<br>~~Ge~~<br>~~Ee~~||||||
|Frequency range<br>~~Ge~~|–<br>~~Ge~~|2402<br>~~Ge~~|–<br>~~Ge~~|2480<br>~~Ge~~|MHz<br>~~Ge~~|
|Class1: GFSK Tx power[12]<br>~~Ge~~|–<br>~~Ge~~|–<br>~~Ge~~|12<br>~~Ge~~|–<br>~~Ge~~|dBm<br>~~Ge~~|
|Class1: EDR Tx power[13]<br>~~Ge~~<br>~~Se~~|–<br>~~Ge~~<br>~~Se~~|–<br>~~Ge~~<br>~~Se~~|9<br>~~Ge~~<br>~~Se~~|–<br>~~Ge~~<br>~~Se~~|dBm<br>~~Ge~~<br>~~Se~~|
|Class 2: GFSK Tx power<br>~~Ge~~|–<br>~~Ge~~|–<br>~~Ge~~|2<br>~~Ge~~|–<br>~~Ge~~|dBm<br>~~Ge~~|
|Power control step<br>~~Ge~~|–<br>~~Ge~~|2<br>~~Ge~~|4<br>~~Ge~~|8<br>~~Ge~~|dB<br>~~Ge~~|
|**Modulation Accuracy**<br>~~Ge~~<br>~~Re~~||||||
|/4-DQPSK Frequency Stability<br>~~Ge~~|–<br>~~Ge~~|–10<br>~~Ge~~|–<br>~~Ge~~|10<br>~~Ge~~|kHz<br>~~Ge~~|
|/4-DQPSK RMS DEVM<br>~~Ge~~|–<br>~~Ge~~|–<br>~~Ge~~|–<br>~~Ge~~|20<br>~~Ge~~|%<br>~~Ge~~|
|/4-QPSK Peak DEVM<br>~~Ge~~<br>~~Se~~|–<br>~~Ge~~<br>~~Se~~|–<br>~~Ge~~<br>~~Se~~|–<br>~~Ge~~<br>~~Se~~|35<br>~~Ge~~<br>~~Se~~|%<br>~~Ge~~<br>~~Se~~|
|/4-DQPSK 99% DEVM<br>~~Ge~~|–<br>~~Ge~~|–<br>~~Ge~~|–<br>~~Ge~~|30<br>~~Ge~~|%<br>~~Ge~~|
|8-DPSK frequency stability<br>~~Ge~~|–<br>~~Ge~~|–10<br>~~Ge~~|–<br>~~Ge~~|10<br>~~Ge~~|kHz<br>~~Ge~~|
|8-DPSK RMS DEVM<br>~~Ge~~<br>~~Se~~|–<br>~~Ge~~<br>~~Se~~|–<br>~~Ge~~<br>~~Se~~|–<br>~~Ge~~<br>~~Se~~|13<br>~~Ge~~<br>~~Se~~|%<br>~~Ge~~<br>~~Se~~|
|8-DPSK Peak DEVM<br>~~Ge~~|–<br>~~Ge~~|–<br>~~Ge~~|–<br>~~Ge~~|25<br>~~Ge~~|%<br>~~Ge~~|
|8-DPSK 99% DEVM<br>~~Ge~~|–<br>~~Ge~~|–<br>~~Ge~~|–<br>~~Ge~~|20<br>~~Ge~~|%<br>~~Ge~~|
|**In-Band Spurious Emissions**<br>~~Ge~~<br>~~Re~~||||||
|1.0 MHz < |M – N| < 1.5 MHz<br>~~Ge~~|–<br>~~Ge~~|–<br>~~Ge~~|–<br>~~Ge~~|–26<br>~~Ge~~|dBc<br>~~Ge~~|
|1.5 MHz < |M – N| < 2.5 MHz<br>~~Ge~~|–<br>~~Ge~~|–<br>~~Ge~~|–<br>~~Ge~~|–20<br>~~Ge~~|dBm<br>~~Ge~~|
||M – N|><br>2.5 MHz<br>~~Ge~~<br>~~De~~|–<br>~~Ge~~<br>~~De~~|–<br>~~Ge~~<br>~~De~~|–<br>~~Ge~~<br>~~De~~|–40<br>~~Ge~~<br>~~De~~|dBm<br>~~Ge~~<br>~~De~~|
|**Out-of-Band Spurious Emissions**<br>~~Pe~~||||||
|30 MHz to 1 GHz<br>~~a~~|–|–|–|–36.0[14]|dBm|
|1 GHz to 12.75 GHz<br>~~a~~<br>~~Se~~|–<br>~~Se~~|–<br>~~Se~~|–<br>~~Se~~|–30.0[14, 15]<br>~~Se~~|dBm<br>~~Se~~|
|1.8 GHz to 1.9 GHz<br>~~Ge~~|–<br>~~Ge~~|–<br>~~Ge~~|–<br>~~Ge~~|–47.0<br>~~Ge~~|dBm<br>~~Ge~~|
|5.15 GHz to 5.3 GHz<br>~~Ge~~|–<br>~~Ge~~|–<br>~~Ge~~|–<br>~~Ge~~|–47.0<br>~~Ge~~|dBm<br>~~Ge~~|



**Table 17.  Chipset Bluetooth LE RF Specifications** 

|**Parameter**|**Conditions**|**Minimum**|**Typical**|**Maximum**|**Unit**|
|---|---|---|---|---|---|
|Frequency range|N/A|2402|–|2480|MHz|
|Rx sense[16]|GFSK, 0.1% BER, 1 Mbps|–|–96.5|–|dBm|
|Tx power[17]|N/A|–|9|–|dBm|
|Mod Char: Delta F1 average|N/A|225|255|275|kHz|
|Mod Char: Delta F2 max[18]|N/A|99.9|–|–|%|
|Mod Char: Ratio|N/A|0.8|0.95|–|%|



## **Notes** 

12. TBD dBm output for GFSK measured with PAVDD = 2.5 V. 

13. TBD dBm output for EDR measured with PAVDD = 2.5 V. 

14. Maximum value is the value required for Bluetooth qualification. 

15. Meets this spec using a front-end band-pass filter. 

> 16. Dirty Tx is Off. 

17. The Bluetooth LE Tx power can be increased to compensate for front-end losses such as BPF, diplexer, switch, etc. The output is capped at 12 dBm out. The Bluetooth LE Tx power at the antenna port cannot exceed the 10 dBm EIRP specification limit. 

18. At least 99.9% of all delta F2 max frequency values recorded over 10 packets must be greater than 185 kHz. 

Document Number: 002-23132 Rev. *E 

Page 26 of 47 

**CYBT-353027-02** 

## **Timing and AC Characteristics** 

In this section, use the numbers listed in the **Reference** column of each table to interpret the following timing diagrams. 

## **UART Timing** 

**Table 18.  UART Timing Specifications** 

|**Reference**|**Characteristics**|**Min**|**Max**|**Unit**|
|---|---|---|---|---|
|1|Delay time, UART_CTS_N low to UART_TXD valid|–|24|Baud out cycles|
|2|Setup time, UART_CTS_N high before midpoint of stop bit|–|10|ns|
|3|Delay time, midpoint of stop bit to UART_RTS_N high|–|2|Baud out cycles|



**Figure 12.  UART Timing** 

Document Number: 002-23132 Rev. *E 

Page 27 of 47 

**CYBT-353027-02** 

## **SPI Timing** 

The SPI interface supports clock speeds up to 12 MHz. 

Table 19 and Figure 13 show the timing requirements when operating in SPI Mode 0 and 2, and SPI Mode 1 and 3, respectively. 

## **Table 19.  SPI Mode 0 and 2** 

|**Reference**|**Characteristics**|**Minimum**|**Maximum**|**Unit**|
|---|---|---|---|---|
|1|Time from slave assert SPI_INT to master assert SPI_CSN (DirectRead)|0||ns|
|2|Time from master assert SPI_CSN to slave assert SPI_INT (DirectWrite)|0||ns|
|3|Time from master assert SPI_CSN to first clock edge|20||ns|
|4|Setup time for MOSI data lines|8|½ ×SCK|ns|
|5|Hold time for MOSI data lines|8|½ ×SCK|ns|
|6|Time from last sample on MOSI/MISO to slave deassert SPI_INT|0|100|ns|
|7|Time from slave deassert SPI_INT to master deassert SPI_CSN|0||ns|
|8|Idle time between subsequent SPI transactions|1 × SCK||ns|



**Figure 13.  SPI Timing – Mode 0 and 2** 

Document Number: 002-23132 Rev. *E 

Page 28 of 47 

**CYBT-353027-02** 

Table 20 and Figure 14 show the timing requirements when operating in SPI Mode 1 and 3. 

**Table 20.  SPI Mode 1 and 3** 

|**Reference**|**Characteristics**|**Minimum**|**Maximum**|**Unit**|
|---|---|---|---|---|
|1|Time from slave assert SPI_INT to master assert SPI_CSN (DirectRead)|0||ns|
|2|Time from master assert SPI_CSN to slave assert SPI_INT (DirectWrite)|0||ns|
|3|Time from master assert SPI_CSN to first clock edge|20||ns|
|4|Setup time for MOSI data lines|8|½ ×SCK|ns|
|5|Hold time for MOSI data lines|8|½ ×SCK|ns|
|6|Time from last sample on MOSI/MISO to slave deassert SPI_INT|0|100|ns|
|7|Time from slave deassert SPI_INT to master deassert SPI_CSN|0||ns|
|8|Idle time between subsequent SPI transactions|1 × SCK||ns|



**Figure 14.  SPI Timing – Mode 1 and 3** 

Document Number: 002-23132 Rev. *E 

Page 29 of 47 

**CYBT-353027-02** 

## **BSC Interface Timing** 

**Table 21.  BSC Interface Timing Specifications** 

|**Reference**<br>~~en~~|**Characteristics**<br>~~en~~|**Min**<br>~~en~~|**Max**<br>~~en~~|**Unit**<br>~~en~~|
|---|---|---|---|---|
|1|Clock frequency|–|100<br>~~|~~|kHz|
||||400<br>~~|~~<br>~~|~~||
||||800<br>~~|~~||
||||1000<br>~~|~~<br>~~|~~||
|2<br>~~en~~<br>~~es~~|START condition setup time<br>~~en~~<br>|650<br>~~en~~<br>|–<br>~~en~~<br>|ns<br>~~en~~<br>|
|3<br>~~en~~<br>~~es~~|START condition hold time<br>~~en~~<br>|280<br>~~en~~<br>|–<br>~~en~~<br>|ns<br>~~en~~<br>|
|4<br>~~esen~~<br>~~es~~|Clock low time<br>~~en~~<br>|650<br>~~en~~<br>|–<br>~~en~~<br>|ns<br>~~en~~<br>|
|5<br>~~en~~<br>~~es~~|Clock high time<br>~~en~~<br>|280<br>~~en~~<br>|–<br>~~en~~<br>|ns<br>~~en~~<br>|
|6<br>~~esen~~<br>~~es~~|Data input hold time[19]<br>~~en~~<br>|0<br>~~en~~<br>|–<br>~~en~~<br>|ns<br>~~en~~<br>|
|7<br>~~en~~<br>~~es~~|Data input setup time<br>~~en~~<br>|100<br>~~en~~<br>|–<br>~~en~~<br>|ns<br>~~en~~<br>|
|8<br>~~esen~~<br>~~es~~|STOP condition setup time<br>~~en~~<br>|280<br>~~en~~<br>|–<br>~~en~~<br>|ns<br>~~en~~<br>|
|9<br>~~en~~<br>~~es~~|Output valid from clock<br>~~en~~<br>|–<br>~~en~~<br>|400<br>~~en~~<br>|ns<br>~~en~~<br>|
|10<br>~~esen~~|Bus free time[20]<br>~~en~~|650<br>~~en~~|–<br>~~en~~|ns<br>~~en~~|



## **Figure 15.  BSC Interface Timing Diagram** 

## **Notes** 

19. As a transmitter, 125 ns of delay is provided to bridge the undefined region of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 20. Time that the cbus must be free before a new transaction can start. 

Document Number: 002-23132 Rev. *E 

Page 30 of 47 

**CYBT-353027-02** 

## **PCM Interface Timing** 

_Short Frame Sync, Master Mode_ 

## **Figure 16.  PCM Timing Diagram (Short Frame Sync, Master Mode)** 

**Table 22.  PCM Interface Timing Specifications (Short Frame Sync, Master Mode)** 

|**Reference**<br>~~re~~<br>~~es~~|**Characteristics**<br>~~ee~~<br>~~rf~~|**Minimum**<br>~~ee~~<br>~~rf~~|**Typical**<br>~~ee~~<br>~~rf~~|**Maximum**<br>~~ee~~<br>~~rf~~|**Unit**<br>~~ee~~<br>~~rf~~|
|---|---|---|---|---|---|
|1<br>~~re~~<br>~~es~~<br>~~ee~~|PCM bit clock frequency<br>~~ee~~<br>~~rf~~|–<br>~~ee~~<br>~~rf~~|–<br>~~ee~~<br>~~rf~~|20.0<br>~~ee~~<br>~~rf~~|MHz<br>~~ee~~<br>~~rf~~|
|2<br>~~es~~<br>~~ee~~<br>~~rs~~|PCM bit clock LOW<br>~~rf~~<br>~~ee~~|20.0<br>~~rf~~|–<br>~~rf~~|–<br>~~rf~~|ns<br>~~rf~~|
|3<br>~~ee~~<br>~~rs~~<br>~~ee~~|PCM bit clock HIGH<br>~~ee~~|20.0|–|–|ns|
|4<br>~~rs ~~<br>~~ee~~<br>~~rs~~|PCM_SYNC delay<br> ~~ee~~<br>~~ee~~|0|–|5.7|ns|
|5<br>~~ee~~<br>~~rs~~<br>~~ee~~|PCM_OUT delay<br>~~ee~~|–0.4|–|5.6|ns|
|6<br>~~rs ~~<br>~~ee~~|PCM_IN setup<br> ~~ee~~|16.9|–|–|ns|
|7<br>~~ee~~|PCM_IN hold|25.0|–|–|ns|
|8|Delay from rising edge of PCM_BCLK during last bit<br>period to PCM_OUT becoming high impedance|–0.4|–|5.6|ns|



Document Number: 002-23132 Rev. *E 

Page 31 of 47 

**CYBT-353027-02** 

_Short Frame Sync, Slave Mode_ 

## **Figure 17.  PCM Timing Diagram (Short Frame Sync, Slave Mode)** 

**Table 23.  PCM Interface Timing Specifications (Short Frame Sync, Slave Mode)** 

|**Reference**<br>~~ee~~<br>~~es~~<br>~~ee~~|**Characteristics**<br>~~es~~<br>~~fe~~|**Minimum**<br>~~es~~<br>~~fe~~|**Typical**<br>~~es~~<br>~~fe~~<br>~~G~~|**Maximum**<br>~~es~~<br>~~fe~~|**Unit**<br>~~es~~<br>~~fe~~|
|---|---|---|---|---|---|
|1<br>~~ee~~<br>~~es~~<br>~~ee~~|PCM bit clock frequency<br>~~es~~<br>~~fe~~|–<br>~~es~~<br>~~fe~~|–<br>~~es~~<br>~~fe~~<br>~~G~~|TBD<br>~~es~~<br>~~fe~~|MHz<br>~~es~~<br>~~fe~~|
|2<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~ee~~|PCM bit clock LOW<br>~~fe~~<br>~~sf~~|TBD<br>~~fe~~<br>~~sf~~|–<br>~~fe~~<br>~~G~~<br>~~sf~~<br>~~G~~|–<br>~~fe~~<br>~~sf~~|ns<br>~~fe~~<br>~~sf~~|
|3<br>~~ee~~<br>~~es~~<br>~~ee~~|PCM bit clock HIGH<br>~~sf~~|TBD<br>~~sf~~|–<br>~~G~~<br>~~sf~~<br>~~G~~|–<br>~~sf~~|ns<br>~~sf~~|
|4<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~ee~~|PCM_SYNC setup<br>~~sf~~<br>~~sf~~|TBD<br>~~sf~~<br>~~sf~~|–<br>~~sf~~<br>~~G~~<br>~~sf~~<br>~~G~~|–<br>~~sf~~<br>~~sf~~|ns<br>~~sf~~<br>~~sf~~|
|5<br>~~ee~~<br>~~es~~<br>~~ee~~|PCM_SYNC hold<br>~~sf~~|TBD<br>~~sf~~|–<br>~~G~~<br>~~sf~~<br>~~G~~|–<br>~~sf~~|ns<br>~~sf~~|
|6<br>~~es~~<br>~~ee~~<br>~~es~~<br>~~ee~~|PCM_OUT delay<br>~~sf~~<br>~~sf~~|TBD<br>~~sf~~<br>~~sf~~|–<br>~~sf~~<br>~~G~~<br>~~sf~~<br>~~G~~|TBD<br>~~sf~~<br>~~sf~~|ns<br>~~sf~~<br>~~sf~~|
|7<br>~~ee~~<br>~~es~~<br>~~ee~~|PCM_IN setup<br>~~sf~~|TBD<br>~~sf~~|–<br>~~G~~<br>~~sf~~<br>~~G~~|–<br>~~sf~~|ns<br>~~sf~~|
|8<br>~~es~~<br>~~ee~~|PCM_IN hold<br>~~sf~~|TBD<br>~~sf~~|–<br>~~sf~~<br>~~G~~|–<br>~~sf~~|ns<br>~~sf~~|
|9<br>~~ee~~|Delay from rising edge of PCM_BCLK during last bit<br>period to PCM_OUT becoming high impedance|TBD|–<br>~~G~~|TBD|ns|



Document Number: 002-23132 Rev. *E 

Page 32 of 47 

**CYBT-353027-02** 

_Long Frame Sync, Master Mode_ 

## **Figure 18.  PCM Timing Diagram (Long Frame Sync, Master Mode)** 

**Table 24.  PCM Interface Timing Specifications (Long Frame Sync, Master Mode)** 

|**Reference**<br>~~a~~<br>~~BP~~|**Characteristics**|**Minimum**|**Typical**|**Maximum**|**Unit**|
|---|---|---|---|---|---|
|1<br>~~BP~~<br>~~BP~~|PCM bit clock frequency<br>|–<br>|–<br>|TBD<br>|MHz<br>|
|2<br>~~BP~~<br>~~BP~~|PCM bit clock LOW<br>|TBD<br>|–<br>|–<br>|ns<br>|
|3<br>~~BPPf~~<br>~~BP~~|PCM bit clock HIGH<br>~~Pf~~<br>|TBD<br>~~Pf~~<br>|–<br>~~Pf~~<br>|–<br>~~Pf~~<br>|ns<br>~~Pf~~<br>|
|4<br>~~BP~~|PCM_SYNC delay<br>|TBD<br>|–<br>|TBD<br>|ns<br>|
|5<br>~~BPPf~~<br>~~BP~~|PCM_OUT delay<br>~~Pf~~<br>|TBD<br>~~Pf~~<br>|–<br>~~Pf~~<br>|TBD<br>~~Pf~~<br>|ns<br>~~Pf~~<br>|
|6<br>~~BP~~|PCM_IN setup<br>|TBD<br>|–<br>|–<br>|ns<br>|
|7<br>~~BPPf~~|PCM_IN hold<br>~~Pf~~|TBD<br>~~Pf~~|–<br>~~Pf~~|–<br>~~Pf~~|ns<br>~~Pf~~|
|8|Delay from rising edge of PCM_BCLK during last bit<br>period to PCM_OUT becoming high impedance|TBD|–|TBD|ns|



Document Number: 002-23132 Rev. *E 

Page 33 of 47 

**CYBT-353027-02** 

_Long Frame Sync, Slave Mode_ 

## **Figure 19.  PCM Timing Diagram (Long Frame Sync, Slave Mode)** 

**Table 25.  PCM Interface Timing Specifications (Long Frame Sync, Slave Mode)** 

|**Reference**<br>~~ee~~<br>~~re~~|**Characteristics**<br>~~a~~|**Minimum**|**Typical**|**Maximum**|**Unit**|
|---|---|---|---|---|---|
|1<br>~~ee~~<br>~~re~~|PCM bit clock frequency<br>~~a~~|–|–|TBD|MHz|
|2<br>~~re~~<br>~~a~~|PCM bit clock LOW|TBD|–|–|ns|
|3<br>~~a~~<br>~~a~~<br>~~ee~~|PCM bit clock HIGH<br>~~a~~|TBD<br>~~a~~|–<br>~~a~~|–<br>~~a~~|ns<br>~~a~~|
|4<br><br>~~ee~~|PCM_SYNC setup<br>~~a~~|TBD<br>~~a~~|–<br>~~a~~|–<br>~~a~~|ns<br>~~a~~|
|5<br><br>~~ee~~<br>~~a~~|PCM_SYNC hold<br>~~a~~|TBD<br>~~a~~|–<br>~~a~~|–<br>~~a~~|ns<br>~~a~~|
|6<br>~~a~~<br>~~a~~<br>~~ee~~|PCM_OUT delay<br>~~a~~|TBD<br>~~a~~|–<br>~~a~~|TBD<br>~~a~~|ns<br>~~a~~|
|7<br><br>~~ee~~|PCM_IN setup<br>~~a~~|TBD<br>~~a~~|–<br>~~a~~|–<br>~~a~~|ns<br>~~a~~|
|8<br><br>~~ee~~<br>~~a~~|PCM_IN hold<br>~~a~~|TBD<br>~~a~~|–<br>~~a~~|–<br>~~a~~|ns<br>~~a~~|
|9<br>~~a~~|Delay from rising edge of PCM_BCLK during last bit<br>period to PCM_OUT becoming high impedance|TBD|–|TBD|ns|



Document Number: 002-23132 Rev. *E 

Page 34 of 47 

**CYBT-353027-02** 

## **I[2] S Interface Timing** 

The I[2] S interface supports both master and slave modes. The I[2] S signals are: 

■ I[2] S clock: I[2] S SCK 

■ I[2] S Word Select: I[2] S WS 

■ I[2] S Data Out: I[2] S SDO 

■ I[2] S Data In: I[2] S SDI 

I[2] S SCK and I[2] S WS become outputs in master mode and inputs in slave mode, while I[2] S SDO always stays as an output. The channel word length is 16 bits and the data is justified so that the MSB of the left-channel data is aligned with the MSB of the I[2] S bus, per the I[2] S specification. The MSB of each data word is transmitted one bit clock cycle after the I[2] S WS transition, synchronous with the falling edge of bit clock. Left-channel data is transmitted when I[2] S WS is low, and right-channel data is transmitted when I[2] S WS is high. Data bits sent by the CYBT-013033-01 are synchronized with the falling edge of I2S_SCK and should be sampled by the receiver on the rising edge of I2S_SSCK. 

The clock rate in master mode is either of the following: 

■ 48 kHz × 32 bits per frame = 1.536 MHz 

■ 48 kHz × 50 bits per frame = 2.400 MHz 

The master clock is generated from the input reference clock using a N/M clock divider. In the slave mode, any clock rate is supported to a maximum of 3.072 MHz. Timing values specified in Table 26 are relative to high and low threshold levels. 

**Table 26.  Timing for I[2] S Transmitters and Receivers** 

|~~SS~~<br>~~Rs~~|**Transmitter**<br>~~a~~<br>~~SS~~|**Transmitter**<br>~~a~~<br>~~SS~~|**Transmitter**<br>~~a~~<br>~~SS~~|**Transmitter**<br>~~a~~<br>~~SS~~|**Receiver**<br>~~a~~<br>~~SS~~|**Receiver**<br>~~a~~<br>~~SS~~|**Receiver**<br>~~a~~<br>~~SS~~|**Receiver**<br>~~a~~<br>~~SS~~|**Notes**<br>|
|---|---|---|---|---|---|---|---|---|---|
||**Lower LImit**<br>~~eG~~<br>~~SS~~||**Upper Limit**<br>~~eG~~<br>~~SS~~||**Lower Limit**<br>~~eG~~<br>~~SS~~||**Upper Limit**<br>~~eG~~<br>~~SS~~|||
||**Min**<br>~~SS~~<br>|**Max**<br>~~SS~~<br>|**Min**<br>~~SS~~<br>|**Max**<br>~~SS~~<br>|**Min**<br>~~SS~~<br>|**Max**<br>~~SS~~<br>|**Min**<br>~~SS~~<br>|**Max**<br>~~SS~~<br>||
|Clock Period T<br>~~Rs~~|Ttr<br>|–<br>|–<br>|–<br>|Tr<br>|–<br>|–<br>|–<br>|Note 21<br>|
|**Master Mode: Clock generated by transmitter or receiver**<br>~~Rs|~~<br>~~Re~~||||||||||
|HIGH tHC<br>~~Re~~|0.35 × Ttr|–|–|–|0.35 × Ttr|–|–|–|Note 22|
|LOW tLC<br>~~Re~~<br>~~se~~|0.35 × Ttr<br>~~se~~|–|–|–|0.35 × Ttr|–|–|–|Note 22|
|**Slave Mode: Clock accepted by transmitter or receiver**<br>~~|~~<br>~~Rs~~||||||||||
|HIGH tHC<br>~~|~~<br>~~Rs~~<br>~~Rs~~|–<br>~~|~~|0.35 × Ttr<br>~~|~~|–<br>~~|~~|–<br>~~|~~|–<br>~~|~~|0.35 × Ttr<br>~~|~~|–<br>~~|~~|–<br>~~|~~|Note 23<br>~~|~~|
|LOW tLC<br>~~Rs~~<br>~~Rs~~<br>~~Re~~|–<br>|0.35 × Ttr<br>|–<br>|–<br>|–<br>|0.35 × Ttr<br>|–<br>|–<br>|Note 23<br>|
|Rise time tRC<br>~~Rs~~<br>~~Re~~|–<br>|–<br>|0.15 × Ttr<br>|–<br>|–<br>|–<br>||–<br>|Note 24<br>|
|**Transmitter**<br>~~RepC~~<br>~~po~~||||||||||
|Delay tdtr<br>~~po~~<br>~~po~~|–<br>~~po~~<br>|–<br>|–<br>|0.8 × T<br>|–<br>|–<br>|–<br>|–<br>|Note 25<br>|
|Hold time thtr<br>~~po~~<br>~~po~~|0<br>~~po~~<br>|–<br>|–<br>|–<br>|–<br>|–<br>|–<br>|–<br>|Note 25<br>|
|**Receiver**<br>~~po|~~<br>~~Re~~||||||||||
|Setup time tsr<br>~~|~~<br>~~Re~~<br>~~po~~|–<br>~~|~~<br>~~po~~|–<br>~~|~~|–<br>~~|~~|–<br>~~|~~|–<br>~~|~~|0.2 × Tr<br>~~|~~|–<br>~~|~~|–<br>~~|~~|Note 26<br>~~|~~|
|Hold time thr<br>~~Re~~<br>~~po~~|–<br>~~po~~|–|–|–|–|0|–|–|Note 26|



**Notes** 

> 21. The system clock period T must be greater than Ttr and Tr because both the transmitter and receiver have to be able to handle the data transfer rate. 

> 22. At all data rates in master mode, the transmitter or receiver generates a clock signal with a fixed mark/space ratio. For this reason, tHC and tLC are specified with respect to T. 

> 23. In slave mode, the transmitter and receiver need a clock signal with minimum HIGH and LOW periods so that they can detect the signal. So long as the minimum periods are greater than 0.35Tr, any clock that meets the requirements can be used. 

> 24. Because the delay (tdtr) and the maximum transmitter speed (defined by Ttr) are related, a fast transmitter driven by a slow clock edge can result in tdtr not exceeding tRC which means thtr becomes zero or negative. Therefore, the transmitter has to guarantee that thtr is greater than or equal to zero, so long as the clock rise-time tRC is not more than tRCmax, where tRCmax is not less than 0.15 × Ttr. 

25. To allow data to be clocked out on a falling edge, the delay is specified with respect to the rising edge of the clock signal and T, always giving the receiver sufficient setup time. 

> 26. The data setup and hold time must not be less than the specified receiver setup and hold time. 

Document Number: 002-23132 Rev. *E 

Page 35 of 47 

**CYBT-353027-02** 

## **Environmental Specifications** 

## **Environmental Compliance** 

This CYBT-353027-02 Bluetooth LE module is produced in compliance with the Restriction of Hazardous Substances (RoHS) and Halogen-Free (HF) directives. The Cypress module and components used to produce this module are RoHS and HF compliant. 

## **RF Certification** 

The CYBT-353027-02 module will be certified under the following RF certification standards at production release. 

■ FCC: WAP3027 

■ CE 

■ IC: 7922A-3027 

■ MIC: 203-JN0859 

## **Safety Certification** 

The CYBT-353027-02 module complies with the following safety regulations: 

■ Underwriters Laboratories, Inc. (UL): Filing E331901 

■ CSA 

- TUV 

## **Environmental Conditions** 

Table 27 describes the operating and storage conditions for the Cypress Bluetooth LE module. 

## **Table 27.  Environmental Conditions for CYBT-353027-02** 

|**Description**|**Minimum Specification**|**Maximum Specification**|
|---|---|---|
|Operating temperature|–30 °C|85 °C|
|Operating humidity (relative, non-condensation)|5%|85%|
|Thermal ramp rate|–|3 °C/minute|
|Storage temperature|–40 °C|85 °C|
|Storage temperature and humidity|–|85 °C at 85%|
|ESD: Module integrated into end system Components[27]|–|15 kV Air<br>2.0 kV Contact|



## **ESD and EMI Protection** 

Exposed components require special attention to ESD and electromagnetic interference (EMI). 

A grounded conductive layer inside the device enclosure is suggested for EMI and ESD performance. Any openings in the enclosure near the module should be surrounded by a grounded conductive layer to provide ESD protection and a low-impedance path to ground. **Device Handling** : Proper ESD protocol must be followed in manufacturing to ensure component reliability. 

> 27. This does not apply to the RF pins (ANT). 

**Note** 

Document Number: 002-23132 Rev. *E 

Page 36 of 47 

**CYBT-353027-02** 

## **Regulatory Information** 

## **FCC** 

## FCC NOTICE: 

The device CYBT-353027-02 complies with Part 15 of the FCC Rules. The device meets the requirements for modular transmitter approval as detailed in FCC public Notice DA00-1407.transmitter Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. 

## CAUTION: 

The FCC requires the user to be notified that any changes or modifications made to this device that are not expressly approved by Cypress Semiconductor may void the user’s authority to operate the equipment. 

This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC Rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures: 

■ Reorient or relocate the receiving antenna. 

■ Increase the separation between the equipment and receiver. 

■ Connect the equipment into an outlet on a circuit different from that to which the receiver is connected. 

■ Consult the dealer or an experienced radio/TV technician for help 

## LABELING REQUIREMENTS: 

The Original Equipment Manufacturer (OEM) must ensure that FCC labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor FCC identifier for this product as well as the FCC Notice above. The FCC identifier is FCC ID: WAP3027. 

In any case the end product must be labeled exterior with “Contains FCC ID: WAP3027” 

## ANTENNA WARNING: 

This device is tested with a standard SMA connector and with the antenna listed in Table 6 on page 12. When integrated in the OEMs product, these fixed antennas require installation preventing end-users from replacing them with non-approved antennas. Any antenna not in the following table must be tested to comply with FCC Section 15.203 for unique antenna connectors and Section 15.247 for emissions. 

## RF EXPOSURE: 

To comply with FCC RF Exposure requirements, the Original Equipment Manufacturer (OEM) must ensure to install the approved antenna in the previous. 

The preceding statement must be included as a CAUTION statement in manuals, for products operating with the approved antenna in Table 6 on page 12, to alert users on FCC RF Exposure compliance. Any notification to the end user of installation or removal instructions about the integrated radio module is not allowed. 

The radiated output power of CYBT-353027-02 with the trace antenna is far below the FCC radio frequency exposure limits. Nevertheless, use CYBT-353027-02 in such a manner that minimizes the potential for human contact during normal operation. 

End users may not be provided with the module installation instructions. OEM integrators and end users must be provided with transmitter operating conditions for satisfying RF exposure compliance. 

Document Number: 002-23132 Rev. *E 

Page 37 of 47 

**CYBT-353027-02** 

## **ISED** 

## **Innovation, Science and Economic Development Canada (ISED) Certification** 

CYBT-353027-02 is licensed to meet the regulatory requirements of Innovation, Science and Economic Development Canada (ISED), License: IC: 7922A-3027 

Manufacturers of mobile, fixed or portable devices incorporating this module are advised to clarify any regulatory questions and ensure compliance for SAR and/or RF exposure limits. Users can obtain Canadian information on RF exposure and compliance from www.ic.gc.ca. 

This device has been designed to operate with the antennas listed in Table 6 on page 12, having a maximum gain of -0.5 dBi. Antennas not included in this list or having a gain greater than -0.5 dBi are strictly prohibited for use with this device. The required antenna impedance is 50 ohms. The antenna used for this transmitter must not be co-located or operating in conjunction with any other antenna or transmitter. 

## ISED NOTICE: 

The device CYBT-353027-02 including the built-in trace antenna complies with Canada RSS-GEN Rules. The device meets the requirements for modular transmitter approval as detailed in RSS-GEN. Operation is subject to the following two conditions: (1) This device may not cause harmful interference, and (2) This device must accept any interference received, including interference that may cause undesired operation. 

L'appareil CYBT-353027-02, y compris l'antenne intégrée, est conforme aux Règles RSS-GEN de Canada. L'appareil répond aux exigences d'approbation de l'émetteur modulaire tel que décrit dans RSS-GEN. L'opération est soumise aux deux conditions suivantes: (1) Cet appareil ne doit pas causer d'interférences nuisibles, et (2) Cet appareil doit accepter toute interférence reçue, y compris les interférences pouvant entraîner un fonctionnement indésirable. 

## ISED INTERFERENCE STATEMENT FOR CANADA 

This device complies with Innovation, Science and Economic Development (ISED) Canada licence-exempt RSS standard(s). Operation is subject to the following two conditions: (1) this device may not cause interference, and (2) this device must accept any interference, including interference that may cause undesired operation of the device. 

Cet appareil est conforme à la norme sur l'innovation, la science et le développement économique (ISED) norme RSS exempte de licence. L'exploitation est autorisée aux deux conditions suivantes: (1) l'appareil ne doit pas produire de brouillage, et (2) l'utilisateur de l'appareil doit accepter tout brouillage radioélectrique subi, même si le brouillage est susceptible d'en compromettre le fonctionnement. 

## ISED RADIATION EXPOSURE STATEMENT FOR CANADA 

This equipment complies with ISED radiation exposure limits set forth for an uncontrolled environment. 

Cet équipement est conforme aux limites d'exposition aux radiations ISED prévues pour un environnement incontrôlé. 

## LABELING REQUIREMENTS: 

The Original Equipment Manufacturer (OEM) must ensure that ISED labelling requirements are met. This includes a clearly visible label on the outside of the OEM enclosure specifying the appropriate Cypress Semiconductor IC identifier for this product as well as the ISED Notices above. The IC identifier is 7922A-3027. In any case, the end product must be labeled in its exterior with “Contains IC: 7922A-3027”. 

Document Number: 002-23132 Rev. *E 

Page 38 of 47 

**CYBT-353027-02** 

## **European Declaration of Conformity** 

Hereby, Cypress Semiconductor declares that the Bluetooth module CYBT-353027-02 complies with the essential requirements and other relevant provisions of Directive 2014. As a result of the conformity assessment procedure described in Annex III of the Directive 2014, the end-customer equipment should be labeled as follows: 

All versions of the CYBT-353027-02 in the specified reference design can be used in the following countries: Austria, Belgium, Cyprus, Czech Republic, Denmark, Estonia, Finland, France, Germany, Greece, Hungary, Ireland, Italy, Latvia, Lithuania, Luxembourg, Malta, Poland, Portugal, Slovakia, Slovenia, Spain, Sweden, The Netherlands, the United Kingdom, Switzerland, and Norway. 

## **MIC Japan** 

CYBT-353027-02 is certified as a module with certification number 203-JN0859. End products that integrate CYBT-353027-02 do not need additional MIC Japan certification for the end product. 

End product can display the certification label of the embedded module. 

Document Number: 002-23132 Rev. *E 

Page 39 of 47 

**CYBT-353027-02** 

## **Packaging** 

**Table 28.  Solder Reflow Peak Temperature** 

|**Module Part Number**|**Package**|**Maximum Peak Temperature**|**Maximum Time at Peak Temperature**|**No. of Cycles**|
|---|---|---|---|---|
|CYBT-353027-02|19-pad SMT|260 °C|30 seconds|2|



**Table 29.  Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2** 

|**Module Part Number**|**Package**|**MSL**|
|---|---|---|
|CYBT-353027-02|19-pad SMT|MSL 3|



The CYBT-353027-02 is offered in tape and reel packaging. Figure 20 details the tape dimensions used for the CYBT-353027-02. 

**Figure 20.  CYBT-353027-02 Tape Dimensions** 

Figure 21 details the orientation of the CYBT-353027-02 in the tape as well as the direction for unreeling. 

**Figure 21.  Component Orientation in Tape and Unreeling Direction** 

Document Number: 002-23132 Rev. *E 

Page 40 of 47 

**CYBT-353027-02** 

Figure 22 details reel dimensions used for the CYBT-353027-02. 

**Figure 22.  Reel Dimensions** 

The CYBT-353027-02 is designed to be used with pick-and-place equipment in an SMT manufacturing environment. The center-of-mass for the CYBT-353027-02 is detailed in Figure 23. 

**Figure 23.  CYBT-353027-02 Center of Mass** 

Document Number: 002-23132 Rev. *E 

Page 41 of 47 

**CYBT-353027-02** 

## **Ordering Information** 

Table 30 lists the CYBT-353027-02 part number and features. Table 31 lists the reel shipment quantities for the CYBT-353027-02. 

## **Table 30.  Ordering Information** 

|**Ordering Part**<br>**Number**|**Max CPU**<br>**Speed**<br>**(MHz)**|**SFlash**<br>**Size**<br>**(KB)**|**SFlash**<br>**RAM**<br>**Size**<br>**(KB)**|**UART**|**I2C**|**SPI**|**I2S**|**PCM**|**PWM**|**ADC**<br>**Inputs**|**GPIOs**|**Package**|**Packaging**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|CYBT-353027-02|24|512|352|Yes|Yes|Yes|Yes|Yes|–|5|8|19-SMT|Tape and Reel|



**Table 31.  Tape and Reel Package Quantity and Minimum Order Amount** 

|**Description**|**Minimum Reel Quantity**|**Maximum Reel Quantity**|**Comments**|
|---|---|---|---|
|Reel Quantity|500|500|Ships in 500 unit reel quantities.|
|Minimum Order Quantity (MOQ)|500|–|–|
|Order Increment (OI)|500|–|–|



The CYBT-353027-02 is offered in tape and reel packaging. The CYBT-353027-02 ships in a reel size of 500. 

For additional information and a complete list of Cypress Semiconductor Wireless products, contact your local Cypress sales representative. To locate the nearest Cypress office, visit our website. 

|U.S. Cypress Headquarters Address|198 Champion Court, San Jose, CA 95134|
|---|---|
|U.S. Cypress Headquarter Contact Info|(408) 943-2600|
|Cypress website address|http://www.cypress.com|



Document Number: 002-23132 Rev. *E 

Page 42 of 47 

**CYBT-353027-02** 

## **Acronyms** 

**Table 32.  Acronyms Used in this Document** 

|**Acronym**<br>~~ee~~<br>~~Pf~~|**Description**<br>~~I~~<br>~~Pf~~|**Acronym**<br>~~(Ot~~|**Description**|
|---|---|---|---|
|ADC<br>~~ee~~<br>~~Pf~~<br>~~Pf~~|analog-to-digital converter<br>~~I ~~<br>~~Pfee~~<br>~~Pf~~|IDE<br> ~~(Ot~~|integrated development environment|
|ALU<br>~~Pf~~<br>~~Pf~~<br>~~Pf~~|arithmetic logic unit<br>~~Pf~~<br>~~Pfee~~<br>~~Pf~~|I2C, or IIC|Inter-Integrated Circuit, a communications protocol|
|AMUXBUS <br>~~Pf~~<br>~~Pf~~<br>~~Pf~~|analog multiplexer bus<br>~~Pfee~~<br>~~Pfeee~~<br>~~Pf~~|IC|Industry Canada|
|API<br>~~Pf~~<br>~~Pf~~<br>~~Pf~~|application programming interface<br>~~Pf~~<br>~~Pfee~~<br>~~Pf~~|IIR|infinite impulse response, see also FIR|
|ARM®<br>~~Pf~~<br>~~Pf~~|advanced RISC machine, a CPU architecture<br>~~Pfee~~<br>~~Pfeee~~|ILO|internal low-speed oscillator, see also IMO|
|BLE<br>~~Pf~~<br>~~a es~~|Bluetooth Low Energy<br>~~Pf~~<br>~~es~~|IMO<br>~~Ge~~|internal main oscillator, see also ILO|
|Bluetooth<br>SIG<br>~~a es~~|Bluetooth Special Interest Group<br>~~es~~|INL<br>~~Ge~~|integral nonlinearity, see also DNL|
|BW<br>~~a es~~<br>~~Pe~~<br>~~ee~~|bandwidth<br>~~es~~<br>~~Pe~~<br>~~nD~~|I/O<br>~~Ge~~<br>~~tIIIttnD~~|input/output, see also GPIO, DIO, SIO, USBIO<br>~~GR~~|
|CAN<br>~~Pe~~<br>~~ee~~|Controller Area Network, a communications protocol <br>~~Pe~~<br>~~nD~~|IPOR<br>~~tIIIttnD~~|initial power-on reset<br>~~GR~~|
|CE<br>~~ee~~<br>~~Pe~~<br>~~ee~~|European Conformity<br>~~nD ~~<br>~~Pe~~<br>~~nD~~|IPSR<br> ~~tIIIttnD~~<br>~~tIIIttnD~~|interrupt program status register<br>~~GR~~<br>~~GR~~|
|CSA<br>~~Pe~~<br>~~ee~~|Canadian Standards Association<br>~~Pe~~<br>~~nD~~|IRQ<br>~~tIIIttnD~~|interrupt request<br>~~GR~~|
|CMRR<br>~~ee~~<br>~~Pe~~<br>~~ee~~|common-mode rejection ratio<br>~~nD ~~<br>~~Pe~~<br>~~nD~~|ITM<br> ~~tIIIttnD~~<br>~~tIIIttnD~~|instrumentation trace macrocell<br>~~GR~~<br>~~GR~~|
|CPU<br>~~Pe~~<br>~~ee~~|central processing unit<br>~~Pe~~<br>~~nD~~|KC<br>~~tIIIttnD~~|Korea Certification<br>~~GR~~|
|CRC<br>~~ee~~<br>~~a es~~|cyclic redundancy check, an error-checking protocol <br>~~nD ~~<br>~~es~~|LCD<br> ~~tIIIttnD~~<br>~~Ge~~|liquid crystal display<br>~~GR~~|
|ECC<br>~~a es~~|error correcting code<br>~~es~~|LIN<br>~~Ge~~|Local Interconnect Network, a communications<br>protocol.|
|ECO<br>~~a es~~<br>~~a ee~~|external crystal oscillator<br>~~es~~<br>~~ee~~|LNA<br>~~Ge~~<br>~~Ge~~|low noise amplifier|
|EEPROM<br>~~a ee~~<br>~~Pf~~|electrically erasable programmable read-only<br>memory<br>~~ee~~<br>~~Pf~~|LR<br>~~Ge~~|link register|
|EMI<br>~~a ee~~<br>~~Pf~~<br>~~Pf~~|electromagnetic interference<br>~~ee~~<br>~~Pf~~<br>~~Pf~~|LUT<br>~~Ge~~|lookup table|
|EMIF<br>~~Pf~~<br>~~Pf~~<br>~~Pf~~|external memory interface<br>~~Pf~~<br>~~Pfeee~~<br>~~Pf~~|LVD|low-voltage detect, see also LVI|
|EOC<br>~~Pf~~<br>~~Pf~~<br>~~Pf~~|end of conversion<br>~~Pf~~<br>~~Pf~~<br>~~Pf~~|LVI|low-voltage interrupt, see also HVI|
|EOF<br>~~Pf~~<br>~~Pf~~<br>~~Pf~~|end of frame<br>~~Pf~~<br>~~Pfeee~~<br>~~Pf~~|LVTTL|low-voltage transistor-transistor logic|
|ESD<br>~~Pf~~<br>~~Pf~~|electrostatic discharge<br>~~Pf~~<br>~~Pfee~~|MAC|multiply-accumulate|
|FCC<br>~~Pf~~<br>~~a es~~|Federal Communications Commission<br>~~Pf~~<br>~~es~~|MCU<br>~~Ge~~|microcontroller unit|
|FET<br>~~a es~~<br>~~ee~~|field-effect transistor<br>~~es~~<br>~~nD~~|MIC<br>~~Ge~~<br>~~tIIIttnD~~|Ministry of Internal Affairs and Communications<br>(Japan)<br>~~GR~~|
|FIR<br>~~a es~~<br>~~ee~~|finite impulse response, see also IIR<br>~~es~~<br>~~nD~~|MISO<br>~~Ge~~<br>~~tIIIttnD~~|master-in slave-out<br>~~GR~~|
|FPB<br>~~ee~~<br>~~Pe~~<br>~~ee~~|flash patch and breakpoint<br>~~nD ~~<br>~~Pe~~<br>~~nD~~|NC<br> ~~tIIIttnD~~<br>~~tIIIttnD~~|no connect<br>~~GR~~<br>~~GR~~|
|FS<br>~~Pe~~<br>~~ee~~|full-speed<br>~~Pe~~<br>~~nD~~|NMI<br>~~tIIIttnD~~|nonmaskable interrupt<br>~~GR~~|
|GPIO<br>~~ee~~<br>~~Pe~~<br>~~ee~~|general-purpose input/output, applies to a PSoC pin <br>~~nD ~~<br>~~Pe~~<br>~~nD~~|NRZ<br> ~~tIIIttnD~~<br>~~tIIIttnD~~|non-return-to-zero<br>~~GR~~<br>~~GR~~|
|HCI<br>~~Pe~~<br>~~ee~~|host controller interface<br>~~Pe~~<br>~~nD~~|NVIC<br>~~tIIIttnD~~|nested vectored interrupt controller<br>~~GR~~|
|HVI<br>~~ee~~<br>~~Pe~~<br>~~ee~~|high-voltage interrupt, see also LVI, LVD<br>~~nD ~~<br>~~Pe~~<br>~~nD~~|NVL<br> ~~tIIIttnD~~<br>~~tIIIttnD~~|nonvolatile latch, see also WOL<br>~~GR~~<br>~~GR~~|
|IC<br>~~Pe~~<br>~~ee~~|integrated circuit<br>~~Pe~~<br>~~nD~~|Opamp<br>~~tIIIttnD~~|operational amplifier<br>~~GR~~|
|IDAC<br>~~ee~~<br>~~Pe~~<br>~~ee~~|current DAC, see also DAC, VDAC<br>~~nD ~~<br>~~Pe~~<br>~~nD~~|PA<br> ~~tIIIttnD~~<br>~~tIIIttnD~~|power amplifier<br>~~GR~~<br>~~GR~~|
|PAL<br>~~Pe~~<br>~~ee~~|programmable array logic, see also PLD<br>~~Pe~~<br>~~nD~~|SOF<br>~~tIIIttnD~~|start of frame<br>~~GR~~|
|PC<br>~~ee~~<br>~~Pe~~<br>~~ee~~|program counter<br>~~nD ~~<br>~~Pe~~<br>~~nD~~|S/H<br> ~~tIIIttnD~~<br>~~POIs~~|sample and hold<br>~~GR~~<br>~~GRO~~|
|PCB<br>~~Pe~~<br>~~ee~~|printed circuit board<br>~~Pe~~<br>~~nD~~|SINAD<br>~~POIs~~|signal to noise and distortion ratio<br>~~GRO~~|



Document Number: 002-23132 Rev. *E 

Page 43 of 47 

**CYBT-353027-02** 

**Table 32.  Acronyms Used in this Document** (continued) 

|**Acronym**<br>~~ee~~<br>~~a es~~|**Description**<br>~~eS~~<br>~~es~~|**Acronym**<br>~~(OUD~~<br>~~Ge~~|**Description**<br>~~(I~~|
|---|---|---|---|
|PGA<br>~~ee~~<br>~~a es~~|programmable gain amplifier<br>~~eS~~<br>~~es~~|SIO<br>~~(OUD~~<br>~~Ge~~|special input/output, GPIO with advanced features.<br>See GPIO.<br>~~(I~~|
|PHUB<br>~~a es~~<br>~~a es~~|peripheral hub<br>~~es~~<br>~~es~~|SMT<br>~~Ge~~<br>~~Gn~~|surface-mount technology; a method for producing<br>electronic circuitry in which the components are<br>placed directly onto the surface of PCBs|
|PHY<br>~~a es~~|physical layer<br>~~es~~|SPI<br>~~Gn~~|Serial Peripheral Interface, a communications<br>protocol|
|PICU<br>~~a es~~<br>~~Pe~~<br>~~ee~~|port interrupt control unit<br>~~es~~<br>~~Pe~~<br>~~nD~~|SR<br>~~Gn~~<br>~~tIIIttnD~~|slew rate<br>~~GR~~|
|PLA<br>~~Pe~~<br>~~ee~~|programmable logic array<br>~~Pe~~<br>~~nD~~|SRAM<br>~~tIIIttnD~~|static random access memory<br>~~GR~~|
|PLD<br>~~ee~~<br>~~Pe~~<br>~~ee~~|programmable logic device, see also PAL<br>~~nD ~~<br>~~Pe~~<br>~~nD~~|SRES<br> ~~tIIIttnD~~<br>~~tIIIttnD~~|software reset<br>~~GR~~<br>~~GR~~|
|PLL<br>~~Pe~~<br>~~ee~~|phase-locked loop<br>~~Pe~~<br>~~nD~~|STN<br>~~tIIIttnD~~|super twisted nematic<br>~~GR~~|
|PMDD<br>~~ee~~<br>~~Pe~~<br>~~ee~~|package material declaration data sheet<br>~~nD ~~<br>~~Pe~~<br>~~nD~~|SWD<br> ~~tIIIttnD~~<br>~~tIIIttnD~~|serial wire debug, a test protocol<br>~~GR~~<br>~~GR~~|
|POR<br>~~Pe~~<br>~~ee~~|power-on reset<br>~~Pe~~<br>~~nD~~|SWV<br>~~tIIIttnD~~|single-wire viewer<br>~~GR~~|
|PRES<br>~~ee~~<br>~~Pe~~<br>~~ee~~|precise power-on reset<br>~~nD ~~<br>~~Pe~~<br>~~nD~~|TD<br> ~~tIIIttnD~~<br>~~tIIIttnD~~|transaction descriptor, see also DMA<br>~~GR~~<br>~~GR~~|
|PRS<br>~~Pe~~<br>~~ee~~|pseudo random sequence<br>~~Pe~~<br>~~nD~~|THD<br>~~tIIIttnD~~|total harmonic distortion<br>~~GR~~|
|PS<br>~~ee~~<br>~~Pe~~<br>~~ee~~|port read data register<br>~~nD ~~<br>~~Pe~~<br>~~nD~~|TIA<br> ~~tIIIttnD~~<br>~~tIIIttnD~~|transimpedance amplifier<br>~~GR~~<br>~~GR~~|
|PSoC®<br>~~Pe~~<br>~~ee~~|Programmable System-on-Chip™<br>~~Pe~~<br>~~nD~~|TN<br>~~tIIIttnD~~|twisted nematic<br>~~GR~~|
|PSRR<br>~~ee~~<br>~~Pe~~<br>~~ee~~|power supply rejection ratio<br>~~nD ~~<br>~~Pe~~<br>~~nD~~|TRM<br> ~~tIIIttnD~~<br>~~tIIIttnD~~|technical reference manual<br>~~GR~~<br>~~GR~~|
|PWM<br>~~Pe~~<br>~~ee~~<br>~~a ee~~|pulse-width modulator<br>~~Pe~~<br>~~nD~~<br>~~ee~~|TTL<br>~~tIIIttnD~~<br>~~Ge~~|transistor-transistor logic<br>~~GR~~|
|QDID<br>~~ee~~<br>~~a ee~~<br>~~Pf~~|qualification design ID<br>~~nD ~~<br>~~ee~~<br>~~Pf~~|TUV<br> ~~tIIIttnD~~<br>~~Ge~~|Germany: Technischer Überwachungs-Verein<br>(Technical Inspection Association)<br>~~GR~~|
|RAM<br>~~a ee~~<br>~~Pf~~<br>~~a es~~|random-access memory<br>~~ee~~<br>~~Pf~~<br>~~es~~|TX<br>~~Ge~~<br>~~Ge~~|transmit|
|RISC<br>~~Pf~~<br>~~a es~~|reduced-instruction-set computing<br>~~Pf~~<br>~~es~~|UART<br>~~Ge~~|Universal Asynchronous Transmitter Receiver, a<br>communications protocol|
|RMS<br>~~a es~~<br>~~Pe~~<br>~~ee~~|root-mean-square<br>~~es~~<br>~~Pe~~<br>~~nD~~|UDB<br>~~Ge~~<br>~~tIIIttnD~~|universal digital block<br>~~GR~~|
|RTC<br>~~Pe~~<br>~~ee~~<br>~~a es~~|real-time clock<br>~~Pe~~<br>~~nD~~<br>~~es~~|USB<br>~~tIIIttnD~~<br>~~Gn~~|Universal Serial Bus<br>~~GR~~|
|RTL<br>~~ee~~<br>~~a es~~|register transfer language<br>~~nD ~~<br>~~es~~|USBIO<br> ~~tIIIttnD~~<br>~~Gn~~|USB input/output, PSoC pins used to connect to a<br>USB port<br>~~GR~~|
|RTR<br>~~a es~~<br>~~Pe~~<br>~~ee~~|remote transmission request<br>~~es~~<br>~~Pe~~<br>~~nD~~|VDAC<br>~~Gn~~<br>~~tIIIttnD~~|voltage DAC, see also DAC, IDAC<br>~~GR~~|
|RX<br>~~Pe~~<br>~~ee~~|receive<br>~~Pe~~<br>~~nD~~|WDT<br>~~tIIIttnD~~|watchdog timer<br>~~GR~~|
|SAR<br>~~ee~~<br>~~Pe~~<br>~~ee~~|successive approximation register<br>~~nD ~~<br>~~Pe~~<br>~~nD~~|WOL<br> ~~tIIIttnD~~<br>~~tIIIttnD~~|write once latch, see also NVL<br>~~GR~~<br>~~GR~~|
|SC/CT<br>~~Pe~~<br>~~ee~~|switched capacitor/continuous time<br>~~Pe~~<br>~~nD~~|WRES<br>~~tIIIttnD~~|watchdog timer reset<br>~~GR~~|
|SCL<br>~~ee~~<br>~~Pe~~<br>~~ee~~|I2C serial clock<br>~~nD ~~<br>~~Pe~~<br>~~eS~~|XRES<br> ~~tIIIttnD~~<br>~~OttItIttnD~~|external reset I/O pin<br>~~GR~~<br>~~DRO~~|
|SDA<br>~~Pe~~<br>~~ee~~|I2C serial data<br>~~Pe~~<br>~~eS~~|XTAL<br>~~OttItIttnD~~|crystal<br>~~DRO~~|
|SOC<br>~~ee~~<br>~~a~~|start of conversion<br>~~eS ~~|~~OttItIttnDDRO~~||



Document Number: 002-23132 Rev. *E 

Page 44 of 47 

**CYBT-353027-02** 

## **Document Conventions** 

## **Units of Measure** 

## **Table 33.  Units of Measure** 

|**Symbol**<br>~~ee~~<br>~~ee~~|**Unit of Measure**|
|---|---|
|°C<br>~~ee~~<br>~~ee~~<br>~~ee~~|degrees Celsius|
|dB<br>~~ee~~<br>~~ee~~<br>~~ee~~|decibel|
|dBm<br>~~ee~~<br>~~ee~~<br>~~ee~~|decibel-milliwatts|
|fF<br>~~ee~~<br>~~ee~~<br>~~ee~~|femtofarads|
|Hz<br>~~ee~~<br>~~ee~~<br>~~ee~~|hertz|
|KB<br>~~ee~~<br>~~ee~~<br>~~ee~~|1024 bytes|
|kbps<br>~~ee~~<br>~~ee~~<br>~~ee~~|kilobits per second|
|Khr<br>~~ee~~<br>~~ee~~<br>~~ee~~|kilohour|
|kHz<br>~~ee~~<br>~~ee~~<br>~~ee~~|kilohertz|
|k<br>~~ee~~<br>~~ee~~<br>~~ee~~|kilo ohm|
|ksps<br>~~ee~~<br>~~ee~~<br>~~ee~~|kilosamples per second|
|LSB<br>~~ee~~<br>~~ee~~<br>~~ee~~|least significant bit|
|Mbps<br>~~ee~~<br>~~ee~~<br>~~ee~~|megabits per second|
|MHz<br>~~ee~~<br>~~ee~~<br>~~ee~~|megahertz|
|M<br>~~ee~~<br>~~ee~~<br>~~ee~~|mega-ohm|
|Msps<br>~~ee~~<br>~~ee~~<br>~~ee~~|megasamples per second|
|µA<br>~~ee~~<br>~~ee~~<br>~~ee~~|microampere|
|µF<br>~~ee~~<br>~~ee~~<br>~~ee~~|microfarad|
|µH<br>~~ee~~<br>~~ee~~<br>~~ee~~|microhenry|
|µs<br>~~ee~~<br>~~ee~~<br>~~ee~~|microsecond|
|µV<br>~~ee~~<br>~~ee~~<br>~~ee~~|microvolt|
|µW<br>~~ee~~<br>~~ee~~<br>~~ee~~|microwatt|
|mA<br>~~ee~~<br>~~ee~~<br>~~ee~~|milliampere|
|ms<br>~~ee~~<br>~~ee~~<br>~~ee~~|millisecond|
|mV<br>~~ee~~<br>~~ee~~<br>~~ee~~|millivolt|
|nA<br>~~ee~~<br>~~ee~~<br>~~ee~~|nanoampere|
|ns<br>~~ee~~<br>~~ee~~<br>~~ee~~|nanosecond|
|nV<br>~~ee~~<br>~~ee~~<br>~~ee~~|nanovolt|
|<br>~~ee~~<br>~~ee~~<br>~~ee~~|ohm|
|pF<br>~~ee~~<br>~~ee~~<br>~~ee~~|picofarad|
|ppm<br>~~ee~~<br>~~ee~~<br>~~ee~~|parts per million|
|ps<br>~~ee~~<br>~~ee~~<br>~~ee~~|picosecond|
|s<br>~~ee~~<br>~~ee~~<br>~~ee~~|second|
|sps<br>~~ee~~<br>~~ee~~<br>~~ee~~|samples per second<br>~~ee~~|
|sqrtHz<br>~~ee~~<br>~~ee~~<br>~~ee~~|square root of hertz<br>~~ee~~|
|V<br>~~ee~~<br>~~ee~~|volt<br>~~ee~~|



Document Number: 002-23132 Rev. *E 

Page 45 of 47 

**CYBT-353027-02** 

## **Document History Page** 

**Document Title: CYBT-353027-02, EZ-BT WICED Module Document Number: 002-23132** 

|**Document Title: CYBT-353027-02, EZ-BT WICED Module**<br>**Document Number: 002-23132**|**Document Title: CYBT-353027-02, EZ-BT WICED Module**<br>**Document Number: 002-23132**|**Document Title: CYBT-353027-02, EZ-BT WICED Module**<br>**Document Number: 002-23132**|**Document Title: CYBT-353027-02, EZ-BT WICED Module**<br>**Document Number: 002-23132**|
|---|---|---|---|
|**Revision**|**ECN**|**Submission**<br>**Date**|**Description of Change**|
|**|6106677|03/22/2018|Preliminary datasheet for CYBT-353027-02 module.|
|*A|6483011|02/12/2019|Changed status from Preliminary to Final.<br>UpdatedElectrical Characteristics:<br>UpdatedTable 13.<br>Completing Sunset Review.|
|*B|6492039|02/22/2019|Updated File Properties.<br>No technical updates.|
|*C|6496268|02/27/2019|UpdatedElectrical Characteristics:<br>UpdatedTable 13.|
|*D|6825227|03/06/2020|UpdatedFeatures:<br>UpdatedModule Description:<br>Updated description.<br>UpdatedFunctional Capabilities:<br>Updated description.<br>UpdatedOverview:<br>UpdatedFunctional Block Diagram:<br>UpdatedFigure 1.<br>UpdatedModule Connections:<br>UpdatedTable 4.<br>Removed “Global Coexistence Interface”.<br>UpdatedEnvironmental Specifications:<br>UpdatedRF Certification:<br>Updated description.<br>UpdatedRegulatory Information:<br>UpdatedFCC:<br>Updated description.<br>UpdatedISED:<br>Updated description.<br>UpdatedMIC Japan:<br>Updated description.<br>Added image.<br>UpdatedPackaging:<br>UpdatedFigure 20(Added image).<br>UpdatedFigure 21(Added image).<br>UpdatedFigure 23(Added image).<br>Updated to new template.<br>Completing Sunset Review.|
|*E|7115543|04/02/2021|Replaced “BLE stack” with “Bluetooth stack” in all instances across the document.<br>Replaced “Bluetooth Low Energy (BLE)” with “Bluetooth Low Energy” in all instances across<br>the document.<br>Replaced “BLE” with “Bluetooth LE” in all instances across the document.<br>Completing Sunset Review.|



Document Number: 002-23132 Rev. *E 

Page 46 of 47 

**CYBT-353027-02** 

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Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries.  For a more complete list of Cypress trademarks, visit cypress.com.  Other names and brands may be claimed as property of their respective owners. 

Document Number: 002-23132 Rev. *E 

Page 47 of 47 

Revised April 2, 2021
Updated at April 28, 2026
Infineon Technologies is a globally recognized leader in semiconductor solutions, renowned for driving innovation in power management, energy efficiency, and modern mobility. With a strong legacy of engineering excellence, the company provides highly reliable components designed to meet the rigorous demands of industrial, automotive, and advanced commercial applications. The core of our Infineon portfolio is centered on their industry-leading discrete semiconductors. We offer an extensive selection of single and dual MOSFETs, alongside a robust range of single IGBTs and advanced IGBT modules. These flagship power transistors are essential for high-efficiency power conversion and motor control, providing engineers with superior thermal performance and minimized switching losses. Beyond advanced field-effect transistors, the selection includes a comprehensive array of diodes and rectifiers, heavily featuring Schottky diodes, as well as fast-recovery and RF/PIN diodes. This power foundation is further supported by bipolar transistors, intelligent power modules, and thyristor SCR modules, delivering the critical building blocks required for complex power system designs. To support broader system integration, the portfolio also encompasses specialized solutions such as solid-state relays, AC/DC LED driver ICs, and Bluetooth communications modules. From high-power industrial rectifiers to wireless connectivity adapters, Infineon equips designers with the precision components needed to build efficient, scalable, and fully connected electronic systems.
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