CY8C9520A-24PVXIT

I/O Expander, 8bit, 100 kHz, I2C, 3 V, 5.25 V, SSOP

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Manufacturer: Cypress
Product type: I/O Expanders
No. of Pins: 28Pins
No. of I/O's: 20I/O's
Bus Frequency: 100kHz
IC Interface Type: I2C
Chip Configuration: 8bit
Supply Voltage Max: 5.25V
Supply Voltage Min: 3V
Interface Case Style: SSOP
Delivery and price
Units per pack	50
Price	5.47 €
Current stock	500+
Lead time	7 days
Datasheet
**CY8C9520A CY8C9540A CY8C9560A** 

## 20-, 40-, and 60-Bit I/O Expander with EEPROM 

## **Features** 

- I[2] C interface logic electrically compatible with SMBus 

- Up to 20 (CY8C9520A), 40 (CY8C9540A), or 60 (CY8C9560A) I/O data pins independently configurable as inputs, outputs, Bi-directional input/outputs, or PWM outputs 

- 4/8/16 PWM sources with 8-bit resolution 

- Extendable soft addressing algorithm allowing flexible I[2] C address configuration 

- Internal 3-/11-/27-Kbyte EEPROM 

- User default storage, I/O port settings in internal EEPROM 

- Optional EEPROM write disable (WD) input 

- Interrupt output indicates input pin level changes and pulse width modulator (PWM) state changes 

- Internal power on reset (POR) 

- Internal configurable watchdog timer 

## **Top Level Block Diagram** 

**==> picture [232 x 256] intentionally omitted <==**

**----- Start of picture text -----**<br>
WD ; [CisdzC] EEPROM<br>User User<br>Settings Available<br>Area Area<br>|_|<br>Clocks<br>32 kHz GPort 0 8 Bit IO<br>24 MHz —| |,<br>1.5 MHz 5 Bit IO<br>GPort 1 3 Bit IO<br>93.75 kHz or A4-A6<br>—<br>Divider (1-255) GPort 2 4 Bit IOor A1-A3, WD6<br>— —} | i:<br>Control<br>PWM 0 Unit GPort 3 8 Bit IO<br>=<br>PWM 15 GPort 7 8 Bit IO<br>SCL<br>SDA [ti“‘“C;C;*SS ia +i INT<br>V dd Power-on-Reset A0<br>V ss<br>——— a<br>**----- End of picture text -----**<br>


## **Overview** 

The CY8C95xxA is a multi-port I/O expander with on board user available EEPROM and several PWM outputs. All devices in this family operate identically but differ in I/O pins, number of PWMs, and internal EEPROM size. 

The CY8C95xxA operates as two I[2] C slave devices. The first device is a multi port I/O expander (single I[2] C address to access all ports through registers). The second device is a serial EEPROM. Dedicated configuration registers can be used to disable the EEPROM. The EEPROM uses 2-byte addressing to support the 28 Kbyte EEPROM address space. The selected device is defined by the most significant bits of the I[2] C address or by specific register addressing. 

The I/O expander's data pins can be independently assigned as inputs, outputs, quasi-bidirectional input/outputs or PWM ouputs. The individual data pins can be configured as open drain or collector, strong drive (10 mA source, 25 mA sink), resistively pulled up or down, or high impedance. The factory default configuration is pulled up internally. 

The system master writes to the I/O configuration registers through the I[2] C bus. Configuration and output register settings are storable as user defaults in a dedicated section of the EEPROM. If user defaults were stored in EEPROM, they are restored to the ports at power up. While this device can share the bus with SMBus devices, it can only communicate with I[2] C masters. The I[2] C slave in this device requires that the I[2] C master supports clock stretching. 

There is one dedicated pin that is configured as an interrupt output (INT) and can be connected to the interrupt logic of the system master. This signal can inform the system master that there is incoming data on its ports or that the PWM output state was changed. 

The EEPROM is byte readable and supports byte-by-byte writing. A pin can be configured as an EEPROM Write Disable (WD) input that blocks write operations when set high. The configuration registers can also disable EEPROM operations. 

The CY8C95xxA has one fixed address pin (A0) and up to six additional pins (A1-A6), which allow up to 128 devices to share a common two wire I[2] C data bus. The Extendable Soft Addressing algorithm provides the option to choose the number of pins needed to assign the desired address. Pins not used for address bits are available as GPIO pins. 

There are 4 (CY8C9520A), 8 (CY8C9540A), or 16 (CY8C9560A) independently configurable 8-bit PWMs. These PWMs are listed as PWM0-PWM15. Each PWM can be clocked by one of six available clock sources. 

Errata: For information on silicon errata, see Errata on page 30. Details include trigger conditions, devices affected, and proposed workaround. 

**Cypress Semiconductor Corporation** • 198 Champion Court Document Number: 38-12036 Rev. *I 

San Jose, CA 95134-1709 • 408-943-2600 Revised April 1, 2015 

• 

**CY8C9520A CY8C9540A CY8C9560A** 

## **Contents** 

**Architecture ......................................................................3** Applications .................................................................3 **Device Access Addressing ..............................................4** Serial EEPROM Device ...............................................4 Multi Port I/O Device ...................................................4 **Pinouts ..............................................................................5** 28-Pin Part Pinout .......................................................5 48-Pin Part Pinout .......................................................6 100-Pin Part Pinout .....................................................7 **Pin Descriptions ...............................................................9** Extendable Soft Addressing ........................................9 Interrupt Pin (INT) ........................................................9 Write Disable Pin (WD) ...............................................9 External Reset Pin (XRES) .........................................9 Working with PWMs ....................................................9 **Register Mapping Table .................................................11 Register Descriptions ....................................................11** Input Port Registers (00h–07h) .................................11 Output Port Registers (08h–0Fh) ..............................11 Int. Status Port Registers (10h–17h) .........................12 Port Select Register (18h) .........................................12 Interrupt Mask Port Register (19h) ............................12 Select PWM Register (1Ah) ......................................12 Inversion Register (1Bh) ............................................12 Port Direction Register (1Ch) ....................................12 Drive Mode Registers (1Dh–23h) ..............................12 PWM Select Register (28h) .......................................12 Config (29h) ...............................................................13 Period Register (2Ah) ................................................13 Pulse Width Register (2Bh) .......................................13 Divider Register (2Ch) ...............................................13 Enable Register (2Dh) ...............................................13 Device ID/Status Register (2Eh) ...............................13 Watchdog Register (2Fh) ..........................................14 Command Register (30h) ..........................................14 

**Commands Description .................................................14** Store Config to E2 POR Defaults Cmd (01h) ............14 Restore Factory Defaults Cmd (02h) .........................14 Write E2 POR Defaults Cmd (03h) ............................14 Read E2 POR Defaults Cmd (04h) ...........................15 Write Device Config Cmd (05h) .................................15 Read Device Config Cmd (06h) ................................15 Reconfigure Device Cmd (07h) .................................15 **Electrical Specifications ................................................16** Absolute Maximum Ratings .......................................16 Operating Temperature .............................................16 DC Electrical Characteristics .....................................17 AC Electrical Characteristics .....................................19 **Packaging Dimensions ..................................................21** Thermal Impedances .................................................23 Solder Reflow Specifications .....................................23 **Features and Ordering Information ..............................24** Ordering Code Definitions .........................................24 **Acronyms ........................................................................25 Reference Documents ....................................................25 Document Conventions .................................................25** Units of Measure .......................................................25 **Numeric Conventions ....................................................25** Numeric Naming ........................................................25 **Glossary ..........................................................................26 Errata ...............................................................................30** Part Numbers Affected ..............................................30 Qualification Status ...................................................30 Errata Summary ........................................................30 **Document History Page .................................................31 Sales, Solutions, and Legal Information ......................32** Worldwide Sales and Design Support .......................32 Products ....................................................................32 PSoC® Solutions ......................................................32 Cypress Developer Community .................................32 Technical Support .....................................................32 

Page 2 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** 

## **Architecture** 

The Top Level Block Diagram on page 1 illustrates the device block diagram. The main blocks include the control unit, PWMs, EEPROM, and I/O ports. The control unit executes commands received from the I[2] C bus and transfers data between other bus devices and the master device. 

The on chip EEPROM can be separated conventionally into two regions. The first region is designed to store data and is available for byte wide read/writes through the I[2] C bus. It is possible to prevent write operations by setting the WD pin to high. All EEPROM operations can be blocked by configuration register settings. The second region allows the user to store the port and PWM default settings using special commands. These defaults are automatically reloaded and processed after device power on. 

The number of I/O lines and PWM sources are listed in the following table. 

**Table 1.  GPIO Availability** 

|**Port**|**CY8C9520A**|**CY8C9540A**|**CY8C9560A**|
|---|---|---|---|
|GPort 0|8 bit|8 bit|8 bit|
|GPort 1|5-8 bit[1]|5-8bit[1]|5-8 bit[1]|
|GPort 2|0-4 bit[1]|0-4it[1]|0-4 bit[1]|
|GPort 3|–|8 bit|8 bit|
|GPort 4|–|8 bit|8 bit|
|GPort 5|–|4 bit|8 bit|
|GPort 6|–|–|8 bit|
|GPort 7|–|–|8 bit|
|PWMs|4|8|16|



There are four pins on GPort 2 and three on GPort 1 that can be used as general purpose I/O or EEPROM Write Disable (WD) and I[2] C-address input (A1-A6), depending on configuration settings. 

Figure 1 shows the single port logical structure. The Port Drive Mode register gives the option to select one of seven available modes for each pin separately: pulled up/down, open drain high/low, strong drive fast/slow, or high impedance. By default these configuration registers store values setting I/O pins to be pulled up. The Invert register enables inversion of the logic of the Input registers separately for each pin. The Select PWM register assigns pins as PWM outputs. All of these configuration registers are read/writable using corresponding commands in the multi-port device. 

**Figure 1.  Logical Structure of the I/O Port** 

**==> picture [227 x 233] intentionally omitted <==**

**----- Start of picture text -----**<br>
GPortx<br>7 Drive Mode<br>Registers<br>Output<br>Drive Mode Register<br>Pull-Up<br>Data<br>Drive Mode<br>High Z<br>PWMs<br>Select PWM<br>. oe<br>Interrupt<br>Status<br>3<br>Input Register 8 Bit IO<br>Interrupt<br>Mask<br>|<br>Pin Direction Inversion<br>Ff ft<br>**----- End of picture text -----**<br>


The Port Input and Output registers are separated. When the Output register is written, the data is sent to the external pins. When the Input register is read, the external pin logic levels are captured and transferred. As a result, the read data can be different from written Output register data. This enables implementation of a quasi-bidirectional input-output mode, when the corresponding binary digit is configured as pulled up/down output. 

Each port has an Interrupt Mask register and an Interrupt Status register. Each high bit in the Interrupt Status register signals that there has been a change in the corresponding input line since the last read of that Interrupt Status register. The Interrupt Status register is cleared after each read. The Interrupt Mask register enables/disables activation of the INT line when input levels are changed. Each high in the Interrupt Mask register masks (disables) an interrupt generated from the corresponding input line. 

## **Applications** 

Each GPIO pin can be used to monitor and control various board level devices, including LEDs and system intrusion detection devices. 

The on board EEPROM can be used to store information such as error codes or board manufacturing data for read-back by application software for diagnostic purposes. 

> 1. This port contains configuration-dependant GPIO lines or A1-A6 and WD lines. 

**Note** 

Page 3 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** 

## **Device Access Addressing** 

Following a start condition, the I[2] C master device sends a byte to address an I[2] C slave. This address accesses the device in the CY8C95xx. By default there are two possible address formats in binary representation: 010000A0X and 101000A0X. The first is used to access the multi port device and the second to access the EEPROM. If additional address lines (A1-A6) are used then the Device Addressing. Table 2 defines the device addresses. This addressing method uses a technique called Extendable Soft Addressing, described in the section Extendable Soft Addressing on page 9. 

**Table 2.  Device Addressing** 

|**Multi-Port Device**<br>~~ee~~<br>~~FTTTITTTrr~~|**Multi-Port Device**<br>~~ee~~<br>~~FTTTITTTrr~~|**Multi-Port Device**<br>~~ee~~<br>~~FTTTITTTrr~~|**Multi-Port Device**<br>~~ee~~<br>~~FTTTITTTrr~~|**Multi-Port Device**<br>~~ee~~<br>~~FTTTITTTrr~~|**Multi-Port Device**<br>~~ee~~<br>~~FTTTITTTrr~~|**Multi-Port Device**<br>~~ee~~<br>~~FTTTITTTrr~~|**Multi-Port Device**<br>~~ee~~<br>~~FTTTITTTrr~~|**EEPROM Device**<br>~~ee~~<br>~~FTTTITTTrr rl~~|**EEPROM Device**<br>~~ee~~<br>~~FTTTITTTrr rl~~|**EEPROM Device**<br>~~ee~~<br>~~FTTTITTTrr rl~~|**EEPROM Device**<br>~~ee~~<br>~~FTTTITTTrr rl~~|**EEPROM Device**<br>~~ee~~<br>~~FTTTITTTrr rl~~|**EEPROM Device**<br>~~ee~~<br>~~FTTTITTTrr rl~~|**EEPROM Device**<br>~~ee~~<br>~~FTTTITTTrr rl~~|**EEPROM Device**<br>~~ee~~<br>~~FTTTITTTrr rl~~|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|01<br>~~FTTTITTTrr~~<br>~~a~~|~~FTTTITTTrr~~<br>~~a~~|0<br>~~FTTTITTTrr~~|0<br>~~FTTTITTTrr~~|0<br>~~FTTTITTTrr~~|0<br>~~FTTTITTTrr~~|A0<br>~~FTTTITTTrr~~|R/W<br>~~FTTTITTTrr~~|1<br>~~FTTTITTTrr~~|0<br>~~FTTTITTTrr rl~~|1<br>~~rl~~|0<br>~~rl~~|0<br>~~rl~~|0<br>~~rl~~|A0<br>~~rl~~|R/W<br>~~rl~~|
|0<br>~~FTTTITTTrr~~<br>~~a~~<br>~~a~~|1<br>~~FTTTITTTrr~~<br>~~a~~<br>~~a~~|0<br>~~FTTTITTTrr~~|0<br>~~FTTTITTTrr~~|0<br>~~FTTTITTTrr~~|A1<br>~~FTTTITTTrr~~|A0<br>~~FTTTITTTrr~~|R/W<br>~~FTTTITTTrr~~|1<br>~~FTTTITTTrr~~|0<br>~~FTTTITTTrr rl~~|1<br>~~rl~~|0<br>~~rl~~|0<br>~~rl~~|A1<br>~~rl~~|A0<br>~~rl~~|R/W<br>~~rl~~|
|0<br>~~a~~<br>~~a~~|1<br>~~a~~<br>~~a~~|0|0|A2|A1|A0|R/W|1|0|1|0|A2|A1|A0|R/W|
|0<br>~~a~~<br>~~a~~|1<br>~~a~~<br>~~a~~|0|A3|A2|A1|A0|R/W|1|0|1|A3|A2|A1|A0|R/W|
|0<br>~~a~~<br>~~a~~|1<br>~~a~~<br>~~a~~|A4|A3|A2|A1|A0|R/W|1|0|A4|A3|A2|A1|A0|R/W|
|0<br>~~a~~<br>~~fs~~|A5<br>~~a~~<br>~~fs~~|A4|A3|A2|A1|A0|R/W|1|A5|A4|A3|A2|A1|A0|R/W|
|A6<br>~~fs~~|A5<br>~~fs~~|A4|A3|A2|A1|A0|R/W|A6|A5|A4|A3|A2|A1|A0|R/W|



When all address lines A1-A6 are used, the device being accessed is defined by the first byte following the address in the write transaction. If the most significant bit (MSb) of this byte is ‘0’, this byte is treated as a command (register address) byte of the multi-port device. If the MSb is ‘1’, this byte is the first of a 2-byte EEPROM address. In this case, the device masks the MSb to determine the EEPROM address. 

To read one or more bytes, the master device addresses the unit with a write cycle (= 0) to send AHI followed by ALO, readdresses the unit with a read cycle (= 1), and reads one or more data bytes. Each data byte read increments the internal address counter by one up to the end of the EEPROM address space. A read or write beyond the end of the EEPROM address space must result in a NAK response by the Port Expander. 

To write data to the EEPROM, the master device performs one write cycle, with the first two bytes being AHI followed by ALO. This is followed by one or more data bytes. In the case of block writing it is advisable to set the starting address on the beginning of the 64-byte boundary, for example 01C0h or 0080h, but this is not mandatory. When a 64-byte boundary is crossed in the EEPROM, the I[2] C clock is stretched while the device performs an EEPROM write sequence. If the end of available EEPROM space is reached, then further writes are responded to with a NAK. 

Refer to Figure 6 on page 10, which illustrates memory reading and writing procedures for the EEPROM device. 

## **Multi Port I/O Device** 

This device allows the user to set configurations and I/O operations through internal registers. 

Each data transfer is preceded by the command byte. This byte is used as a pointer to a register that receives or transmits data. Available registers are listed in Table 6 on page 11. 

## **Serial EEPROM Device** 

EEPROM reading and writing operations require 2 bytes, AHI and ALO, which indicate the memory address to use. 

Page 4 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** 

## **Pinouts** 

The CY8C95xxA device is available in a variety of packages, which are listed and illustrated in the following tables. 

## **28-Pin Part Pinout** 

**Table 3.  28-Pin Part Pinout (SSOP)** 

|**Pin**<br>**No.**<br>~~ee~~|**Pin Name**<br>~~ee~~|**Description**<br>~~ee~~|
|---|---|---|
|1<br>~~ee~~<br>~~a~~|GPort0_Bit0_PWM3<br>~~ee~~|Port 0, Bit 0, PWM 3.<br>~~ee~~|
|2<br>~~a~~|GPort0_Bit1_PWM1|Port 0, Bit 1, PWM 1.|
|3<br>~~a~~<br>~~a~~|GPort0_Bit2_PWM3|Port 0, Bit 2, PWM 3.|
|4<br>5<br>~~a~~<br>~~a~~|GPort0_Bit3_PWM1<br>GPort0_Bit4_PWM3|Port 0, Bit 3, PWM 1.<br>Port 0, Bit 4, PWM 3.|
|5<br>6<br>~~a~~<br>~~a~~|GPort0_Bit4_PWM3<br>GPort0_Bit5_PWM1|Port 0, Bit 4, PWM 3.<br>Port 0, Bit 5, PWM 1.|
|6<br>7<br>~~a~~<br>~~a~~|GPort0_Bit5_PWM1<br>GPort0_Bit6_PWM3|Port 0, Bit 5, PWM 1.<br>Port 0, Bit 6, PWM 3.|
|7<br>8<br>~~a~~<br>~~a~~|GPort0_Bit6_PWM3<br>GPort0_Bit7_PWM1|Port 0, Bit 6, PWM 3.<br>Port 0, Bit 7, PWM 1.|
|8<br>~~a~~<br>~~a~~|GPort0_Bit7_PWM1|Port 0, Bit 7, PWM 1.<br>Ground connection.|
|9<br>~~a~~<br>~~a~~|VSS<br>~~2~~|Ground connection.<br>~~2~~|
|10<br>~~a~~<br>~~a~~|I~~2~~C Serial Clock (SCL)<br>~~2~~|I~~2~~C Clock.<br>~~2~~|
|11<br>~~a~~|I~~2~~C Serial Data (SDA)|I~~2~~C Data.|
|12<br>~~a~~|GPort2_Bit3_PWM3/A1|Port 2, Bit 3, PWM 3, Address 1.|
|13<br>~~a~~|A0|Address 0.|
|14<br>~~a~~|VSS|Ground connection.|
|15<br>~~a~~<br>~~a~~|GPort2_Bit2_PWM0/WD|Port 2, Bit 2, PWM 0, E~~2~~Write Disable.|
|16<br>~~a~~<br>~~a~~|INT<br>||
|17<br>~~es~~|GPort2_Bit1_PWM0/A2<br>~~es~~|Port 2, Bit 1, PWM 0, Address 2.<br>~~es~~|
|18<br>~~es~~|GPort2_Bit0_PWM2/A3<br>~~es~~|Port 2, Bit 0, PWM 2, Address 3.<br>~~es~~|
|19<br>~~es~~<br>~~ee~~|XRES<br>~~es~~<br>~~ee~~|Active high external reset with internal pull<br>down.<br>~~es~~<br>~~ee~~|
|20<br>~~ee~~<br>~~a~~|GPort1_Bit7_PWM0/A4<br>~~ee~~|Port 1, Bit 7, PWM 0, Address 4.<br>~~ee~~|
|21<br>~~a~~|GPort1_Bit6_PWM2/A5|Port 1, Bit 6, PWM 2, Address 5.|
|22<br>~~a~~|GPort1_Bit5_PWM0/A6|Port 1, Bit 5, PWM 0, Address 6.|
|23<br>~~a~~<br>~~a~~|GPort1_Bit4_PWM2|Port 1, Bit 4, PWM 2.|
|24<br>~~a~~|GPort1_Bit3_PWM0|Port 1, Bit 3, PWM 0.|
|25<br>~~a~~|GPort1_Bit2_PWM2|Port 1, Bit 2, PWM 2.|
|26<br>~~a~~<br>~~a~~|GPort1_Bit1_PWM0|Port 1, Bit 1, PWM 0.|
|27<br>~~a~~|GPort1_Bit0_PWM2|Port 1, Bit 0, PWM 2.|
|28<br>~~a~~|Vdd|Supply voltage.|



## **Figure 2.  CY8C9520A 28-Pin Device** 

|GPort0_Bit0_PWM3||1||28||Vdd||
|---|---|---|---|---|---|---|---|
|GPort0_Bit1_PWM1||2||27||GPort1_Bit0_PWM2||
|GPort0_Bit2_PWM3||3||26||GPort1_Bit1_PWM0||
|GPort0_Bit3_PWM1<br>GPort0_Bit4_PWM3<br>GPort0_Bit5_PWM1<br>GPort0_Bit6_PWM3<br>GPort0_Bit7_PWM1<br>Vss<br>I2C Serial Clock (SCL)<br>I2C Serial Data (SDA)<br>GPort2_Bit3_PWM3/A1<br>A0<br>Vss||4<br>5<br>6<br>7<br>8<br>9<br>10<br>11<br>12<br>13<br>14|**SSOP**|25<br>24<br>23<br>22<br>21<br>20<br>19<br>18<br>17<br>16<br>15||GPort1_Bit2_PWM2<br>GPort1_Bit3_PWM0<br>GPort1_Bit4_PWM2<br>GPort1_Bit5_PWM0/A6<br>GPort1_Bit6_PWM2/A5<br>GPort1_Bit7_PWM0/A4<br>XRES<br>GPort2_Bit0_PWM2/A3<br>GPort2_Bit1_PWM0/A2<br>INT<br>GPort2_Bit2_PWM0/WD<br>;||



Page 5 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** 

## **48-Pin Part Pinout** 

**Table 4.  48-Pin Part Pinout (SSOP)** 

|**Pin**<br>**No.**<br>~~ee~~|**Pin Name**<br>~~ee~~|**Description**<br>~~ee~~|
|---|---|---|
|1<br>~~a~~<br>~~a~~|GPort0_Bit0_PWM7<br>~~es~~|Port 0, Bit 0, PWM 7.|
|2<br>~~a~~<br>~~a~~|GPort0_Bit1_PWM5<br>~~es~~|Port 0, Bit 1, PWM 5.|
|3<br>~~a~~<br>~~a~~|GPort0_Bit2_PWM3<br>~~es~~|Port 0, Bit 2, PWM 3.|
|4<br>~~a~~<br>~~a~~|GPort0_Bit3_PWM1<br>~~es~~|Port 0, Bit 3, PWM 1.|
|5<br>~~a~~<br>~~a~~<br>~~a~~|GPort0_Bit4_PWM7<br>~~es~~|Port 0, Bit 4, PWM 7.|
|6<br>~~a~~<br>~~a~~|GPort0_Bit5_PWM5<br>~~es~~|Port 0, Bit 5, PWM 5.|
|7<br>~~a~~<br>~~a~~|GPort0_Bit6_PWM3<br>~~es~~|Port 0, Bit 6, PWM 3.|
|8<br>~~a~~<br>~~a~~<br>~~a~~|GPort0_Bit7_PWM1<br>~~es~~|Port 0, Bit 7, PWM 1.|
|9<br>~~a~~<br>~~a~~|GPort3_Bit0_PWM7<br>~~es~~|Port 3, Bit 0, PWM 7.|
|10<br>~~a~~<br>~~a~~<br>~~a~~|GPort3_Bit1_PWM5<br>~~es~~<br>~~es~~|Port 3, Bit 1, PWM 5.|
|11<br>~~a~~<br>~~a~~<br>~~a~~|GPort3_Bit2_PWM3<br>~~es~~|Port 3, Bit 2, PWM 3.|
|12<br>~~a~~|GPort3_Bit3_PWM1<br>~~es~~|Port 3, Bit 3, PWM 1.|
|13<br>~~a~~<br>~~a~~|VSS<br>~~es~~|Ground connection.|
|14<br>~~a~~<br>~~a~~<br>~~a~~|GPort3_Bit4_PWM7<br>~~es~~|Port 3, Bit 4, PWM 7.|
|15<br>~~a~~|GPort3_Bit5_PWM5<br>~~es~~|Port 3, Bit 5, PWM 5.|
|16<br>~~a~~<br>~~a~~|GPort3_Bit6_PWM3<br>~~es~~|Port 3, Bit 6, PWM 3.|
|17<br>~~a~~<br>~~a~~<br>~~a~~|GPort3_Bit7_PWM1<br>~~es~~|Port 3, Bit 7, PWM 1.|
|18<br>~~a~~|GPort5_Bit2_PWM3<br>~~es~~|Port 5, Bit 2, PWM 3.|
|19<br>~~a~~<br>~~a~~|GPort5_Bit3_PWM1<br>~~2~~<br>~~es~~|Port 5, Bit 3, PWM 1.<br>~~2~~|
|20<br>21<br>~~a~~<br>~~a~~<br>~~a~~|I~~2~~C Serial Clock (SCL)<br>I~~2~~C Serial Data (SDA)<br>~~es~~|I~~2~~C Clock.<br>I~~2~~C Data.|
|21<br>22<br>~~a~~<br>~~a~~|I~~2~~C Serial Data (SDA)<br>GPort2_Bit3_PWM3/A1<br>~~es~~|I~~2~~C Data.<br>Port 2, Bit 3, PWM 3, Address 1.|
|22<br>23<br>~~a~~<br>~~a~~<br>~~a~~|GPort2_Bit3_PWM3/A1<br>A0<br>~~es~~|Port 2, Bit 3, PWM 3, Address 1.<br>Address 0.|
|23<br>~~a~~<br>~~a~~|A0<br>~~es~~|Address 0.|
|24<br>~~a~~<br>~~a~~|VSS<br>GPort2_Bit2_PWM0/WD<br>~~es~~|Ground connection.<br>Port 2, Bit 2, PWM 0, E~~2~~Write Disable.|
|25<br>~~a~~<br>~~a~~|GPort2_Bit2_PWM0/WD<br>~~es~~|Port 2, Bit 2, PWM 0, E~~2~~Write Disable.|
|26<br>~~a~~<br>~~a~~|INT<br>~~es~~||
|27<br>~~a~~|GPort2_Bit1_PWM4/A2<br>~~es~~|Port 2, Bit 1, PWM 4, Address 2.|
|28<br>~~a~~<br>~~a~~|GPort2_Bit0_PWM6/A3<br>~~es~~|Port 2, Bit 0, PWM 6, Address 3.|
|29<br>~~a~~<br>~~a~~<br>~~a~~|GPort5_Bit1_PWM0<br>~~es~~|Port 5, Bit 1, PWM 0.|
|30<br>~~a~~|GPort5_Bit0_PWM2<br>~~es~~|Port 5, Bit 0, PWM 2.|
|31<br>~~a~~<br>~~a~~|GPort4_Bit7_PWM0<br>~~es~~|Port 4, Bit 7, PWM 0.|
|32<br>~~a~~<br>~~a~~<br>~~a~~|GPort4_Bit6_PWM2<br>~~es~~|Port 4, Bit 6, PWM 2.|
|33<br>~~a~~|GPort4_Bit5_PWM4<br>~~es~~|Port 4, Bit 5, PWM 4.|
|34<br>~~a~~|GPort4_Bit4_PWM6<br>|Port 4, Bit 4, PWM 6.<br>|
|35<br>~~aee~~|XRES<br>~~ee~~|Active high external reset with internal pull<br>down.<br>~~ee~~|
|36<br>~~a~~|GPort4_Bit3_PWM0<br>~~a~~<br>~~a~~|Port 4, Bit 3, PWM 0.|
|37<br>~~a~~|GPort4_Bit2_PWM2<br>~~a~~|Port 4, Bit 2, PWM 2.|
|38<br>~~a~~<br>~~a~~|GPort4_Bit1_PWM4<br>~~a~~<br>~~a~~|Port 4, Bit 1, PWM 4.|
|39<br>~~a~~|GPort4_Bit0_PWM6<br>~~a~~<br>~~a~~|Port 4, Bit 0, PWM 6.|
|40<br>~~a~~|GPort1_Bit7_PWM0/A4|Port 1, Bit 7, PWM 0, Address 4.|
|41<br>~~a~~<br>~~a~~|GPort1_Bit6_PWM2/A5|Port 1, Bit 6, PWM 2, Address 5.|
|42<br>~~a a~~|GPort1_Bit5_PWM4/A6<br>~~a~~|Port 1, Bit 5, PWM 4, Address 6.|
|43<br>~~a~~|GPort1_Bit4_PWM6|Port 1, Bit 4, PWM 6.|
|44<br>~~a~~<br>~~a~~|GPort1_Bit3_PWM0|Port 1, Bit 3, PWM 0.|
|45<br>~~a a~~|GPort1_Bit2_PWM2<br>~~a~~|Port 1, Bit 2, PWM 2.|
|46<br>~~a~~|GPort1_Bit1_PWM4|Port 1, Bit 1, PWM 4.|
|47<br>~~a~~<br>~~a~~|GPort1_Bit0_PWM6|Port 1, Bit 0, PWM 6.|
|48<br>~~a~~|Vdd|Supply voltage.|



**Figure 3.  CY8C9540A 48-Pin Device** 

|GPort0_Bit0_PWM7<br>GPort0_Bit1_PWM5<br>GPort0_Bit2_PWM3<br>GPort0_Bit3_PWM1<br>GPort0_Bit4_PWM7<br>GPort0_Bit5_PWM5<br>GPort0_Bit6_PWM3<br>GPort0_Bit7_PWM1<br>GPort3_Bit0_PWM7<br>GPort3_Bit1_PWM5<br>GPort3_Bit2_PWM3<br>GPort3_Bit3_PWM1<br>Vss<br>GPort3_Bit4_PWM7||1<br>2<br>3<br>4<br>5<br>6<br>7<br>8<br>9<br>10<br>11<br>12<br>13<br>14|**SSOP**|48<br>47<br>46<br>45<br>43<br>44<br>42<br>40<br>41<br>39<br>38<br>37<br>36<br>35||Vdd<br>GPort1_Bit0_PWM6<br>GPort1_Bit1_PWM4<br>GPort1_Bit2_PWM2<br>GPort1_Bit3_PWM0<br>GPort1_Bit4_PWM6<br>GPort1_Bit5_PWM4/A6<br>GPort1_Bit6_PWM2/A5<br>GPort1_Bit7_PWM0/A4<br>GPort4_Bit0_PWM6<br>GPort4_Bit1_PWM4<br>GPort4_Bit2_PWM2<br>GPort4_Bit3_PWM0<br>XRES|
|---|---|---|---|---|---|---|
|GPort3_Bit5_PWM5<br>GPort3_Bit6_PWM3<br>GPort3_Bit7_PWM1||15<br>16<br>17||33<br>34<br>32||GPort4_Bit4_PWM6<br>GPort4_Bit5_PWM4<br>GPort4_Bit6_PWM2|
|GPort5_Bit2_PWM3<br>GPort5_Bit3_PWM1<br>I2C Serial Clock (SCL)<br>I2C Serial Data (SDA)<br>GPort2_Bit3_PWM3/A1<br>A0<br>Vss||18<br>19<br>20<br>21<br>22<br>23<br>24||31<br>30<br>29<br>28<br>27<br>26<br>25||GPort4_Bit7_PWM0<br>GPort5_Bit0_PWM2<br>GPort5_Bit1_PWM0<br>GPort2_Bit0_PWM6/A3<br>GPort2_Bit1_PWM4/A2<br>INT<br>GPort2_Bit2_PWM0/WD|



Page 6 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** 

## **100-Pin Part Pinout** 

**Table 5.  100-Pin Part Pinout (TQFP)** 

|**Pin**<br>**No.**<br>~~ee~~|**Name**<br>~~ee~~|**Description**<br>~~eS~~|**Pin**<br>**No.**<br>~~0~~|**Name**|**Description**|
|---|---|---|---|---|---|
|1<br>~~ee~~<br>~~a~~|DNU<br>~~ee~~<br>~~a~~<br>~~a~~|DNU = Do Not Use; leave floating.<br>~~eS ~~|51<br> ~~0~~|DNU|DNU = Do Not Use; leave floating.|
|2<br>~~a~~<br>~~a~~|DNU<br>~~a~~<br>~~a~~<br>~~a~~<br>~~ee~~|DNU = Do Not Use; leave floating.<br>~~ee~~|52<br>~~(eG~~|GPort5_Bit1_PWM8<br>~~(eG~~|Port 5, Bit 1, PWM 8.<br>~~(eG~~|
|3<br>~~a~~|GPort0_Bit3_PWM1|Port 0, Bit 3, PWM 1.|53|GPort5_Bit0_PWM10|Port 5, Bit 0, PWM 10.|
|4<br>~~a~~<br>~~a~~|GPort0_Bit4_PWM7|Port 0, Bit 4, PWM 7.|54|GPort5_Bit4_PWM12|Port 5, Bit 4, PWM 12.|
|5<br>~~a~~<br>~~a~~|GPort0_Bit5_PWM5<br>~~ee~~|Port 0, Bit 5, PWM 5.<br>~~ee~~|55<br>~~(eG~~|GPort5_Bit5_PWM14<br>~~(eG~~|Port 5, Bit 5, PWM 14.<br>~~(eG~~|
|6<br>~~a~~|GPort0_Bit6_PWM3|Port 0, Bit 6, PWM 3.|56|GPort4_Bit7_PWM8|Port 4, Bit 7, PWM 8.|
|7<br>~~a~~<br>~~a~~|GPort0_Bit7_PWM1|Port 0, Bit 7, PWM 1.|57|GPort4_Bit6_PWM10|Port 4, Bit 6, PWM 10.|
|8<br>~~a~~<br>~~a~~|GPort3_Bit0_PWM7<br>~~ee~~|Port 3, Bit 0, PWM 7.<br>~~ee~~|58<br>~~(eG~~|GPort4_Bit5_PWM12<br>~~(eG~~|Port 4, Bit 5, PWM 12.<br>~~(eG~~|
|9<br>~~a~~|GPort3_Bit1_PWM5|Port 3, Bit 1, PWM 5.|59|GPort4_Bit4_PWM14|Port 4, Bit 4, PWM 14.|
|10<br>~~a~~<br>~~a~~|GPort3_Bit2_PWM3|Port 3, Bit 2, PWM 3.|60|DNU|DNU = Do Not Use; leave floating.|
|11<br>~~a~~<br>~~a~~|GPort3_Bit3_PWM1<br>~~ee~~|Port 3, Bit 3, PWM 1.<br>~~ee~~|61<br>~~(eG~~|DNU<br>~~(eG~~|DNU = Do Not Use; leave floating.<br>~~(eG~~|
|12<br>~~a~~<br><br>~~a~~|DNU<br>~~a~~<br>~~a~~<br>~~es~~<br>|DNU = Do Not Use; leave floating.<br>|62<br>|XRES<br>|Active high external reset with internal pull down.<br>|
|13<br>~~a~~<br>~~a~~|DNU<br>~~aes~~<br>|DNU = Do Not Use; leave floating.<br>|63<br>|GPort4_Bit3_PWM0<br>|Port 4, Bit 3, PWM 0.<br>|
|14<br>~~a~~<br>~~a~~|DNU<br>~~aes~~<br>~~ee~~|DNU = Do Not Use; leave floating.<br>~~ee~~|64<br>~~(eG~~|GPort4_Bit2_PWM2<br>~~(eG~~|Port 4, Bit 2, PWM 2.<br>~~(eG~~|
|15<br>~~a~~<br><br>~~a~~|VSS<br>~~a~~<br>~~a~~<br>~~rs~~<br>|Ground connection.<br>|65<br>|VSS<br>|Ground connection.<br>|
|16<br>~~a~~<br>~~a~~|GPort3_Bit4_PWM15<br>~~ars~~<br>|Port 3, Bit 4, PWM 15.<br>|66<br>|GPort4_Bit1_PWM4<br>|Port 4, Bit 1, PWM 4.<br>|
|17<br>~~a~~<br>~~a~~|GPort3_Bit5_PWM13<br>~~ars~~<br>~~ee~~|Port 3, Bit 5, PWM 13.<br>~~ee~~|67<br>~~(eG~~|GPort4_Bit0_PWM6<br>~~(eG~~|Port 4, Bit 0, PWM 6.<br>~~(eG~~|
|18<br>~~a~~<br><br>~~a~~|GPort3_Bit6_PWM11<br>~~a~~<br>~~a~~<br>~~rs~~<br>|Port 3, Bit 6, PWM 11.<br>|68<br>|GPort1_Bit7_PWM0/A4<br>|Port 1, Bit 7, PWM 0, Address 4.<br>|
|19<br>~~a~~<br>~~a~~|GPort3_Bit7_PWM9<br>~~ars~~<br>|Port 3, Bit 7, PWM 9.<br>|69<br>|GPort1_Bit6_PWM2/A5<br>|Port 1, Bit 6, PWM 2, Address 5.<br>|
|20<br>~~a~~<br>~~a~~|GPort5_Bit7_PWM15<br>~~ars~~<br>~~ee~~|Port 5, Bit 7, PWM 15.<br>~~ee~~|70<br>~~(eG~~|GPort1_Bit5_PWM4/A6<br>~~(eG~~|Port 1, Bit 5, PWM 4, Address 6.<br>~~(eG~~|
|21<br>~~a~~<br><br>~~a~~|GPort5_Bit6_PWM13<br>~~a~~<br>~~a~~<br>~~rs~~<br>|Port 5, Bit 6, PWM 13.<br>|71<br>|DNU<br>|DNU = Do Not Use; leave floating.<br>|
|22<br>~~a~~<br>~~a~~|GPort5_Bit2_PWM11<br>~~ars~~<br>|Port 5, Bit 2, PWM 11.<br>|72<br>|GPort1_Bit4_PWM6<br>|Port 1, Bit 4, PWM 6.<br>|
|23<br>~~a~~<br>~~a~~|GPort5_Bit3_PWM9<br>~~2~~<br>~~ars~~<br>~~ee~~|Port 5, Bit 3, PWM 9.<br>~~2~~<br>~~ee~~|73<br>~~(eG~~|DNU<br>~~(eG~~|DNU = Do Not Use; leave floating.<br>~~(eG~~|
|24<br>~~a~~|I~~2~~C Serial Clock (SCL)<br>~~a~~<br>~~a~~|I~~2~~C Clock.<br>~~a~~<br>~~a~~|74<br>~~a~~|GPort1_Bit3_PWM0|Port 1, Bit 3, PWM 0.|
|25<br>~~a~~|DNU<br>~~a~~|DNU = Do Not Use; leave floating.<br>~~a~~|75|DNU|DNU = Do Not Use; leave floating.|
|26<br>~~a~~<br>~~a~~|DNU<br>~~a~~<br>~~a~~<br>~~ee~~|DNU = Do Not Use; leave floating.<br>~~a~~<br>~~a~~<br>~~ee~~|76<br>~~(eG~~|DNU<br>~~(eG~~|DNU = Do Not Use; leave floating.<br>~~(eG~~|
|27<br>~~a~~|DNU<br>~~2~~<br>~~a~~<br>~~a~~|DNU = Do Not Use; leave floating.<br>~~2~~<br>~~a~~<br>~~a~~|77<br>~~a~~|GPort1_Bit2_PWM2|Port 1, Bit 2, PWM 2.|
|28<br>~~a~~|I~~2~~C Serial Data (SDA)<br>~~a~~|I~~2~~C Data.<br>~~a~~|78|DNU|DNU = Do Not Use; leave floating.|
|29<br>~~a~~<br>~~a~~|GPort2_Bit3_PWM11/A1<br>~~a~~<br>~~a~~<br>~~ee~~|Port 2, Bit 3, PWM 11, Address 1.<br>~~a~~<br>~~a~~<br>~~ee~~|79<br>~~(eG~~|GPort1_Bit1_PWM4<br>~~(eG~~|Port 1, Bit 1, PWM 4.<br>~~(eG~~|
|30<br>~~a~~|A0<br>~~a~~<br>~~a~~|Address 0.<br>~~a~~<br>~~a~~|80<br>~~a~~|DNU|DNU = Do Not Use; leave floating.|
|31<br>~~a~~|DNU<br>~~a~~|DNU = Do Not Use; leave floating.<br>~~a~~|81|GPort1_Bit0_PWM6|Port 1, Bit 0, PWM 6.|
|32<br>~~a~~<br>~~a~~|Vdd<br>~~a~~<br>~~a~~<br>~~ee~~|Supply voltage.<br>~~a~~<br>~~a~~<br>~~ee~~|82<br>~~(eG~~|Vdd<br>~~(eG~~|Supply voltage.<br>~~(eG~~|
|33<br>~~a~~|DNU<br>~~a~~<br>~~a~~|DNU = Do Not Use; leave floating.<br>~~a~~<br>~~a~~|83<br>~~a~~|Vdd|Supply voltage.|
|34<br>~~a~~|VSS<br>~~a~~|Ground connection.<br>~~a~~|84|VSS|Ground connection.|
|35<br>~~a~~<br>~~a~~|DNU<br>~~a~~<br>~~a~~<br>~~ee~~|DNU = Do Not Use; leave floating.<br>~~a~~<br>~~a~~<br>~~ee~~|85<br>~~(eG~~|VSS<br>~~(eG~~|Ground connection.<br>~~(eG~~|
|36<br>~~a~~|GPort7_Bit7_PWM15|Port 7, Bit 7, PWM 15.|86|GPort6_Bit0_PWM0|Port 6, Bit 0, PWM 0.|
|37<br>~~a~~|GPort7_Bit6_PWM14|Port 7, Bit 6, PWM 14.|87|GPort6_Bit1_PWM1|Port 6, Bit 1, PWM 1.|
|38<br>~~a~~<br>~~a~~|GPort7_Bit5_PWM13<br>~~ee~~|Port 7, Bit 5, PWM 13.<br>~~ee~~|88<br>~~(eG~~|GPort6_Bit2_PWM2<br>~~(eG~~|Port 6, Bit 2, PWM 2.<br>~~(eG~~|
|39<br>~~a~~|GPort7_Bit4_PWM12<br>~~a~~<br>~~a~~|Port 7, Bit 4, PWM 12.<br>~~a~~<br>~~a~~|89<br>~~a~~|GPort6_Bit3_PWM3|Port 6, Bit 3, PWM 3.|
|40<br>~~a~~<br>~~a~~|GPort7_Bit3_PWM11<br>~~a~~<br>~~a~~<br>~~a~~|Port 7, Bit 3, PWM 11.<br>~~a~~<br>~~a~~<br>~~a~~|90<br>~~a~~|GPort6_Bit4_PWM4|Port 6, Bit 4, PWM 4.|
|41<br>~~a~~<br>~~a~~|GPort7_Bit2_PWM10<br>~~a~~<br>~~a~~<br>~~ee~~|Port 7, Bit 2, PWM 10.<br>~~a~~<br>~~a~~<br>~~ee~~|91<br>~~(eG~~|GPort6_Bit5_PWM5<br>~~(eG~~|Port 6, Bit 5, PWM 5.<br>~~(eG~~|
|42<br>~~a~~|GPort7_Bit1_PWM9<br>~~a~~<br>~~a~~|Port 7, Bit 1, PWM 9.<br>~~a~~<br>~~a~~|92<br>~~a~~|GPort6_Bit6_PWM6|Port 6, Bit 6, PWM 6.|
|43<br>~~a~~<br>~~a~~|GPort7_Bit0_PWM8<br>~~a~~<br>~~a~~<br>~~a~~|Port 7, Bit 0, PWM 8.<br>~~2~~<br>~~a~~<br>~~a~~<br>~~a~~|93<br>~~a~~|GPort6_Bit7_PWM7|Port 6, Bit 7, PWM 7.|
|44<br>~~a~~<br>~~a~~|GPort2_Bit2_PWM8/WD<br>~~a~~<br>~~a~~<br>~~ee~~|Port 2, Bit 2, PWM 8, E~~2~~Write Disable.<br>~~a~~<br>~~a~~<br>~~ee~~|94<br>~~(eG~~|DNU<br>~~(eG~~|DNU = Do Not Use; leave floating.<br>~~(eG~~|
|45<br>~~a~~|INT<br>~~a~~<br>~~a~~|~~a~~<br>~~a~~|95<br>~~a~~|GPort0_Bit0_PWM7|Port 0, Bit 0, PWM 7.|
|46<br>~~a~~<br>~~a~~|GPort2_Bit1_PWM12/A2<br>~~a~~<br>~~a~~<br>~~a~~|Port 2, Bit 7, PWM 0, Address 4.<br>~~a~~<br>~~a~~<br>~~a~~|96<br>~~a~~|DNU|DNU = Do Not Use; leave floating.|
|47<br>~~a~~<br>~~a~~|GPort2_Bit0_PWM14/A3<br>~~a~~<br>~~a~~<br>~~ee~~|Port 2, Bit 6, PWM 2, Address 5.<br>~~a~~<br>~~a~~<br>~~ee~~|97<br>~~(eG~~|GPort0_Bit1_PWM5<br>~~(eG~~|Port 0, Bit 1, PWM 5.<br>~~(eG~~|
|48<br>~~a~~|DNU<br>~~a~~<br>~~a~~|DNU = Do Not Use; leave floating.<br>~~a~~<br>~~a~~|98<br>~~a~~|DNU|DNU = Do Not Use; leave floating.|
|49<br>~~a~~|DNU<br>~~a~~|DNU = Do Not Use; leave floating.<br>~~a~~|99|GPort0_Bit2_PWM3|Port 0, Bit 2, PWM 3.|
|50<br>~~a~~<br>~~a~~|DNU<br>~~a~~<br>~~a~~<br>~~eG~~|DNU = Do Not Use; leave floating.<br>~~a~~<br>~~a~~<br>~~eG~~|100<br>~~eG~~|DNU<br>~~eG~~|DNU = Do Not Use; leave floating.<br>~~eG~~|



Page 7 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** 

**Figure 4.  CY8C9560A 100-Pin Device**[[2]] 

DNU[a] 1 75 DNU DNU 2 74 GPort1_Bit3_PWM0 GPort0_Bit3_PWM1 3 73 DNU GPort0_Bit4_PWM7 4 72 GPort1_Bit4_PWM6 GPort0_Bit5_PWM5 5 71 DNU GPort0_Bit6_PWM3 6 70 GPort1_Bit5_PWM4/A6 GPort0_Bit7_PWM1 7 69 GPort1_Bit6_PWM2/A5 GPort3_Bit0_PWM7 8 68 GPort1_Bit7_PWM0/A4 GPort3_Bit1_PWM5 9 67 GPort4_Bit0_PWM6 GPort3_Bit2_PWM3 10 66 GPort4_Bit1_PWM4 GPort3_Bit3_PWM1 11 65 Vss DNU 12 64 GPort4_Bit2_PWM2 DNU 13 **TQFP** 63 GPort4_Bit3_PWM0 DNU 14 62 XRES Vss 15 61 DNU GPort3_Bit4_PWM15 16 60 DNU GPort3_Bit5_PWM13 17 59 GPort4_Bit4_PWM14 GPort3_Bit6_PWM11 18 58 GPort4_Bit5_PWM12 GPort3_Bit7_PWM9 19 57 GPort4_Bit6_PWM10 GPort5_Bit7_PWM15 20 56 GPort4_Bit7_PWM8 GPort5_Bit6_PWM13 21 55 GPort5_Bit5_PWM14 GPort5_Bit2_PWM11 22 54 GPort5_Bit4_PWM12 GPort5_Bit3_PWM9 23 53 GPort5_Bit0_PWM10 I2C Serial Clock (SCL) 24 52 GPort5_Bit1_PWM8 DNU 25 51 DNU 

**Note** 

2. DNU = Do Not Use; leave floating. 

Page 8 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** 

## **Pin Descriptions** 

## **Extendable Soft Addressing** 

The A0 line defines the corresponding bit of the I[2] C address. This pin must be pulled up or down. If A0 is a strong pull up or a strong pull down (wired through 330 or less resistor to Vdd or Vss), then that is the only address line being specified and the A1-A6 lines are used as GPIO. If A0 is a weak pull up or a weak pull down (connected to Vdd or Vss through 75K- 200K ohm resistor), then A0 is not the only externally defined address bit. There is a pin assigned to be A1 if it is needed. This pin can be pulled up or pulled down strong or weak with a resistor. As with A0, the type of pull determines whether the address bit is the last externally defined address bit. Differently from A0, A1 is not dedicated as an address pin. It is only used if A0 is not the only address bit externally defined. There are also predefined pins for A2, A3, A4, A5, and A6 that is only used for addressing if needed. The last address bit in the chain is pulled strong. That way, only the number of pins needed to assign the address desired for the part are allocated as address pins, any pins not used for address bits can be used as GPIO pins. The Table 2 on page 4 defines the resulting device I[2] C address. 

**Note:** It is not recommended to share pull up/down resistors between multiple devices. 

POR. When the part is held in reset, all In and Out pins are held at their default High-Z State. 

## **Working with PWMs** 

There are four independent PWMs in the CY8C9520A, eight in the CY8C9540A and sixteen in the CY8C9560A. Each I/O pin can be configured as a PWM output by writing ‘1’ to the corresponding bit of the Select PWM register (see Table 7 on page 12). 

The next step of PWM configuration is clock source selection using the Config PWM registers. There are six available clock sources: 32 kHz (default), 24 MHz, 1.5 MHz, 93.75 kHz, 367.6 Hz or previous PWM output. (see Figure 5) 

## **Figure 5.  Clock Sources** 

**==> picture [167 x 71] intentionally omitted <==**

**----- Start of picture text -----**<br>
32 kHz<br>24 mHz<br>1.5 mHz<br>93.75 kHz<br>367.6 Hz  -<br>Divider (1-255)<br>—— 93.75 kHz<br>**----- End of picture text -----**<br>


## **Interrupt Pin (INT)** 

The interrupt output (if enabled) is activated if one of these events occurs: 

- One of the GPIO port pins changes state and the corresponding bit in the Interrupt Mask register is set low. 

- When a PWM driven by the slowest clock source (367.6 Hz) and assigned to a pin changes state and the pin’s corresponding bit in the Interrupt Mask register is set low. 

The interrupt line is deactivated when the master device performs a read from the corresponding Interrupt Status register. The INT output is active high output and the drive mode of this pin is strong drive mode. 

## **Write Disable Pin (WD)** 

If this feature is enabled, ‘0’ allows writes to the EEPROM and ‘1’ blocks any memory writes. This pin is checked immediately before performing any write to memory. If the EEE bit in the Enable register is not set (EEPROM disabled) or bit EERO is set (EEPROM is read-only) then WD line level is ignored. 

By default, 32 kHz is selected as the PWM clock. 

PWM Period registers are used to set the output period: 

**==> picture [113 x 13] intentionally omitted <==**

Allowed values are between 1 and FFh. 

The PWM Pulse Width register sets the duration of the PWM output pulse. Allowed values are between zero and the (Period-1) value. The duty cycle ratio is computed using thsi equation: 

**==> picture [138 x 24] intentionally omitted <==**

Note that ‘1’ on this line blocks all commands that perform operations with EEPROM (see Table 14 on page 14). 

This line may be enabled/disabled by bit 1 of the Enable register (2Dh): ‘1’ enables WD function, ‘0’ disables. 

## **External Reset Pin (XRES)** 

A full device reset is caused by pulling the XRES pin high. The XRES pin has an always-on pull down resistor, so it does not require an external pull down for operation. It can be tied directly to ground or left open. Behavior after XRES is similar to 

Page 9 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** 

**Figure 6.  Memory Reading and Writing** 

**==> picture [455 x 234] intentionally omitted <==**

**----- Start of picture text -----**<br>
Slave Address Memory Address<br>R/W R/W Stop<br>S A6 A5 A4 A3 A2 A1 A0 0 A High(Addr) A Low(Addr) A S A6 A5 A4 A3 A2 A1 A0 1 A data(Addr) A data(Addr+1) A ... N P<br>OO<br>Start ACK from ACK from ACK from ACK from ACK from ACK from No ACK<br>Slave Slave Slave Slave Master Master from Master<br>Reading from EEPROM<br>Slave Address Memory Address Up to the End of Address Space<br>R/W Stop<br>S A6 A5 A4 A3 A2 A1 A0 0 A High(Addr) A Low(Addr) A data 1 A data 2 A ... A P<br>Start ACK from ACK from ACK from<br>Slave Slave Slave<br>If current address crosses<br>64-byte block boundary,<br>Writing to EEPROM then device performs realwriting to EEPROM<br>**----- End of picture text -----**<br>


**Figure 7.  Port Reading and Writing in Multi-Port Device** 

**==> picture [455 x 225] intentionally omitted <==**

**----- Start of picture text -----**<br>
Slave Address Register Address = 1 Reading from GPort 2<br>At this moment, device<br>performs reading from GPort 1<br>H H ' i<br>R/W R/W Stop<br>S A6 A5 A4 A3 A2 A1 A0 0 A 0 0 0 0 0 0 0 1 A S A6 A5 A4 A3 A2 A1 A0 1 A data from GPort1 A data from GPort 2 A ... N P<br>A AA<br>Start ACK from ACK from ACK from No ACK<br>Slave Slave Master from Master<br>Reading from GPort 1<br>Slave Address Register Address = 09h Output to GPort 2 Output to GPort 3<br>At this moment, device<br>performs output to GPort 1<br>H' H '<br>R/W Stop<br>S A6 A5 A4 A3 A2 A1 A0 0 A 0 0 0 0 1 0 0 1 A data from GPort1 A data from GPort 2 A data from GPort 3 A ... P<br># # * # K<br>Start ACK from ACK from ACK from ACK from<br>Slave Slave Slave Slave<br>Writing from GPort 1<br>**----- End of picture text -----**<br>


Page 10 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** 

## **Register Mapping Table** 

The register address is auto-incrementing. If the master device writes or reads data to or from one register and then continues data transfer in the same I[2] C transaction, sequential bytes are written or read to or from the following registers. For example, if the first byte is sent to the Output Port 1 register, then the next bytes are written to Output Port 2, Output Port 3, Output Port 4 etc. The first byte of each write transaction is treated as the register address. 

To read data from a seires of registers, the master device must write the starting register address byte then perform a start and series of read transactions. If no address was sent, reads start from address 0. 

To read a specific register address, the master device must write the register address byte, then perform a start and read transaction. 

See Figure 7 on page 10. 

The device’s register mapping is listed in Table 6. 

**Table 6.  The Device Register Address Map** 

|**Address**<br>~~2~~<br>~~es~~|**Register**<br>~~2~~<br>~~en~~|**Default**<br>**Register Value**<br>~~2~~|
|---|---|---|
|00h<br>~~2~~<br>~~es~~|Input Port 0<br>~~2~~<br>~~en~~|None<br>~~2 ~~|
|01h<br><br>~~es~~<br>~~Fr.~~|Input Port 1<br><br>~~en~~<br>~~Fr.~~|None<br> <br>~~Fr.~~|
|02h<br>~~Fr.~~<br>~~FOUTS~~|Input Port 2<br>~~Fr.~~<br>~~FOUTS~~|None<br>~~Fr.~~<br>~~FOUTS~~|
|03h<br>~~FOUTS~~<br>~~POO~~|Input Port 3<br>~~FOUTS~~<br>~~POO~~|None<br>~~FOUTS~~<br>~~POO~~|
|04h<br>~~POO~~<br>~~Fr.~~|Input Port 4<br>~~POO~~<br>~~Fr.~~|None<br>~~POO~~<br>~~Fr.~~|
|05h<br>~~Fr.~~<br>~~FOUTS~~|Input Port 5<br>~~Fr.~~<br>~~FOUTS~~|None<br>~~Fr.~~<br>~~FOUTS~~|
|06h<br>~~FOUTS~~<br>~~POO~~|Input Port 6<br>~~FOUTS~~<br>~~POO~~|None<br>~~FOUTS~~<br>~~POO~~|
|07h<br>~~POO~~<br>~~OS~~<br>~~T_T~~|Input Port 7<br>~~POO~~<br>~~OS~~<br>~~T_T~~|None<br>~~POO~~<br>~~OS~~<br>~~T_T~~|
|08h<br>~~T_T~~<br>~~es~~|Output Port 0<br>~~T_T~~|FFh<br>~~T_T~~|
|09h<br>~~T_T~~<br>~~es~~<br>~~es~~|Output Port 1<br>~~T_T~~<br>~~ee~~|FFh<br>~~T_T~~<br>~~ee~~|
|0Ah<br>~~es~~<br>~~es~~<br>~~es~~|Output Port 2<br>~~ee~~|FFh<br>~~ee~~|
|0Bh<br>~~es~~<br>~~es~~<br>~~es~~|Output Port 3<br>~~ee~~|FFh<br>~~ee~~|
|0Ch<br>~~es~~<br>~~es~~<br>~~es~~|Output Port 4<br>~~ee~~|FFh<br>~~ee~~|
|0Dh<br>~~es~~<br>~~es~~<br>~~ee~~|Output Port 5<br>~~ee~~|FFh<br>~~ee~~|
|0Eh<br>~~es~~<br>~~ee~~<br>~~es~~|Output Port 6<br>~~ee~~|FFh<br>~~ee~~|
|0Fh<br>~~ee~~<br>~~es~~|Output Port 7|FFh|
|10h<br>~~es~~<br>~~a~~<br>~~es~~|Interrupt Status Port 0|00h|
|11h<br>~~a~~<br>~~es~~<br>~~es~~|Interrupt Status Port 1|00h|
|12h<br>~~es~~<br>~~es~~<br>~~es~~|Interrupt Status Port 2<br>~~ee~~|00h<br>~~ee~~|
|13h<br>~~es~~<br>~~es~~<br>~~es~~|Interrupt Status Port 3<br>~~ee~~|00h<br>~~ee~~|
|14h<br>~~es~~<br>~~es~~<br>~~es~~|Interrupt Status Port 4<br>~~ee~~|00h<br>~~ee~~|
|15h<br>~~es~~<br>~~es~~<br>~~es~~|Interrupt Status Port 5<br>~~ee~~|00h<br>~~ee~~|
|16h<br>~~es~~<br>~~es~~<br>~~es~~|Interrupt Status Port 6<br>~~ee~~|00h<br>~~ee~~|
|17h<br>~~es~~<br>~~es~~|Interrupt Status Port 7<br>~~ee~~|00h<br>~~ee~~|
|18h<br>~~es~~<br>~~a~~<br>~~es~~|Port Select<br>~~ee~~|00h<br>~~ee~~|
|19h<br>~~a~~<br>~~es~~|Interrupt Mask<br>~~ee~~|FFh<br>~~ee~~|



**Table 6.  The Device Register Address Map** (continued) 

|**Address**<br>~~ee~~|**Register**|**Default**<br>**Register Value**|
|---|---|---|
|1Ah<br>~~ee~~<br>~~es~~|Select PWM for Port Output <br>~~ee~~|00h<br>~~ee~~|
|1Bh<br>~~ee~~<br>~~es~~<br>~~es~~|Inversion<br>~~ee~~|00h<br>~~ee~~|
|1Ch<br>~~es~~<br>~~es~~<br>~~ee~~|Pin Direction - Input/Output<br>~~ee~~<br>~~ee~~|00h<br>~~ee~~<br>~~ee~~|
|1Dh<br>~~es~~<br>~~ee~~|Drive Mode - Pull Up<br>~~ee~~|FFh<br>~~ee~~|
|1Eh<br>~~ee~~|Drive Mode - Pull Down<br>~~ee~~|00h<br>~~ee~~<br>~~eee~~|
|1Fh<br>~~a ee~~|Drive Mode - Open Drain<br>High<br>~~ee~~|00h<br>~~ee~~<br>~~eee~~|
|20h<br>~~a ee~~<br>~~es~~|Drive Mode - Open Drain<br>Low<br>~~ee~~|00h<br>~~ee~~<br>~~eee~~|
|21h<br>~~es~~<br>~~ee~~|Drive Mode - Strong<br>~~ee~~|00h<br>~~ee~~|
|22h<br>~~es~~<br>~~ee~~<br>~~ee~~|Drive Mode - Slow Strong<br>~~ee~~|00h<br>~~ee~~|
|23h<br>~~ee~~<br>~~ee~~<br>~~es~~|Drive Mode - High-Z<br>~~ee~~|00h<br>~~ee~~|
|24h<br>~~ee~~<br>~~es~~<br>~~es~~|Reserved|None|
|25h<br>~~es~~<br>~~es~~<br>~~ee~~<br>|Reserved<br>|None<br>|
|26h<br>~~es~~<br>~~ee~~<br>~~ee~~|Reserved<br>~~eee~~|None<br>~~eee~~|
|27h<br>~~ee~~<br>~~ee~~|Reserved<br>~~eee~~|None<br>~~eee~~|
|28h<br>~~ee~~<br> ~~ee~~|PWM Select<br>~~eee~~<br>~~PO~~|00h<br>~~eee~~|
|29h<br> ~~ee~~|Config PWM<br>~~eee~~<br>~~PO~~|00h<br>~~eee~~|
|2Ah|Period PWM|FFh|
|2Bh|Pulse Width PWM|80h|
|2Ch|Programmable Divider|FFh|
|2Dh|Enable WDE, EEE, EERO|00h|
|2Eh|Device ID/Status|20h/40h/60h|
|2Fh<br>~~rE~~|Watchdog|00h|
|30h<br>~~rE~~|Command|00h|



## **Register Descriptions** 

The registers for the CY8C95xx are described in the sections that follow. Note that the PWM registers are located at addresses 28h to 2Bh. 

## **Input Port Registers (00h–07h)** 

These registers represent actual logical levels on the pins and are used for I/O port reading operations. They are read only. The Inversion registers changes the state of reads to these ports. 

## **Output Port Registers (08h–0Fh)** 

These registers are used for writing data to GPIO ports. By default, all ports are in the pull up mode allowing quasi-bidirectional I/O. To allow input operations without reconfiguration, these registers have to store ’1’s. 

Output register data also affects pin states when PWMs are enabled. See Table 7 on page 12 for details. 

See Figure 7 on page 10 illustrates port read/write procedures. 

The Inversion registers have no effect on these ports. 

Page 11 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** 

## **Int. Status Port Registers (10h–17h)** 

Each ’1’ bit in these registers signals that there was a change in the corresponding input line since the last read of that Interrupt Status register. Each Interrupt (Int.) Status register is cleared only after a read of that register. 

If a PWM is assigned to a pin, then all state changes of the PWM sets the corresponding bit in the Interrupt Status register. If the pin's interrupt mask is cleared and the PWM is set to the slowest possible rate allowed (driven by the programmable clock source with divide register 2Dh set to FFh), then the INT line also drives on the PWM state change. 

## **Port Select Register (18h)** 

This register configures the GPort. Write a value of 0–7 to this register to select the port to program with registers 19h–23h. 

## **Interrupt Mask Port Register (19h)** 

The Interrupt Mask register enables or disables activation of the INT line when GPIO input levels are changed. Each ’1’ in the Interrupt Mask register masks (disables) interrupts generated from the corresponding input line of the GPort selected by the Port Select register (18h). 

## **Select PWM Register (1Ah)** 

This register allows each port to act as a PWM output. By default, all ports are configured as GPIO lines. Each ’1’ in this register connects the corresponding pin of the GPort selected by the Port Select register (18h) to the PWM output. Output register data also affects the pin state when a PWM is enabled. See Table 7. 

Note that a pin used as PWM output must be configured to the appropriate drive mode. See Table 9 for more information. 

Table 7 describes the logic of the Output and Select PWM registers. 

**Table 7.  Output and Select PWM Registers Logic** 

|**Output**|**Select PWM**|**Pin State**|
|---|---|---|
|0|0|0|
|1|0|1|
|0|1|0|
|1|1|Current PWM|



## **Inversion Register (1Bh)** 

This register can invert the logic of the input ports. Each ’1’ written to this register inverts the logic of the corresponding bit in the Input register of the GPort selected by the Port Select register (18h). 

The Input registers' logic is presented in Table 8. These registers have no effect on outputs or PWMs. 

**Table 8.  Inversion Register Logic** 

|**Pin State**|**Invert**|**Input**|
|---|---|---|
|0|0|0|
|1|0|1|
|0|1|1|
|1|1|0|



## **Port Direction Register (1Ch)** 

Each bit in a port is configurable as either an input or an output. To perform this configuration, the Port Direction register (1Ch) is used for the GPort selected by the Port Select register (18h). If a bit in this register is set (written with '1'), the corresponding port pin is enabled as an input. If a bit in this register is cleared (written with '0'), the corresponding port pin is enabled as an output. 

## **Drive Mode Registers (1Dh–23h)** 

Each port's data pins can be set separately to one of seven available modes: pull up or down, open drain high/low, strong drive fast/slow, or high-impedance input. To perform this configuration, the seven drive mode registers are used for the GPort selected by the Port Select register (18h). Each ’1’ written to this register changes the corresponding line drive mode. Registers 1Dh through 23h have last register priority meaning that the bit set to high in which the last register was written overrides those that came before. Reading these registers reflects the actual setting, not what was originally written. 

**Table 9.  Drive Mode Register Settings** 

|**Reg.**|**Pin State**|**Description**|
|---|---|---|
|1Dh|Resistive Pull Up|Resistive High, Strong Low<br>(default)|
|1Eh|Resistive Pull Down|Strong High, Resistive Low|
|1Fh|Open Drain High|Slow Strong High, High Z Low|
|20h|Open Drain Low|Slow Strong Low, High Z High|
|21h|Strong Drive|Strong High, Strong Low, Fast<br>Output Mode|
|22h|Slow Strong Drive|Strong High, Strong Low,<br>Slow Output Mode|
|23h|High Impedance|High Z|



## **PWM Select Register (28h)** 

This register is configures the PWM. Write a value of 00h-0Fh to this register to select the PWM to program with registers 29h-2Bh. 

Page 12 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** 

## **Config (29h)** 

This register selects the clock source for the PWM selected by the PWM Select register (28h) and interrupt logic. 

There are six available clock sources: 32 kHz (default), 24 MHz, 1.5 MHz, 93.75 kHz, 367.6 Hz, or previous PWM output. The 367.6 Hz clock is user programmable. It divides the 93.75 kHz clock source by the divisor stored in the Divider register (2Ch). The default divide ratio is 255. (see Table 10 for details). By default, all PWMs are clocked from 32 kHz. 

## **Table 10.  PWM Clock Sources** 

|**Config PWM**|**PWM Clock Source**|
|---|---|
|xxxxx000b|32 kHz (default)|
|xxxxx001b|24 MHz|
|xxxxx010b|1.5 MHz|
|xxxxx011b|93.75 kHz|
|xxxxx100b|367.6 Hz (programmable)|
|xxxxx101b|Previous PWM|



Each PWM can generate an interrupt at the rising or falling edge of the output pulse. There is a limitation on the clock source for a PWM to generate an interrupt. Only the slowest speed source (programmed to 367.6 Hz) with the divider equal to 255 allows interrupt generation. Consequently, to create a PWM interrupt, it is necessary to choose the programmable divider output as the clock source (write xxxxx100b to Config register (29h)), write 255 to the Divide register (2Ch), and select PWM for pin output (1Ah). 

Interrupt status is reflected in the Interrupt Status registers (10h-17h) and can cause INT line activation if enabled by the corresponding mask bit in the Interrupt Mask register: 

## **Period Register (2Ah)** 

## **Table 11.  Period Register** 

|**Config PWM**|**PWM Interrupt on**|
|---|---|
|xxxx0xxxb|Falling pulse edge (default)|
|xxxx1xxxb|Rising pulse edge|



## **Divider Register (2Ch)** 

This register sets the frequency on the output of the programmable divider: 

93.75 _kHz Frequency_  . _Divider_ 

Allowed values are between 1 and 255. 

## **Enable Register (2Dh)** 

The WDE bit configures the write disable pin to operate either as a GPIO or as WD. It also enables/disables EEPROM operations (EEE bit) or makes the EEPROM read-only (EERO bit). Bit assignments are shown in Table 12 on page 13. 

**Table 12.  Enable Register** 

|**Bit**|**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**|
|---|---|---|---|---|---|---|---|---|
|Function|Reserved|||||EERO|EEE|WDE|
|Default|Reserved|||||0|0|0|



Each ’1’ enables the corresponding feature, ’0’ disables. Writes to this register differ from other registers. The write sequence to modify the Enable register is as follows: 

1. Send device I[2] C address with bit 0. 

2. Send register address 2Dh. 

3. Send unlock key - the sequence of three bytes: 43h, 4Dh, 53h; ('C', 'M', 'S' in ASCII bytes). 

4. Send new Enable register value. 

This write sequence secures the register from accidental changes. The register can be read without the use of the unlock key. 

By default, EERO and EEPROM (EEE bit) are disabled and WD line (WDE bit) is set to GPIO (WD disabled). 

When performing a burst write operation that crosses this register, the data written to this register is ignored and the address increments to 2Eh. 

## **Device ID/Status Register (2Eh)** 

This register sets the period of the PWM counter. Allowed values are between 1 and FFh. The effective output waveform period of the PWM is: 

_tOUT_  _Period_  _tCLK_ 

## **Pulse Width Register (2Bh)** 

This register sets the pulse width of the PWM output. Allowed values are between zero and the (Period - 1) value. The duty cycle ratio can be computed using the following equation: 

_PulseWidth DutyCycle_  . _Period_ 

This register stores device identifiers (2xh/4xh/6xh) and reflects which settings were loaded during startup, either factory defaults (FD) or user defaults (UD). By default during startup, the device attempts to load the user default block. If it is corrupted then factory defaults are loaded and the low nibble of this register is set high to inform which set is active. The high nibble is always equal to 2 for CY8C9520A, 4 for CY8C9540A, and 6 for CY8C9560A. 

This register is read-only. 

**Table 13.  Device ID Status Register** 

|**Bit**|**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**|
|---|---|---|---|---|---|---|---|---|
|Function|Device Family (2, 4,or 6)||||Reserved|||FD/UD|



Page 13 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** 

## **Watchdog Register (2Fh)** 

This register controls the internal Watchdog timer. This timer can trigger a device reset if the device is not responding to I[2] C requests due to misconfiguration. Device operation is not affected when the Watchdog register = 0. If the I[2] C master writes any non zero value to the Watchdog register, the countdown mechanism is activated and each second the register is decremented. Upon transition from 1 to 0, the device is rebooted, which restores user defaults. After reboot, the Watchdog register value is reset to zero. Any I[2] C transaction (addressing the Expander) resets the Watchdog register to the previously stored value. Any device reboot (caused by a POR or Watchdog) sets the Watchdog register to zero (turns off the Watchdog feature). The Watchdog timer can be disabled by writing zero to the Watchdog register (2Fh) or by using the Reconfigure Device Cmd (07h). 

**Note** The Watchdog timer is not intended to track precise time intervals. The timer's frequency can vary in range between –50% on up to +100%. This variation must be taken into account when selecting the appropriate value for the Watchdog register. 

## **Command Register (30h)** 

This register sends commands to the device, including current configuration as new POR defaults, restore factory defaults, define POR defaults, read POR defaults, write device configuration, read device configuration, and reconfigure device with stored POR defaults. The command set is presented in Table 14. 

**Note** Registers are not restored in parallel. Do not assume any particular order to the restoration process. 

**Table 14.  Available Commands** 

|**Command**|**Description**|
|---|---|
|01h|Store device configuration to EEPROM POR<br>defaults|
|02h|Restore Factory Defaults|
|03h|Write EEPROM POR defaults|
|04h|Read EEPROM POR defaults|
|05h|Write device configuration|
|06h|Read device configuration|
|07h|Reconfigure device with stored POR defaults|



## **Commands Description** 

## **Store Config to E[2] POR Defaults Cmd (01h)** 

The current ports settings (drive modes and output data) and other configuration registers are saved in the EEPROM by using the store configuration command (Cmd). These settings are automatically loaded after the next device power up or if the 07h command is issued. 

## **Restore Factory Defaults Cmd (02h)** 

This command replaces the saved user configuration with the factory default configuration. Current settings are unaffected by this command. New settings are loaded after the next device power up or if the 07h command is issued. 

## **Write E[2] POR Defaults Cmd (03h)** 

This command sends new power up defaults to the CY8C95xx without changing current settings unless the 07h command is issued afterwards. This command is followed by 147 data bytes according to Table 15. The CRC is calculated as the XOR of the 146 data bytes (00h-91h). If the CRC check fails or an incomplete block is sent, then the slave responds with a NAK and the data does not get saved to EEPROM. 

To define new POR defaults the user must: 

■ Write command 03h 

- Write 146 data bytes with new values of registers 

- Write 1 CRC byte calculated as XOR of previous 146 data bytes. 

Content of the data block is described in Table 15. 

**Table 15.  POR Defaults Data Structure** 

|**Offset**<br>~~ee~~|**Value**<br>~~ee~~|
|---|---|
|00h–07h<br>~~ee~~<br>~~ee~~|Output Port 0–7<br>~~ee~~|
|08h–0Fh<br>~~ee~~|Interrupt mask Port 0–7|
|10h–17h<br>~~ee~~<br>~~ee~~|Select PWM Port 0–7<br>~~ee~~|
|18h–1Fh<br>~~ee~~<br>~~ee~~|Inversion Port 0–7<br>~~ee~~|
|20h–27h<br>~~ee~~<br>~~ee~~|Pin Direction Port 0–7<br>~~ee~~|
|28h<br>~~ee~~<br>~~ee~~|Resistive pull up Drive Mode Port 0<br>~~ee~~|
|29h<br>~~ee~~<br>~~ee~~<br>~~ee~~|Resistive pull down Drive Mode Port 0<br>~~ee~~<br>~~ee~~|
|2Ah<br>~~ee~~<br>~~ee~~|Open drain high Drive Mode Port 0<br>~~ee~~|
|2Bh<br>~~ee~~<br>~~ee~~|Open drain low Drive Mode Port 0<br>~~ee~~|
|2Ch<br>~~ee~~<br>~~ee~~<br>~~ee~~|Strong drive Drive Mode Port 0<br>~~ee~~<br>~~ee~~|
|2Dh<br>~~ee~~<br>~~ee~~|Slow strong drive Drive Mode Port 0<br>~~ee~~|
|2Eh<br>~~ee~~<br>~~ee~~<br>~~ee~~|High impedance Drive Mode Port 0<br>~~ee~~<br>~~ee~~|
|2Fh–35h<br>~~ee~~<br>~~ee~~<br>~~ee~~|Drive Modes Port 1<br>~~ee~~<br>~~ee~~|
|36h–3Ch<br>~~ee~~|Drive Modes Port 2|
|3Dh–43h<br>~~ee~~<br>~~ee~~<br>~~ee~~|Drive Modes Port 3<br>~~ee~~<br>~~ee~~|
|44h–4Ah<br>~~ee~~<br>~~ee~~|Drive Modes Port 4<br>~~ee~~|
|4Bh–51h<br>~~ee~~<br>~~ee~~|Drive Modes Port 5<br>~~ee~~|
|52h–58h<br>~~ee~~<br>~~ee~~<br>~~ee~~|Drive Modes Port 6<br>~~ee~~<br>~~ee~~|
|59h–5Fh<br>~~ee~~<br>~~ee~~<br>~~ee~~|Drive Modes Port 7<br>~~ee~~<br>~~ee~~|
|60h<br>~~ee~~<br>~~ee~~|Config setting PWM0<br>~~ee~~|
|61h<br>~~ee~~<br>~~ee~~|Period setting PWM0<br>~~ee~~|
|62h<br>~~ee~~<br>~~ee~~<br>~~ee~~|Pulse Width setting PWM0<br>~~ee~~<br>~~ee~~|
|63h–65h<br>~~ee~~<br>~~ee~~|PWM1 settings<br>~~ee~~|
|…<br>~~ee~~<br>~~ee~~|…<br>~~ee~~|
|8Dh–8Fh<br>~~ee~~<br>~~ee~~|PWM15 settings<br>~~ee~~<br>~~ee~~|
|90h<br>~~ee~~<br>~~ee~~|Divider<br>~~ee~~<br>~~ee~~|
|91h<br>~~ee~~<br>~~ee~~|Enable<br>~~ee~~<br>~~ee~~|
|92h<br>~~ee~~<br>~~ee~~|CRC<br>~~ee~~<br>~~ee~~|



Page 14 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** 

## **Read E2 POR Defaults Cmd (04h)** 

This command reads the POR settings stored in the EEPROM. To read POR defaults the user must: 

- Write command 04h 

- Read 146 data bytes (see Table 15 on page 14) 

- Read 1 CRC byte. 

## **Write Device Config Cmd (05h)** 

This command sends a new device configuration to the CY8C95xx. It is followed by 146 data bytes according to Table 15. The CRC is calculated as the XOR of the 146 data bytes (00h-91h). If the CRC check fails or an incomplete block is sent, then the slave responds with a NAK and the device does not use the data. This gives the user ‘flat-address-space’ access to all device settings. 

## **Read Device Config Cmd (06h)** 

This command reads the current device configuration. It gives the user ‘flat-address-space’ access to all device settings. 

To read device configuration the user must: 

- Write command 06h 

- Read 146 data bytes (see Table 15 on page 14). 

- Read 1 CRC byte. 

## **Reconfigure Device Cmd (07h)** 

This command immediately reconfigures the device with actual POR defaults from EEPROM. It has the same effect on the registers as a POR. 

To set the current device configuration the user must: 

- Write command 05h 

- Write 146 data bytes with new values of registers 

- Write 1 CRC byte calculated as XOR of previous 146 data bytes. 

If the CRC check passes, then the device uses the new settings immediately. 

Content of the data block is described in Table 15 on page 14. 

Page 15 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** SS Cypress ~~Te~~ **Electrical Specifications** This section lists the DC and AC electrical specifications of the CY8C95xxA device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com. 

Specifications are valid for –40 C  TA  85 C and TJ  100 C, except where noted. 

## **Absolute Maximum Ratings** 

**Table 16.  Absolute Maximum Ratings** 

|**Symbol**|**Description**|**Min**|**Typ**|**Max**|**Units**|**Notes**|
|---|---|---|---|---|---|---|
|TSTG|Storage temperature|–55|25|+100|C|Higher storage temperatures<br>reduces data retention time.<br>Recommended storage temper-<br>ature is +25C ± 25C. Extended<br>duration storage temperatures<br>above 65C degrades reliability.|
|TBAKETEMP|Bake Temperature|–|125|See<br>package<br>label|package<br>C||
|TBAKETIME<br>~~pf~~|Bake Time<br>~~pf~~|See<br>package<br>label<br>~~pf~~|–<br>~~pf~~|72<br>~~pf~~|Hours<br>~~pf~~|~~pf~~|
|TA<br>~~pf~~|Ambient temperature withpower applied<br>~~pf~~|–40<br>~~pf~~|–<br>~~pf~~|+85<br>~~pf~~|C<br>~~pf~~|~~pf~~|
|Vdd<br>~~pf~~<br>~~SS~~<br>~~ee~~|Supplyvoltage on Vdd relative to Vss<br>~~pf~~<br>~~SS~~<br>~~ee~~|–0.5<br>~~pf~~<br>~~SS~~<br>~~ee~~|–<br>~~pf~~<br>~~SS~~<br>~~ee~~|+6.0<br>~~pf~~<br>~~SS~~<br>~~ee~~|V<br>~~pf~~<br>~~SS~~<br>~~ee~~|~~pf~~<br>~~SS~~<br>~~ee~~|
|VIO<br>~~SS~~<br>~~ee~~<br>~~pf~~|DC input voltage<br>~~SS~~<br>~~ee~~<br>~~pf~~|Vss - 0.5<br>~~SS~~<br>~~ee~~<br>|–<br>~~SS~~<br>~~ee~~<br>|Vdd +<br>0.5<br>~~SS~~<br>~~ee~~|V<br>~~SS~~<br>~~ee~~|~~SS~~<br>~~ee~~|
|VIOZ<br>~~ee~~<br>~~pf~~|DC voltage applied to tri-state<br>~~ee~~<br>~~pf~~|Vss - 0.5<br>~~ee~~<br>|–<br>~~ee~~<br>|Vdd +<br>0.5<br>~~ee~~|V<br>~~ee~~|~~ee~~|
|IMIO<br>~~ee~~<br>~~pfa~~|Maximum current into any portpin<br>~~ee~~<br>~~pfa~~|–25<br>~~ee~~<br>~~a~~|–<br>~~ee~~<br>~~a~~|+50<br>~~ee~~|mA<br>~~ee~~|~~ee~~|
|ESD<br>~~pf~~<br>~~ee~~|Electro Static Discharge Voltage<br>~~pf~~<br>~~ee~~<br>~~ee~~|2000<br><br>~~ee~~<br>~~ee~~|–<br><br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|V<br>~~ee~~<br>~~ee~~|Human BodyModel ESD.<br>~~ee~~<br>~~ee~~|
|LU<br>~~ee~~|Latch upcurrent<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|200<br>~~ee~~<br>~~ee~~|mA<br>~~ee~~<br>~~ee~~|~~ee~~<br>~~ee~~|



## **Operating Temperature** 

**Table 17.  Operating Temperature** 

|**Symbol**|**Description**|**Min**|**Typ**|**Max**|**Units**|**Notes**|
|---|---|---|---|---|---|---|
|TA|Ambient temperature|–40|–|+85|C||
|TJ|Junction temperature|–40|–|+100|C|The temperature rise from<br>ambient to junction is package<br>specific. See“Thermal Imped-<br>ances per Package” on page 23.<br>The user must limit the power<br>consumption to comply with this<br>requirement.|



Page 16 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** 

## **DC Electrical Characteristics** 

## _DC Chip-Level Specifications_ 

Table 18 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 ° C  TA  85 ° C, or 3.0 V to 3.6 V and –40 ° C  TA  85 ° C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 ° C and are for design guidance only. 

## **Table 18.  CY8C9520A DC Chip-Level Specifications** 

|**Symbol**|**Description**|**Min**|**Typ**|**Max**|**Units**|**Notes**|
|---|---|---|---|---|---|---|
|Vdd|Supply voltage|3.00|–|5.25|V||
|IDD|Supply current Vdd 5 V|–|3.8|5|mA|Conditions are 5.0 V, TA= 25C, IOH= 0.|
|IDD3|Supply current Vdd 3.3 V|–|2.3|3|mA|Conditions are 3.3 V, TA= 25C, IOH= 0.|



## **Table 19.  CY8C9540A DC Chip-Level Specifications** 

|**Symbol**|**Description**|**Min**|**Typ**|**Max**|**Units**|**Notes**|
|---|---|---|---|---|---|---|
|Vdd|Supply voltage|3.00|–|5.25|V||
|IDD|Supply current Vdd 5 V|–|6|9|mA|Conditions are 5.0 V, TA= 25C, IOH= 0.|
|IDD3|Supply current Vdd 3.3 V|–|3.3|6|mA|Conditions are 3.3 V, TA= 25C, IOH= 0.|



**Table 20.  CY8C9560A DC Chip-Level Specifications** 

|**Symbol**|**Description**|**Min**|**Typ**|**Max**|**Units**|**Notes**|
|---|---|---|---|---|---|---|
|Vdd|Supply voltage|3.00|–|5.25|V||
|IDD|Supply current Vdd 5 V|–|15|25|mA|Conditions are 5.0 V, TA= 25C, IOH= 0.|
|IDD3|Supply current Vdd 3.3 V|–|5|9|mA|Conditions are 3.3 V, TA= 25C, IOH= 0.|



## _DC Programming Specifications_ 

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 ° C  TA  85 ° C, or 3.0 V to 3.6 V and –40 ° C  TA  85 ° C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 ° C and are for design guidance only. 

## **Table 21.  DC Programming Specifications** 

|**Symbol**|**Description**|**Min**|**Typ**|**Max**|**Units**|**Notes**|
|---|---|---|---|---|---|---|
|FlashENPB|Flash(EEPROM)endurance(byblock)|10,000|–|–|–|Erase/write cycles byblock.|
|FlashENT|Flash endurance(total)[3]|1,800,000|–|–|–|Erase/write cycles.|
|FlashDR|Flash data retention|10|–|–|Years||



## _DC I[2] C Specifications_ 

Table 22 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 ° C  TA  85 ° C, or 3.0 V to 3.6 V and –40 ° C  TA  85 ° C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 ° C and are for design guidance only. 

## **Table 22.  DC I[2] C Specifications**[[4]] 

|**Symbol**|**Description**|**Min**|**Typ**|**Max**|**Units**|**Notes**|
|---|---|---|---|---|---|---|
|VILI2C|Input low level|–|–|0.3 × VDD|V|3.0 VVDD 3.6 V|
|||–|–|0.25 × VDD|V|4.75 VVDD 5.25 V|
|VIHI2C|Input high level|0.7 × VDD|–|–|V|3.0 VVDD 5.25 V|



## **Note** 

3. A maximum of 180 x 10,000 block endurance cycles is allowed. This may be balanced between operations on 180x1 blocks of 10,000 maximum cycles each, 180x2 blocks of 5,000 maximum cycles each, or 180x4 blocks of 2,500 maximum cycles each (to limit the total number of cycles to 180x10,000 and that no single block ever sees more than 10,000 cycles). 

4. All GPIO meet the DC GPIO VIL and VIH specifications found in the DC GPIO Specifications sections.  The I[2] C GPIO pins also meet the above specs. 

Page 17 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** 

## _DC GPIO Specifications_ 

The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 ° C  TA  85 ° C, or 3.0 V to 3.6 V and –40 ° C  TA  85 ° C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 ° C and are for design guidance only. 

## **Table 23.  DC GPIO Specifications** 

|**Symbol**|**Description**|**Min**|**Typ**|**Max**|**Units**|**Notes**|
|---|---|---|---|---|---|---|
|VOH|High output level|Vdd - 1.0|–|–|V|IOH= 10 mA for any one pin,<br>Vdd = 4.75 to 5.25 V.<br>40 mA maximum combined IOH for<br>GPort0; GPort2_Bit3; GPort3;<br>GPort5_Bit2, 3, 6, 7; GPort6.<br>40 mA maximum combined IOH for<br>GPort1; GPort2_Bit0, 1, 2; GPort4;<br>GPort5_Bit0, 1, 4, 5; GPort7.<br>80 mA maximum combined IOH.|
|VOL|Low output level|–|–|0.75|V|IOL= 25 mA for any one pin,<br>Vdd = 4.75 to 5.25 V.<br>100 mA maximum combined IOL for<br>GPort0; GPort2_Bit3; GPort3;<br>GPort5_Bit2, 3, 6, 7; GPort6.<br>100 mA maximum combined IOLfor<br>GPort1; GPort2_Bit0, 1, 2; GPort4;<br>GPort5_Bit0, 1, 4, 5; GPort7.<br>200 mA maximum combined IOL.|
|IOH<br>~~a~~|High Level Source Current<br>~~a~~|10<br>~~ee~~|–<br>~~ee~~|–|mA|VOH= Vdd–1.0 V, see the limitations of<br>the total current in the note for VOH|
|IOL<br>~~a ~~<br>~~a ~~|Low Level Sink Current<br> ~~a~~<br> ~~a~~|25<br>~~ee~~<br>~~ee~~|–<br>~~ee~~<br>~~ee~~|–|mA|VOL= 0.75 V, see the limitations of the<br>total current in the note for VOL|
|VIL<br>~~se~~|Input low level<br>~~se~~|–<br>~~se~~|–<br>~~se~~|0.8<br>~~se~~|V<br>~~se~~|Vdd = 3.0 to 5.5.<br>~~se~~|
|VIH<br>~~De~~|Input high level<br>~~De~~|2.1<br>~~De~~|–<br>~~De~~|–<br>~~De~~|V<br>~~De~~|Vdd = 3.0 to 5.5.<br>~~De~~|
|IIL<br>~~se~~|Input leakage (absolute value)<br>~~se~~|–<br>~~se~~|1<br>~~se~~|–<br>~~se~~|nA<br>~~se~~|Gross tested to 1A.<br>~~se~~|
|CIN<br>~~a~~|Capacitive load on pins as input<br>~~a~~|–<br>~~ee~~|3.5<br>~~ee~~|10|pF|Package and pin dependent.<br>Temp = 25C.|
|COUT<br>~~a ~~<br>~~a~~|Capacitive load on pins as output<br> ~~a~~<br>~~a~~|–<br>~~ee~~<br>~~ee~~|3.5<br>~~ee~~<br>~~ee~~|10|pF|Package and pin dependent.<br>Temp = 25C.|
|RPU<br>~~a ~~<br>~~De~~|Pull-up resistor<br> ~~a~~<br>~~De~~|4<br>~~ee~~<br>~~De~~|5.6<br>~~ee~~<br>~~De~~|8<br>~~De~~<br>~~GO~~|k<br>~~De~~<br>~~GO~~|None<br>~~De~~|
|RPD<br>~~a ~~|Pull-down resistor<br> ~~GG~~|4<br>~~GG~~|5.6<br>~~GG~~|8<br>~~GG~~<br>~~GO~~|k<br>~~GG~~<br>~~GO~~|None<br>~~GG~~|



Page 18 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** 

## **AC Electrical Characteristics** 

## _AC GPIO Specifications_ 

Table 24 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 ° C  TA  85 ° C, or 3.0 V to 3.6 V and –40 ° C  TA  85 ° C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 ° C and are for design guidance only or unless otherwise specified. 

**Table 24.  AC GPIO Specifications** 

~~es~~ FGPIO **Symbol** GPIO Operating Frequency ~~a~~ **Description** ~~GG~~ **Min** 0 **Typ** – **Max** 12 **Units** MHz Normal Strong Mode **Notes** ~~ee~~ TRiseF Rise time, normal strong mode, 3 – 18 ns Vdd = 4.75 to 5.25 V, Cload = 50 pF 10%–90% ~~a~~ TFallF Fall time, normal strong mode, Cload = 50 pF ~~ee ee~~ 2 – 18 ~~ee~~ ns Vdd = 4.75 to 5.25 V, 10%–90% ~~a ee~~ TRiseS Rise time, slow strong mode, Cload = 50 pF 10 27 – ns Vdd = 3 to 5.25 V, 10%–90% ~~a eeee~~ TFallS Fall time, slow strong mode, Cload = 50 pF 10 22 – ns Vdd = 3 to 5.25 V, 10%–90% ~~a eeee~~ TIOAccess IO access time – – 2.485 ms None TPulsewidth Minimum pulse width on I/Os to assert INT 5.03 – – ms No I[2] C activity or line. EEPROM operation happens during input pulse duration. ~~ee~~ **Figure 8.  GPIO Timing Diagram** 90% GPIO Pin Output Voltage 10% TRiseF TFallF ~~JN~~ TRiseS TFallS 

## _AC PWM Specifications_ 

Table 25 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 ° C  TA  85 ° C, or 3.0 V to 3.6 V and –40 ° C  TA  85 ° C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 ° C and are for design guidance only or unless otherwise specified. 

## **Table 25.  AC PWM Specifications** 

|**Symbol**|**Description**|**Min**|**Typ**|**Max**|**Units**|**Notes**|
|---|---|---|---|---|---|---|
|Jitter24MHzPWM|24 MHz based PWM peak-to-peak period<br>jitter|–|0.1|1.5|%|24 MHz, 1.5 MHz,<br>93.75 kHz and 367.6 Hz<br>(programmable)<br>sources.|
|Jitter32kHzPWM|32 kHz-based PWM peak-to-peak period<br>jitter|–|2.5|5.0|%|32 kHz clock source.|
|F24MHzPWM|Input Frequency of 24 MHz based PWM|23.4|24|24.6|MHz||
|F32kHzPWM|Input Frequency of 32 kHz based PWM|15|32|64|kHz||
|F1.5MHzPWM|Input frequency of 1.5 MHz based PWM|1.46|1.5|1.53|MHz||



Page 19 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** 

**Table 25.  AC PWM Specifications** ~~Da~~ F93.75kHzPWM Input Frequency of 93.75 kHz based PWM ~~GQ~~ 91.40 93.75 96.09 kHz _AC_ I[2] C _Specifications_ 

Table 26 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 ° C  TA  85 ° C, or 3.0 V to 3.6 V and –40 ° C  TA  85 ° C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 ° C and are for design guidance only or unless otherwise specified. 

**Table 26.  AC Characteristics of the I[2] C SDA and SCL Pins** 

|**Symbol**<br>~~PE~~<br>~~re~~|**Description**<br>~~PE~~<br>~~ee~~|**Standard Mode**<br>~~PE~~|**Standard Mode**<br>~~PE~~|**Units**<br>~~PE~~<br>~~eG~~|**Notes**<br>~~PE~~|
|---|---|---|---|---|---|
|||**Min**<br>~~PE~~<br>~~eG~~|**Max**<br>~~PE~~<br>~~eG~~|||
|FSCLI2C<br>~~PE~~<br>~~re~~|SCL clock frequency<br>~~PE~~<br>~~ee~~|0<br>~~PE~~<br>~~eG~~|100<br>~~PE~~<br>~~eG~~|kHz<br>~~PE~~<br>~~eG~~|~~PE~~|
|THDSTAI2C<br>~~re ~~<br>~~a~~<br>~~re~~|Hold time (repeated) START condition. After this period,<br>the first clock pulse is generated.<br> ~~ee~~<br>~~er~~|4.0<br>~~eG~~<br>~~er~~<br>~~re~~|–<br>~~eG~~<br>~~er~~|s<br>~~eG~~<br>~~er~~|~~er~~|
|TLOWI2C<br>~~re~~|LOW period of the SCL clock<br>~~er~~|4.7<br>~~er~~<br>~~re~~|–<br>~~er~~|s<br>~~er~~|~~er~~|
|THIGHI2C<br>~~re~~|HIGH period of the SCL clock<br>~~er~~|4.0<br>~~er~~<br>~~re~~|–<br>~~er~~|s<br>~~er~~|~~er~~|
|TSUSTAI2C|Setup time for a repeated START condition|4.7|–|s||
|THDDATI2C|Data hold time|0|–|s||
|TSUDATI2C<br>~~a~~|Data setup time<br>~~a~~|250<br>~~a~~|–<br>~~a~~|ns<br>~~a~~|~~a~~|
|TSUSTOI2C<br>~~a~~|Setup time for STOP condition<br>~~a~~|4.0<br>~~a~~|–<br>~~a~~|s<br>~~a~~|~~a~~|
|TBUFI2C<br>~~>~~|Bus free time between a STOP and START Condition<br>~~>~~|4.7<br>~~>~~|–<br>~~>~~|s<br>~~>~~|~~>~~|
|TSPI2C<br>~~>~~|Pulse width of spikes are suppressed by the input filter.<br>~~>~~|–<br>~~>~~|–<br>~~>~~|ns<br>~~>~~|~~>~~|



**Note:** Fast mode I[2] C is not supported. 

**Figure 9.  Definition for Timing for Standard Mode on the I[2] C Bus** 

**==> picture [486 x 150] intentionally omitted <==**

**----- Start of picture text -----**<br>
I2C_SDA<br>THDSTAI2CTSUDATI2C THDDATI2CTSUSTAI2C TSPI2C TBUFI2C<br>I2C_SCL<br>THIGHI2C TLOWI2C TSUSTOI2C<br>P S<br>S Sr<br>START Condition Repeated START Condition STOP Condition<br>**----- End of picture text -----**<br>


_AC EEPROM Write Specifications_ 

Table 27 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 ° C  TA  85 ° C, or 3.0 V to 3.6 V and –40 ° C  TA  85 ° C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 ° C and are for design guidance only or unless otherwise specified. 

**Table 27.  AC EEPROM Write Specifications** 

|**Symbol**|**Description**|**Min**|**Typ**|**Max**|**Units**|**Notes**|
|---|---|---|---|---|---|---|
|TEEPROMWrite_Hot|EEPROM Erase + Write time|–|–|100|ms|0 °CTj100 °C|
|TEEPROMWrite_Cold|EEPROM Erase + Write time|–|–|200|ms|–40 °CTj0 °C|



Page 20 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** 

## **Packaging Dimensions** 

This section illustrates the packaging specifications for the CY8C95xxA device, along with the thermal impedances for each package and the solder reflow peak temperature. 

**Important Note** Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tools’ dimensions, refer to the emulator pod drawings at http://www.cypress.com. 

## **F** ~~**i**~~ **gure 10.  28-pin SSOP (210 Mils) Package Outline** 

**==> picture [39 x 40] intentionally omitted <==**

**----- Start of picture text -----**<br>
or-8<br>51-85079 *F<br>**----- End of picture text -----**<br>


Page 21 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** 

**Figure 11.  48-pin SSOP (300 Mils) Package Outline** 

**==> picture [39 x 6] intentionally omitted <==**

**----- Start of picture text -----**<br>
51-85061 *F<br>**----- End of picture text -----**<br>


## **Figure 12.  100-pin TQFP (14 × 14 × 1.0 mm) Package Outline** 

51-85048 *I 

Page 22 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** 

## **Thermal Impedances** 

**Table 28.  Thermal Impedances per Package** 

|**Package**|**Typical****JA**<br>[5]|
|---|---|
|28-pin SSOP|101C/W|
|48-pin SSOP|69C/W|
|100-pin TQFP|48C/W|



## **Solder Reflow Specifications** 

Table 29 shows the solder reflow temperature limits that must not be exceeded. 

## **Table 29.  Solder Reflow Specifications** 

|**Package**|**Maximum Peak Temperature (TC)**|**Maximum Time above TC – 5****C**|
|---|---|---|
|28-pin SSOP|260 °C|30 seconds|
|48-pin SSOP|260 °C|30 seconds|
|100-pin TQFP|260 °C|30 seconds|



> 5. TJ = TA + POWER x JA. 

**Notes** 

Page 23 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** 

## **Features and Ordering Information** 

Table 30 lists the CY8C95xxA device’s key package features and ordering codes. A definition of the ordering number code follows. 

## **Table 30.  CY8C95xxA Device Key Features and Ordering Information** 

|**Package**|**Ordering Code**[6]|**EEPROM**<br>**(Bytes)**|**Temperature**<br>**Range**|**PWM**<br>**Sources**|**Configurable**<br>**I/O Pins**|
|---|---|---|---|---|---|
|28 Pin (210 Mil) SSOP|CY8C9520A-24PVXI|3K|–40C to +85C|4|20|
|28 Pin (210 Mil) SSOP (Tape and Reel)|CY8C9520A-24PVXIT|3K|–40C to +85C|4|20|
|48 Pin (300 Mil) SSOP|CY8C9540A-24PVXI|11K|–40C to +85C|8|40|
|48 Pin (300 Mil) SSOP (Tape and Reel)|CY8C9540A-24PVXIT|11K|–40C to +85C|8|40|
|100 Pin TQFP|CY8C9560A-24AXI|27K|–40C to +85C|16|60|
|100 Pin TQFP (Tape and Reel)|CY8C9560A-24AXIT|27K|–40C to +85C|16|60|



## **Ordering Code Definitions** 

CY 8 C  9 xxx-SPxx 

Package Type: Thermal Rating: PX = PDIP Pb-Free C = Commercial SX = SOIC Pb-Free I = Industrial PVX = SSOP Pb-Free E = Extended LFX/LKX/LTX/LQX/LCX = QFN Pb-Free AX = TQFP Pb-Free Speed: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress 

> 6. The A after the existing port expander part number indicates new device firmware. 

**Note** 

Page 24 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** 

## **Acronyms** 

Table 31 lists the acronyms that are used in this document. 

## **Table 31.  Acronyms Used in this Datasheet** 

|**Acronym**|**Description**|**Acronym**|**Description**|
|---|---|---|---|
|AC|alternating current|POR|power on reset|
|API|application programming interface|PSoC®|Programmable System-on-Chip|
|CMOS|complementary metal oxide semiconductor|PWM|pulse width modulator|
|CRC|cyclic redundancy check|SSOP|shrink small-outline package|
|DC|direct current|TQFP|thin quad flat pack|
|EEPROM|electrically erasable programmable read-only<br>memory|UART|universal asynchronous reciever / transmitter|
|GPIO|general purpose I/O|USB|universal serial bus|
|I/O|input/output|WDT|watchdog timer|
|MSB|most-significant bit|XRES|external reset|
|PCB|printed circuit board|||



## **Document Conventions** 

## **Units of Measure** 

Table 32 lists the units of measures. 

## **Table 32.  Units of Measure** 

|**Symbol**|**Unit of Measure**|**Symbol**|**Unit of Measure**|
|---|---|---|---|
|°C|degree Celsius|mm|millimeter|
|Hz|hertz|ms|millisecond|
|kHz|kilohertz|nA|nanoampere|
|k|kilohm|ns|nanosecond|
|MHz|megahertz||ohm|
|µA|microampere|%|percent|
|µs|microsecond|pF|picofarad|
|V|microvolt|V|volt|
|Vrms|microvolts root-mean-square|W|watt|
|mA|milliampere|||



## **Numeric Conventions** 

## **Numeric Naming** 

Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals. 

Page 25 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** 

## **Glossary** 

- active high 1. A logic signal having its asserted state as the logic 1 state. 

   2. A logic signal having the logic 1 state as the higher voltage of the two states. 

analog blocks The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more. 

analog-to-digital A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts (ADC) a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation. 

Application A series of software routines that comprise an interface between a computer application and lower level services programming and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that interface (API) create software applications. 

asynchronous A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. 

bandgap A stable voltage reference design that matches the positive temperature coefficient of VT with the negative reference temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference. 

- bandwidth 1. The frequency range of a message or information processing system measured in hertz. 

   2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum. 

- bias 1. A systematic deviation of a value from a reference value. 

   2. The amount by which the average of a set of values departs from a reference value. 

   3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. 

- block 1. A functional unit that performs a single function, such as an oscillator. 

2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or an analog PSoC block. 

buffer 1. A storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. Usually refers to an area reserved for IO operations, into which data is read, or from which data is written. 

   2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 

   3. An amplifier used to lower the output impedance of a system. 

- bus 1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing patterns. 

   2. A set of signals performing a common function and carrying similar data. Typically represented using vector notation; for example, address[7:0]. 

   3. One or more conductors that serve as a common connection for a group of related devices. 

clock The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to synchronize different logic blocks. 

comparator An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. 

compiler A program that translates a high level language, such as C, into machine language. 

configuration In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’. space 

crystal oscillator An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components. 

cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear feedback shift check (CRC) register. Similar calculations may be used for a variety of other purposes such as data compression. 

data bus A bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. More generally, a set of signals used to convey data between digital functions. 

Page 26 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** 

## **Glossary** (continued) 

|**Glossary**(continued)|(continued)|
|---|---|
|debugger|A hardware and software system that allows you to analyze the operation of the system under development. A|
||debugger usually allows the developer to step through the firmware one step at a time, set break points, and|
||analyze memory.|
|dead band|A period of time when neither of two or more signals are in their active state or in transition.|
|digital blocks|The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator,|
||pseudo-random number generator, or SPI.|
|digital-to-analog|A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital (ADC)|
|(DAC)|converter performs the reverse operation.|
|duty cycle|The relationship of a clock period high time to its low time, expressed as a percent.|
|emulator|Duplicates (provides an emulation of) the functions of one system with a different system, so that the second|
||system appears to behave like the first system.|
|External Reset|An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop|
|(XRES)|and return to a pre-defined state.|
|Flash|An electrically programmable and erasable, non-volatile technology that provides you the programmability and|
||data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is|
||OFF.|
|Flash block|The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash|
||space that may be protected. A Flash block holds 64 bytes.|
|frequency|The number of cycles or events per unit of time, for a periodic function.|
|gain|The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually|
||expressed in dB.|
|I2C|A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated|
||Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in|
||the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building|
||control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5 V and pulled high|
||with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode.|
|ICE|The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging|
||device activity in a software environment (PSoC Designer).|
|input/output (I/O) A device that introduces data into or extracts data from a system.|input/output (I/O) A device that introduces data into or extracts data from a system.|
|interrupt|A suspension of a process, such as the execution of a computer program, caused by an event external to that|
||process, and performed in such a way that the process can be resumed.|
|interrupt service|A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many|
|routine (ISR)|interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends|
||with the RETI instruction, returning the device to the point in the program where it left normal program execution.|
|jitter|1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on|
||serial data streams.|
||2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between|
||successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.|
|low-voltage|A circuit that senses Vdd and provides an interrupt to the system when Vdd falls below a selected threshold.|
|detect (LVD)||
|M8C|An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by|
||interfacing to the Flash, SRAM, and register space.|
|master device|A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in|
||width, the master device is the one that controls the timing for data exchanges between the cascaded devices|
||and an external interface. The controlled device is called the**_slave device_.**|



Page 27 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** 

## **Glossary** (continued) 

microcontroller An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for general-purpose computation as is a microprocessor. 

|microcontroller|An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a<br>microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the<br>realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This<br>in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for<br>general-purpose computation as is a microprocessor.|
|---|---|
|mixed-signal|The reference to a circuit containing both analog and digital techniques and components.|
|modulator|A device that imposes a signal on a carrier.|
|noise|1. A disturbance that affects a signal and that may distort the information carried by the signal.|
||2. The random variations of one or more characteristics of any entity such as voltage, current, or data.|
|oscillator|A circuit that may be crystal controlled and is used to generate a clock frequency.|
|parity|A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the|
||digits of the binary data either always even (even parity) or always odd (odd parity).|
|Phase-locked|An electronic circuit that controls an**_oscillator_**so that it maintains a constant phase angle relative to a reference|
|loop (PLL)|signal.|
|pinouts|The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their|
||physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between|
||schematic and PCB design (both being computer generated files) and may also involve pin names.|
|port|A group of pins, usually eight.|
|Power on reset|A circuit that forces the PSoC device to reset when the voltage is below a pre-set level. This is one type of hardware|
|(POR)|reset.|
|PSoC®|Cypress Semiconductor’s PSoC®is a registered trademark and Programmable System-on-Chip™ is a trademark|
||of Cypress.|
|PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.|PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.|
|pulse width|An output in the form of duty cycle which varies as a function of the applied measurand|
|modulator (PWM)||
|RAM|An acronym for random access memory. A data-storage device from which data can be read out and new data|
||can be written in.|
|register|A storage device with a specific capacity, such as a bit or byte.|
|reset|A means of bringing a system back to a know state. See hardware reset and software reset.|
|ROM|An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot|
||be written in.|
|serial|1. Pertaining to a process in which all events occur one after the other.|
||2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or|
||channel.|
|settling time|The time it takes for an output signal or value to stabilize after the input has changed from one value to another.|
|shift register|A memory storage device that sequentially shifts a word either left or right to output a stream of serial data.|
|slave device|A device that allows another device to control the timing for data exchanges between two devices. Or when|
||devices are cascaded in width, the slave device is the one that allows another device to control the timing of data|
||exchanges between the cascaded devices and an external interface. The controlling device is called the master|
||device.|
|SRAM|An acronym for static random access memory. A memory device where you can store and retrieve data at a high|
||rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged|
||until it is explicitly altered or until power is removed from the device.|
|SROM|An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate|
||circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code,|
||operating from Flash.|



Page 28 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** 

## **Glossary** (continued) 

stop bit A signal following a character or block that prepares the receiving device to receive the next character or block. 

synchronous 1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. A system whose operation is synchronized by a clock signal. 

tri-state A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net. 

UART 

A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. 

user modules Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high level _**API (Application Programming Interface)**_ for the peripheral function. 

user space The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during the initialization phase of the program. 

VDD A name for a power net meaning “voltage drain.” The most positive power supply signal. Usually 5 V or 3.3 V. 

VSS A name for a power net meaning “voltage source.” The most negative power supply signal. 

watchdog timer A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time. 

Page 29 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** 

## **Errata** 

This section describes the errata for CY8C9560A device. Details include the trigger condition, scope of impact, available workaround, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions. 

## **Part Numbers Affected** 

## **Part Number** 

CY8C9560A 

## **Qualification Status** 

CY8C9560A Rev. A – In Production 

## **Errata Summary** 

The following table defines the errata applicability to available devices. 

|**Items**|**Part Number**|**Silicon Revision**|**Fix Status**|
|---|---|---|---|
|1.The command 01h cannot store more<br>than128 bytes of configuration data from<br>SRAM to EEPROM.|CY8C9560A|A|No silicon fix planned.<br>Workaround is required.|



## **1. The command 01h cannot store more than128 bytes of configuration data from SRAM to EEPROM.** 

## ❐ **Problem Definition** 

The Store Config to E[2] POR Defaults Cmd (01h) can write only up to 128 bytes of configuration data from SRAM to the EEPROM. Configuration data exceeding 128 bytes are ignored. 

- ❐ **Parameters Affected** 

NA 

## ❐ **Trigger Condition** 

NA 

## ❐ **Scope of Impact** 

Configuration data from SRAM to EEPROM exceeding 128 bytes are ignored. 

## ❐ **Workaround** 

As a workaround, use the Write E[2] POR Defaults Cmd (03h) command to explicitly write all configuration data to EEPROM using I[2] C. 

## ❐ **Fix Status** 

No fixes are planned. You must use the recommended workaround. 

Page 30 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** 

## **Document History Page** 

**Document Title: CY8C9520A/CY8C9540A/CY8C9560A, 20-, 40-, and 60-Bit I/O Expander with EEPROM Document Number: 38-12036** 

|**Document Title: CY8C9520A/CY8C9540A/CY8C9560A, 20-, 40-, and 60-Bit I/O Expander with EEPROM**<br>**Document Number: 38-12036**|**Document Title: CY8C9520A/CY8C9540A/CY8C9560A, 20-, 40-, and 60-Bit I/O Expander with EEPROM**<br>**Document Number: 38-12036**|**Document Title: CY8C9520A/CY8C9540A/CY8C9560A, 20-, 40-, and 60-Bit I/O Expander with EEPROM**<br>**Document Number: 38-12036**|**Document Title: CY8C9520A/CY8C9540A/CY8C9560A, 20-, 40-, and 60-Bit I/O Expander with EEPROM**<br>**Document Number: 38-12036**|**Document Title: CY8C9520A/CY8C9540A/CY8C9560A, 20-, 40-, and 60-Bit I/O Expander with EEPROM**<br>**Document Number: 38-12036**|
|---|---|---|---|---|
|**Revision**<br>~~a~~<br>~~ee~~|**ECN**<br>~~es~~|**Orig. of**<br>**Change**<br>~~es Se~~|**Submission**<br>**Date**<br>~~Se~~|**Description of Change**<br>~~(RU~~|
|**<br>~~ee~~|346754<br>~~es~~|HMT<br>~~es Se~~|See ECN<br>~~Se~~|New silicon, document.<br>~~(RU~~|
|*A<br>~~ee~~<br>~~Pf~~|392484<br>~~es~~<br>~~Pf~~<br>~~|~~|HMT<br>~~es Se~~<br>~~**f**~~|See ECN<br>~~Se ~~<br>~~**f**t~~|Correct pin 79 on the TQFP. Add AC PWM Output Jitter spec. table. Upgrade<br>to CY Perform logo and update zip code and trademarks.<br> ~~(RU~~|
|*B<br>~~Pf~~|1336984<br>~~Pf~~<br>~~|~~|HMT /<br>AESA<br>~~**f**~~|See ECN<br>~~**f**t~~|Update typical and recommended Storage Temperature per industrial specs.<br>Update copyright and trademarks. Add Watchdog timer details. Add “A” to<br>existing part numbers to indicate new firmware. Fix errors. Implement CY<br>template.<br>~~o~~|
|*C<br>~~Pf~~|2843174<br>~~Pf~~<br>~~|~~|YARA<br>~~**f**~~|01/08/2010<br>~~**f**t~~|AddedContents.UpdatedOverview. Updated Pin 11 description inFigure 2<br>on page 5. Modified Note 3. Added IOHand IOLspecifications inDC GPIO<br>Specifications. Removed “Output Jitter” from AC PWM Specifications section<br>on page 18. Added F24MHzPWM, F32kHzPWM, and F93.5kHzPWM specifi-<br>cations inTable 25.AddedTable 27.|
|*D|2903402|NJF|04/01/2010|Updated Cypress website links<br>Added TBAKETEMPand TBAKETIMEparameters<br>Updated package diagrams|
|*E|3110285|NJF|12/14/10|Added text “When the part is held in reset all In and Out pins are held at their<br>default High-Z State” to section “External Reset Pin (XRES)” on page 9.<br>Added DC I2C Specifications table.<br>Updated Units of Measure, Acronyms, Glossary, and References sections.<br>Updated solder reflow specifications.<br>No specific changes made to I2C Timing Diagram. It has been updated for<br>clearer understanding.|
|*F|3381717|NPD|09/23/11|Updated solder reflow specifications to improve clarity.<br>Updated package diagrams.|
|*G<br>~~ee~~|4512488<br>~~rs ns~~|DIMA<br>~~ns~~|09/24/2014<br>~~nn~~|UpdatedPin Descriptions:<br>UpdatedExtendable Soft Addressing:<br>Updated description.<br>UpdatedInterrupt Pin (INT):<br>Updated description.<br>UpdatedElectrical Specifications:<br>UpdatedDC Electrical Characteristics:<br>UpdatedDC GPIO Specifications:<br>UpdatedTable 23:<br>Added RPU, RPDparameters and their details.<br>UpdatedAC Electrical Characteristics:<br>UpdatedAC GPIO Specifications:<br>UpdatedTable 24:<br>Added TIOAccess parameter and its details.<br>UpdatedAC I2C Specifications:<br>UpdatedTable 26(Removed the column “Fast Mode”).<br>UpdatedFigure 9(No change in figure, removed “Fast” in caption only).<br>UpdatedPackaging Dimensions:<br>spec 51-85061 – Changed revision from *E to *F.<br>spec 51-85048 – Changed revision from *E to *I.<br>Updated to new template.<br>Completing Sunset Review.<br>~~(RO~~|
|*H<br>~~ee~~|4569861<br>~~rs ns~~|ASRI<br>~~ns~~|11/22/2014<br>~~nn~~|AddedErrata.<br>~~(RO~~|
|*I<br>~~ee ~~<br>~~a~~|4708108<br> ~~rs ns~~<br>~~a~~|DIMA<br>~~ns ~~|04/01/2015<br> ~~nn ~~|Added minimum input pulse width inTable 24.<br>Removed reference to obsolete application note, AN2304.<br> ~~(RO~~|



Page 31 of 32 

Document Number: 38-12036 Rev. *I 

**CY8C9520A CY8C9540A CY8C9560A** 

## **Sales, Solutions, and Legal Information** 

## **Worldwide Sales and Design Support** 

Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. 

## **Products** 

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## **Technical Support** 

cypress.com/go/support 

© Cypress Semiconductor Corporation, 2005-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. 

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. 

Use may be limited by and subject to the applicable Cypress software license agreement. 

## Document Number: 38-12036 Rev. *I 

## Revised April 1, 2015 

Page 32 of 32 

PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation. Purchase of I[2] C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I[2] C Patent Rights to use these components in an I[2] C system, provided that the system conforms to the I[2] C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders.
Updated at February 9, 2023
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