CSPEMI202AG.

## CSPEMI202AG 

## 2 Channel Headset Microphone EMI Filter with ESD Protection 

## **Product Description** 

The CSPEMI202AG is a dual low−pass filter array integrating two pi−style filters (C−R−C) that reduce EMI/RFI emissions while at the same time providing ESD protection. This part is custom−designed to interface with a microphone port on a cellular telephone or similar device. Each high quality filter provides more than 35 dB attenuation in the 800−2700 MHz range. These pi−style filters support bidirectional filtering, controlling EMI both to and from a microphone element. They also support bipolar signals, enabling audio signals to pass through without distortion. 

In addition, the CSPEMI202AG provides a very high level of protection for sensitive electronic components that may be subjected to electrostatic discharge (ESD). The diodes safely dissipate ESD strikes of ±8 kV, the maximum requirement of the IEC 61000−4−2 international standard. Using the MIL−STD−883 (Method 3015) specification for Human Body Model (HBM) ESD, the device provides protection for contact discharges to greater than ±15 kV. 

The CSPEMI202AG is particularly well−suited for portable electronics (e.g. cellular telephones, PDAs, notebook computers) because of its small package format and low weight. The CSPEMI202AG is available in a space−saving, low−profile Chip Scale Package with RoHS compliant lead−free finishing. 

## **Features** 

- Two Channels of EMI Filtering 

- Pi−Style EMI Filters in a Capacitor−Resistor−Capacitor (C−R−C) Network 

- Greater than 40 dB Attenuation at 1 GHz 

- ±8 kV ESD Protection on each Channel (IEC 61000−4−2 Level 4, Contact Discharge) 

- ±15 kV ESD Protection on each Channel (HBM) 

- Supports Bipolar Signals − Ideal for Audio Applications 

- Chip Scale Package Features Extremely Low Lead Inductance for Optimum Filter and ESD Performance 

- 5−Bump, 0.930 x 1.410 mm Footprint Chip Scale Package (CSP) 

- These Devices are Pb−Free and are RoHS Compliant 

## **Applications** 

- EMI Filtering and ESD Protection for Headset Microphone Ports 

- Wireless Handsets 

- Handheld PCs / PDAs 

- MP3 Players 

## **http://onsemi.com** 

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WLCSP5<br>AG SUFFIX<br>CASE 567AZ<br>**----- End of picture text -----**<br>


## **ELECTRICAL SCHEMATIC** 

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68<br>A1 C1<br>47 pF 47 pF<br>68<br>A3 C3<br>47 pF 47 pF<br>B2<br>e el<br>MARKING DIAGRAM<br>+<br>AD<br>AD = CSPEMI202AG<br>ORDERING INFORMATION<br>Device Package Shipping [†]<br>CSPEMI202AG CSP−5 3500/Tape & Reel<br>(Pb−Free)<br>=<br>†For information on tape and reel specifications,<br>including part orientation and tape sizes, please<br>refer to our Tape and Reel Packaging Specification<br>Brochure, BRD8011/D.<br>MIC_IN1 MIC_OUT1<br>MIC_IN2<br>MIC_OUT2<br>GND<br>**----- End of picture text -----**<br>


- Digital Camcorders 

- Notebooks 

- Desktop PCs 

Publication Order Number: **CSPEMI202AG/D** 

**1** 

© Semiconductor Components Industries, LLC, 2011 **May, 2011 − Rev. 4** 

**CSPEMI202AG** 

## **Table 1. PIN DESCRIPTIONS** 

|**Table 1. PIN DESCRIPTIONS**|**Table 1. PIN DESCRIPTIONS**|**Table 1. PIN DESCRIPTIONS**|
|---|---|---|
||||
||**5−bump CSP Package**||
|**Pin**|**Name**|**Description**|
|A1|MIC_IN1|Microphone Input 1 (from microphone)|
|A3|MIC_IN2|Microphone Input 2 (from microphone)|
|B2|GND|Device Ground|
|C1|MIC_OUT1|Microphone Output 1 (to audio circuitry)|
|C3|MIC_OUT1|Microphone Output 2 (to audio circuitry)|



## **PACKAGE / PINOUT DIAGRAMS** 

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Top View Bottom View<br>(Bumps Down View) (Pins Up View)<br>Orientation<br>Marking 1   2   3<br>+<br>A C1 C3<br>Orientation<br>B Marking B2<br>A1<br>C A1 A3<br>CSPEMI202A<br>CSP Package<br>**----- End of picture text -----**<br>


## **SPECIFICATIONS** 

## **Table 2. ABSOLUTE MAXIMUM RATINGS** 

|**Table 2. ABSOLUTE MAXIMUM RATINGS**|||
|---|---|---|
|**Parameter**|**Rating**|**Units**|
|Storage Temperature Range|−65 to +150|°C|
|DC Power per Resistor|100|mW|
|DC Package Power Rating|200|mW|



Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 

## **Table 3. STANDARD OPERATING CONDITIONS** 

|**Table 3. STANDARD OPERATING CONDITIONS**|**Table 3. STANDARD OPERATING CONDITIONS**|**Table 3. STANDARD OPERATING CONDITIONS**||||||
|---|---|---|---|---|---|---|---|
|**Parameter**|||**Rating**||||**Units**|
|Operating Temperature Range|||−40 to +85||||°C|
|**Table 4. ELECTRICAL OPERATING CHARACTERISTICS**(Note 1)||||||||
|**Symbol**|**Parameter**|**Conditions**||**Min**|**Typ**|**Max**|**Units**|
|R1|Resistance|||61|68|75|�|
|C1|Capacitance|||38|47|56|pF|
|ILEAK|Diode Leakage Current|VIN= 5.0 V||||1.0|�A|
|VSIG|Signal Voltage<br>Positive Clamp<br>Negative Clamp|ILOAD= 10 mA||5<br>−15|7<br>−10|15<br>−5|V|
|VESD|In−system ESD Withstand Voltage<br>a) Human Body Model, MIL−STD−883, Method 3015<br>b) Contact Discharge per IEC 61000−4−2 Level 4|(Note 2)||±15<br>±8|||kV|
|VCL|Clamping Voltage during ESD Discharge<br>MIL−STD−883 (Method 3015), 8 kV<br>Positive Transients<br>Negative Transients|(Notes 2 and 3)|||+15<br>−19||V|
|fC|Cut−off frequency<br>ZSOURCE= 50�, ZLOAD= 50�|R = 68�, C = 47 pF|||60||MHz|



1. TA = 25 ° C unless otherwise specified. 

2. ESD applied to input and output pins with respect to GND, one at a time. 

3. Clamping voltage is measured at the opposite side of the EMI filter to the ESD pin. For example, if ESD is applied to Pin A1, then clamping voltage is measured at Pin C1. 

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**2** 

**CSPEMI202AG** 

## **PERFORMANCE INFORMATION** 

## **Typical Filter Performance (nominal conditions unless specified otherwise, 50  Environment)** Q 

**Figure 1. Insertion Loss vs. Frequency (A1−C1 to GND B2)** 

**Figure 2. Insertion Loss vs. Frequency (A3−C3 to GND B2)** 

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**3** 

**CSPEMI202AG** 

## **APPLICATION INFORMATION** 

|**Parameter**|**Value**|
|---|---|
|Pad Size on PCB|0.240 mm|
|Pad Shape|Round|
|Pad Definition|Non−Solder Mask defined pads|
|Solder Mask Opening|0.290 mm Round|
|Solder Stencil Thickness|0.125 mm − 0.150 mm|
|Solder Stencil Aperture Opening (laser cut, 5% tapered walls)|0.300 mm Round|
|Solder Flux Ratio|50/50 by volume|
|Solder Paste Type|No Clean|
|Pad Protective Finish|OSP (Entek Cu Plus 106A)|
|Tolerance − Edge To Corner Ball|±50�m|
|Solder Ball Side Coplanarity|±20�m|
|Maximum Dwell Time Above Liquidous|60 seconds|
|Maximum Soldering Temperature for Lead−free Devices using a Lead−free Solder Paste|260°C|



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Non−Solder Mask Defined Pad<br>0.240 mm DIA.<br>Solder Stencil Opening<br>0.300 mm DIA.<br>Solder Mask Opening<br>0.290 mm DIA.<br>**----- End of picture text -----**<br>


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**Figure 3. Recommended Non−Solder Mask Defined Pad Illustration** 

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250<br>200<br>150<br>100<br>50<br>0 1:00.0 2:00.0 3:00.0 4:00.0<br>Time (minutes)<br>C)<br>( �<br>Temperature<br>**----- End of picture text -----**<br>


**Figure 4. Lead−free (SnAgCu) Solder Ball Reflow Profile** 

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**4** 

**CSPEMI202AG** 

## **PACKAGE DIMENSIONS** 

**WLCSP5, 0.94x1.41** CASE 567AZ−01 ISSUE O 

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D A B NOTES:<br>PIN A1 1. DIMENSIONING AND TOLERANCING PER<br>REFERENCE ASME Y14.5M, 1994.<br>2. CONTROLLING DIMENSION: MILLIMETERS.<br>ÈÈ 3. COPLANARITY APPLIES TO SPHERICAL<br>ro t og CROWNS OF SOLDER BALLS.<br>E MILLIMETERS<br>DIM MIN MAX<br>2X 0.05 C A 0.56 0.72<br>A1 0.21 0.27<br>A2 0.40 REF<br>2X 0.05 C b 0.29 0.35<br>eo TOP VIEW D 0.94 BSC<br>E 1.41 BSC<br>OptiGuard Option A2 eD 0.50 BSC<br>ait 0.05 C ÉÉÉ E eE 0.435 BSC g<br>A RECOMMENDED<br>TT tt SOLDERING FOOTPRINT*<br>0.05 C<br>ely PACKAGE<br>NOTE 3 A1 SIDE VIEW C SEATINGPLANE A1 OUTLINE<br>eD/2<br>0.87<br>5X b eD<br>i _ ber<br>0.05 C A B eE<br>C 0.44<br>0.03 C<br>5X 0.25<br>B 0.25<br>A 0.50<br>ota  n e DIMENSIONS: MILLIMETERS ie<br>1 2 3<br>BOTTOM VIEW *For additional information on our Pb−Free strategy and soldering<br>**----- End of picture text -----**<br>


*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

**ON Semiconductor** and          are registered trademarks of Semiconductor Components Industries, LLC (SCILLC).  SCILLC reserves the right to make changes without further notice to any products herein.  SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time.  All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts.  SCILLC does not convey any license under its patent rights nor the rights of others.  SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.  Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part.  SCILLC is an Equal Opportunity/Affirmative Action Employer.  This literature is subject to all applicable copyright laws and is not for resale in any manner. 

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