CSD75204W15

**CSD75204W15** 

SLPS221A –OCTOBER 2009–REVISED OCTOBER 2010 

**www.ti.com** 

## **Dual P-Channel NexFET™Power MOSFET** 

**Check for Samples: CSD75204W15** 

## **1FEATURES** 

- **Dual P-Ch MOSFETs** 

- **Common Source Configuration** 

- **Small Footprint 1.5-mm × 1.5-mm** 

- **Gate-Source Voltage Clamp** 

- **Gate ESD Protection –3kV** 

- **Pb Free** 

- **RoHS Compliant** 

- **Halogen Free** 

## **APPLICATIONS** 

- **Battery Management** 

## **PRODUCT SUMMARY** 

|VD1D2|Drain to Drain Voltage|–20|–20|V|
|---|---|---|---|---|
|Qg|Gate Charge Total (-4.5V)|2.8||nC|
|Qgd|Gate Charge Gate to Drain|0.6||nC|
|RD1D2(on)|Drain to Drain On Resistance|VGS = –1.8V|140|mΩ|
|||VGS= –2.5V|105|mΩ|
|||VGS= –4.5V|80|mΩ|
|VGS(th)|Threshold Voltage|–0.7||V|



## **ORDERING INFORMATION** 

|**Device**|**Package**|**Media**|**Qty**|**Ship**|
|---|---|---|---|---|
|CSD75204W15|1.5-mm × 1.5-mm<br>Wafer Level Package|7-Inch<br>Reel|3000|Tape and<br>Reel|



- **Battery Protection** 

## **ABSOLUTE MAXIMUM RATINGS** 

## **DESCRIPTION** 

The device has been designed to deliver the lowest on resistance and gate charge in the smallest outline possible with excellent thermal characteristics in an ultra low profile. Low on resistance coupled with the small footprint and low profile make the device ideal for battery operated space constrained applications. 

## **Top View** 

**==> picture [62 x 58] intentionally omitted <==**

**----- Start of picture text -----**<br>
G1 D1 D1<br>SS D2 D1<br>G2 D2 D2<br>**----- End of picture text -----**<br>


|TA= 25°C unless otherwise stated|TA= 25°C unless otherwise stated|**VALUE**|**UNIT**|
|---|---|---|---|
|VD1D2|Drain to Drain Voltage|–20|V|
|VGS|Gate to Source Voltage|-6|V|
|ID1D2|Continuous Drain to Drain Current,<br>TC= 25°C(1)|–3|A|
||Pulsed Drain to Drain Current,<br>TC= 25°C(2)|-28|A|
|IS|Continuous Source Pin Current|-1.2|A|
||Pulsed Source Pin Current(2)|-15|A|
|IG|Continuous Gate Clamp Current|-0.5|A|
||Pulsed Gate Clamp Current(2)|-7|A|
|PD|Power Dissipation(1)|0.7|W|
|TJ,<br>TSTG|Operating Junction and Storage<br>Temperature Range|–55 to 150|°C|



(1) Per device, both sides in conduction 

- (2) Pulse duration 10 m s, duty cycle ≤ 2% 

**==> picture [12 x 3] intentionally omitted <==**

**----- Start of picture text -----**<br>
P0109-01<br>**----- End of picture text -----**<br>


**RD1D2(on) vs VGS** 

## **Gate Charge (Per MOSFET)** 

**==> picture [435 x 126] intentionally omitted <==**

**----- Start of picture text -----**<br>
300 6<br>ID1D2 = −1A ID1D2 = −1A<br>250 5 V D1D2  = −10V<br>200 TJ = 125°C 4<br>150 TJ = 25°C 3<br>100 2<br>PONS<br>50 1<br>0 Seer 0<br>0 1 2 3 4 5 6 0.0 0.5 1.0 1.5 2.0 2.5 3.0<br>ney Series<br>−VGS − Gate to Source Voltage − V G006 Qg − Gate Charge − nC G003<br>Ω<br> − On-State Resistance − m  − Gate to Source Voltage − V<br>GS<br>D1D2(on) −V<br>R<br>**----- End of picture text -----**<br>


Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. ~~Bo~~ 

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. 

Copyright © 2009–2010, Texas Instruments Incorporated 

**CSD75204W15** 

SLPS221A –OCTOBER 2009–REVISED OCTOBER 2010 

**www.ti.com** 

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 

## **ELECTRICAL CHARACTERISTICS** 

|**PARAMETER**<br>~~eG~~|**TEST CONDITIONS**<br>~~eG~~|**MIN**<br>**TYP**<br>**MAX**<br>~~eG~~|**UNIT**<br>~~eG~~|
|---|---|---|---|
|**Static Characteristics**<br>~~eG~~<br>~~Ce~~||||
|BVD1D2<br>Drain to Drain Voltage<br>~~Ce~~<br>~~a~~|VGS = 0V, ID1D2 = –250mA<br>~~Ce~~<br>~~G~~|–20<br>~~Ce~~<br>~~G~~|V<br>~~Ce~~<br>~~G~~|
|BVGSS<br>Gate to Source Voltage<br>~~a~~<br>~~eG~~|VD1D2 = 0V, IG = -250mA<br>~~G~~<br>~~eG~~|-6.1<br>-7.2<br>~~G~~<br>~~eG~~|V<br>~~G~~<br>~~eG~~|
|IDDS<br>Drain to Drain Leakage Current<br>~~eG~~<br>~~eG~~|VGS = 0V, VD1D2 = –16V<br>~~eG~~<br>~~eG~~|–1<br>~~eG~~<br>~~eG~~|mA<br>~~eG~~<br>~~eG~~|
|IGSS<br>Gate to Source Leakage Current<br>~~eG~~<br>~~eG~~|VD1D2 = 0V, VGS = -6V<br>~~eG~~<br>~~eG~~|–100<br>~~eG~~<br>~~eG~~|nA<br>~~eG~~<br>~~eG~~|
|VGS(th)<br>Gate to Source Threshold Voltage<br>~~eG~~<br>~~eG~~|VD1D2 = VGS, IDS = –250mA<br>~~eG~~<br>~~eG~~|–0.5<br>–0.7<br>–0.9<br>~~eG~~<br>~~eG~~|V<br>~~eG~~<br>~~eG~~|
|RD1D2(on)<br>Drain to Drain On Resistance<br>~~eG~~|VGS = –1.8V, ID1D2 = –1A<br>~~eG~~<br>~~es~~|140<br>175<br>~~eG~~<br>~~es~~|mΩ<br>~~eG~~<br>~~es~~|
||VGS = –2.5V, ID1D2 = –1A<br>~~es~~<br>~~es~~|105<br>130<br>~~es~~<br>~~es~~|mΩ<br>~~es~~<br>~~es~~|
||VGS = –4.5V, ID1D2 = –1A<br>~~es~~<br>~~es~~|80<br>100<br>~~es~~<br>~~es~~|mΩ<br>~~es~~<br>~~es~~|
|gfs<br>Transconductance<br>~~eG~~|VD1D2 = –10V, ID1D2 = –1A<br>~~es~~<br>~~eG~~|5.3<br>~~es~~<br>~~eG~~|S<br>~~es~~<br>~~eG~~|
|**Dynamic Characteristics**<br>~~eG~~<br>~~|~~<br>~~PO~~<br>~~Pr~~||||
|CISS<br>Input Capacitance<br>~~|~~<br>~~PO~~<br>~~PO~~|VGS= 0V, VD1D2= –10V,<br>f = 1MHz<br>~~|~~|315<br>410<br>~~|~~<br>~~Pr~~<br>~~PT~~|pF<br>~~|~~<br>~~Pr~~<br>~~PT~~|
|COSS<br>Output Capacitance<br>~~PO~~<br>~~PO~~<br>~~pO~~||128<br>165<br>~~Pr~~<br>~~PT~~<br>~~PC~~|pF<br>~~Pr~~<br>~~PT~~<br>~~PC~~|
|CRSS<br>Reverse Transfer Capacitance<br>~~PO~~<br>~~pO~~<br>~~PO~~||43<br>55<br>~~PT~~<br>~~PC~~<br>~~PC~~|pF<br>~~PT~~<br>~~PC~~<br>~~PC~~|
|Qg<br>Gate Charge Total(–4.5V)<br>~~pO~~<br>~~PO~~<br>~~PO~~|VD1D2= –10V,<br>ID1D2= –1A|2.8<br>3.9<br>~~PC~~<br>~~PC~~<br>~~PT~~|nC<br>~~PC~~<br>~~PC~~<br>~~PT~~|
|Qgd<br>Gate Charge - Gate to Drain<br>~~PO~~<br>~~PO~~<br>~~PO~~||0.6<br>~~PC~~<br>~~PT~~<br>~~PT~~|nC<br>~~PC~~<br>~~PT~~<br>~~PT~~|
|Qgs<br>Gate Charge - Gate to Source<br>~~PO~~<br>~~PO~~<br>~~pO~~||0.5<br>~~PT~~<br>~~PT~~<br>~~PC~~|nC<br>~~PT~~<br>~~PT~~<br>~~PC~~|
|Qg(th)<br>Gate Charge at Vth<br>~~PO~~<br>~~pO~~||0.2<br>~~PT~~<br>~~PC~~|nC<br>~~PT~~<br>~~PC~~|
|QOSS<br>Output Charge<br>~~pO~~<br>~~eG~~<br>~~PO~~|VD1D2 = –9.5V, VGS = 0V<br>~~eG~~|2.2<br>~~PC~~<br>~~eG~~<br>~~PC~~|nC<br>~~PC~~<br>~~eG~~<br>~~PC~~|
|td(on)<br>Turn On Delay Time<br>~~eG~~<br>~~PO~~<br>~~PO~~|VD1D2= –10V, VGS= –4.5V,<br>ID1D2= –1A, RG= 30Ω<br>~~eG~~|7.8<br>~~eG~~<br>~~PC~~<br>~~PT~~|ns<br>~~eG~~<br>~~PC~~<br>~~PT~~|
|tr<br>Rise Time<br>~~PO~~<br>~~PO~~<br>~~PO~~||6.7<br>~~PC~~<br>~~PT~~<br>~~PT~~|ns<br>~~PC~~<br>~~PT~~<br>~~PT~~|
|td(off)<br>Turn Off Delay Time<br>~~PO~~<br>~~PO~~<br>~~PO~~||45<br>~~PT~~<br>~~PT~~<br>~~PT~~|ns<br>~~PT~~<br>~~PT~~<br>~~PT~~|
|tf<br>Fall Time<br>~~PO~~<br>~~PO~~||26<br>~~PT~~<br>~~PT~~|ns<br>~~PT~~<br>~~PT~~|
|**Diode Characteristics**<br>~~PO~~<br>~~PT~~<br>~~|~~||||
|VSD<br>Diode Forward Voltage<br>~~|~~<br>~~a~~|ID1D2 = –1A, VGS = 0V<br>~~|~~<br>~~a~~<br>~~G~~|0.75<br>1<br>~~|~~<br>~~a~~<br>~~G~~|V<br>~~|~~<br>~~a~~<br>~~G~~|
|Qrr<br>Reverse RecoveryCharge<br>~~a~~<br>~~eG~~|Vdd = –9.5V, IF = –1A, di/dt = 200A/ms<br>~~a~~<br>~~G~~<br>~~eG~~|10.5<br>~~a~~<br>~~G~~<br>~~eG~~|nC<br>~~a~~<br>~~G~~<br>~~eG~~|
|trr<br>Reverse RecoveryTime<br>~~eG~~<br>~~eG~~|Vdd = –9.5V, IF = –1A, di/dt = 200A/ms<br>~~eG~~<br>~~eG~~|23<br>~~eG~~<br>~~eG~~|ns<br>~~eG~~<br>~~eG~~|



## **THERMAL CHARACTERISTICS** 

## (TA = 25°C unless otherwise stated) 

|**THERMAL CHARACTERISTICS**<br>(TAA = 25°C5°C°CC unless otherwise stated)|**THERMAL CHARACTERISTICS**<br>(TAA = 25°C5°C°CC unless otherwise stated)|||
|---|---|---|---|
|**PARAMETER**||**MIN**<br>**TYP**<br>**MAX**|**UNIT**|
|R qJA|Thermal Resistance Junction to Ambient(1) (2)|200|°C/W|
||Thermal Resistance Junction to Ambient (3) (2)|94|°C/W|



(1) Device mounted on FR4 material with Minimum Cu mounting area. 

(2) Measured with both devices biased in a parallel condition. 

(3) Device mounted on FR4 material with 1-inch[2] of Cu (2oz). 

_Submit Documentation Feedback_ 

2 

Copyright © 2009–2010, Texas Instruments Incorporated 

Product Folder Link(s): _CSD75204W15_ 

**CSD75204W15** 

SLPS221A –OCTOBER 2009–REVISED OCTOBER 2010 

**www.ti.com** 

Max R q JA = 94°C/W when mounted on 1 inch[2] (6.45 cm[2] ) of 2-oz. (0.071-mm thick) Cu. `G1 S G2 D2 D1` M0169-01 

**==> picture [130 x 132] intentionally omitted <==**

**----- Start of picture text -----**<br>
G1 S G2 D2 D1<br>M0170-01<br>**----- End of picture text -----**<br>


Max R q JA = 200°C/W when mounted on minimum pad area of 2-oz. (0.071-mm thick) Cu. 

## **TYPICAL MOSFET CHARACTERISTICS** 

Graphs are Per MOSFET at TA = 25°C, unless stated otherwise. Drain to Drain measurements are done with both MOSFETs in series (common source configuration). 

**==> picture [491 x 224] intentionally omitted <==**

**----- Start of picture text -----**<br>
10<br>1<br>0.5<br>0.3<br>0.1 0.1<br>0.05<br>0.02 Duty�Cycle�=�t 1 /t 2<br>0.01 0.01<br>P<br>Single�Pulse t1<br>0.001 t 2<br>Typical�R�JA =�161 C/W�(min�Cu)o<br>T J =�P x�Z �JA x�R �JA<br>0.0001<br>0.0001 0.001 0.01 0.1 1 10 100 1k<br>t P −Pulse�Duration −s<br>G012<br> −Normalized Thermal�Impedance<br>θJA<br>Z<br>**----- End of picture text -----**<br>


**Figure 1. Transient Thermal Impedance** 

_Submit Documentation Feedback_ 

3 

Copyright © 2009–2010, Texas Instruments Incorporated 

Product Folder Link(s): _CSD75204W15_ 

**CSD75204W15** 

SLPS221A –OCTOBER 2009–REVISED OCTOBER 2010 

**www.ti.com** 

## **TYPICAL MOSFET CHARACTERISTICS (continued)** 

Graphs are Per MOSFET at TA = 25°C, unless stated otherwise. Drain to Drain measurements are done with both MOSFETs in series (common source configuration). 

**==> picture [225 x 547] intentionally omitted <==**

**----- Start of picture text -----**<br>
5.0<br>4.5<br>4.0 V GS  = −1.8V<br>VGS = −2V<br>3.5<br>3.0<br>2.5<br>2.0<br>VGS = −2.5V VGS = −1.5V<br>1.5<br>1.0 V GS  = −4.5V<br>0.5<br>0.0<br>0.0 0.5 1.0 1.5 2.0 2.5 3.0<br>−VD1D2 −Drain�to�Drain�Voltage −V G001<br>Figure 2. Saturation Characteristics<br>6<br>ID1D2 = −1A<br>5 V D1D2  = −10V<br>4<br>3<br>2<br>1<br>0<br>0.0 0.5 1.0 1.5 2.0 2.5 3.0<br>Qg − Gate Charge − nC G003<br>Figure 4. Gate Charge<br>1.0<br>0.9 I D1D2  = −250µA<br>0.8<br>0.7<br>0.6<br>0.5<br>0.4<br>0.3<br>0.2<br>0.1<br>0.0<br>−75 −25 25 75 125 175<br>TJ − Junction Temperature − °C G005<br> −Drain�to�Drain�Current −A<br>D1D2<br>−I<br> − Gate to Source Voltage − V<br>GS<br>−V<br> − Threshold Voltage − V<br>GS(th)<br>−V<br>**----- End of picture text -----**<br>


**Figure 6. Threshold Voltage vs. Temperature** 

**==> picture [224 x 547] intentionally omitted <==**

**----- Start of picture text -----**<br>
5.0<br>4.5 V D1D2  = −5V<br>4.0<br>3.5<br>3.0 T J  = 125°C<br>2.5<br>2.0 TJ = 25°C<br>1.5<br>1.0<br>0.5 TJ = −55°C<br>0.0<br>0.50 0.75 1.00 1.25 1.50 1.75<br>−VGS − Gate to Source Voltage − V G002<br>Figure 3. Transfer Characteristics<br>400<br>f = 1MHz<br>350<br>VGS = 0V<br>300<br>250 COSS = CDS + CGD CISS = CGD + CGS<br>200<br>150<br>100 CRSS = CGD<br>50<br>0<br>0 5 10 15 20<br>−VD1D2 − Drain to Drain Voltage − V G004<br>Figure 5. Capacitance<br>300<br>ID1D2 = −1A<br>250<br>200 TJ = 125°C<br>150 TJ = 25°C<br>100<br>50<br>0<br>0 1 2 3 4 5 6<br>−VGS − Gate to Source Voltage − V G006<br> − Drain to Drain Current − A<br>D1D2<br>−I<br>C − Capacitance − pF<br>Ω<br> − On-State Resistance − m<br>D1D2(on)<br>R<br>**----- End of picture text -----**<br>


**Figure 7. On-State Resistance vs. Gate to Source Voltage** 

_Submit Documentation Feedback_ 

4 

Copyright © 2009–2010, Texas Instruments Incorporated 

Product Folder Link(s): _CSD75204W15_ 

**CSD75204W15** 

SLPS221A –OCTOBER 2009–REVISED OCTOBER 2010 

**www.ti.com** 

## **TYPICAL MOSFET CHARACTERISTICS (continued)** 

Graphs are Per MOSFET at TA = 25°C, unless stated otherwise. Drain to Drain measurements are done with both MOSFETs in series (common source configuration). 

**==> picture [225 x 352] intentionally omitted <==**

**----- Start of picture text -----**<br>
1.6<br>ID1D2 = −1A<br>1.4<br>V GS  = −4.5V<br>1.2<br>1.0<br>0.8<br>0.6<br>0.4<br>0.2<br>0.0<br>−75 −25 25 75 125 175<br>TJ − Case Temperature − °C G007<br>Figure 8. Normalized On-State Resistance vs.<br>100<br>10<br>1ms<br>1<br>10ms<br>0.1 Area�Limited by�RD1D2(on) 100ms<br>Typical�RSingle�Pulse �JA =�161 C/W�(min�Cu) o DC<br>0.01<br>0.1 1 10 100<br>−VD1D2 −Drain�to�Drain�Voltage −V G009<br> −Drain�to�Drain�Current −A<br>D1D2<br>−I<br>Normalized On-State Resistance<br>**----- End of picture text -----**<br>


**Figure 8. Normalized On-State Resistance vs. Temperature** 

**Figure 10. Maximum Safe Operating Area** 

**==> picture [225 x 351] intentionally omitted <==**

**----- Start of picture text -----**<br>
10<br>1 TJ = 125°C<br>0.1<br>TJ = 25°C<br>0.01<br>0.001<br>0.0001<br>0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4<br>−VSD − Source to Drain Voltage − V G008<br>Figure 9. Typical Diode Forward Voltage<br>4.5<br>4.0<br>3.5<br>3.0<br>2.5<br>2.0<br>1.5<br>1.0<br>0.5<br>0.0<br>−50 −25 0 25 50 75 100 125 150 175<br>TJ − Junction Temperature − °C G011<br> − Source to Drain Current − A<br>SD<br>−I<br> − Drain to Drain Current − A<br>D1D2<br>−I<br>**----- End of picture text -----**<br>


**Figure 11. Maximum Drain Current vs. Temperature** 

_Submit Documentation Feedback_ 5 

Copyright © 2009–2010, Texas Instruments Incorporated 

Product Folder Link(s): _CSD75204W15_ 

**CSD75204W15** 

SLPS221A –OCTOBER 2009–REVISED OCTOBER 2010 

**www.ti.com** 

## **MECHANICAL DATA** 

## **CSD75204W15 Package Dimensions** 

**==> picture [501 x 377] intentionally omitted <==**

**----- Start of picture text -----**<br>
Pin�1 Solder�Ball<br>Mark Ø�0.31 ±0.075<br>1 2 3 3 2 1<br>A A<br>B B<br>C C<br>1.50 [+0.00] –0.08 0.62�Max 0.50<br>Top�View Side�View Bottom�View<br>Seating�Plate<br>Front�View<br>0.50<br>+0.00 –0.08<br>1.00<br>1.50<br>0.35 ±0.10<br>0.04<br>0.62�Max<br>**----- End of picture text -----**<br>


**==> picture [24 x 5] intentionally omitted <==**

**----- Start of picture text -----**<br>
M0171-01<br>**----- End of picture text -----**<br>


NOTE: All dimensions are in mm (unless otherwise specified) 

**Pinout** 

|**POSITION**|**DESIGNATION**|
|---|---|
|A1|Gate1|
|A2, A3, B3|Drain1|
|C1|Gate2|
|C2, C3, B2|Drain2|
|B1|Source Sense|



_Submit Documentation Feedback_ 

6 

Copyright © 2009–2010, Texas Instruments Incorporated 

Product Folder Link(s): _CSD75204W15_ 

**CSD75204W15** 

SLPS221A –OCTOBER 2009–REVISED OCTOBER 2010 

**www.ti.com** 

## **Land Pattern Recommendation** 

**==> picture [217 x 209] intentionally omitted <==**

**----- Start of picture text -----**<br>
�0.25<br>1 2 3<br>A<br>B<br>C<br>0.50<br>M0172-01<br>0.50<br>1.00<br>**----- End of picture text -----**<br>


NOTE: All dimensions are in mm (unless otherwise specified) 

## **Tape and Reel Information** 

**==> picture [494 x 268] intentionally omitted <==**

**----- Start of picture text -----**<br>
4.00�±0.10 2.00�±0.05 Ø�1.50�±0.10<br>5°�Max<br>4.00�±0.10 Ø�0.50�±0.05<br>0.86�±0.05 0.254�±0.02<br>5°�Max<br>1.60�±0.05<br>M0173-01<br>+0.30 –0.10<br>8.00 1.75�±0.10<br>3.50�±0.05<br>1.60�±0.05<br>**----- End of picture text -----**<br>


NOTE: All dimensions are in mm (unless otherwise specified) 

_Submit Documentation Feedback_ 

7 

Copyright © 2009–2010, Texas Instruments Incorporated 

Product Folder Link(s): _CSD75204W15_ 

**CSD75204W15** 

SLPS221A –OCTOBER 2009–REVISED OCTOBER 2010 

**www.ti.com** 

## **REVISION HISTORY** 

|**Changes from Original (October 2009) to Revision A**<br>**Page**|
|---|
|•<br>Deleted the Package Marking Information sectiom .............................................................................................................. 7|



8 _Submit Documentation Feedback_ 

Copyright © 2009–2010, Texas Instruments Incorporated 

Product Folder Link(s): _CSD75204W15_ 

## **IMPORTANT NOTICE** 

Texas Instruments Incorporated (TI) reserves the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. 

TI’s published terms of sale for semiconductor products (http://www.ti.com/sc/docs/stdterms.htm) apply to the sale of packaged integrated circuit products that TI has qualified and released to market. Additional terms may apply to the use or sale of other types of TI products and services. 

Reproduction of significant portions of TI information in TI data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such reproduced documentation. Information of third parties may be subject to additional restrictions. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. 

Buyers and others who are developing systems that incorporate TI products (collectively, “Designers”) understand and agree that Designers remain responsible for using their independent analysis, evaluation and judgment in designing their applications and that Designers have full and exclusive responsibility to assure the safety of Designers' applications and compliance of their applications (and of all TI products used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will thoroughly test such applications and the functionality of such TI products as used in such applications. 

TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information, including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource solely for this purpose and subject to the terms of this Notice. 

TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections, enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically described in the published documentation for a particular TI Resource. Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. 

TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM, INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL, DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. 

Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949 and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements. 

Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use. Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S. 

TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product). Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory requirements in connection with such selection. 

Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice. 

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2017, Texas Instruments Incorporated