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BUK9Y53-100B,115
Power MOSFET, N Channel, 100 V, 23 A, 0.049 ohm, LFPAK56, Surface Mount
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- Manufacturer: NEXPERIA
- Product type: Single MOSFETs
- MSL: MSL 1 - Unlimited
- SVHC: Lead (25-Jun-2025)
- No. of Pins: 4Pins
- Channel Type: N Channel
- Product Range: TrenchMOS
- Qualification: AEC-Q101
- Power Dissipation: 75W
- Transistor Mounting: Surface Mount
- Rds(on) Test Voltage: 10V
- Transistor Case Style: LFPAK56
- Drain Source Voltage Vds: 100V
- Operating Temperature Max: 175°C
- Continuous Drain Current Id: 23A
- Drain Source On State Resistance: 0.049ohm
- Gate Source Threshold Voltage Max: 1.5V
| Delivery and price | |
|---|---|
| Units per pack | 500 |
| Price | 0.879 € |
| Current stock | 1000+ |
| Lead time | 30 days |
Datasheet
**==> picture [102 x 65] intentionally omitted <==** ## **BUK9Y53-100B** ## **N-channel TrenchMOS logic level FET** **Rev. 01 — 30 August 2007** ## **Product data sheet** ## **1.** ## **1.1 General description** N-channel enhancement mode power Field-Effect Transistor (FET) in a plastic package using NXP High-Performance Automotive (HPA) TrenchMOS technology. ## **1.2 Features** I Very low on-state resistance I 175 °C rated I Q101 compliant I Logic level compatible ## **1.3 Applications** I Automotive systems I Motors, lamps and solenoids I General purpose power switching I 12 V, 24 V and 42 V loads ## **1.4 Quick reference data** I E ≤ 85 mJ DS(AL)S I ID ≤ 23 A I RDSon = 45 mΩ (typ) I Ptot ≤ 75 W ## **2. Pinning information** ## **Table 1. Pinning** **==> picture [497 x 98] intentionally omitted <==** **----- Start of picture text -----**<br> Pin Description Simplified outline Symbol<br>1, 2, 3 source (S)<br>mb D<br>4 gate (G)<br>mb mounting base; connected to drain (D)<br>G<br>1 2 3 4 mbl798 S1 S2 S3<br>**----- End of picture text -----**<br> **==> picture [72 x 10] intentionally omitted <==** **----- Start of picture text -----**<br> SOT669 (LFPAK)<br>**----- End of picture text -----**<br> **==> picture [211 x 101] intentionally omitted <==** **BUK9Y53-100B** **NXP Semiconductors** **N-channel TrenchMOS logic level FET** ## **3. Ordering information** ## **Table 2. Ordering information** |**Type number**|**Package**|**Package**|**Package**| |---|---|---|---| ||**Name**|**Description**|**Version**| |BUK9Y53-100B|LFPAK<br>plastic single-ended surface-mounted package (LFPAK); 4 leads<br>SOT669||| ## **4. Limiting values** ## **Table 3. Limiting values** In accordance with the Absolute Maximum Rating System (IEC 60134). |**Symbol**|**Parameter**|**Conditions**||||||||||**Min**|**Max**|**Unit**| |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| |VDS|drain-source voltage|||||||||||-|100|V| |VDGR|drain-gate voltage (DC)|RGS= 20 kΩ||||||||||-|100|V| |VGS|gate-source voltage|||||||||||-|±15|V| |ID|drain current|Tmb= 25°C; VGS|= 5 V;|see|Figure||2||and|3||-|23|A| |||Tmb= 100°C; VGS= 5 V; see||||Figure|||2|||-|16|A| |IDM|peak drain current|Tmb= 25°C; pulsed; tp≤10|||µs; see|||Figure|||3|-|94|A| |Ptot|total power dissipation|Tmb= 25°C; see|Figure|1||||||||-|75|W| |Tstg|storage temperature|||||||||||−55|+175|°C| |Tj|junction temperature|||||||||||−55|+175|°C| |**Source-drain diode**||||||||||||||| |IDR|reverse drain current|Tmb= 25°C||||||||||-|23|A| |IDRM|peak reverse drain current|Tmb= 25°C; pulsed; tp≤10|||µs|||||||-|94|A| |**Avalanche ruggedness**||||||||||||||| |EDS(AL)S|non-repetitive drain-source avalanche|unclamped inductive load; ID= 23 A;||||||||||-|85|mJ| ||energy|VDS≤100 V; VGS|= 5 V;|RGS= 50Ω;|||||starting at|||||| |||Tj= 25°C||||||||||||| |EDS(AL)R|repetitive drain-source avalanche|||||||||||-|[1]|-| ||energy|||||||||||||| [1] Conditions: a) Figure 16. b) Single-pulse avalanche rating limited by Tj(max) of 175 °C. c) Repetitive avalanche rating limited by Tj(avg) of 170 °C. d) Refer to application note AN10273 for further information. © NXP B.V. 2007. All rights reserved. BUK9Y53-100B_1 **Product data sheet** **Rev. 01 — 30 August 2007** **2 of 12** **BUK9Y53-100B** **NXP Semiconductors** **N-channel TrenchMOS logic level FET** **==> picture [497 x 272] intentionally omitted <==** **----- Start of picture text -----**<br> 003aab844 003aab225<br>120 30<br>Pder ID<br>(%) (A)<br>80 20<br>40 10<br>0 0<br>0 50 100 150 200 0 50 100 150 200<br>Tmb (°C) Tmb (°C)<br>Pder = ---------------------- PtotP ( tot25 ° C - ) × 100 % VGS ≥ 5 V<br>Fig 1. Normalized total power dissipation as a Fig 2. Continuous drain current as a function of<br>function of mounting base temperature mounting base temperature<br>**----- End of picture text -----**<br> **==> picture [481 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 003aab226<br>10 [3]<br>ID<br>(A)<br>Limit RDSon = VDS / ID<br>10 [2]<br>tp = 10 µs<br>10 100 µs<br>DC<br>1<br>1 ms<br>10 ms<br>100 ms<br>10 [−][1]<br>1 10 10 [2] 10 [3]<br>VDS (V)<br>**----- End of picture text -----**<br> Tmb = 25 °C; IDM is single pulse. **Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage** © NXP B.V. 2007. All rights reserved. BUK9Y53-100B_1 **Product data sheet** **Rev. 01 — 30 August 2007** **3 of 12** **BUK9Y53-100B** **NXP Semiconductors** **N-channel TrenchMOS logic level FET** ## **5. Thermal characteristics** ## **Table 4: Thermal characteristics** |**Symbol**|**Parameter**<br>**Conditions**|**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---| |Rth(j-mb)|thermal resistance from junction to mounting base see<br>Figure<br>4|-|-|2|K/W| **==> picture [481 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 003aab219<br>1<br>Zth(j−mb)<br>(K/W)<br>1 δ = 0.5<br>0.2<br>0.1<br>10 [−1] 0.05 P δ = Ttp<br>0.02<br>tp t<br>single pulse T<br>10 [−][2]<br>10 [−][6] 10 [−][5] 10 [−][4] 10 [−][3] 10 [−][2] 10 [−][1] 1<br>tp (s)<br>**----- End of picture text -----**<br> **Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration** © NXP B.V. 2007. All rights reserved. BUK9Y53-100B_1 **Product data sheet** **Rev. 01 — 30 August 2007** **4 of 12** **BUK9Y53-100B** **NXP Semiconductors** **N-channel TrenchMOS logic level FET** ## **6. Characteristics** ## **Table 5: Characteristics** ## Tj = 25 ° |**Symbol**<br>**Parameter**|**Conditions**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**| |---|---| |**Static characteristics**|| |V(BR)DSS<br>drain-source breakdown voltage|ID= 0.25 mA; VGS= 0 V| ||Tj= 25°C<br>100<br>-<br>-<br>V| ||Tj=−55°C<br>89<br>-<br>-<br>V| |VGS(th)<br>gate-source threshold voltage|ID= 1 mA; VDS= VGS; see<br>Figure<br>9and<br>10| ||Tj= 25°C<br>1.1<br>1.5<br>2<br>V| ||Tj= 175°C<br>0.5<br>-<br>-<br>V| ||Tj=−55°C<br>-<br>-<br>2.3<br>V| |IDSS<br>drain leakage current|VDS= 100 V; VGS= 0 V| ||Tj= 25°C<br>-<br>0.02<br>1<br>µA| ||Tj= 175°C<br>-<br>-<br>500<br>µA| |IGSS<br>gate leakage current|VGS=±15 V; VDS= 0 V<br>-<br>2<br>100<br>nA| |RDSon<br>drain-source on-state resistance|VGS= 5 V; ID= 10 A; see<br>Figure<br>6and<br>8| ||Tj= 25°C<br>-<br>45<br>53<br>mΩ| ||Tj= 175°C<br>-<br>-<br>132<br>mΩ| ||VGS= 4.5 V; ID= 10 A<br>-<br>-<br>59<br>mΩ| ||VGS= 10 V; ID= 10 A<br>-<br>41<br>49<br>mΩ| |**Dynamic characteristics**|| |QG(tot)<br>total gate charge|ID= 15 A; VDS= 80 V; VGS= 5 V;<br>see<br>Figure<br>14<br>-<br>18<br>-<br>nC<br>-<br>4.1<br>-<br>nC<br>-<br>8<br>-<br>nC| |QGS<br>gate-source charge|| |QGD<br>gate-drain charge|| |Ciss<br>input capacitance|VGS= 0 V; VDS= 25 V; f = 1 MHz;<br>see<br>Figure<br>12<br>-<br>1600<br>2130<br>pF<br>-<br>141<br>170<br>pF<br>-<br>60<br>82<br>pF| |Coss<br>output capacitance|| |Crss<br>reverse transfer capacitance|| |td(on)<br>turn-on delay time|VDS= 30 V; RL= 2.5Ω;<br>VGS= 5 V; RG= 10Ω<br>-<br>18<br>-<br>ns<br>-<br>26<br>-<br>ns<br>-<br>52<br>-<br>ns<br>-<br>16<br>-<br>ns| |tr<br>rise time|| |td(off)<br>turn-off delay time|| |tf<br>fall time|| |**Source-drain diode**|| |VSD<br>source-drain voltage|IS= 25 A; VGS= 0 V; see<br>Figure<br>15<br>-<br>0.85<br>1.2<br>V| |trr<br>reverse recovery time|IS= 20 A; dIS/dt =−100 A/µs;<br>VGS=0V; VR= 30 V<br>-<br>71<br>-<br>ns<br>-<br>83<br>-<br>nC| |Qr<br>recovered charge|| © NXP B.V. 2007. All rights reserved. BUK9Y53-100B_1 **Product data sheet** **Rev. 01 — 30 August 2007** **5 of 12** **BUK9Y53-100B** **NXP Semiconductors** **N-channel TrenchMOS logic level FET** **==> picture [497 x 527] intentionally omitted <==** **----- Start of picture text -----**<br> 003aab421 003aab423<br>60 56<br>VGS (V) = 15<br>5<br>ID 4 R(mDSonΩ)<br>(A) 3.4<br>52<br>40 3.2<br>3 48<br>20 2.8<br>44<br>2.6<br>2.4<br>2.2<br>0 40<br>0 2 4 6 8 10 3 6 9 12 15<br>VDS (V) VGS (V)<br>Tj = 25 °C Tj = 25 °C; ID = 20 A<br>Fig 5. Output characteristics: drain current as a Fig 6. Drain-source on-state resistance as a function<br>function of drain-source voltage; typical values of gate-source voltage; typical values<br>003aab422 03aa29<br>100 3<br>RDSon 3.8<br>(mΩ) VGS (V) = 3 3.4 45 a<br>80 15<br>2<br>60<br>1<br>40<br>20 0<br>0 10 20 30 40 ID (A) 50 -60 0 60 120 Tj (°C) 180<br>Tj = 25 °C a = ---------------------------- RDSon -<br>RDSon ( 25 ° C )<br>Fig 7. Drain-source on-state resistance as a function Fig 8. Normalized drain-source on-state resistance<br>of drain current; typical values factor as a function of junction temperature<br>**----- End of picture text -----**<br> © NXP B.V. 2007. All rights reserved. BUK9Y53-100B_1 **Product data sheet** **Rev. 01 — 30 August 2007** **6 of 12** **BUK9Y53-100B** **NXP Semiconductors** ## **N-channel TrenchMOS logic level FET** **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 003aab986<br>2.5<br>VGS(th)<br>(V)<br>2.0<br>max<br>1.5<br>typ<br>min<br>1.0<br>0.5<br>0.0<br>−60 0 60 120 180<br>Tj (°C)<br>**----- End of picture text -----**<br> ## ID = 1 mA; VDS = VGS **Fig 9. Gate-source threshold voltage as a function of junction temperature** **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 003aab425<br>50<br>gfs<br>(S)<br>40<br>30<br>20<br>5 10 15 20 25 30<br>ID (A)<br>**----- End of picture text -----**<br> Tj = 25 °C; VDS = 25 V **Fig 11. Forward transconductance as a function of drain current; typical values** **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 003aab987<br>10 [−][1]<br>ID<br>(A)<br>10 [−][2]<br>min typ max<br>10 [−][3]<br>10 [−][4]<br>10 [−][5]<br>10 [−][6]<br>0 1 2 3<br>VGS (V)<br>**----- End of picture text -----**<br> **==> picture [78 x 9] intentionally omitted <==** **----- Start of picture text -----**<br> Tj = 25 °C; VDS = VGS<br>**----- End of picture text -----**<br> **Fig 10. Sub-threshold drain current as a function of gate-source voltage** **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 003aab418<br>2500<br>C<br>(pF)<br>2000<br>Ciss<br>15000<br>1000<br>500 Coss<br>Crss<br>0<br>10 [−][1] 1 10 10 [2]<br>VDS (V)<br>**----- End of picture text -----**<br> VGS = 0 V; f = 1 MHz **Fig 12. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values** © NXP B.V. 2007. All rights reserved. BUK9Y53-100B_1 **Product data sheet** **Rev. 01 — 30 August 2007** **7 of 12** **BUK9Y53-100B** **NXP Semiconductors** **N-channel TrenchMOS logic level FET** **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 003aab424<br>50<br>ID<br>(A)<br>40<br>30<br>20<br>10<br>Tj = 175 °C Tj = 25 °C<br>0<br>0 1 2 3 4<br>VGS (V)<br>**----- End of picture text -----**<br> VDS = 25 V **Fig 13. Transfer characteristics: drain current as a function of gate-source voltage; typical values** **==> picture [233 x 209] intentionally omitted <==** **----- Start of picture text -----**<br> 003aab419<br>50<br>IS<br>(A)<br>40<br>30<br>20<br>Tj = 175 °C<br>Tj = 25 °C<br>10<br>0<br>0.0 0.2 0.4 0.6 0.8 1.0<br>VSD (V)<br>VGS = 0 V<br>**----- End of picture text -----**<br> **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 003aab420<br>5<br>VGS<br>(V)<br>4<br>VDS = 14 V<br>VDS = 80 V<br>3<br>2<br>1<br>0<br>0 5 10 15 20<br>QG (nC)<br>**----- End of picture text -----**<br> Tj = 25 °C; ID = 10 A **Fig 14. Gate-source voltage as a function of gate charge; typical values** **==> picture [233 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> 003aab224<br>10 [2]<br>IAL<br>(A) (1)<br>10 (2)<br>(3)<br>1<br>10 [−][3] 10 [−][2] 10 [−][1] 1 10<br>tAL (ms)<br>**----- End of picture text -----**<br> - See Table note 1 of Table 3 Limiting values. - (1) Single-pulse; Tj = 25 °C. - (2) Single-pulse; Tj = 150 °C. - (3) Repetitive. **Fig 15. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values** **Fig 16. Single-pulse and repetitive avalanche rating; avalanche current as a function of avalanche time** © NXP B.V. 2007. All rights reserved. BUK9Y53-100B_1 **Product data sheet** **Rev. 01 — 30 August 2007** **8 of 12** **BUK9Y53-100B** **NXP Semiconductors** **N-channel TrenchMOS logic level FET** ## **7. Package outline** ## **Plastic single-ended surface-mounted package (LFPAK); 4 leads** ## **SOT669** **==> picture [478 x 570] intentionally omitted <==** **----- Start of picture text -----**<br> A2<br>E A C<br>b2 c2 E1<br>L1 b3<br>mounting<br>base b4<br>D1<br>H D<br>L2<br>1 2 3 4<br>X<br>e b w M A c<br>1/2 e<br>A<br>(A )3<br>A1 C<br>θ<br>L<br>detail X<br>y C<br>0 2.5 5 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>UNIT A A1 A2 A3 b b2 b3 b4 c c2 D [(1)] D1max [(1)] E [(1)] E1(1) e H L L1 L2 w y θ<br>1.20 0.15 1.10 0.50 4.41 2.2 0.9 0.25 0.30 4.10 5.0 3.3 6.2 0.85 1.3 1.3 8°<br>mm 1.01 0.00 0.95 0.25 0.35 3.62 2.0 0.7 0.19 0.24 3.80 4.20 4.8 3.1 1.27 5.8 0.40 0.8 0.8 0.25 0.1 0°<br>Note<br>1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>04-10-13<br>SOT669 MO-235<br>06-03-16<br>**----- End of picture text -----**<br> **Fig 17. Package outline SOT669 (LFPAK)** © NXP B.V. 2007. All rights reserved. BUK9Y53-100B_1 **Product data sheet** **Rev. 01 — 30 August 2007** **9 of 12** **BUK9Y53-100B** **NXP Semiconductors** **N-channel TrenchMOS logic level FET** ## **8. Revision history** |**Table 6.**|**Revision**|**history**|||| |---|---|---|---|---|---| |**Document**|**ID**|**Release date**|**Data sheet status**|**Change notice**|**Supersedes**| |BUK9Y53-100B_01||20070830|Product data sheet|-|-| © NXP B.V. 2007. All rights reserved. BUK9Y53-100B_1 **Product data sheet** **Rev. 01 — 30 August 2007** **10 of 12** **BUK9Y53-100B** **NXP Semiconductors** **N-channel TrenchMOS logic level FET** ## **9. Legal information** ## **9.1 Data sheet status** |**Document statu**|**s**<br>**[1]**<br>**[2]**<br>**Product status**<br>**[3]**<br>**Defnition**| |---|---| |Objective [short] data sheet<br>Development<br>This document contains data from the objective specifcation for product development.|| |Preliminary [short] data sheet<br>Qualifcation<br>This document contains data from the preliminary specifcation.|| |Product [short] data sheet<br>Production<br>This document contains the product specifcation.|| [1] Please consult the most recently issued document before initiating or completing a design. [2] [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. ## **9.2** **Draft —** The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. **Short data sheet —** A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. ## **9.3 Disclaimers** **General —** Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. **Right to make changes —** NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. **Suitability for use —** NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. **Applications —** Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. **Limiting values —** the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. **Terms and conditions of sale —** NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. **No offer to sell or license —** Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. ## **9.4 Trademarks** Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. **TrenchMOS —** is a trademark of NXP B.V. ## **10. Contact information** For additional information, please visit: **http://www.nxp.com** **salesaddresses@nxp.com** © NXP B.V. 2007. All rights reserved. BUK9Y53-100B_1 **Product data sheet** **Rev. 01 — 30 August 2007** **11 of 12** **BUK9Y53-100B** **NXP Semiconductors** **N-channel TrenchMOS logic level FET** ## **11. Contents** |**11. **|**Contents**| |---|---| |**1**|**Product profle . . . . . . . . . . . . . . . . . . . . . . . . . . 1**| |1.1|General description. . . . . . . . . . . . . . . . . . . . . . 1| |1.2|Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1| |1.3|Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1| |1.4|Quick reference data. . . . . . . . . . . . . . . . . . . . . 1| |**2**|**Pinning information. . . . . . . . . . . . . . . . . . . . . . 1**| |**3**|**Ordering information . . . . . . . . . . . . . . . . . . . . . 2**| |**4**|**Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2**| |**5**|**Thermal characteristics. . . . . . . . . . . . . . . . . . . 4**| |**6**|**Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 5**| |**7**|**Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 9**| |**8**|**Revision history. . . . . . . . . . . . . . . . . . . . . . . . 10**| |**9**|**Legal information. . . . . . . . . . . . . . . . . . . . . . . 11**| |9.1|Data sheet status . . . . . . . . . . . . . . . . . . . . . . 11| |9.2|Defnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 11| |9.3|Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 11| |9.4|Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 11| |**10**|**Contact information. . . . . . . . . . . . . . . . . . . . . 11**| |**11**|**Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12**| **==> picture [151 x 121] intentionally omitted <==** Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. **© NXP B.V. 2007.** **All rights reserved.** For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **Date of release: 30 August 2007 Document identifier: BUK9Y53-100B_1**
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Novapart is a B2B electronic component broker specialising in stock shortages and cost reduction. We source hard-to-find parts and identify compliant alternatives across a catalogue of 410,000+ components from 500+ manufacturers.
Learn more →Stock Shortage Specialist
When a component is unavailable, discontinued or has an unacceptable lead time, we tap into our network of vetted European and Asian distributors to source what you need — without compromising on quality or traceability.
Request a quote →Compliant Alternatives
We identify pin-to-pin, electrically equivalent substitutes that meet the same certifications (RoHS, AEC-Q100, REACH) as your original specification — validated against datasheets, not just part numbers. Often at a lower cost.
BOM Analysis service →