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BUK9832-55A/CUX
Power MOSFET, N Channel, 55 V, 12 A, 0.029 ohm, SC-73, Surface Mount
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- Manufacturer: NEXPERIA
- Product type: Single MOSFETs
- SVHC: No SVHC (25-Jun-2025)
- No. of Pins: 4Pins
- Channel Type: N Channel
- Product Range: TrenchMOS Series
- Qualification: AEC-Q101
- Power Dissipation: 8W
- Transistor Mounting: Surface Mount
- Rds(on) Test Voltage: 10V
- Transistor Case Style: SC-73
- Drain Source Voltage Vds: 55V
- Operating Temperature Max: 150°C
- Continuous Drain Current Id: 12A
- Drain Source On State Resistance: 0.029ohm
- Gate Source Threshold Voltage Max: 1.5V
| Delivery and price | |
|---|---|
| Units per pack | 3000 |
| Price | 0.278 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
## **BUK9832-55A** ## **N-channel TrenchMOS logic level FET** **Rev. 02 — 1 June 2010** ## **Product data sheet** ## **1. Product profile** ## **1.1 General description** Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using TrenchMOS technology. This product has been designed and qualified to the appropriate AEC standard for use in automotive critical applications. ## **1.2 Features and benefits** - Low conduction losses due to low on-state resistance - Suitable for logic level gate drive sources - Q101 compliant ## **1.3 Applications** - 12 V and 24 V loads - Motors, lamps and solenoids - Automotive and general purpose power switching ## **1.4 Quick reference data** |**Quick reference data**|**Quick reference data**| |---|---| |**Table 1.**<br>**Quick reference data**|| |**Symbol**<br>**Parameter**|**Conditions**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**| |VDS<br>drain-source<br>voltage|Tj≥25 °C; Tj≤150 °C<br>-<br>-<br>55<br>V| |ID<br>drain current|VGS= 5 V; Tsp= 25 °C;<br>seeFigure 1<br>;see Figure 3<br>-<br>-<br>12<br>A| |Ptot<br>total power<br>dissipation|Tsp= 25 °C; seeFigure 2<br>-<br>-<br>8<br>W| |**Static characteristics**|| |RDSon<br>drain-source<br>on-state<br>resistance|VGS= 4.5 V; ID= 8 A;<br>Tj= 25 °C<br>-<br>-<br>36<br>mΩ| ||VGS= 10 V; ID= 8 A; Tj= 25 °C<br>-<br>25<br>29<br>mΩ| ||VGS= 5 V; ID= 8 A; Tj= 25 °C;<br>seeFigure 12<br>;seeFigure 13<br>-<br>27<br>32<br>mΩ| |**Avalanche ruggedness**|| |EDS(AL)S<br>non-repetitive<br>drain-source<br>avalanche energy|ID= 10 A; Vsup≤55 V;<br>RGS= 50 Ω; VGS= 5 V;<br>Tj(init)= 25 °C; unclamped<br>-<br>-<br>100<br>mJ| **==> picture [172 x 101] intentionally omitted <==** **BUK9832-55A** **NXP Semiconductors** **N-channel TrenchMOS logic level FET** ## **2. Pinning information** ## **Table 2. Pinning information** |**Pin**|**Symbol**|**Description**|**Simplified**|**Simplified**|**Simplified**|**outline**|**outline**|**outline**|**outline**|**outline**|**outline**||||**Graphic symbol**||||| |---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---| |1|G|gate|||||||||||||||||| |2|D|drain||||||||4|||||||D||| ||||||||||||||||||||| |3|S|source|||||||||||||||||| |4|D|drain||||1|||2|||3|||G<br>_mbb076_||S||| ||||**SOT223 (SC-73)**||||||||||||||||| ## **3. Ordering information** ## **Table 3. Ordering information** |**Type number**|**Package**| |---|---| ||**Name**<br>**Description**<br>**Version**| |BUK9832-55A|SC-73<br>plastic surface-mounted package with increased heatsink; 4<br>leads<br>SOT223| © NXP B.V. 2010. All rights reserved. All information provided in this document is subject to legal disclaimers. BUK9832-55A **Product data sheet** **Rev. 02 — 1 June 2010** **2 of 13** **BUK9832-55A** **NXP Semiconductors** **N-channel TrenchMOS logic level FET** ## **4. Limiting values** **Table 4. Limiting values** _In accordance with the Absolute Maximum Rating System (IEC 60134)._ |**Symbol**|**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**| |---|---|---|---|---|---|---| |VDS|drain-source voltage|Tj≥25 °C; Tj≤150 °C|-|-|55|V| |VDGR|drain-gate voltage|RGS= 20 kΩ|-|-|55|V| |VGS|gate-source voltage||-10|-|10|V| |ID|drain current|Tsp= 25 °C; VGS= 5 V; seeFigure 1<br>;|-|-|12|A| |||seeFigure 3||||| |||Tsp= 100 °C; VGS= 5 V; see Figure 1|-|-|7|A| |IDM|peak drain current|Tsp= 25 °C; tp≤10 µs; pulsed;|-|-|47|A| |||seeFigure 3||||| |Ptot|total power dissipation|Tsp= 25 °C; see Figure 2|-|-|8|W| |Tstg|storage temperature||-55|-|150|°C| |Tj|junction temperature||-55|-|150|°C| |VGSM|peak gate-source|pulsed; tp≤50 µs|-15|-|15|V| ||voltage|||||| |**Source-drain diode**|**Source-drain diode**|||||| |IS|source current|Tsp= 25 °C|-|-|12|A| |ISM|peak source current|tp≤10 µs; pulsed; Tsp= 25 °C|-|-|47|A| |**Avalanche ruggedness**||||||| |EDS(AL)S|non-repetitive|ID= 10 A; Vsup≤55 V; RGS= 50 Ω;|-|-|100|mJ| ||drain-source|VGS= 5 V; Tj(init)= 25 °C; unclamped||||| ||avalanche energy|||||| **==> picture [454 x 253] intentionally omitted <==** **----- Start of picture text -----**<br> 03aa25 03aa17<br>120 120<br>Ider EEREEEEE Pder BERR<br>(%)80 ESNEEEEEBERNGEEE (%)80 ENEREEEEEENSEEEE<br>40 40<br>LUE IN || LEN Ty<br>SERRE Ly EN TT<br>0 EEEEEAEE 0 Titi<br>0 50 100 150 200 0 50 100 N 150 | 200<br>Tsp (°C) Tsp (°C)<br>Fig 1. Normalized continuous drain current as a Fig 2. Normalized total power dissipation as a<br>function of solder point temperature function of solder point temperature<br>**----- End of picture text -----**<br> All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. BUK9832-55A **Product data sheet** **Rev. 02 — 1 June 2010** **3 of 13** **BUK9832-55A** **NXP Semiconductors** ## **N-channel TrenchMOS logic level FET** **==> picture [320 x 186] intentionally omitted <==** **----- Start of picture text -----**<br> 03nc44<br>10 [3]<br>ID<br>(A) po<br>10 [2]<br>SS RDSon = VDS/ID eee tp = 10 μs<br>OO ey<br>Po ae SE Re<br>100 μs<br>10<br>ee eee eeeee<br>1 ms<br>——=—===-=.-——_— ===. --- =e<br>PoE 10 ms<br>1 ee P δ = tp D.C. 100 ms<br>T<br>I} — RR<br>10 [−][1] | e a e e e<br>10 [−][2] [| BTLa tp T t POCETGOTTGG GO OO OO<br>10 [−][1] 1 10 10 [2]<br>VDS (V)<br>**----- End of picture text -----**<br> **Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage** ## **5. Thermal characteristics** ## **Table 5. Thermal characteristics** **==> picture [480 x 298] intentionally omitted <==** **----- Start of picture text -----**<br> Symbol Parameter Conditions Min Typ Max Unit<br>Rth(j-sp) thermal resistance - - 15 K/W<br>from junction to solder<br>point<br>Rth(j-a) thermal resistance see Figure 4 - 70 - K/W<br>from junction to<br>ambient<br>03nc45<br>10 [2]<br>Zth(j-sp) [oTSeo [TTT] TT)oe<br>(K/W) | |<br>10 aINNeoEI TIE | I — eTon|<br>δ = 0.5<br>Cot tr Ft ti<br>0.2<br>S e<br>0.1 1H ect<br>1<br>0.05<br>= 0.02 1Se P δ = —| tp |ll]<br>10 [−][1] TTI |r TT ITI T |<br>re ee ee — — I<br>Ser Single Shot tp | t ll]<br>er a l CoCr -| _ T | i<br>10 [−][2] me ee i—— —|<br>10 [−][6] 10 [−][5] 10 [−][4] 10 [−][3] 10 [−][2] 10 [−][1] 1 10 1 [2]<br>tp (s)<br>**----- End of picture text -----**<br> **Fig 4. Transient thermal impedance from junction to solder point as a function of pulse duration** All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. BUK9832-55A **Product data sheet** **Rev. 02 — 1 June 2010** **4 of 13** **BUK9832-55A** **NXP Semiconductors** **N-channel TrenchMOS logic level FET** ## **6. Characteristics** |**Table 6.**<br>**Characteristics**||| |---|---|---| |**Symbol**<br>**Parameter**|**Conditions**|**Min**<br>**Typ**<br>**Max**<br>**Unit**| |**Static characteristics**||| |V(BR)DSS<br>drain-source<br>breakdown voltage|ID= 0.25 mA; VGS= 0 V; Tj= -55 °C|50<br>-<br>-<br>V| ||ID= 0.25 mA; VGS= 0 V; Tj= 25 °C|55<br>-<br>-<br>V| |VGS(th)<br>gate-source threshold<br>voltage|ID= 1 mA; VDS= VGS; Tj= 25 °C;<br>seeFigure 11|1<br>1.5<br>2<br>V| ||ID= 1 mA; VDS= VGS; Tj= -55 °C;<br>seeFigure 11|-<br>-<br>2.3<br>V| ||ID= 1 mA; VDS= VGS; Tj= 150 °C;<br>seeFigure 11|0.6<br>-<br>-<br>V| |IDSS<br>drain leakage current|VDS= 55 V; VGS= 0 V; Tj= 150 °C|-<br>-<br>500<br>µA| ||VDS= 55 V; VGS= 0 V; Tj= 25 °C|-<br>0.05<br>10<br>µA| |IGSS<br>gate leakage current|VDS= 0 V; VGS= 10 V; Tj= 25 °C|-<br>2<br>100<br>nA| ||VDS= 0 V; VGS= -10 V; Tj= 25 °C|-<br>2<br>100<br>nA| |RDSon<br>drain-source on-state<br>resistance|VGS= 4.5 V; ID= 8 A; Tj= 25 °C|-<br>-<br>36<br>mΩ| ||VGS= 5 V; ID= 8 A; Tj= 150 °C;<br>seeFigure 12<br>;seeFigure 13|-<br>-<br>59<br>mΩ| ||VGS= 10 V; ID= 8 A; Tj= 25 °C|-<br>25<br>29<br>mΩ| ||VGS= 5 V; ID= 8 A; Tj= 25 °C;<br>seeFigure 12<br>;seeFigure 13|-<br>27<br>32<br>mΩ| |**Dynamic characteristics**||| |Ciss<br>input capacitance|VGS= 0 V; VDS= 25 V; f = 1 MHz;<br>Tj= 25 °C; seeFigure 14|-<br>1195<br>1594<br>pF| |Coss<br>output capacitance||-<br>212<br>254<br>pF| |Crss<br>reverse transfer<br>capacitance||-<br>144<br>198<br>pF| |td(on)<br>turn-on delay time|VDS= 30 V; RL= 1.2 Ω; VGS= 5 V;<br>RG(ext)= 10 Ω; Tj= 25 °C|-<br>14<br>-<br>ns| |tr<br>rise time||-<br>125<br>-<br>ns| |td(off)<br>turn-off delay time||-<br>64<br>-<br>ns| |tf<br>fall time||-<br>68<br>-<br>ns| |**Source-drain diode**||| |VSD<br>source-drain voltage|IS= 18 A; VGS= 0 V; Tj= 25 °C;<br>seeFigure 15|-<br>0.85<br>1.2<br>V| |trr<br>reverse recovery time|IS= 20 A; dIS/dt = -100 A/µs;<br>VGS= -10 V; VDS= 30 V; Tj= 25 °C|-<br>51<br>-<br>ns| |Qr<br>recovered charge||-<br>80<br>-<br>nC| © NXP B.V. 2010. All rights reserved. All information provided in this document is subject to legal disclaimers. **Rev. 02 — 1 June 2010** BUK9832-55A **Product data sheet** **5 of 13** **BUK9832-55A** **NXP Semiconductors** **N-channel TrenchMOS logic level FET** **==> picture [483 x 499] intentionally omitted <==** **----- Start of picture text -----**<br> 03nc41 03nc40<br>ID 90 35<br>(A) VGS (V) = 10 RDSon<br>80 76 (mΩ)<br>70 PT 5<br>60 30<br>50 4<br>40<br>30 25<br>20 = 3 —<br>10<br>0 =| 2.2 20 OTe<br>0 2 4 6 8 10 2 4 6 8 10<br>VDS (V) VGS (V)<br>Tj = 25°C Tj =25°CjIp =15A<br>Fig 5. Output characteristics: drain current as a Fig 6. Drain-source on-state resistance as a function<br>function of drain-source voltage; typical values of gate-source voltage; typical values<br>03aa36 03nc38<br>10 [-1] 30<br>ID (S)gfsgfsfs<br>(A)<br>10 [-2] ——effpeffp 25 | ft<br>20<br>10 [-3]<br>min typ max 15<br>= 7-= i<br>10 [-4]<br>= f = 10 ||<br>| |<br>10 [-5]<br>5<br>10 [-6] 0<br>0 i 1 2 3 0 p | 10 20 i ft 30 |} 40 50<br>VGS (V) ID (A)D (A) (A)<br>F223" OV Max T2297CC Vi. = 25¥ = 25¥ 25¥<br>Fig 7. Sub-threshold drain current as a function of Fig 8. Forward transconductance as a function of<br>gate-source voltage drain current; typical values<br>**----- End of picture text -----**<br> **==> picture [222 x 241] intentionally omitted <==** **----- Start of picture text -----**<br> 03nc38<br>30<br>(S)gfsgfsfs<br>25 | ft<br>20<br>15<br>i<br>10 ||<br>| |<br>5<br>0<br>0 p | 10 20 i ft 30 |} 40 50<br>ID (A)D (A) (A)<br>T2297CC Vi. = 25¥ = 25¥ 25¥<br>Fig 8. Forward transconductance as a function of<br>drain current; typical values<br>**----- End of picture text -----**<br> © NXP B.V. 2010. All rights reserved. All information provided in this document is subject to legal disclaimers. **Rev. 02 — 1 June 2010** BUK9832-55A **Product data sheet** **6 of 13** **BUK9832-55A** **NXP Semiconductors** **N-channel TrenchMOS logic level FET** **==> picture [186 x 185] intentionally omitted <==** **----- Start of picture text -----**<br> 03nc39<br>20<br>ID<br>(A)<br>15 TEE LLAL<br>10 EEL d L<br>Tj = 150 °C<br>5 T oa d<br>|<br>Tj = 25 °C<br>0 fae<br>0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5<br>VGS (V)<br>**----- End of picture text -----**<br> **Fig 9. Transfer characteristics: drain current as a function of gate-source voltage; typical values** **==> picture [191 x 186] intentionally omitted <==** **----- Start of picture text -----**<br> 03aa33<br>2.5<br>VGS(th)<br>FDL LLLLL<br>(V)<br>2<br>max<br>fe e<br>1.5 o p typ eee<br>1 BE L min PK<br> A<br>SoAEe<br>0.5<br>0 Ft | | tt | ft<br>-60 0 60 120 180<br>Tj (°C)<br>**----- End of picture text -----**<br> **Fig 11. Gate-source threshold voltage as a function of junction temperature** **==> picture [200 x 439] intentionally omitted <==** **----- Start of picture text -----**<br> 03nc37<br>5<br>VGS<br>(V) VDD = 14 V<br>4<br>ff<br>3<br>VDD = 44 V<br>Lf<br>2<br>oS<br>1 fo<br>0 fo<br>0 10 20 30<br>QG (nC)<br>T; = 25°C;Ip =15A<br>Fig 10. Gate-source voltage as a function of turn-on<br>gate charge; typical values<br>03nc42<br>80<br>RDSon<br>(mΩ) 70 Ft VGS (V) = 3 3.2 3.4 3.8 5<br>3.6 4<br>60<br>[ | |<br>50 eee<br>40<br>30<br>ZELT<br>ZZ<br>20<br>100 | | | | |<br>0 20 40 60 80<br>ID (A)<br>**----- End of picture text -----**<br> **Fig 10. Gate-source voltage as a function of turn-on gate charge; typical values** **Fig 12. Drain-source on-state resistance as a function of drain current; typical values** © NXP B.V. 2010. All rights reserved. All information provided in this document is subject to legal disclaimers. **Rev. 02 — 1 June 2010** BUK9832-55A **Product data sheet** **7 of 13** **BUK9832-55A** **NXP Semiconductors** **N-channel TrenchMOS logic level FET** **==> picture [429 x 186] intentionally omitted <==** **----- Start of picture text -----**<br> 03nc24 03nc43<br>a 2 a 3500<br>1.8 EEREi EEA C (pF)3000 Ciss FET|<br>1.6 A ~<br>1.4 Seee oe 2500 T SN EEA<br>Coss<br>1.2 4 mill \<br>EEE eA EEE 2000 Tits LN<br>1 Crss<br>0.80.6 aeSESEPe» eeEES 15001000 Astk STNNNNUNNINGllTESITTl<br>BEER EEE Nt<br>0.4<br>EEREee EE EEE 500 OUTILEil<br>0.2 es KN<br>0 Peea 0 LIMDILSTHillisREST<br>-60 -20 20 60 100 140 180 10 [−][2] 10 [−][1] 1 10 10 [2]<br>Tj (°C) VDS (V)<br>**----- End of picture text -----**<br> **Fig 13. Normalized drain source on-state resistance factor as a function of junction temperature** **Fig 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values** **==> picture [185 x 183] intentionally omitted <==** **----- Start of picture text -----**<br> 03nc36<br>60<br>IS<br>(A)<br>40<br>Tj = 150 °C<br>20<br>Tj = 25 °C<br>0<br>0.0 0.5 1.0 1.5<br>VSD (V)<br>**----- End of picture text -----**<br> **Fig 15. Reverse diode current as a function of reverse diode voltage; typical value** © NXP B.V. 2010. All rights reserved. All information provided in this document is subject to legal disclaimers. **Rev. 02 — 1 June 2010** BUK9832-55A **Product data sheet** **8 of 13** **BUK9832-55A** **NXP Semiconductors** **N-channel TrenchMOS logic level FET** ## **7. Package outline** **Plastic surface-mounted package with increased heatsink; 4 leads** ## **SOT223** **==> picture [478 x 570] intentionally omitted <==** **----- Start of picture text -----**<br> D B E A X<br>c<br>y<br>HE v M A<br>b1<br>4<br>Q<br>A<br>A1<br>1 2 3 Lp<br>e1 bp w M B detail X<br>e<br>0 2 4 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>UNIT A A1 bp b1 c D E e e1 HE Lp Q v w y<br>1.8 0.10 0.80 3.1 0.32 6.7 3.7 7.3 1.1 0.95<br>mm 4.6 2.3 0.2 0.1 0.1<br>1.5 0.01 0.60 2.9 0.22 6.3 3.3 6.7 0.7 0.85<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>04-11-10<br> SOT223 SC-73<br>06-03-16<br>**----- End of picture text -----**<br> ## **Fig 16. Package outline SOT223 (SC-73)** BUK9832-55A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. **Product data sheet** **Rev. 02 — 1 June 2010 9 of 13** **BUK9832-55A** **NXP Semiconductors** **N-channel TrenchMOS logic level FET** ## **8. Revision history** **Table 7. Revision history** |**Document ID**|**Release date**<br>**Data sheet status**|**Change notice**|**Supersedes**| |---|---|---|---| |BUK9832-55A v.2|20100601<br>Product data sheet|-|BUK9832-55A-01| |Modifications:|**•** The format of this data sheet has been redesigned to comply with the new identity guidelines||| ||of NXP Semiconductors.||| ||**•** Legal texts have been adapted to the new company name where appropriate.||| |BUK9832-55A-01|20010131<br>Product specification|-|-| |(9397 750 07734)|||| © NXP B.V. 2010. All rights reserved. All information provided in this document is subject to legal disclaimers. **Rev. 02 — 1 June 2010** BUK9832-55A **Product data sheet** **10 of 13** **BUK9832-55A** **NXP Semiconductors** **N-channel TrenchMOS logic level FET** ## **9. Legal information** ## **9.1 Data sheet status** |**Document status[1]**<br>**[2]**|**Product status[3]**|**Definition**| |---|---|---| |Objective [short] data sheet|Development|This document contains data from the objective specification for product development.| |Preliminary [short] data sheet|Qualification|This document contains data from the preliminary specification.| |Product [short] data sheet|Production|This document contains the product specification.| [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. ## **9.2 Definitions** **Draft** — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. **Short data sheet** — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. **Product specification** — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. ## **9.3 Disclaimers** **Limited warranty and liability** — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the _Terms and conditions of commercial sale_ of NXP Semiconductors. **Right to make changes** — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. **Suitability for use in automotive applications** — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. **Applications** — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer’s third party customer(s) (hereinafter both referred to as “Application”). It is customer’s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. **Quick reference data** — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. **Terms and conditions of commercial sale** — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. **No offer to sell or license** — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. © NXP B.V. 2010. All rights reserved. BUK9832-55A All information provided in this document is subject to legal disclaimers. **Product data sheet Rev. 02 — 1 June 2010** **11 of 13** **BUK9832-55A** **NXP Semiconductors** ## **N-channel TrenchMOS logic level FET** **Export control** — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. ## **9.4 Trademarks** Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. **Adelante** , **Bitport** , **Bitsound** , **CoolFlux** , **CoReUse** , **DESFire** , **EZ-HV** , **FabKey** , **GreenChip** , **HiPerSmart** , **HITAG** , **I²C-bus** logo, **ICODE** , **I-CODE** , **ITEC** , **Labelution** , **MIFARE** , **MIFARE Plus** , **MIFARE Ultralight** , **MoReUse** , **QLPAK** , **Silicon Tuner** , **SiliconMAX** , **SmartXA** , **STARplug** , **TOPFET** , **TrenchMOS** , **TriMedia** and **UCODE** — are trademarks of NXP B.V. **HD Radio** and **HD Radio** logo — are trademarks of iBiquity Digital Corporation. ## **10. Contact information** For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com © NXP B.V. 2010. All rights reserved. All information provided in this document is subject to legal disclaimers. **Rev. 02 — 1 June 2010** BUK9832-55A **Product data sheet** **12 of 13** **BUK9832-55A** **NXP Semiconductors** **N-channel TrenchMOS logic level FET** ## **11. Contents** |**11. **|**Contents**| |---|---| |**1**|**Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1**| |1.1|General description . . . . . . . . . . . . . . . . . . . . . .1| |1.2|Features and benefits. . . . . . . . . . . . . . . . . . . . .1| |1.3|Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1| |1.4|Quick reference data . . . . . . . . . . . . . . . . . . . . .1| |**2**|**Pinning information. . . . . . . . . . . . . . . . . . . . . . .2**| |**3**|**Ordering information. . . . . . . . . . . . . . . . . . . . . .2**| |**4**|**Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3**| |**5**|**Thermal characteristics . . . . . . . . . . . . . . . . . . .4**| |**6**|**Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .5**| |**7**|**Package outline . . . . . . . . . . . . . . . . . . . . . . . . . .9**| |**8**|**Revision history. . . . . . . . . . . . . . . . . . . . . . . . .10**| |**9**|**Legal information. . . . . . . . . . . . . . . . . . . . . . . .11**| |9.1|Data sheet status . . . . . . . . . . . . . . . . . . . . . . .11| |9.2|Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11| |9.3|Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .11| |9.4|Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .12| |**10**|**Contact information. . . . . . . . . . . . . . . . . . . . . .12**| Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. **© NXP B.V. 2010.** **All rights reserved.** For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **Date of release: 1 June 2010 Document identifier: BUK9832-55A**
Updated at April 24, 2026
Nexperia is a dedicated global leader in discretes, logic, and MOSFET devices. Built on over half a century of semiconductor expertise and operating independently since 2017, the company produces consistently reliable components at an exceptional volume of 85 billion units annually. With its own manufacturing facilities, Nexperia delivers industry-leading small packages that combine power and thermal efficiency with best-in-class quality, meeting the rigorous standards of the automotive sector. Our extensive Nexperia portfolio is heavily focused on discrete semiconductors, providing engineers with a robust selection of core building blocks. This includes a comprehensive range of diodes and rectifiers, featuring a vast selection of Zener single diodes and Schottky diodes designed for precise voltage regulation and efficient power routing. Additionally, we offer an expansive array of bipolar transistors and single MOSFETs tailored for reliable switching and amplification in demanding applications. Beyond these primary offerings, the lineup extends into specialized circuit protection and passive components. This includes transient voltage suppressor (TVS) diodes, Zener array diodes, and small signal diodes, alongside dual MOSFETs and fast recovery rectifiers. For comprehensive design needs, the selection also encompasses integrated passive filters, common mode chokes, and precision timers and oscillators, ensuring a complete solution for high-performance electronic systems.
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