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BUK6E4R0-75C
Power MOSFET, N Channel, 75 V, 120 A, 0.0036 ohm, SOT-226, Surface Mount
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- Manufacturer: NEXPERIA
- Product type: Single MOSFETs
- No. of Pins: 3Pins
- Channel Type: N Channel
- Power Dissipation: 306W
- Transistor Mounting: Surface Mount
- Transistor Polarity: N Channel
- Power Dissipation Pd: 306W
- Rds(on) Test Voltage: 10V
- On Resistance Rds(on): 0.0036ohm
- Transistor Case Style: SOT-226
- Drain Source Voltage Vds: 75V
- Operating Temperature Max: 175°C
- Continuous Drain Current Id: 120A
- Drain Source On State Resistance: 0.0036ohm
- Gate Source Threshold Voltage Max: 2.3V
| Delivery and price | |
|---|---|
| Units per pack | 7000 |
| Price | 1.04 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
## **BUK6E4R0-75C**
## **N-channel TrenchMOS FET**
**Rev. 02 — 30 August 2010**
## **Product data sheet**
## **1. Product profile**
## **1.1 General description**
Intermediate level gate drive N-channel enhancement mode Field-Effect Transistor (FET) in a plastic package using advanced TrenchMOS technology. This product has been designed and qualified to the appropriate AEC Q101 standard for use in high performance automotive applications.
## **1.2 Features and benefits**
- AEC Q101 compliant
- Suitable for intermediate level gate drive sources
- Suitable for thermally demanding environments due to 175 °C rating
## **1.3 Applications**
- 12 V Automotive systems
- Electric and electro-hydraulic power steering
- Motors, lamps and solenoid control
- Start-Stop micro-hybrid applications
- Transmission control
- Ultra high performance power switching
## **1.4 Quick reference data**
|**Table 1.**|**Quick reference data**|||||||
|---|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Conditions**||**Min**|**Typ**|**Max**|**Unit**|
|VDS|drain-source voltage|Tj≥25 °C; Tj≤175 °C||-|-|75|V|
|ID|drain current|VGS= 10 V; Tmb= 25 °C;|[1]|-|-|120|A|
|||see Figure 1||||||
|Ptot|total power|Tmb= 25 °C; see Figure 2||-|-|306|W|
||dissipation|||||||
|**Static characteristics**||||||||
|RDSon|drain-source on-state|VGS= 10 V; ID= 25 A;||-|3.6|4.2|mΩ|
||resistance|Tj= 25 °C; seeFigure 11||||||
**==> picture [172 x 101] intentionally omitted <==**
**BUK6E4R0-75C**
**NXP Semiconductors**
**N-channel TrenchMOS FET**
|**Table 1.**|**Quick reference data**|_…continued_|||||
|---|---|---|---|---|---|---|
|**Symbol**|**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|**Avalanche**|**ruggedness**||||||
|EDS(AL)S|non-repetitive|ID= 120 A; Vsup≤75 V;|-|-|523|mJ|
||drain-source|RGS= 50 Ω; VGS= 10 V;|||||
||avalanche energy|Tj(init)= 25 °C; unclamped|||||
|**Dynamic characteristics**|||||||
|QGD|gate-drain charge|ID= 25 A; VDS= 60 V;|-|63|-|nC|
|||VGS= 10 V; see Figure 13<br>;|||||
|||see Figure 14|||||
[1] Continuous current is limited by package.
## **2. Pinning information**
## **Table 2. Pinning information**
|**Pin**|**Symbol**|**Description**|**Simplified outline**|**Simplified outline**||**Graphic symbol**|||||
|---|---|---|---|---|---|---|---|---|---|---|
|1|G|gate|||||||||
|2|D|drain||mb||||D|||
|3|S|source|||||||||
|||||||G|||||
|mb|D|mounting base; connected to<br>drain||3<br>2<br>1||_mbb076_||S|||
||||**SOT226 (I2PAK)**||||||||
## **3. Ordering information**
## **Table 3. Ordering information**
|**Type number**|**Package**|
|---|---|
||**Name**<br>**Description**<br>**Version**|
|BUK6E4R0-75C|I2PAK<br>plastic single-ended package (I2PAK); TO-262<br>SOT226|
© NXP B.V. 2010. All rights reserved.
BUK6E4R0-75C
All information provided in this document is subject to legal disclaimers.
**Product data sheet**
**Rev. 02 — 30 August 2010**
**2 of 14**
**BUK6E4R0-75C**
**NXP Semiconductors**
**N-channel TrenchMOS FET**
## **4. Limiting values**
## **Table 4. Limiting values**
_In accordance with the Absolute Maximum Rating System (IEC 60134)._
|**Symbol**<br>**Parameter**|**Conditions**<br>**Min**<br>**Max**<br>**Unit**|
|---|---|
|VDS<br>drain-source voltage|Tj≥25 °C; Tj≤175 °C<br>-<br>75<br>V|
|VGS<br>gate-source voltage|DC<br>[1]<br>-16<br>16<br>V|
||Pulsed<br>[2]<br>-20<br>20<br>V|
|ID<br>drain current|Tmb= 25 °C; VGS= 10 V; seeFigure 1<br>[3]<br>-<br>120<br>A|
||Tmb= 100 °C; VGS= 10 V; seeFigure 1<br>[3]<br>-<br>120<br>A|
|IDM<br>peak drain current|Tmb= 25 °C; tp≤10 µs; pulsed;<br>seeFigure 3<br>-<br>670<br>A|
|Ptot<br>total power dissipation|Tmb= 25 °C; see Figure 2<br>-<br>306<br>W|
|Tstg<br>storage temperature|-55<br>175<br>°C|
|Tj<br>junction temperature|-55<br>175<br>°C|
|**Source-drain diode**||
|IS<br>source current|Tmb= 25 °C<br>[3]<br>-<br>120<br>A|
|ISM<br>peak source current|tp≤10 µs; pulsed; Tmb= 25 °C<br>-<br>670<br>A|
|**Avalanche ruggedness**||
|EDS(AL)S<br>non-repetitive drain-source<br>avalanche energy|ID= 120 A; Vsup≤75 V; RGS= 50 Ω;<br>VGS= 10 V; Tj(init)= 25 °C; unclamped<br>-<br>523<br>mJ|
|EDS(AL)R<br>repetitive drain-source<br>avalanche energy|[4]<br>[5]<br>[6]<br>-<br>-<br>J|
[1] -16V accumulated duration not to exceed 168 hrs
[2] Accumulated pulse duration not to exceed 5 mins.
[3] Continuous current is limited by package.
[4] Single-pulse avalanche rating limited by maximum junction temperature of 175 °C.
[5] Repetitive avalanche rating limited by an average junction temperature of 170 °C.
[6] Refer to application note AN10273 for further information.
© NXP B.V. 2010. All rights reserved.
BUK6E4R0-75C
All information provided in this document is subject to legal disclaimers.
**Product data sheet**
**Rev. 02 — 30 August 2010**
**3 of 14**
**BUK6E4R0-75C**
**NXP Semiconductors**
**N-channel TrenchMOS FET**
**==> picture [190 x 185] intentionally omitted <==**
**----- Start of picture text -----**<br>
003aae374<br>200<br>ID<br>(A)<br>150<br>PN EEE<br>P L PK L LL<br>(1)<br>100 PPR NEL<br>Se e<br>50 eft<br>tt TERI<br>0<br>0 50 100 150 200<br>Tmb (°C)<br>**----- End of picture text -----**<br>
**==> picture [190 x 186] intentionally omitted <==**
**----- Start of picture text -----**<br>
03aa16<br>120<br>Pder<br>(%)<br>\]<br>80 LINE EEL<br>40 TT INT TT<br>\<br>TTT TINE<br>0<br>0 50 100 150 200<br>Tmb (°C)<br>**----- End of picture text -----**<br>
**Fig 1. Continuous drain current as a function of Fig 2. Normalized total power dissipation as a mounting base temperature function of mounting base temperature**
**==> picture [436 x 186] intentionally omitted <==**
**----- Start of picture text -----**<br>
003aae376<br> 10 [3]<br>ID Limit RDSon = VDS / ID<br>SSS SE Se<br>(A)<br>tp =10 μ s<br> 10 [2] a|es te eeNTT 100 μ s<br>Po RNR RN<br>+f | ty ENS RHE _1—_f EE<br> 10<br>DC<br>ee N ea<br>1 ms<br>nc en n<br>RA N T fT tT EE<br> 1 10 ms<br>ee eee 100 ms eee<br>== =2S<br>10 [-1] foSsCUT CE CE TT SS ee e ae eeeeet<br>10 [-1] 1 10 10 [2] 10 [3]<br>V DS (V)<br>**----- End of picture text -----**<br>
**Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage**
© NXP B.V. 2010. All rights reserved.
BUK6E4R0-75C
All information provided in this document is subject to legal disclaimers.
**Product data sheet**
**Rev. 02 — 30 August 2010**
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**BUK6E4R0-75C**
**NXP Semiconductors**
**N-channel TrenchMOS FET**
## **5. Thermal characteristics**
## **Table 5. Thermal characteristics**
**==> picture [497 x 305] intentionally omitted <==**
**----- Start of picture text -----**<br>
Symbol Parameter Conditions Min Typ Max Unit<br>Rth(j-mb) thermal resistance from junction to see Figure 4 - - 0.49 K/W<br>mounting base<br>Rth(j-a) thermal resistance from junction to vertical in free air - 60 - K/W<br>ambient<br>003aae375<br> 1<br>Zth (K/W)<br>δ = 0.5<br>10 [-1]<br>0.2<br>0.1<br>0.05<br>P δ = tp<br>10 [-2] 0.02 T<br>single shot tp t<br>T<br>10 [-3]<br>10 [-6] 10 [-5] 10 [-4] 10 [-3] 10 [-2] 10 [-1] 1<br>tp (s)<br>Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration<br>**----- End of picture text -----**<br>
© NXP B.V. 2010. All rights reserved.
BUK6E4R0-75C
All information provided in this document is subject to legal disclaimers.
**Product data sheet**
**Rev. 02 — 30 August 2010**
**5 of 14**
**BUK6E4R0-75C**
**NXP Semiconductors**
**N-channel TrenchMOS FET**
## **6. Characteristics**
|**Table 6.**<br>**Characteristics**|||
|---|---|---|
|**Symbol**<br>**Parameter**|**Conditions**|**Min**<br>**Typ**<br>**Max**<br>**Unit**|
|**Static characteristics**|||
|V(BR)DSS<br>drain-source breakdown<br>voltage|ID= 250 µA; VGS= 0 V; Tj= 25 °C|75<br>-<br>-<br>V|
||ID= 250 µA; VGS= 0 V; Tj= -55 °C|68<br>-<br>-<br>V|
|VGS(th)<br>gate-source threshold voltage|ID= 1 mA; VDS= VGS; Tj= 25 °C;<br>seeFigure 9<br>;see Figure 10|1.8<br>2.3<br>2.8<br>V|
||ID= 1 mA; VDS= VGS; Tj= -55 °C;<br>seeFigure 10|-<br>-<br>3.3<br>V|
||ID= 2.5 mA; VDS= VGS; Tj= 175 °C;<br>seeFigure 10|0.8<br>-<br>-<br>V|
|IDSS<br>drain leakage current|VDS= 75 V; VGS= 0 V; Tj= 175 °C|-<br>-<br>500<br>µA|
||VDS= 75 V; VGS= 0 V; Tj= 25 °C|-<br>0.02<br>1<br>µA|
|IGSS<br>gate leakage current|VDS= 0 V; VGS= 20 V; Tj= 25 °C|-<br>2<br>100<br>nA|
||VDS= 0 V; VGS= -20 V; Tj= 25 °C|-<br>2<br>100<br>nA|
|RDSon<br>drain-source on-state<br>resistance|VGS= 10 V; ID= 25 A; Tj= 25 °C;<br>seeFigure 11|-<br>3.6<br>4.2<br>mΩ|
||VGS= 4.5 V; ID= 25 A; Tj= 25 °C;<br>seeFigure 11|-<br>4.4<br>6<br>mΩ|
||VGS= 5 V; ID= 25 A; Tj= 25 °C;<br>seeFigure 11|-<br>4.1<br>5.3<br>mΩ|
||||
||VGS= 10 V; ID= 25 A; Tj= 175 °C;<br>seeFigure 11<br>;seeFigure 12|-<br>-<br>10.9<br>mΩ|
|**Dynamic characteristics**|||
|QG(tot)<br>total gate charge|ID= 25 A; VDS= 60 V; VGS= 10 V;<br>seeFigure 13<br>; seeFigure 14|-<br>234<br>-<br>nC|
||ID= 25 A; VDS= 60 V; VGS= 5 V;<br>seeFigure 13<br>; seeFigure 14|-<br>132<br>-<br>nC|
|QGS<br>gate-source charge|ID= 25 A; VDS= 60 V; VGS= 10 V;<br>seeFigure 13<br>; seeFigure 14|-<br>32<br>-<br>nC|
|QGD<br>gate-drain charge||-<br>63<br>-<br>nC|
|Ciss<br>input capacitance|VGS= 0 V; VDS= 25 V; f = 1 MHz;<br>Tj= 25 °C; see Figure 15|-<br>11580<br>15450<br>pF|
|Coss<br>output capacitance||-<br>870<br>1040<br>pF|
|Crss<br>reverse transfer capacitance||-<br>580<br>800<br>pF|
|td(on)<br>turn-on delay time|VDS= 55 V; RL= 2.2 Ω; VGS= 10 V;<br>RG(ext)= 10 Ω|-<br>52<br>-<br>ns|
|tr<br>rise time||-<br>81<br>-<br>ns|
|td(off)<br>turn-off delay time||-<br>412<br>-<br>ns|
|tf<br>fall time||-<br>156<br>-<br>ns|
|LD<br>internal drain inductance|from drain lead 6 mm from package<br>to centre of die ; Tj= 25 °C|-<br>4.5<br>-<br>nH|
|LS<br>internal source inductance|from source lead to source bond<br>pad ; Tj= 25 °C|-<br>7.5<br>-<br>nH|
© NXP B.V. 2010. All rights reserved.
BUK6E4R0-75C **Product data sheet**
All information provided in this document is subject to legal disclaimers.
**Rev. 02 — 30 August 2010**
**6 of 14**
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**N-channel TrenchMOS FET**
**Table 6. Characteristics** _…continued_
|**Symbol**|**Parameter**|**Conditions**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|**Source-drain diode**|**Source-drain diode**||||||
|VSD|source-drain voltage|IS= 25 A; VGS= 0 V; Tj= 25 °C;|-|0.8|1.2|V|
|||seeFigure 16|||||
|trr|reverse recovery time|IS= 20 A; dIS/dt = -100 A/µs;|-|72|-|ns|
|Qr|recovered charge|VGS= 0 V; VDS= 25 V|-|218|-|nC|
**==> picture [480 x 487] intentionally omitted <==**
**----- Start of picture text -----**<br>
160 003aae377 100 003aae378<br>ID 5 4.5 VGS (V) = 4.0 ID<br>ea {ft<br>(A) (A) tt yg |<br>10<br>80<br>120 3.8<br>Yo<br>2 60 PPP<br>80<br>3.6<br>f o 40 si<br>| —— H EE Tj = 175 °C L<br>40 3.4 25 °C<br>Pe 20 TEE ATE<br>3.3<br>3.2<br>|Z TE E<br>0 y-—__T 0 a oe<br>0 1 2 3 0 1 2 3 4<br>VDS (V) VGS (V)<br>Tj = 25 °C; tp = 300 μs VDS < ID x RDSon<br>Fig 5. Output characteristics: drain current as a Fig 6. Transfer characteristics: drain current as a<br>function of drain-source voltage; typical values function of gate-source voltage; typical values<br>003aae383 003aae379<br>20 250<br>RDSon gfs<br>TT... PTT TLL,<br>(mΩ) (S)<br>200<br>15<br>SAE | 150 ACRE<br>10<br>FREER 100 nA<br>5<br>50<br>oe | AEEEEEE<br>0 P| | | | ft 0 AaPEECEPeece<br>0 4 8 12 0 25 50 75 100<br>VGS (V) ID (A)<br>Tj = 25 °C; ID = 25 A<br>Fig 7. Drain-source on-state resistance as a function Fig 8. Forward transconductance as a function of<br>of gate-source voltage; typical values. drain current; typical values<br>**----- End of picture text -----**<br>
**Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values**
© NXP B.V. 2010. All rights reserved.
BUK6E4R0-75C
All information provided in this document is subject to legal disclaimers.
**Product data sheet**
**Rev. 02 — 30 August 2010**
**7 of 14**
**BUK6E4R0-75C**
**NXP Semiconductors**
**N-channel TrenchMOS FET**
**==> picture [437 x 184] intentionally omitted <==**
**----- Start of picture text -----**<br>
003aad806 003aae542<br>10 [-1] 4<br>ID VGS(th)<br>(A) SS == Ep (V) tt<br>10 [-2] ee tt yt tT<br>se 3 [-—™— max @1mA<br>e e min typ max mF<br>10 [-3]<br>eee — — SO<br>p e r 2 PIN<br>es es Gy esOG —~_| typ @1mA SY<br>10 [-4] er LS<br>min @2.5mA<br>SS 1 | | | | |<br>10 [-5]<br>—————— WO !<br>SSS P| | tt tte re<br>10 [-6] ee [ee] [ee] 0 P| | tt tt fl<br>0 1 2 3 VGS (V) 4 -60 0 60 120 Tj (°C) 180<br>**----- End of picture text -----**<br>
**Fig 9. Sub-threshold drain current as a function of gate-source voltage**
**Fig 10. Gate-source threshold voltage as a function of junction temperature**
**==> picture [439 x 213] intentionally omitted <==**
**----- Start of picture text -----**<br>
003aae381 003aad804<br>12 3<br>VGS (V) = 3.4 3.6 3.8<br>a<br>RDSon 2.5 Feet<br>(mΩ)<br>T ot) | EEREEEE<br>8 J J) ff 2 FEEes<br>OY 4.0 1.5 ae<br>= 4.5 RH<br>4 | — 1<br>beret eT<br>10 5.0<br>CRE TE 0 0.5 EEEEE-eRAS EEE<br>0 Serre 0 PTFEEL E<br>0 40 80 120 -60 0 60 120 180<br>ID (A) Tj (°C)<br>Tj = 25 °C; tp = 300 μs<br>**----- End of picture text -----**<br>
**Fig 11. Drain-source on-state resistance as a function of drain current; typical values**
**Fig 12. Normalized drain-source on-state resistance factor as a function of junction temperature**
© NXP B.V. 2010. All rights reserved.
BUK6E4R0-75C
All information provided in this document is subject to legal disclaimers.
**Product data sheet**
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## **N-channel TrenchMOS FET**
**==> picture [463 x 500] intentionally omitted <==**
**----- Start of picture text -----**<br>
003aae452<br>10<br>VDS VGS<br>— TE<br>(V)<br>ID 8<br>i\\ Sanne 440<br>VGS(pl) an SeGen//4n8 14V<br>6<br>VGS(th) LY SEPP AZ VDS = 60V<br>C O A<br>VGS 4 SanyCannee<br>QGS1 QGS2<br>TT ey<br>QGS QGD 2 VAnReennne<br>QG(tot)<br>7ECE<br>003aaa508 ARGEESnen<br>0<br>0 50 100 150 200 250<br>QG (nC)<br>Tj; = 25°CjIp =25A<br>Gate charge waveform definitions Fig 14. Gate-source voltage as a function of gate<br>charge; typical values<br>003aae451 003aae425<br> 10 [5] 120<br>IS<br>C (A)<br>(pF) 100<br>easaieeii aa FSS<br> 10 [4] ee Ciss | 80 ee<br>60<br>SSSSTH SSS TT<br> 10 [3] aSi Coss ll 40 SS Tj = 175 °C Tj = 25 °C<br>Crss<br>20<br>asim nasliiimmmil SST FS<br>CE CCl Ta<br> 10 [2] 0<br>10 [-1] 1 10 10 [2] 0 0.3 0.6 0.9 1.2<br>VDS (V) VSD (V)<br>Ves = OV;f = 1MHz Ves= OV<br>Input, output and reverse transfer capacitances Fig 16. Source current as a function of source-drain<br>as a function of drain-source voltage; typical voltage; typical values<br>**----- End of picture text -----**<br>
**Fig 13. Gate charge waveform definitions**
**Fig 15. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values**
© NXP B.V. 2010. All rights reserved.
BUK6E4R0-75C
All information provided in this document is subject to legal disclaimers. **Rev. 02 — 30 August 2010**
**Product data sheet**
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**BUK6E4R0-75C**
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**N-channel TrenchMOS FET**
## **7. Package outline**
**Plastic single-ended package (I2PAK); low-profile 3-lead TO-262**
**SOT226**
**==> picture [478 x 561] intentionally omitted <==**
**----- Start of picture text -----**<br>
A<br>D1 E A1<br>mounting<br>base<br>D<br>L1<br>Q<br>b1<br>L<br>1 2 3<br>b c<br>e e<br>0 5 10 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>UNIT A A1 b b1 c maxD D1 E e L L1 Q<br>4.5 1.40 0.85 1.3 0.7 1.6 10.3 15.0 3.30 2.6<br>mm 11 2.54<br>4.1 1.27 0.60 1.0 0.4 1.2 9.7 13.5 2.79 2.2<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC JEITA PROJECTION<br>06-02-14<br> SOT226 TO-262<br>09-08-25<br>**----- End of picture text -----**<br>
## **Fig 17. Package outline SOT226 (I2PAK)**
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
BUK6E4R0-75C
**Product data sheet**
**Rev. 02 — 30 August 2010**
**10 of 14**
**BUK6E4R0-75C**
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**N-channel TrenchMOS FET**
## **8. Revision history**
|**Table 7.**<br>**Revision**|**history**||||
|---|---|---|---|---|
|**Document ID**|**Release date**|**Data sheet status**|**Change notice**|**Supersedes**|
|BUK6E4R0-75C v.2|20100830|Product data sheet|-|BUK6E4R0-75C v.1|
|Modifications:|**•** Status changed from objective to product.||||
||**•** Various changes to content.||||
|BUK6E4R0-75C v.1|20100709|Objective data sheet|-|-|
© NXP B.V. 2010. All rights reserved.
BUK6E4R0-75C
All information provided in this document is subject to legal disclaimers.
**Product data sheet**
**Rev. 02 — 30 August 2010**
**11 of 14**
**BUK6E4R0-75C**
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**N-channel TrenchMOS FET**
## **9. Legal information**
## **9.1 Data sheet status**
|**Document status[1]**<br>**[2]**|**Product status[3]**|**Definition**|
|---|---|---|
|Objective [short] data sheet|Development|This document contains data from the objective specification for product development.|
|Preliminary [short] data sheet|Qualification|This document contains data from the preliminary specification.|
|Product [short] data sheet|Production|This document contains the product specification.|
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term 'short data sheet' is explained in section "Definitions".
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
## **9.2 Definitions**
**Draft** — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information.
**Short data sheet** — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
**Product specification** — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet.
## **9.3 Disclaimers**
**Limited warranty and liability** — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the _Terms and conditions of commercial sale_ of NXP Semiconductors.
**Right to make changes** — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.
**Suitability for use in automotive applications** — This NXP Semiconductors product has been qualified for use in automotive applications. The product is not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.
**Quick reference data** — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
**Applications** — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products.
NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect.
**Limiting values** — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device.
**Terms and conditions of commercial sale** — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual
BUK6E4R0-75C
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved. **12 of 14**
**Product data sheet**
**Rev. 02 — 30 August 2010**
**BUK6E4R0-75C**
**NXP Semiconductors**
**N-channel TrenchMOS FET**
agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer.
**No offer to sell or license** — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
**Export control** — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
## **9.4 Trademarks**
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
**Adelante** , **Bitport** , **Bitsound** , **CoolFlux** , **CoReUse** , **DESFire** , **EZ-HV** , **FabKey** , **GreenChip** , **HiPerSmart** , **HITAG** , **I²C-bus** logo, **ICODE** , **I-CODE** , **ITEC** , **Labelution** , **MIFARE** , **MIFARE Plus** , **MIFARE Ultralight** , **MoReUse** , **QLPAK** , **Silicon Tuner** , **SiliconMAX** , **SmartXA** , **STARplug** , **TOPFET** , **TrenchMOS** , **TriMedia** and **UCODE** — are trademarks of NXP B.V.
**HD Radio** and **HD Radio** logo — are trademarks of iBiquity Digital Corporation.
## **10. Contact information**
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
© NXP B.V. 2010. All rights reserved.
BUK6E4R0-75C
All information provided in this document is subject to legal disclaimers.
**Product data sheet**
**Rev. 02 — 30 August 2010**
**13 of 14**
**BUK6E4R0-75C**
**NXP Semiconductors**
**N-channel TrenchMOS FET**
## **11. Contents**
|**11. **|**Contents**|
|---|---|
|**1**|**Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1**|
|1.1|General description . . . . . . . . . . . . . . . . . . . . . .1|
|1.2|Features and benefits. . . . . . . . . . . . . . . . . . . . .1|
|1.3|Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1|
|1.4|Quick reference data . . . . . . . . . . . . . . . . . . . . .1|
|**2**|**Pinning information. . . . . . . . . . . . . . . . . . . . . . .2**|
|**3**|**Ordering information. . . . . . . . . . . . . . . . . . . . . .2**|
|**4**|**Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3**|
|**5**|**Thermal characteristics . . . . . . . . . . . . . . . . . . .5**|
|**6**|**Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . .6**|
|**7**|**Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10**|
|**8**|**Revision history. . . . . . . . . . . . . . . . . . . . . . . . .11**|
|**9**|**Legal information. . . . . . . . . . . . . . . . . . . . . . . .12**|
|9.1|Data sheet status . . . . . . . . . . . . . . . . . . . . . . .12|
|9.2|Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . .12|
|9.3|Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .12|
|9.4|Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .13|
|**10**|**Contact information. . . . . . . . . . . . . . . . . . . . . .13**|
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.
**© NXP B.V. 2010.**
**All rights reserved.**
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com **Date of release: 30 August 2010 Document identifier: BUK6E4R0-75C**
Updated at February 9, 2023
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