BSS84

## **Is Now Part of** 

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February 2013<br>**----- End of picture text -----**<br>


## **BSS84** 

## **P-Channel Enhancement Mode Field-Effect Transistor** 

## **Features** 

- -0.13 A, -50 V,  RDS(ON) = 10 Ω at VGS = -5 V 

- Voltage-Controlled P-Channel Small-Signal Switch 

- High-Density Cell Design for Low RDS(ON) 

- High Saturation Current 

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D<br>D<br>S<br>SOT-23 G G S<br>**----- End of picture text -----**<br>


## **Description** 

This P-channel enhancement-mode field-effect transistor is produced using Fairchild’s proprietary, high cell density, DMOS technology. This very high density process minimizes on-state resistance and to provide rugged and reliable performance and fast switching. The BSS84 can be used, with a minimum of effort, in most applications requiring up to 0.13 A DC and can deliver current up to 0.52 A. This product is particularly suited to low-voltage applications requiring a low-current high-side switch. 

## **Absolute Maximum Ratings** 

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Values are at TA = 25°C unless otherwise noted. 

|**Symbol**|**mbol**<br>**Parameter**|**mbol**<br>**Parameter**|**Ratings**|**Unit**|
|---|---|---|---|---|
|VDSS|Drain-Source Voltage||−50|V|
|VGSS|Gate-Source Voltage||±20|V|
|ID|Drain Current(1)|Continuous|−0.13|A|
|||Pulsed|−0.52|A|
|PD|Maximum Power Dissipation(1)<br>DerateAbove25°C||0.36|W|
||||2.9|mW/ °C|
|TJ,TSTG|G<br>Operatingand Storage Junction Temperature Range||−55 to +150|°C|
|TL|Maximum Lead Temperature for Soldering<br>Purposes,1/16” fromCasefor 10 Seconds||300|°C|



## **Thermal Characteristics** 

R θ JA Thermal Resistance, Junction-to-Ambient ~~[(1)]~~ 350 ° C/W 

## **Note:** 

1. R θ JA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. R θ JA is guaranteed by design, while R θ JA is determined by the user's board design. 

   - a) 350°C/W when mounted on a minimum pad 

Scale 1: 1 on letter-size paper. 

## **Package Marking and Ordering Information** 

|**Device Marking**|**Device**|**Reel Size**|**Tape width**|**Quantity**|
|---|---|---|---|---|
|SP|BSS84|7’’|8mm|3000|



© 2002 Fairchild Semiconductor Corporation BSS84  •  Rev. 1.1.0 

www.fairchildsemi.com 

## **Electrical Characteristics**[(2)] 

|**Symbol**|**Parameter**|**Conditions**|**Min.**|**Typ.**|**Max.**|**Unit**|
|---|---|---|---|---|---|---|
|**Off Characteristics**|||||||
|BVDSS|Drain–Source Breakdown Voltage|VGS=0V,ID= –250 μA|–50|||V|
|ΔBV<br>DSS<br>ΔTJ|Breakdown Voltage Temperature<br>Coefficient|ID= –250μA,<br>Referenced to 25℃||–48||mV /℃|
|IDSS|Zero Gate Voltage Drain Current|VDS= –50 V,VGS= 0 V|||–15|μA|
|||VDS= –50 V, VGS= 0 V,<br>TJ= 125°C|||–60|μA|
|IGSS|Gate–BodyLeakage.|VGS=±20V,VDS=0V|||±10|nA|
|BVDSS|Drain–Source Breakdown Voltage|VGS=0V,<br>ID= –250 μA|–50|||V|
|**On Characteristics**(2)|||||||
|VGS(th)|GateThresholdVoltage|VDS= VGS,ID= –1 mA|–0.8|–1.7|–2|V|
|GS(th)<br>V<br>GS(TH)<br>TJ|Gate Threshold Voltage<br>Temperature Coefficient|ID= –1 mA,<br>Referenced to 25℃||3||mV /℃|
|RDS(on)|Static Drain–Source<br>On–Resistance|VGS= –5 V,ID= –0.10 A||1.2|10.0|Ω|
|||VGS= –5 V, ID= –0.10 A,<br>TJ =125°C||1.9|17.0|Ω|
|ID(on)|On–State Drain Current|VGS = –5 V, VDS = –10 V|–0.6|||A|
|D(on)<br>gFS|Forward Transconductance|VDS = –25 V, ID = –0.10 A|0.05|0.60||S|
|**Dynamic Characteristics**|||||||
|CISS|Input Capacitance|VDS= –25 V,<br>VGS= 0 V,<br>f=1.0 MHz||73||pF|
|COSS|Output Capacitance|||10||pF|
|CRSS|Reverse Transfer Capacitance|||5||pF|
|RG|Gate Resistance|VGS= –15 mV,f = 1.0 MHz||9||Ω|
|**Switching Characteristics(2)**|||||||
|td(on)|Turn–On Delay|VDD= –30 V, ID= – 0.27 A,<br>VGS= –10 V, RGEN= 6||2.5|5.0|ns|
|d(on)<br>tr|Turn–On RiseTime|||6.3|13.0|ns|
|td(off)|Turn–Off Delay|||10|20|ns|
|d(off)<br>tf|Turn–Off Fall Time|||4.8|9.6|ns|
|Qg|Total Gate Charge|VDS= –25 V, ID= –0.10 A,<br>VGS= –5 V||0.9|1.3|nC|
|g<br>Qgs|Gate–Source Charge|||0.2||nC|
|gs<br>Qgd|Gate–DrainCharge|||0.3||nC|
|gd<br>**Drain-Source Diode Characteristics and Maximum Ratings **|||||||
|IS|Maximum Continuous Drain-Source Diode Forward Current||||-0.13|A|
|VSD|Drain-Source Diode Forward<br>Voltage|VGS= 0 V, IS= - 0.26 A(2)||-0.8|-1.2|V|
|tRR|Diode Reverse-RecoveryTime|IF= -0.1 A,<br>diF/ dt= 100 A / µs(2)||10||ns|
|QRR|Diode Reverse-RecoveryCharge|||3||nC|



## **Note:** 

2. Pulse Test: Pulse Width ≤ 300 μ s, Duty Cycle ≤ 2.0%. 

© 2002 Fairchild Semiconductor Corporation BSS84  •  Rev. 1.1.0 

www.fairchildsemi.com 

2 

## **Typical Characteristics** 

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1 2<br>VGS = -5V -4.5V -3.5V<br>0.8 1.8<br>VGS=-3.0V<br>1.6<br>0.6<br>-3.0V<br>1.4<br>0.4  -3.5V<br>1.2  -4.0V<br>0.2 -2.5V  -4.5V  -5.0V<br>1<br>0 f= 0.8 ps<br>0 1 2 3 4 5 0 0.2 0.4 0.6 0.8 1<br>-VDS, DRAIN TO SOURCE VOLTAGE (V) -ID, DRAIN CURRENT (A)<br>Figure 1. On-Region Characteristics  Figure 2. On-Resistance Variation with Drain<br>Current and Gate Voltage<br>1.8 5<br>1.6 IVD = -0.10AGS = -5V ID = -0.05A<br>1.4 4<br>1.2<br>3<br>1 TA = 125 [o] C<br>0.8<br>2<br>0.6 TA = 25 [o] C<br>0.4 Baie 1 wee<br>-50 -25 0 25 50 75 100 125 150<br>2 2.5 3 3.5 4 4.5 5<br>TJ, JUNCTION TEMPERATURE ( [o] C) -VGS, GATE TO SOURCE VOLTAGE (V)<br>Figure 3. On-Resistance Variation with  Figure 4. On-Resistance Variation with Gate-to-<br>Temperature  Source Voltage<br>1 1<br>VDS = -5V TA = -55 [o] C 25 [o] C VGS = 0V<br>0.8<br>0.1<br>125 [o] C TA = 125 [o] C<br>0.6<br>25 [o] C<br>0.01<br>0.4 -55 [o] C<br>0.001<br>0.2<br>0 Si 0.0001<br>1 1.5 2 2.5 3 3.5 4 0.0 0.2 0.4 0.6 0.8 1.0 1.2<br>-VGS, GATE TO SOURCE VOLTAGE (V) -VSD,  BODY DIODE FORWARD VOLTAGE (V)<br>Figure 5. Transfer Characteristics  Figure 6. Body Diode Forward Voltage Variation with<br>Source Current and Temperature<br>, NORMALIZED<br>, DRAIN CURRENT (A)-ID RDS(ON)<br>DRAIN-SOURCE ON-RESISTANCE<br>, NORMALIZED<br>DS(ON) , ON-RESISTANCE (OHM)<br>R DS(ON)<br>R<br> DRAIN-SOURCE ON-RESISTANCE<br>, DRAIN CURRENT (A)-ID<br>, REVERSE DRAIN CURRENT (A)-IS<br>**----- End of picture text -----**<br>


© 2002 Fairchild Semiconductor Corporation BSS84  •  Rev. 1.1.0 

www.fairchildsemi.com 

3 

## **Typical Characteristics** (Continued) 

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5 100<br>ID = -0.10A VDS = -8V -25V f = 1 MHzVGS = 0 V<br>4 80<br>-30V CISS<br>3 60<br>2 40<br>1 20<br>COSS<br>0 0 CRSS<br>0 0.2 0.4 0.6 0.8 1 0 10 20 30 40 50<br>Qg, GATE CHARGE (nC) -VDS, DRAIN TO SOURCE VOLTAGE (V)<br>CAPACITANCE (pF)<br>, GATE-SOURCE VOLTAGE (V)<br>GS<br>-V<br>**----- End of picture text -----**<br>


**Figure 7. Gate Charge Characteristics** 

**Figure 9. Maximum Safe Operating Area** 

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Figure 8. Capacitance Characteristics<br>5<br>SINGLE PULSE<br>R θ JA = 350캜 /W<br>4 T A  = 25캜<br>L<br>3 r<br>2<br>1<br>0<br>0.01 0.1 1 10 100<br>t1, TIME (sec)<br>Figure 10. Single-Pulse Maximum Power<br>Dissipation<br>P(pk), PEAK TRANSIENT POWER (W)<br>**----- End of picture text -----**<br>


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1<br>D = 0.5<br>R θ JA(t) = r(t)  *  R θ JA<br>0.2 R θ JA = 350 [o] C/W<br>0.1 0.1<br>0.05 P(pk)<br>0.02 t 1<br>0.01 0.01 t2<br>TJ - TA = P * R θ JA(t)<br>Duty Cycle, D = t 1  / t 2<br>SINGLE PULSE<br>0.001<br>0.0001 0.001 0.01 0.1 1 10 100 1000<br>t1, TIME (sec)<br>Figure 11. Transient Thermal Response Curve<br>Thermal characterization performed using the conditions described on page 1.<br>Transient thermal response will change depending on the circuit board design.<br>THERMAL RESISTANCE<br>r(t), NORMALIZED EFFECTIVE TRANSIENT<br>**----- End of picture text -----**<br>


© 2002 Fairchild Semiconductor Corporation BSS84  •  Rev. 1.1.0 

www.fairchildsemi.com 

4 

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Physical Dimension<br>SOT-23 3L<br>**----- End of picture text -----**<br>


## **Figure 12. 3-LEAD, SOT23, JEDEC TO-236, LOW PROFILE** 

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_Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/._ 

_For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area: http://www.fairchildsemi.com/packaging/tr/SOT23-3L_tr.pdf._ 

© 2002 Fairchild Semiconductor Corporation BSS84  •  Rev. 1.1.0 

www.fairchildsemi.com 

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|**Definition of Terms**|||
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|**Datasheet Identification**|**Product Status**|**Definition**|
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Rev. I64 

© 2002 Fairchild Semiconductor Corporation BSS84  •  Rev. 1.1.0 

www.fairchildsemi.com 

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