BSP250,115

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## **DISCRETE SEMICONDUCTORS** 

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DATA SHEET<br>**----- End of picture text -----**<br>


## **BSP250** P-channel enhancement mode vertical D-MOS transistor 

Supersedes data of November 1994 File under Discrete Semiconductors, SC13b 

1997 Jun 20 

**Philips Semiconductors** 

**BSP250** 

## **P-channel enhancement mode vertical D-MOS transistor** 

## **FEATURES** 

- High-speed switching 

- No secondary breakdown 

- Very low on-resistance. 

## **APPLICATIONS** 

## **PINNING - SOT223** 

|**PIN**|**SYMBOL**|**DESCRIPTION**|
|---|---|---|
|1|g|gate|
|2|d|drain|
|3|s|source|
|4|d|drain|



- Low-loss motor and actuator drivers 

- Power switching. 

## **DESCRIPTION** 

P-channel enhancement mode vertical D-MOS transistor in a SOT223 plastic SMD package. 

## **CAUTION** 

The device is supplied in an antistatic package. The gate-source input must be protected against static discharge during transport or handling. 

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handbook, halfpage 4 d<br>g<br>1 2 3 s<br>Top view MAM121<br>**----- End of picture text -----**<br>


Fig.1  Simplified outline and symbol. 

## **QUICK REFERENCE DATA** 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**MIN.**|**MAX.**|**UNIT**|
|---|---|---|---|---|---|
|VDS|drain-source voltage (DC)||−|−30|V|
|VSD|source-drain diode forward voltage|IS =−1.25 A|−|−1.6|V|
|VGSO|gate-source voltage (DC)|open drain|−|±20|V|
|VGSth|gate-source threshold voltage|ID =−1 mA; VDS = VGS|−1|−2.8|V|
|ID|drain current (DC)||−|−3|A|
|RDSon|drain-source on-state resistance|ID =−1 A; VGS =−10 V|−|0.25|Ω|
|Ptot|total power dissipation|Ts= 100°C|−|5|W|



1997 Jun 20 

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Philips Semiconductors 

## P-channel enhancement mode vertical D-MOS transistor 

## BSP250 

## **LIMITING VALUES** 

In accordance with the Absolute Maximum Rating System (IEC 134). 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**MIN.**|**MAX.**|**UNIT**|
|---|---|---|---|---|---|
|VDS|drain-source voltage (DC)||−|−30|V|
|VGSO|gate-source voltage (DC)|open drain|−|±20|V|
|ID|drain current (DC)|Ts≤100°C|−|−3|A|
|IDM|peak drain current|note 1|−|−12|A|
|Ptot|total power dissipation|Ts= 100°C|−|5|W|
|||Tamb= 25°C; note 2|−|1.65|W|
|Tstg|storage temperature||−65|+150|°C|
|Tj|operating junction temperature||−|150|°C|
|**Source-drain diode**||||||
|IS|source current (DC)|Ts≤100°C|−|−1.5|A|
|ISM|peak pulsed source current|note 1|−|−6|A|



## **Notes** 

1. Pulse width and duty cycle limited by maximum junction temperature. 

2. Device mounted on an epoxy printed-circuit board, 40 × 40 × 1.5 mm; mounting pad for drain lead minimum 6 cm[2] . 

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MLB885 MLB835<br>2.0 −10 [2]<br>handbook, halfpage handbook, halfpage<br>Ptot<br>ID<br>(W)<br>(A)<br>1.6<br>−10 (1) tp =<br>10 µs<br>1.2<br>−1<br>1 ms<br>0.8 P δ [=] tp DC<br>T<br>−10 [−][1]<br>0.4<br>tp t<br>T<br>0 −10− [−] 10 [2] [−][1] −1 −10 −10 [2]<br>0 50 100 150Tamb (°C)200 VDS (V)<br>δ = 0.01.<br>Soldering point temperature Ts = 100 °C.<br>(1) RDSon limitation.<br>Fig.2  Power derating curve. Fig.3  SOAR.<br>**----- End of picture text -----**<br>


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Philips Semiconductors 

## P-channel enhancement mode vertical D-MOS transistor 

## BSP250 

## **THERMAL CHARACTERISTICS** 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**VALUE**|**UNIT**|
|---|---|---|---|---|
|Rth j-a|thermal resistance from junction to ambient|note 1|75|K/W|
|Rth j-s|thermal resistance from junction to soldering point||10|K/W|



## **Note** 

1. Device mounted on an epoxy printed-circuit board, 40 × 40 × 1.5 mm; mounting pad for drain lead minimum 6 cm[2] . 

## **CHARACTERISTICS** 

Tj = 25 ° 

|Tj= 25°C unl|ess otherwise specifed.||||||
|---|---|---|---|---|---|---|
|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**MIN.**|**TYP.**|**MAX.**|**UNIT**|
|V(BR)DSS|drain-source breakdown voltage|VGS = 0; ID =−10µA|−30|−|−|V|
|VGSth|gate-source threshold voltage|VGS = VDS; ID=−1 mA|−1|−|−2.8|V|
|IDSS|drain-source leakage current|VGS = 0; VDS =−24 V|−|−|−100|nA|
|IGSS|gate leakage current|VGS =±20 V; VDS = 0|−|−|±100|nA|
|IDon|on-state drain current|VGS=−10 V; VDS =−1 V|−3|−|−|A|
|||VGS=−4.5 V; VDS =−5 V|−1|−|−|A|
|RDSon|drain-source on-state resistance|VGS=−4.5 V; ID =−0.5 A|−|0.33|0.4|Ω|
|||VGS=−10 V; ID =−1 A|−|0.22|0.25|Ω|
|yfs|forward transfer admittance|VDS =−20 V; ID=−1 A|1|2|−|S|
|Ciss|input capacitance|VGS= 0; VDS =−20 V; f = 1 MHz|−|250|−|pF|
|Coss|output capacitance|VGS= 0; VDS =−20 V; f = 1 MHz|−|140|−|pF|
|Crss|reverse transfer capacitance|VGS= 0; VDS =−20 V; f = 1 MHz|−|50|−|pF|
|QG|total gate charge|VGS=−10 V; VDS =−15 V;<br>ID=−2.3 A|−|10|25|nC|
|QGS|gate-source charge|VGS=−10 V; VDS =−15 V;<br>ID=−2.3 A|−|1|−|nC|
|QGD|gate-drain charge|VGS=−10 V; VDS =−15 V;<br>ID=−2.3 A|−|3|−|nC|
|**Switching times**|||||||
|ton|turn-on time|VGS= 0 to−10 V; VDD =−20 V;<br>ID=−1 A; RL= 20Ω|−|20|80|ns|
|toff|turn-off time|VGS=−10 to 0 V; VDD =−20 V;<br>ID=−1 A; RL= 20Ω|−|50|140|ns|
|**Source-drain diode**|||||||
|VSD|source-drain diode forward voltage|VGD= 0; IS =−1.25 A|−|−|−1.6|V|
|trr|reverse recovery time|IS =−1.25 A; di/dt = 100 A/µs|−|150|200|ns|



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## P-channel enhancement mode vertical D-MOS transistor 

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MBE144<br>600<br>handbook, halfpage<br>C<br>(pF)<br>400<br>Ciss<br>200<br>Coss<br>Crss<br>0<br>0 −10 −20 −30<br>VDS (V)<br>VGS = 0.<br>Tj = 25 °C.<br>**----- End of picture text -----**<br>


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Fig.4 Capacitance as a function of drain source<br>voltage; typical values.<br>**----- End of picture text -----**<br>


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MBE150<br>−16<br>handbook, halfpage<br>ID<br>(A)<br>−12<br>−8<br>−4<br>0<br>0 −2 −4 −6 −8<br>VGS (V)<br>VDS = −10 V.<br>Tj = 25 °C.<br>**----- End of picture text -----**<br>


Fig.6  Transfer characteristic, typical values. 

## BSP250 

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MBE149<br>−12<br>handbook, halfpageID VGS =<br>(A) −10 V −7.5 V<br>−10<br>−6 V<br>−8<br>−6 −5 V<br>−4.5 V<br>−4<br>−4 V<br>−2 −3.5 V<br>−3 V<br>−2.5 V<br>0<br>0 −2 −4 −6 −8 −10 −12<br>V      (V)DS<br>Tj = 25 °C.<br>Fig.5  Output characteristics; typical values.<br>MBE145<br>−10<br>handbook, halfpage<br>VGS<br>(V)<br>−8<br>−6<br>−4<br>−2<br>0<br>0 −2 −4 −6 −8 −10<br>Qg (nC)<br>VDD = −15 V.<br>ID = −3 A.<br>**----- End of picture text -----**<br>


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Fig.7 Gate-source voltage as a function of total<br>gate charge.<br>**----- End of picture text -----**<br>


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## P-channel enhancement mode vertical D-MOS transistor 

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−6 MBE148<br>handbook, halfpage<br>IS<br>(A)<br>−4<br>(1) (2) (3)<br>−2<br>0<br>0 −0.5 −1 −1.5 −2 −2.5<br>VSD (V)<br>VGD = 0.<br>(1) Tj = 150 °C.<br>(2) Tj = 25 °C.<br>**----- End of picture text -----**<br>


## BSP250 

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MDA218<br>10 [4]<br>handbook, halfpage<br>RDSon<br>(mΩ)<br>(1)(2)(3) (4) (5)<br>10 [3]<br>10 [2]<br>0 −2 −4 −6 −8 −10<br>VGS (V)<br>−VDS ≥−ID × RDSon; Tj = 25 °C.<br>(1) ID = −0.1 A. (4) ID = −3 A.<br>(2) ID = −0.5 A. (5) ID = −6 A.<br>(3) ID = −1 A.<br>**----- End of picture text -----**<br>


- (3) Tj = −55 °C. 

Fig.8 Source current as a function of source-drain diode forward voltage. 

**==> picture [242 x 244] intentionally omitted <==**

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MBE138<br>1.2<br>handbook, halfpage<br>k<br>1.1<br>1.0<br>0.9<br>0.8<br>0.7<br>0.6<br>−50 0 50 100 150<br>Tj (°C)<br>k = --------------------------------------VGSthVGSthat 25at T°jC<br>Typical VGSth at ID = −1 mA; VDS =VGS = VGSth.<br>**----- End of picture text -----**<br>


Fig.10 Temperature coefficient of gate-source threshold voltage. 

Fig.9 Drain-source on-state resistance as a function of gate-source voltage; typical values. 

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MBE146<br>1.8<br>handbook, halfpage<br>k<br>1.6<br>(1)<br>(2)<br>1.4<br>1.2<br>1.0<br>0.8<br>0.6<br>−50 0 50 100 150<br>Tj (°C)<br>k = R-----------------------------------------DSonRDSonat 25at T°j C<br>Typical RDSon at:<br>(1) ID = −1 A; VGS = −10 V.<br>(2) ID = −0.5 A; VGS = −4.5 V.<br>**----- End of picture text -----**<br>


Fig.11 Temperature coefficient of drain-source on-resistance. 

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## P-channel enhancement mode vertical D-MOS transistor 

## BSP250 

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MBE147<br>10<br>handbook, full pagewidth δ =<br>0.75<br>Rth j-s 0.5<br>(K/W)<br>0.33<br>0.2<br>0.1<br>1<br>0.05<br>0.02 P δ [=] tp<br>0.01 T<br>0<br>tp t<br>T<br>10 [−][1]<br>10 [−][6] 10 [−][5] 10 [−][4] 10 [−][3] 10 [−][2] 10 [−][1] 1<br>tp (s)<br>**----- End of picture text -----**<br>


Fig.12  Transient thermal resistance from junction to soldering point as a function of pulse time; typical values. 

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Philips Semiconductors 

P-channel enhancement mode vertical D-MOS transistor 

## BSP250 

## **PACKAGE OUTLINE** 

**Plastic surface mounted package; collector pad for good heat transfer; 4 leads SOT223** 

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D B E A X<br>c<br>y<br>HE v M A<br>b1<br>4<br>Q<br>A<br>A1<br>1 2 3 Lp<br>e1 bp w M B detail X<br>e<br>0 2 4 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>UNIT A A1 bp b1 c D E e e1 HE Lp Q v w y<br>1.8 0.10 0.80 3.1 0.32 6.7 3.7 7.3 1.1 0.95<br>mm 4.6 2.3 0.2 0.1 0.1<br>1.5 0.01 0.60 2.9 0.22 6.3 3.3 6.7 0.7 0.85<br>OUTLINE  REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION  IEC  JEDEC  EIAJ PROJECTION<br>96-11-11<br> SOT223<br>97-02-28<br>**----- End of picture text -----**<br>


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P-channel enhancement mode vertical D-MOS transistor 

BSP250 

## **DEFINITIONS** 

|**DEFINITIONS**||
|---|---|
|**Data Sheet Status**||
|Objective specifcation|This data sheet contains target or goal specifcations for product development.|
|Preliminary specifcation|This data sheet contains preliminary data; supplementary data may be published later.|
|Product specifcation|This data sheet contains fnal product specifcations.|
|**Limiting values**||



Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. 

## **Application information** 

## **LIFE SUPPORT APPLICATIONS** 

These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 

1997 Jun 20 

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Philips Semiconductors 

P-channel enhancement mode vertical D-MOS transistor 

BSP250 

## **NOTES** 

1997 Jun 20 

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Philips Semiconductors 

P-channel enhancement mode vertical D-MOS transistor 

BSP250 

## **NOTES** 

1997 Jun 20 

11 

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© Philips Electronics N.V. 1997 

**Internet:** http://www.semiconductors.philips.com 

SCA54 

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Printed in The Netherlands 

**==> picture [204 x 36] intentionally omitted <==**

Date of release: 1997 Jun 20 

137107/00/02/pp12 

Document order number: 9397 750 02331