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BSP130,115
Power MOSFET, N Channel, 300 V, 250 mA, 6 ohm, SOT-223, Surface Mount
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- Manufacturer: NEXPERIA
- Product type: Single MOSFETs
- No. of Pins: 3Pins
- Channel Type: N Channel
- Power Dissipation: 1.5W
- Transistor Mounting: Surface Mount
- Transistor Polarity: N Channel
- Power Dissipation Pd: 1.5W
- Rds(on) Test Voltage: 10V
- On Resistance Rds(on): 6ohm
- Transistor Case Style: SOT-223
- Drain Source Voltage Vds: 300V
- Operating Temperature Max: 150°C
- Continuous Drain Current Id: 250mA
- Drain Source On State Resistance: 6ohm
- Gate Source Threshold Voltage Max: 2V
| Delivery and price | |
|---|---|
| Units per pack | 5000 |
| Price | 0.161 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
## **DISCRETE SEMICONDUCTORS** **==> picture [274 x 256] intentionally omitted <==** **----- Start of picture text -----**<br> DATA SHEET<br>age<br>M3D087<br>**----- End of picture text -----**<br> **BSP130** N-channel enhancement mode vertical D-MOS transistor Supersedes data of 1997 Jun 23 2001 Dec 11 **Philips Semiconductors** **BSP130** ## **N-channel enhancement mode vertical D-MOS transistor** ## **FEATURES** - Direct interface to C-MOS, TTL, etc. - High-speed switching - No secondary breakdown. ## **APPLICATIONS** ## **PINNING - SOT223** |**PIN**|**DESCRIPTION**| |---|---| |1|gate| |2|drain| |3|source| |4|drain| - Line current interruptor in telephone sets - Relay, high-speed and line transformer drivers. ## **DESCRIPTION** N-channel enhancement mode vertical D-MOS transistor in a SOT223 package. **==> picture [242 x 112] intentionally omitted <==** **----- Start of picture text -----**<br> handbook, halfpage 4 d<br>g<br>1 2 3 s<br>Top view MAM054<br>Marking code BSP130.<br>**----- End of picture text -----**<br> Fig.1 Simplified outline and symbol. ## **QUICK REFERENCE DATA** |**SYMBOL**|**PARAMETER**|**CONDITIONS**|**MIN.**|**MAX.**|**UNIT**| |---|---|---|---|---|---| |VDS|drain-source voltage (DC)||−|300|V| |ID|drain current (DC)||−|350|mA| |Ptot|total power dissipation|Tamb≤25°C|−|1.5|W| |VGSO|gate-source voltage|open drain|−|±20|V| |RDSon|drain-source on-state<br>resistance|ID= 250 mA; VGS= 10 V|−|6|Ω| |VGSoff|gate-source cut-off voltage|ID= 1 mA; VDS= VGS|0.8|2|V| ## **LIMITING VALUES** In accordance with the Absolute Maximum Rating System (IEC 60134). |**SYMBOL**|**PARAMETER**|**CONDITIONS**|**MIN.**|**MAX.**|**UNIT**| |---|---|---|---|---|---| |VDS|drain-source voltage (DC)||−|300|V| |VGSO|gate-source voltage (DC)|open drain|−|±20|V| |ID|drain current (DC)||−|350|mA| |IDM|peak drain current||−|1.4|A| |Ptot|total power dissipation|Tamb≤25°C; note 1|−|1.5|W| |Tstg|storage temperature||−55|+150|°C| |Tj|junction temperature||−|150|°C| ## **Note** 1. Device mounted on an epoxy printed-circuit board, 40 x 40 x 1.5 mm, mounting pad for the drain tab minimum 6 cm[2] . 2001 Dec 11 2 Philips Semiconductors ## N-channel enhancement mode vertical D-MOS transistor BSP130 ## **THERMAL CHARACTERISTICS** |**SYMBOL**|**PARAMETER**|**VALUE**|**UNIT**| |---|---|---|---| |Rth j-a|thermal resistance from junction to ambient; note 1|83.3|K/W| ## **Note** 1. Device mounted on an epoxy printed-circuit board, 40 x 40 x 1.5 mm, mounting pad for the drain tab minimum 6 cm[2] . ## **STATIC CHARACTERISTICS** T = 25 ° j |**SYMBOL**|**PARAMETER**|**CONDITIONS**|**MIN.**|**TYP.**|**MAX.**|**UNIT**| |---|---|---|---|---|---|---| |V(BR)DSS|drain-source breakdown voltage|ID= 10µA; VGS= 0|300|−|−|V| |IGSS|gate-source leakage current|VGS=±20 V; VDS= 0|−|−|±100|nA| |VGSth|gate-source threshold voltage|ID= 1 mA; VDS= VGS|0.8|−|2|V| |RDSon|drain-source on-state resistance|ID= 20 mA; VGS= 2.4 V|−|4.8|10|Ω| |||ID= 250 mA; VGS= 10 V|−|3.7|6|Ω| |IDSS|drain-source leakage current|VDS= 240 V; VGS= 0|−|−|100|nA| |Yfs|transfer admittance|ID= 250 mA; VDS= 25 V|200|690|−|mS| |Ciss|input capacitance|VDS= 25 V; VGS= 0; f = 1 MHz|−|100|120|pF| |Coss|output capacitance|VDS= 25 V; VGS= 0; f = 1 MHz|−|21|30|pF| |Crss|feedback capacitance|VDS= 25 V; VGS= 0; f = 1 MHz|−|10|15|pF| |**Switching times (see Figs**2**and**3**)**||||||| |ton|turn-on time|ID= 250 mA; VDD= 50 V;<br>VGS= 0 to 10 V|−|6|10|ns| |toff|turn-off time|ID= 250 mA; VDD= 50 V;<br>VGS= 10 to 0 V|−|46|60|ns| 2001 Dec 11 3 Philips Semiconductors ## N-channel enhancement mode vertical D-MOS transistor **==> picture [241 x 119] intentionally omitted <==** **----- Start of picture text -----**<br> handbook, halfpage VDD = 50 V<br>10 V<br>ID<br>0 V<br>50 Ω<br>MBB691<br>**----- End of picture text -----**<br> Fig.2 Switching times test circuit. **==> picture [242 x 187] intentionally omitted <==** **----- Start of picture text -----**<br> MRC218<br>2<br>handbook, halfpage<br>Ptot<br>(W)<br>1.5<br>1<br>0.5<br>0<br>0 50 100 150 Tj (°C) 200<br>**----- End of picture text -----**<br> ## BSP130 **==> picture [241 x 130] intentionally omitted <==** **----- Start of picture text -----**<br> handbook, halfpage 90 %<br>INPUT<br>10 %<br>90 %<br>OUTPUT<br>10 %<br>ton toff<br>MBB692<br>**----- End of picture text -----**<br> Fig.3 Input and output waveforms. **==> picture [242 x 186] intentionally omitted <==** **----- Start of picture text -----**<br> MLD765<br>250<br>handbook, halfpage<br>C<br>(pF)<br>200<br>150<br>100 Ciss<br>50<br>Coss<br>Crss<br>0<br>0 10 20 30<br>VDS (V)<br>**----- End of picture text -----**<br> VGS = 0; f = 1 MHz; Tj = 25 °C. Fig.4 Power derating curve. Fig.5 Capacitance as a function of drain-source voltage; typical values. 2001 Dec 11 4 Philips Semiconductors ## N-channel enhancement mode vertical D-MOS transistor **==> picture [242 x 238] intentionally omitted <==** **----- Start of picture text -----**<br> MLD766<br>1.2<br>handbook, halfpage VGS = 10 V 5 V<br>ID 4 V<br>(A) 3.5 V<br>3 V<br>0.8<br>0.4<br>2.5 V<br>2 V<br>0<br>0 4 8 12<br>VDS (V)<br>Tj = 25 °C.<br>**----- End of picture text -----**<br> **==> picture [213 x 23] intentionally omitted <==** **----- Start of picture text -----**<br> Fig.6 Typical output characteristics.<br>**----- End of picture text -----**<br> **==> picture [241 x 229] intentionally omitted <==** **----- Start of picture text -----**<br> MLD768<br>30<br>handbook, halfpage VGS = 2 V<br>2.5 V<br>RDSon 3 V 3.5 V<br>(Ω)<br>20<br>10<br>4 V<br>5 V<br>10 V<br>0<br>10 [−][1] 1 10<br>ID (A)<br>Tj = 25 °C.<br>**----- End of picture text -----**<br> Fig.8 Drain-source on-state resistance as a function of drain current; typical values. ## BSP130 **==> picture [242 x 189] intentionally omitted <==** **----- Start of picture text -----**<br> MLD767<br>1.2<br>handbook, halfpage<br>ID<br>(A)<br>0.8<br>0.4<br>0<br>0 2 4 6 8 10<br>VGS (V)<br>**----- End of picture text -----**<br> **==> picture [83 x 8] intentionally omitted <==** **----- Start of picture text -----**<br> VDS = 10 V; Tj = 25 °C.<br>**----- End of picture text -----**<br> Fig.7 Typical transfer characteristics. **==> picture [242 x 228] intentionally omitted <==** **----- Start of picture text -----**<br> MLD769<br>20<br>handbook, halfpage<br>RDSon<br>(Ω)<br>15<br>10<br>5<br>0<br>0 2 4 6 8 10<br>VGS (V)<br>VDS = 100 mV; Tj = 25 °C.<br>**----- End of picture text -----**<br> Fig.9 Drain-source on-state resistance as a function of gate-source voltage; typical values. 2001 Dec 11 5 Philips Semiconductors ## N-channel enhancement mode vertical D-MOS transistor ## BSP130 **==> picture [496 x 227] intentionally omitted <==** **----- Start of picture text -----**<br> MRC221<br>10 [2]<br>handbook, full pagewidthδ =<br>0.75<br>Rth j-a 0.5<br>(K/W)<br>0.2<br>10<br>0.1<br>0.05<br>0.02<br>1 0.01 P δ = tp<br>T<br>0<br>tp t<br>T<br>10 [−][1]<br>10 [−][5] 10 [−][4] 10 [−][3] 10 [−][2] 10 [−][1] 1 10 10 [2] 10 [3]<br>tp (s)<br>**----- End of picture text -----**<br> Fig.10 Transient thermal resistance from junction to ambient as a function of pulse time. **==> picture [242 x 298] intentionally omitted <==** **----- Start of picture text -----**<br> MLD773<br>10<br>handbook, halfpage<br>ID<br>(A)<br>1 (1) tp =<br>10 µs<br>100 µs<br>1 ms<br>10 [−][1] DC 10 ms<br>100 ms<br>P t p<br>δ [=]<br>T 1s<br>10 [−][2]<br>t p t<br>T<br>10 [−][3]<br>1 10 10 [2] 10 [3]<br>VDS (V)<br>δ = 0.01; Tamb = 25 °C.<br>(1) RDSon limitation.<br>Fig.11 SOAR curve.<br>**----- End of picture text -----**<br> 2001 Dec 11 6 Philips Semiconductors ## N-channel enhancement mode vertical D-MOS transistor **==> picture [242 x 291] intentionally omitted <==** **----- Start of picture text -----**<br> MLD771<br>2<br>handbook, halfpage<br>k<br>(1)<br>1.5<br>(2)<br>1<br>0.5<br>0<br>−50 0 50 100 150<br>Tj (°C)<br>k = -----------------------------------------RRDS(on)at 25 at T°jC<br>DS(on)<br>Typical RDSon;<br>(1) ID = 250 mA; VGS = 10 V.<br>(2) ID = 20 mA; VGS = 2.4 V.<br>**----- End of picture text -----**<br> Fig.12 Temperature coefficient of drain-source on-state resistance; typical values. ## BSP130 **==> picture [242 x 290] intentionally omitted <==** **----- Start of picture text -----**<br> MLD772<br>1.25<br>handbook, halfpage<br>k<br>1<br>0.75<br>0.5<br>0.25<br>0<br>-50 0 50 100 150<br>Tj (°C)<br>k = -------------------------------------------.VGSVGS(th()th [at 25] ) [at T][°] j [C]<br>Typical VGSth at 1 mA.<br>**----- End of picture text -----**<br> **==> picture [214 x 30] intentionally omitted <==** **----- Start of picture text -----**<br> Fig.13 Temperature coefficient of gate-source<br>threshold voltage; typical values.<br>**----- End of picture text -----**<br> 2001 Dec 11 7 Philips Semiconductors BSP130 N-channel enhancement mode vertical D-MOS transistor ## **PACKAGE OUTLINE** **Plastic surface mounted package; collector pad for good heat transfer; 4 leads** **==> picture [36 x 8] intentionally omitted <==** **----- Start of picture text -----**<br> SOT223<br>**----- End of picture text -----**<br> **==> picture [495 x 590] intentionally omitted <==** **----- Start of picture text -----**<br> D B E A X<br>c<br>y<br>HE v M A<br>b1<br>4<br>Q<br>A<br>A1<br>1 2 3 Lp<br>e1 bp w M B detail X<br>e<br>0 2 4 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>UNIT A A1 bp b1 c D E e e1 HE Lp Q v w y<br>1.8 0.10 0.80 3.1 0.32 6.7 3.7 7.3 1.1 0.95<br>mm 4.6 2.3 0.2 0.1 0.1<br>1.5 0.01 0.60 2.9 0.22 6.3 3.3 6.7 0.7 0.85<br>OUTLINE REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION IEC JEDEC EIAJ PROJECTION<br>97-02-28<br> SOT223 SC-73<br>99-09-13<br>**----- End of picture text -----**<br> 2001 Dec 11 8 Philips Semiconductors BSP130 ## N-channel enhancement mode vertical D-MOS transistor ## **DATA SHEET STATUS** |**DATA SHEET STATUS**||| |---|---|---| |**DATA SHEET STATUS**(1)|**PRODUCT**<br>**STATUS**(2)|**DEFINITIONS**| |Objective data|Development|This data sheet contains data from the objective specification for product<br>development. Philips Semiconductors reserves the right to change the<br>specifcation in any manner without notice.| |Preliminary data|Qualifcation|This data sheet contains data from the preliminary specification.<br>Supplementary data will be published at a later date. Philips<br>Semiconductors reserves the right to change the specifcation without<br>notice, in order to improve the design and supply the best possible<br>product.| |Product data|Production|This data sheet contains data from the product specification. Philips<br>Semiconductors reserves the right to make changes at any time in order<br>to improve the design, manufacturing and supply. Changes will be<br>communicated according to the Customer Product/Process Change<br>Notifcation (CPCN) procedure SNW-SQ-650A.| ## **Notes** 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. ## **DEFINITIONS** **Short-form specification** The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. **Limiting values definition** Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. **Application information** Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. ## **DISCLAIMERS** **Life support applications** These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. **Right to make changes** Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 2001 Dec 11 9 Philips Semiconductors N-channel enhancement mode vertical D-MOS transistor BSP130 ## **NOTES** 2001 Dec 11 10 Philips Semiconductors N-channel enhancement mode vertical D-MOS transistor BSP130 ## **NOTES** 2001 Dec 11 11 ## **Philips Semiconductors – a worldwide company** ## **Contact information** For additional information please visit **http://www.semiconductors.philips.com** . Fax: **+31 40 27 24825** For sales offices addresses send e-mail to: **sales.addresses@www.semiconductors.philips.com** . © Koninklijke Philips Electronics N.V. 2001 SCA73 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. **==> picture [214 x 95] intentionally omitted <==** Printed in The Netherlands 613510/03/pp12 Date of release: 2001 Dec 11 Document order number: 9397 750 09064
Updated at February 9, 2023
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