BSP122,115

Power MOSFET, N Channel, 200 V, 750 mA, 2.5 ohm, SOT-223, Surface Mount

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Manufacturer: NEXPERIA
Product type: Single MOSFETs
Transistor Polarity:N Channel; Continuous Drain Current Id:750mA; Drain Source Voltage Vds:200V; On Resistance Rds(on):1.7ohm; Rds(on) Test Voltage Vgs:10V; Threshold Voltage Vgs:
MSL: MSL 1 - Unlimited
SVHC: No SVHC (25-Jun-2025)
No. of Pins: 3Pins
Channel Type: N Channel
Qualification: -
Power Dissipation: 1.5W
Transistor Mounting: Surface Mount
Rds(on) Test Voltage: 10V
Transistor Case Style: SOT-223
Drain Source Voltage Vds: 200V
Operating Temperature Max: 150°C
Continuous Drain Current Id: 750mA
Drain Source On State Resistance: 2.5ohm
Gate Source Threshold Voltage Max: 2V

Delivery and price
Units per pack	3000
Price	0.211 €
Current stock	1000+
Lead time	30 days

Datasheet

## **DISCRETE SEMICONDUCTORS** 

## **DATA SHEET** 

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book, halfpage<br>M3D087<br>**----- End of picture text -----**<br>


**BSP122** N-channel enhancement mode vertical D-MOS transistor 

2001 May 18 Supersedes data of 1997 Jun 23 

**Philips Semiconductors** 

**BSP122** 

## **N-channel enhancement mode vertical D-MOS transistor** 

## **FEATURES** 

- Direct interface to C-MOS, TTL, etc. 

- High-speed switching 

- No secondary breakdown. 

## **DESCRIPTION** 

## **QUICK REFERENCE DATA** 

|**SYMBOL**|**PARAMETER**|**MAX.**|**UNIT**|
|---|---|---|---|
|VDS|drain-source voltage (DC)|200|V|
|ID|drain current (DC)|550|mA|
|RDSon|drain-source on-state resistance|2.5|Ω|
|VGSth|gate-source threshold voltage|2|V|



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N-channel enhancement mode<br>vertical D-MOS transistor in a<br>SOT223 package and intended for<br>use as a line current interruptor in handbook, halfpage 4 d<br>telephone sets and for applications in<br>relay, high-speed and line<br>transformer drivers.<br>g<br>PINNING - SOT223 1 2 3 s<br>PIN DESCRIPTION Top view MAM054<br>1 gate<br>2 drain<br>3 source Fig.1  Simplified outline (SOT223) and symbol.<br>4 drain<br>**----- End of picture text -----**<br>


## **LIMITING VALUES** 

In accordance with the Absolute Maximum System (IEC 60134). 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**MIN.**|**MAX.**|**UNIT**|
|---|---|---|---|---|---|
|VDS|drain-source voltage (DC)||−|200|V|
|VGSO|gate-source voltage (DC)|open drain|−|±20|V|
|ID|drain current (DC)||−|550|mA|
|IDM|peak drain current||−|3|A|
|Ptot|total power dissipation|Tamb≤25°C; note 1|−|1.5|W|
|Tstg|storage temperature||−55|+150|°C|
|Tj|junction temperature||−|150|°C|



## **Note** 

1. Transistor mounted on an epoxy printed circuit board, 40 x 40 x 1.5 mm, mounting pad for the drain tab minimum 6 cm[2] . 

## **THERMAL CHARACTERISTICS** 

|**SYMBOL**|**PARAMETER**|**VALUE**|**UNIT**|
|---|---|---|---|
|Rth j-a|thermal resistance from junction to ambient; note 1|83.3|K/W|



## **Note** 

1. Transistor mounted on an epoxy printed circuit board, 40 x 40 x 1.5 mm, mounting pad for the drain tab minimum 6 cm[2] . 

2001 May 18 

2 

Philips Semiconductors 

## N-channel enhancement mode vertical D-MOS transistor 

BSP122 

## **CHARACTERISTICS** 

T = 25 ° j 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**MIN.**|**TYP.**|**MAX.**|**UNIT**|
|---|---|---|---|---|---|---|
|V(BR)DSS|drain-source breakdown voltage|ID= 10µA; VGS= 0|200|−|−|V|
|IDSS|drain-source leakage current|VDS= 160 V; VGS= 0|−|−|1|µA|
|IGSS|gate-source leakage current|VGS=±20 V; VDS= 0|−|−|100|nA|
|VGSth|gate-source threshold voltage|ID= 1 mA; VGS= VDS|0.4|−|2|V|
|RDSon|drain-source on-resistance|ID= 750 mA; VGS= 10 V|−|1.7|2.5|Ω|
|||ID= 20 mA; VGS= 2.4 V|−|3|−|Ω|
|Yfs|transfer admittance|ID= 750 mA; VDS= 25 V|400|900|−|mS|
|Ciss|input capacitance|VDS= 25 V; VGS= 0; f = 1 MHz|−|100|−|pF|
|Coss|output capacitance|VDS= 25 V; VGS= 0; f = 1 MHz|−|20|−|pF|
|Crss|reverse transfer capacitance|VDS= 25 V; VGS= 0; f = 1 MHz|−|10|−|pF|
|**Switching times (see Figs**2**and**3**)**|||||||
|ton|turn-on time|ID= 750 mA; VDD= 50 V;<br>VGS= 0 to 10 V|−|10|20|ns|
|toff|turn-off time|ID= 750 mA; VDD= 50 V;<br>VGS= 0 to 10 V|−|45|60|ns|



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handbook, halfpage 90 %<br>handbook, halfpage VDD = 50 V<br>INPUT<br>10 %<br>90 %<br>10 V OUTPUT<br>ID<br>0 V 10 %<br>50 Ω<br>ton toff<br>MBB691 MBB692<br>VDD = 50 V.<br>Fig.2  Switching times test circuit. Fig.3  Input and output waveforms.<br>**----- End of picture text -----**<br>


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Philips Semiconductors 

N-channel enhancement mode vertical D-MOS transistor 

## BSP122 

## **PACKAGE OUTLINE** 

**Plastic surface mounted package; collector pad for good heat transfer; 4 leads** 

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SOT223<br>**----- End of picture text -----**<br>


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D B E A X<br>c<br>y<br>HE v M A<br>b1<br>4<br>Q<br>A<br>A1<br>1 2 3 Lp<br>e1 bp w M B detail X<br>e<br>0 2 4 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>UNIT A A1 bp b1 c D E e e1 HE Lp Q v w y<br>1.8 0.10 0.80 3.1 0.32 6.7 3.7 7.3 1.1 0.95<br>mm 4.6 2.3 0.2 0.1 0.1<br>1.5 0.01 0.60 2.9 0.22 6.3 3.3 6.7 0.7 0.85<br>OUTLINE  REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION  IEC  JEDEC  EIAJ PROJECTION<br>97-02-28<br> SOT223 SC-73<br>99-09-13<br>**----- End of picture text -----**<br>


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Philips Semiconductors 

BSP122 

## N-channel enhancement mode vertical D-MOS transistor 

## **DATA SHEET STATUS** 

|**DATA SHEET STATUS**|||
|---|---|---|
|**DATA SHEET STATUS**(1)|**PRODUCT**<br>**STATUS**(2)|**DEFINITIONS**|
|Objective data|Development|This data sheet contains data from the objective specification for product<br>development. Philips Semiconductors reserves the right to change the<br>specifcation in any manner without notice.|
|Preliminary data|Qualifcation|This data sheet contains data from the preliminary specification.<br>Supplementary data will be published at a later date. Philips<br>Semiconductors reserves the right to change the specifcation without<br>notice, in order to improve the design and supply the best possible<br>product.|
|Product data|Production|This data sheet contains data from the product specification. Philips<br>Semiconductors reserves the right to make changes at any time in order<br>to improve the design, manufacturing and supply. Changes will be<br>communicated according to the Customer Product/Process Change<br>Notifcation (CPCN) procedure SNW-SQ-650A.|



## **Notes** 

1. Please consult the most recently issued data sheet before initiating or completing a design. 

2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 

## **DEFINITIONS** 

**Short-form specification**  The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. 

**Limiting values definition**  Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. 

**Application information**  Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 

## **DISCLAIMERS** 

**Life support applications**  These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. 

**Right to make changes**  Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 

2001 May 18 

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Philips Semiconductors 

N-channel enhancement mode vertical D-MOS transistor 

BSP122 

## **NOTES** 

2001 May 18 

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Philips Semiconductors 

N-channel enhancement mode vertical D-MOS transistor 

BSP122 

## **NOTES** 

2001 May 18 

7 

## **Philips Semiconductors – a worldwide company** 

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© Philips Electronics N.V. 2001 

SCA 72 

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. 

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. 

Printed in The Netherlands 

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Date of release: 2001 May 18 Document order number: 9397 750 08246 

613510/03/pp8

Updated at April 24, 2026

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