BF1105R,215

Power MOSFET, N Channel, 7 V, 30 mA, SOT-143R, Surface Mount

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Manufacturer: NXP
Product type: Single MOSFETs
No. of Pins: 4Pins
Channel Type: N Channel
Power Dissipation: 200mW
Transistor Mounting: Surface Mount
Transistor Polarity: N Channel
Power Dissipation Pd: 200mW
Transistor Case Style: SOT-143R
Drain Source Voltage Vds: 7V
Operating Temperature Max: 150°C
Continuous Drain Current Id: 30mA
Gate Source Threshold Voltage Max: 800mV
Delivery and price
Units per pack	100
Price	0.197 €
Current stock	10+
Lead time	30 days
Datasheet
## _**DISCRETE SEMICONDUCTORS**_ 

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DATA SHEET<br>**----- End of picture text -----**<br>


## **BF1105; BF1105R; BF1105WR** N-channel dual-gate MOS-FETs 

Product specification 1997 Dec 02 Supersedes data of 1997 Dec 01 

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**NXP Semiconductors** 

**Product specification** 

## **N-channel dual-gate MOS-FETs** 

## **BF1105; BF1105R; BF1105WR** 

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PINNING<br>PIN DESCRIPTION handbook, 2 colu 3 mns 4<br>1 source<br>2 drain<br>3 gate 2 2 1<br>4 gate 1<br>Top view MSB035<br>BF1105R marking code:  NAp.<br>Fig.2 Simplified outline<br>(SOT143R).<br>**----- End of picture text -----**<br>


## **FEATURES** 

- Short channel transistor with high forward transfer admittance to input capacitance ratio 

- Low noise gain controlled amplifier up to 1 GHz. 

- Internal self-biasing circuit to ensure good cross-modulation performance during AGC and good DC stabilization. 

## **APPLICATIONS** 

- VHF and UHF applications with 5 V supply voltage, such as television tuners and professional communications equipment. 

|tuners and professional<br>communications equipment.<br>**DESCRIPTION**<br>Enhancement type N-channel<br>field-effect transistor with source and<br>substrate interconnected. Integrated<br>diodes between gates and source<br>protect against excessive input<br>voltage surges. The BF1105,<br>BF1105R and BF1105WR are<br>encapsulated in the SOT143B,<br>SOT143R and SOT343R plastic<br>packages respectively.<br>**QUICK REFERENCE DATA**|tuners and professional<br>communications equipment.<br>**DESCRIPTION**<br>Enhancement type N-channel<br>field-effect transistor with source and<br>substrate interconnected. Integrated<br>diodes between gates and source<br>protect against excessive input<br>voltage surges. The BF1105,<br>BF1105R and BF1105WR are<br>encapsulated in the SOT143B,<br>SOT143R and SOT343R plastic<br>packages respectively.<br>**QUICK REFERENCE DATA**||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|||_handbook, 2 c_<br>**4**||_olumn_<br>|_s_|||_lfpage_<br>**4**<br>**3**|||||
||||||||||||||
||||||||||||||
|||Fig.1<br>Simplified outline<br>(SOT143B).<br>**BF1105 marking code:**NEp.<br>Top view<br>_MSB014_<br>**1**<br>**2**||||||Fig.3<br>Simplified outline<br>(SOT343R).<br>**BF1105WR marking code:**NA.<br>Top view<br>_MSB842_<br>**2**<br>**1**|||||
||||||||||||||
|**SYMBOL**|**PARAMETER**||**CONDITIONS**||||||**MIN.**|**TYP.**|**MAX.**|**UNIT**|
|VDS|drain-source voltage||||||||||7|V|
|ID|drain current||||||||||30|mA|
|Ptot|totalpower dissipation||Tamb80C||||||||200|mW|
|yfs|forward transfer admittance||||||||25|31||mS|
|Cig1-ss|input capacitance atgate 1|||||||||2.2|2.7|pF|
|Crss|reverse transfer capacitance||f = 1 MHz|||||||25|40|fF|
|F|noise figure||f = 800 MHz|||||||1.7|2.5|dB|
|Xmod|cross-modulation||input level for k = 1% at 40 dB AGC||||||100|||dBV|
|Tj|operating junction temperature||||||||||150|C|



## **CAUTION** 

This product is supplied in anti-static packing to prevent damage caused by electrostatic discharge during transport and handling. 

1997 Dec 02 

2 

NXP Semiconductors 

Product specification 

## N-channel dual-gate MOS-FETs 

## BF1105; BF1105R; BF1105WR 

## **LIMITING VALUES** 

In accordance with the Absolute Maximum Rating System (IEC 134). 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**MIN.**|**MAX.**|**UNIT**|
|---|---|---|---|---|---|
|VDS|drain-source voltage|||7|V|
|ID|drain current|||30|mA|
|IG1|gate 1 current|||10|mA|
|IG2|gate 2 current|||10|mA|
|Ptot|totalpower dissipation|Tamb80C; note 1; see Fig.4||200|mW|
|Tstg|storage temperature||65|+150|C|
|Tj|operating junction temperature|||+150|C|



## **Note** 

1. Device mounted on a printed-circuit board. 

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MGM243<br>250<br>handbook, halfpage<br>Ptot<br>(mW)<br>200<br>150<br>100<br>50<br>0<br>0 40 80 120 160<br>Tamb ( ° C)<br>Fig.4  Power derating curve.<br>**----- End of picture text -----**<br>


1997 Dec 02 

3 

NXP Semiconductors 

Product specification 

## N-channel dual-gate MOS-FETs 

## BF1105; BF1105R; BF1105WR 

## **THERMAL CHARACTERISTICS** 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**VALUE**|**UNIT**|
|---|---|---|---|---|
|Rthj-a|thermal resistance fromjunction to ambient in free air|note 1|350|K/W|
|Rthj-s|thermal resistance fromjunction to soldering point||200|K/W|



## **Note** 

1. Device mounted on a printed-circuit board. 

## **STATIC CHARACTERISTICS** 

Tj = 25 C unless otherwise specified. 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**MIN.**|**TYP.**|**MAX.**|**UNIT**|
|---|---|---|---|---|---|---|
|V(BR)DSS|drain-source breakdown voltage|VG1-S= VG2-S= 0; ID= 10 A|7|||V|
|V(BR)G1-SS|gate 1-source breakdown voltage|VG2-S= 0; ID= 0; IG1-S= 10 A|7|||V|
|V(BR)G2-SS|gate 2-source breakdown voltage|VG1-S= VDS= 0; IG2-S= 10 A|7|||V|
|VG2-S(th)|gate 2-source threshold voltage|VG1-S= 5 V; VDS= 5 V; ID= 20 A|0.3|0.8|1.2|V|
|IDSX|self-biasingdrain current|VG2-S= 4 V; VDS= 5 V|8||16|mA|
|IG1-SS|gate 1 cut-off current|VG1-S= 5 V; VG2-S= 0; ID= 0|||50|nA|
|IG2-SS|gate 2 cut-off current|VG1-S= VDS= 0; VG2-S= 4 V|||20|nA|



## **DYNAMIC CHARACTERISTICS** 

Common source; Tamb = 25 C; VG2-S = 4 V; VDS = 5 V; self-biasing current; unless otherwise specified. 

|**SYMBOL**|**PARAMETER**|**CONDITIONS**|**MIN.**|**TYP.**|**MAX.**|**UNIT**|
|---|---|---|---|---|---|---|
|yfs|forward transfer admittance|pulsed; Tj= 25C|25|31||mS|
|Cig1-ss|input capacitance atgate 1|f = 1 MHz||2.2|2.7|pF|
|Cig2-ss|input capacitance atgate 2|f = 1 MHz||1.6||pF|
|Coss|output capacitance|f = 1 MHz||1.2||pF|
|Crss|reverse transfer capacitance|f = 1 MHz||25|40|fF|
|F|noise figure|f = 800 MHz; YS= YS opt||1.7|2.5|dB|
|Gp|power gain|GS= 2 mS; BS= BS opt; GL= 0.5 mS;<br>BL= BL opt; f = 200 MHz; see Fig.16||38||dB|
|||GS= 3.3 mS; BS= BS opt; GL= 1 mS;<br>BL= BL opt; f = 800 MHz; see Fig.17||20||dB|
|Xmod|cross-modulation|input level for k = 1% at 0 dB AGC;<br>fw= 50 MHz; funw= 60 MHz; see Fig.18|85|||dBV|
|||input level for k = 1% at 40 dB AGC;<br>fw= 50 MHz; funw= 60 MHz; see Fig.18|100|||dBV|



1997 Dec 02 

4 

NXP Semiconductors 

Product specification 

## N-channel dual-gate MOS-FETs 

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MGM244<br>25<br>handbook, halfpage ID VG1 = 1.7 V<br>(mA)<br>20<br>1.6 V<br>1.5 V<br>15<br>1.4 V<br>10 1.3 V<br>1.2 V<br>5 1.1 V<br>1 V<br>0<br>0 2 4 6 8<br>VDS (V)<br>VG2-S = 4 V.<br>Tj = 25 C.<br>Fig.5  Output characteristics; typical values.<br>**----- End of picture text -----**<br>


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MGM246<br>40<br>handbook, halfpage<br>yfs V G2-S  = 4 V<br>(mS)<br>3.5 V<br>30<br>3 V<br>20<br>10<br>2.5 V<br>2 V<br>0<br>0 10 20 30<br>ID (mA)<br>VDS = 5 V.<br>Tj = 25 C.<br>Fig.7 Forward transfer admittance as a function<br>of drain current; typical values.<br>**----- End of picture text -----**<br>


## BF1105; BF1105R; BF1105WR 

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MGM245<br>40<br>handbook, halfpage<br>ID<br>(mA)<br>30 V G2-S  = 4 V 3.5 V<br>3 V<br>2.5 V<br>20<br>2 V<br>10<br>1.5 V<br>1 V<br>0<br>0 0.5 1 1.5 2 2.5<br>VG1 (V)<br>VDS = 5 V.<br>Tj = 25 C.<br>Fig.6  Transfer characteristics; typical values.<br>**----- End of picture text -----**<br>


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MGM247<br>16<br>handbook, halfpage<br>ID<br>(mA)<br>12<br>(1) (2)(3)<br>8<br>(4) (5)<br>4<br>0<br>0 1 2 3 4 5<br>VG2-S (V)<br>(1) VDS = 5 V. (4) VDS = 3.5 V.<br>(2) VDS = 4.5 V. (5) VDS = 3 V.<br>(3) VDS = 4 V.<br>Fig.8 Drain current as a function of gate 2<br>voltage; typical values.<br>**----- End of picture text -----**<br>


1997 Dec 02 

5 

NXP Semiconductors 

Product specification 

## N-channel dual-gate MOS-FETs 

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fMGM248<br>16<br>handbook, halfpage<br>ID<br>(mA)<br>12<br>8<br>4<br>0<br>0 2 4 6 8<br>VDS (V)<br>VG2-S = 4 V.G2-S = 4 V. = 4 V.<br>Tj = 25 C.j = 25 C. = 25 C. C.C.<br>Fig.9 Drain current as a function of drain-source<br>voltage; typical values.<br>**----- End of picture text -----**<br>


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fMGM248<br>16<br>handbook, halfpage<br>ID<br>(mA)<br>12<br>8<br>4<br>0<br>0 2 4 6 8<br>VDS (V)<br>VG2-S = 4 V.G2-S = 4 V. = 4 V.<br>Tj = 25 C.j = 25 C. = 25 C. C.C.<br>Fig.9 Drain current as a function of drain-source<br>voltage; typical values.<br>**----- End of picture text -----**<br>


## BF1105; BF1105R; BF1105WR 

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MGM249<br>16<br>handbook, halfpage<br>ID<br>(mA)<br>12<br>8<br>4<br>0<br>− 8 − 6 − 4 − 2 0<br>IG1 ( μ A)<br>VDS = 5 V; VG2-S = 4 V; Tj = 25 C.DS = 5 V; VG2-S = 4 V; Tj = 25 C. = 5 V; VG2-S = 4 V; Tj = 25 C.G2-S = 4 V; Tj = 25 C. = 4 V; Tj = 25 C.j = 25 C. = 25 C. C.C.<br>Fig.10 Drain current as a function of gate 1 current;<br>typical values.<br>**----- End of picture text -----**<br>


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MGM249<br>16<br>handbook, halfpage<br>ID<br>(mA)<br>12<br>8<br>4<br>0<br>− 8 − 6 − 4 − 2 0<br>IG1 ( μ A)<br>VDS = 5 V; VG2-S = 4 V; Tj = 25 C.DS = 5 V; VG2-S = 4 V; Tj = 25 C. = 5 V; VG2-S = 4 V; Tj = 25 C.G2-S = 4 V; Tj = 25 C. = 4 V; Tj = 25 C.j = 25 C. = 25 C. C.C.<br>Fig.10 Drain current as a function of gate 1 current;<br>typical values.<br>**----- End of picture text -----**<br>


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MGM250<br>110<br>handbook, halfpage<br>Vunw<br>(dB μ V)<br>100<br>90<br>80<br>0 20 40 60<br>gain reduction (dB)<br>VDS = 5 V; VG2nom = 4 V; IDnom = Iself bias; fw = 50 MHz;<br>funw = 60 MHz; Tamb = 25 C.<br>Fig.11 Unwanted voltage for 1% cross-modulation<br>as a function of gain reduction;<br>typical values (see Fig.18).<br>**----- End of picture text -----**<br>


1997 Dec 02 

6 

NXP Semiconductors 

Product specification 

## N-channel dual-gate MOS-FETs 

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MGM251<br>10 [2]<br>handbook, hal fpage<br>yis<br>(mS)<br>10<br>b is<br>1<br>gis<br>10 [−] [1]<br>10 [−] [2]<br>10 10 [2] f (MHz) 10 [3]<br>VDS = 5 V; VG2-S = 4 V.<br>ID = 12 mA; Tamb = 25 C.<br>Fig.12 Input admittance as a function of frequency;<br>typical values.<br>**----- End of picture text -----**<br>


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MGM253<br>10 [[2]] − 10 [[2]]<br>handbook, hal fpage<br>|yfs| ϕ fs<br>(mS) (deg)<br>|yfs|<br>10 − 10<br>ϕ fs<br>1 − 1<br>10 10 [[2]] 10 [[3]]<br>f (MHz)<br>VDS = 5 V; VG2-S = 4 V.DS = 5 V; VG2-S = 4 V. = 5 V; VG2-S = 4 V.G2-S = 4 V. = 4 V.<br>ID = 12 mA; Tamb = 25 C.D = 12 mA; Tamb = 25 C. = 12 mA; Tamb = 25 C.amb = 25 C. = 25 C. C.C.<br>Fig.14 Forward transfer admittance and phase as<br>a function of frequency; typical values.<br>**----- End of picture text -----**<br>


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MGM253<br>10 [[2]] − 10 [[2]]<br>handbook, hal fpage<br>|yfs| ϕ fs<br>(mS) (deg)<br>|yfs|<br>10 − 10<br>ϕ fs<br>1 − 1<br>10 10 [[2]] 10 [[3]]<br>f (MHz)<br>VDS = 5 V; VG2-S = 4 V.DS = 5 V; VG2-S = 4 V. = 5 V; VG2-S = 4 V.G2-S = 4 V. = 4 V.<br>ID = 12 mA; Tamb = 25 C.D = 12 mA; Tamb = 25 C. = 12 mA; Tamb = 25 C.amb = 25 C. = 25 C. C.C.<br>Fig.14 Forward transfer admittance and phase as<br>a function of frequency; typical values.<br>**----- End of picture text -----**<br>


## BF1105; BF1105R; BF1105WR 

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MGM252<br>10 [3] − 10 [3]<br>handbook, hal fpage<br>|yrs| ϕ rs<br> ( μ S) (deg)<br>10 [2] ϕ rs − 10 [2]<br>|yrs|<br>10 − 10<br>1 − 1<br>10 10 [2] f (MHz) 10 [3]<br>VDS = 5 V; VG2-S = 4 V.<br>ID = 12 mA; Tamb = 25 C.<br>Fig.13 Reverse transfer admittance and phase as<br>a function of frequency; typical values.<br>**----- End of picture text -----**<br>


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MGM254<br>10<br>handbook, half page<br>yos<br>(mS)<br>bos<br>1<br>gos<br>10 [[−]] [[1]]<br>10 [[−]] [[2]]<br>10 10 [[2]] 10 [[3]]<br>f (MHz)<br>VDS = 5 V; VG2-S = 4 V.DS = 5 V; VG2-S = 4 V. = 5 V; VG2-S = 4 V.G2-S = 4 V. = 4 V.<br>ID = 12 mA; Tamb = 25 C.D = 12 mA; Tamb = 25 C. = 12 mA; Tamb = 25 C.amb = 25 C. = 25 C. C.C.<br>Fig.15 Output admittance as a function of<br>frequency; typical values.<br>**----- End of picture text -----**<br>


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MGM254<br>10<br>handbook, half page<br>yos<br>(mS)<br>bos<br>1<br>gos<br>10 [[−]] [[1]]<br>10 [[−]] [[2]]<br>10 10 [[2]] 10 [[3]]<br>f (MHz)<br>VDS = 5 V; VG2-S = 4 V.DS = 5 V; VG2-S = 4 V. = 5 V; VG2-S = 4 V.G2-S = 4 V. = 4 V.<br>ID = 12 mA; Tamb = 25 C.D = 12 mA; Tamb = 25 C. = 12 mA; Tamb = 25 C.amb = 25 C. = 25 C. C.C.<br>Fig.15 Output admittance as a function of<br>frequency; typical values.<br>**----- End of picture text -----**<br>


1997 Dec 02 

7 

NXP Semiconductors 

Product specification 

## N-channel dual-gate MOS-FETs 

## BF1105; BF1105R; BF1105WR 

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handbook, full pagewidth VAGC VDS<br>1 nF<br>2  μ H<br>1 nF<br>1 nF<br>1 nF<br>output<br>47 k Ω L2 50  Ω<br>1 nF<br>G2 D<br>BF1105<br>input 5.5 pF G1 BF1105WRBF1105R S 10 pF<br>50  Ω<br>C1 15<br>L1 pF BB405 330 k Ω<br>1 nF<br>1 nF BB405 330 k Ω<br>1 nF<br>Vtun input Vtun output MGM255<br>VDS = 5 V, GS= 2 mS, GL = 0.5 mS, f = 200 MHz.<br>L1 = 45 nH, 4 turns, internal diameter = 4 mm, 0.8 mm copper wire.<br>L2 = 160 nH, 3 turns, internal diameter = 8 mm, 0.8 mm copper wire; tapped at approximately half a turn from the cold side, to set GL = 0.5 mS.<br>C1 adjusted for GS = 2 mS.<br>Fig.16  Gain test circuit.<br>**----- End of picture text -----**<br>


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handbook, full pagewidth VAGC VDS<br>1 nF 1 nF<br>47 k Ω<br>L3<br>1 nF L2 1 nF<br>G2 D � �� � output<br>BF1105 50  Ω<br>1 nF L1 BF1105R<br>input50  Ω � � � G1 BF1105WR S �� 0.5 to 3.5 pF� � 4 to 40 pF<br>MGM256<br>2 to 18 pF 0.5 to 3.5 pF<br>VDS = 5 V, GS= 3.3 mS, GL = 1 mS, f = 800 MHz.<br>L1 = 2 cm, silvered 0.8 mm copper wire 4 mm above ground plane.<br>L2 = 2 cm, silvered 0.8 mm copper wire 4 mm above ground plane.<br>L3 = 11 turns 0.5 mm copper wire without spacing, internal diameter = 3 mm, L = approx. 200 nH.<br>Fig.17  Gain test circuit.<br>**----- End of picture text -----**<br>


1997 Dec 02 

8 

NXP Semiconductors 

Product specification 

## N-channel dual-gate MOS-FETs 

## BF1105; BF1105R; BF1105WR 

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handbook, full pagewidth VG2 VDS<br>4.7 nF<br>10 k Ω<br>47  μ H<br>4.7 nF 10 nF<br>G2 D<br>BF1105<br>10 nF G1 BF1105R S R1 =<br>BF1105WR<br>50  Ω<br>Rgen 50  Ω<br>50  Ω<br>MGM257<br>Vi<br>Fig.18  Cross-modulation test set-up.<br>**----- End of picture text -----**<br>


**Table 1** Scattering parameters: VDS = 5 V; VG2-S = 4 V; ID = 12 mA 

|**f**<br>**(MHz)**|**S11**|**S11**|**S21**|**S21**|**S12**|**S12**|**S22**|**S22**|
|---|---|---|---|---|---|---|---|---|
||**MAGNITUDE**<br>**(ratio)**|**ANGLE**<br>**(deg)**|**MAGNITUDE**<br>**(ratio)**|**ANGLE**<br>**(deg)**|**MAGNITUDE**<br>**(ratio)**|**ANGLE**<br>**(deg)**|**MAGNITUDE**<br>**(ratio)**|**ANGLE**<br>**(deg)**|
|50|0.994|3.8|3.060|175.4|0.000|86.9|0.985|2.1|
|100|0.991|7.5|3.047|170.9|0.002|86.1|0.983|4.2|
|200|0.982|14.7|3.004|162.1|0.003|82.7|0.980|8.3|
|300|0.968|21.7|2.932|153.4|0.004|79.7|0.976|12.1|
|400|0.956|28.8|2.896|145.3|0.006|77.8|0.972|16.2|
|500|0.937|35.4|2.815|137.1|0.007|76.7|0.967|20.0|
|600|0.918|41.8|2.735|129.2|0.007|76.3|0.961|23.7|
|700|0.897|48.1|2.651|121.5|0.008|76.7|0.955|27.3|
|800|0.878|54.0|2.575|114.0|0.008|79.7|0.948|30.9|
|900|0.858|59.9|2.482|106.5|0.008|82.2|0.941|34.4|
|1000|0.840|65.5|2.396|99.5|0.008|88.0|0.935|37.9|



**Table 2** Noise data: VDS = 5 V; VG2-S = 4 V; ID = 12 mA 

|**f**<br>**(MHz)**|**Fmin**<br>**(dB)**|**opt**|**opt**|**Rn**<br>**(****)**|
|---|---|---|---|---|
|||**(ratio)**|**(deg)**||
|800|1.5|0.674|39.7|37.15|



1997 Dec 02 

9 

NXP Semiconductors 

Product specification 

## N-channel dual-gate MOS-FETs 

## BF1105; BF1105R; BF1105WR 

## **PACKAGE OUTLINES** 

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Plastic surface-mounted package; 4 leads SOT143B<br>D B E A X<br>y<br>v M A HE<br>e<br>bp w M B<br>4 3<br>Q<br>A<br>A1<br>c<br>1 2<br>Lp<br>b1<br>e1 detail X<br>0 1 2 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>UNIT A maxA1 bp b1 c D E e e1 HE Lp Q v w y<br>1.1 0.48 0.88 0.15 3.0 1.4 2.5 0.45 0.55<br>mm 0.1 1.9 1.7 0.2 0.1 0.1<br>0.9 0.38 0.78 0.09 2.8 1.2 2.1 0.15 0.45<br>OUTLINE  REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION  IEC  JEDEC  JEITA PROJECTION<br>04-11-16<br>SOT143B<br>06-03-16<br>**----- End of picture text -----**<br>


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## N-channel dual-gate MOS-FETs 

## BF1105; BF1105R; BF1105WR 

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Plastic surface-mounted package; reverse pinning; 4 leads SOT143R<br>D B E A X<br>y<br>v M A HE<br>e<br>bp w M B<br>3 4<br>Q<br>A<br>A1<br>c<br>2 1<br>Lp<br>b1<br>e1 detail X<br>0 1 2 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>UNIT A mA1ax bp b1 c D E e e1 HE Lp Q v w y<br>1.1 0.48 0.88 0.15 3.0 1.4 2.5 0.55 0.45<br>mm 0.1 1.9 1.7 0.2 0.1 0.1<br>0.9 0.38 0.78 0.09 2.8 1.2 2.1 0.25 0.25<br>OUTLINE  REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION  IEC  JEDEC  JEITA PROJECTION<br>04-11-16<br>SOT143R SC-61AA<br>06-03-16<br>**----- End of picture text -----**<br>


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## N-channel dual-gate MOS-FETs 

## BF1105; BF1105R; BF1105WR 

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Plastic surface-mounted package; reverse pinning; 4 leads SOT343R<br>D B E A<br>X<br>y HE v M A<br>e<br>3 4<br>Q<br>A<br>A1<br>c<br>2 1<br>w M B bp b1 Lp<br>e 1 detail X<br>0 1 2 mm<br>scale<br>DIMENSIONS (mm are the original dimensions)<br>UNIT A maxA1 bp b1 c D E e e1 HE Lp Q v w y<br>1.1 0.4 0.7 0.25 2.2 1.35 2.2 0.45 0.23<br>mm 0.1 1.3 1.15 0.2 0.2 0.1<br>0.8 0.3 0.5 0.10 1.8 1.15 2.0 0.15 0.13<br>OUTLINE  REFERENCES EUROPEAN<br>ISSUE DATE<br>VERSION  IEC  JEDEC  EIAJ PROJECTION<br>97-05-21<br> SOT343R<br>06-03-16<br>**----- End of picture text -----**<br>


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## N-channel dual-gate MOS-FETs 

## BF1105; BF1105R; BF1105WR 

## **DATA SHEET STATUS** 

|**DATA SHEET STATUS**|||
|---|---|---|
|**DOCUMENT**<br>**STATUS**(1)|**PRODUCT**<br>**STATUS**(2)|**DEFINITION**|
|Objective data sheet|Development|This document contains data from the objective specification for product<br>development.|
|Preliminarydata sheet|Qualification|This document contains data from thepreliminaryspecification.|
|Product data sheet|Production|This document contains theproduct specification.|



## **Notes** 

1. Please consult the most recently issued document before initiating or completing a design. 

2. The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 

## **DEFINITIONS** 

**Product specification**  The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 

## **DISCLAIMERS** 

**Limited warranty and liability**  Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. 

In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. 

Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the _Terms and conditions of commercial sale_ of NXP Semiconductors. 

**Right to make changes**  NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 

 **Suitability for use** NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. 

 **Applications** Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 

Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. 

1997 Dec 02 

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## N-channel dual-gate MOS-FETs 

NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. 

 **Limiting values** Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. 

**Terms and conditions of commercial sale**  NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. 

## BF1105; BF1105R; BF1105WR 

 **Export control** This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 

**Quick reference data**  The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. 

**Non-automotive qualified products**  Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. 

In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. 

**No offer to sell or license**  Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 

1997 Dec 02 

14 

## _**NXP Semiconductors**_ 

## _**provides High Performance Mixed Signal and Standard Product solutions that leverage its leading RF, Analog, Power Management, Interface, Security and Digital Processing expertise**_ 

## **Customer notification** 

This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal definitions and disclaimers. No changes were made to the technical content, except for package outline drawings which were updated to the latest version. 

## **Contact information** 

For additional information please visit: **http://www.nxp.com** For sales offices addresses send e-mail to: **salesaddresses@nxp.com** 

## © NXP B.V. 2010 

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 15 Date of release: 1997 Dec 021997 Dec 02 

Date of release: 1997 Dec 021997 Dec 02 

R77/03/pp15
Updated at February 9, 2023
NXP Semiconductors is a global leader in secure connectivity solutions, driving innovation across the automotive, industrial, IoT, mobile, and communications infrastructure markets. By developing advanced, purpose-built technologies, NXP enables devices to sense, think, connect, and act intelligently, delivering rigorously tested components that make the connected world safer and more efficient. Within the semiconductor space, NXP is highly regarded for its extensive range of high-performance integrated circuits and discrete devices. The brand's portfolio excels in drivers and interfaces, featuring a comprehensive selection of I/O expanders designed to streamline complex system architectures. For demanding high-frequency and wireless applications, NXP provides industry-leading RF FETs and RF/PIN diodes engineered to deliver exceptional signal integrity, efficiency, and reliability. The NXP product lineup further extends to essential discrete components, including versatile bipolar transistors, JFETs, and small signal diodes optimized for precision switching and amplification. Additionally, the portfolio supports advanced automation and smart applications with precision IC sensors, such as MEMS accelerometers, alongside specialized power management solutions like AC/DC LED driver ICs and single MOSFETs for cutting-edge electronics design.
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