AX5243-1-TW30

## AX5243 

## Advanced High Performance ASK and FSK Narrow-band Transceiver for 27 - 1050 MHz Range 

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## **OVERVIEW** 

The AX5243 is a true single chip ultra−low power narrow−band CMOS transceiver for use in licensed and unlicensed bands from 27 and 1050 MHz. The on−chip transceiver consists of a fully integrated RF front−end with modulator, and demodulator. Base band data processing is implemented in an advanced and flexible communication controller that enables user friendly communication via the SPI interface. 

## **Features** 

Advanced Multi−channel Narrow−band Single Chip UHF Transceiver (FSK / MSK / 4−FSK / GFSK / GMSK / ASK / AFSK / FM / PSK) 

**QFN20 4x4, 0.5P CASE 485EE** 

## **ORDERING INFORMATION** 

|**Device**|**Type**|**Qty**|
|---|---|---|
|AX5243−1−TA05|Tape & Reel|500|
|AX5243−1−TW30|Tape & Reel|3,000|



Low−Power 

- RX 

   - 9.5 mA @ 868 MHz and 433 MHz 6.5 mA @ 169 Hz 

- TX at 868 MHz 

   - 7.5 mA @  0 dBm 16 mA @ 10 dBm 48 mA @ 16 dBm 

- 50 nA Deep Sleep Current 

- 500 nA Power−down Current with Low Frequency Duty Cycle Clock Running 

- Sensitivity with FEC 

   - −137 dBm @ 0.1 kbps, 868 MHz, FSK 

   - −122 dBm @    5 kbps, 868 MHz, FSK 

   - −111 dBm @  50 kbps, 868 MHz, FSK 

- High Selectivity Receiver with up to 45 dB Adjacent Channel Rejection 

- 0 dBm Maximum Input Power 

- > ±10% Data−rate Error Tolerance 

Extended Supply Voltage Range 

- 1.8 V − 3.6 V Single Supply 

High Sensitivity / High Selectivity Receiver 

- Data Rates from 0.1 kbps to 125 kbps 

- Optional Forward Error Correction (FEC) 

- Sensitivity without FEC 

   - −135 dBm @  0.1 kbps, 868 MHz, FSK 

   - −126 dBm @     1 kbps, 868 MHz, FSK −117 dBm @   10 kbps, 868 MHz, FSK −107 dBm @ 100 kbps, 868 MHz, FSK 

   - −105 dBm @ 125 kbps, 868 MHz, FSK 

   - −138 dBm @  0.1 kbps, 868 MHz, PSK 

   - −130 dBm @     1 kbps, 868 MHz, PSK −120 dBm @   10 kbps, 868 MHz, PSK −109 dBm @ 100 kbps, 868 MHz, PSK −108 dBm @ 125 kbps, 868 MHz, PSK 

- Short Preamble Modes Allow the Receiver to Work with as little as 16 Preamble Bits 

- Fast State Switching Times 200 s TX → RX Switching Time 

   - 62   s RX → TX Switching Time 

## Transmitter 

- Data−rates from 0.1 kbps to 125 kbps 

- High Efficiency, High Linearity Integrated Power Amplifier 

- Maximum Output Power 16 dBm @ 868 MHz 16 dBm @ 433 MHz 16 dBm @ 169 MHz 

- Power Level Programmable in 0.5 dB Steps 

- GFSK Shaping with BT = 0.3 or BT = 0.5 

- Unrestricted Power Ramp Shaping 

Publication Order Number: **AX5243/D** 

**1** 

© Semiconductor Components Industries, LLC, 2016 **May, 2016 − Rev. 3** 

**AX5243** 

## Frequency Generation 

- Configurable for Usage in 27 MHz −1050 MHz Bands 

- RF Carrier Frequency and FSK Deviation Programmable in 1 Hz Steps 

- Ultra Fast Settling RF Frequency Synthesizer for Low−power Consumption 

- Fully Integrated RF Frequency Synthesizer with VCO Auto−ranging and Band−width Boost Modes for Fast Locking 

- Configurable for either Fully Integrated VCO, Internal VCO with External Inductor or Fully External VCO 

- Configurable for either Fully Integrated or External Synthesizer Loop Filter for a Large Range of Bandwidths 

- Channel Hopping up to 2000 hops/s 

- Automatic Frequency Control (AFC) 

## Flexible Antenna Interface 

- Integrated RX/TX Switching with Differential Antenna Pins 

## Wakeup−on−Radio 

- 640 Hz or 10 kHz Lowest Power Wake−up Timer 

- Wake−up Time Interval Programmable between 98 �s and 102 s 

## Advanced Crystal Oscillator 

- Fast Start−up and Lowest Power Steady−state XTAL Oscillator for a Wide Range of Crystals 

- Integrated Crystal Tuning Capacitors 

- Possibility of Applying an External Clock Reference (TCXO) 

## Miscellaneous Features 

- Few External Components 

- SPI Microcontroller Interface 

- Extended Register Set 

- Fully Integrated Current/Voltage References 

- QFN20 4 mm x 4 mm Package 

- Internal Power−on−Reset 

- Brown−out Detection 

- 10 Bit 1 MS/s General Purpose ADC (GPADC) 

## **Applications** 

27 − 1050 MHz Licensed and Unlicensed Radio Systems 

- Internet of Things 

- Automatic Meter Reading (AMR) 

- Security Applications 

- Building Automation 

- Wireless Networks 

- Messaging Paging 

## Sophisticated Radio Controller 

- Fully Automatic Packet Reception and Transmission without Micro−controller Intervention 

- Supports HDLC, Raw, Wireless M−Bus Frames and Arbitrary Defined Frames 

- Automatic Channel Noise Level Tracking 

   - Compatible with: Wireless M−Bus, POCSAG, FLEX, KNX, Sigfox, Z−Wave, enocean 

   - Regulatory Regimes: EN 300 220 V2.3.1 including the Narrow−band 12.5 kHz, 20 kHz and 25 kHz Definitions; EN 300 422; FCC Part 15.247; FCC Part 15.249; FCC Part 90 6.25 kHz, 12.5 kHz and 25 kHz 

- �s Resolution Timestamps for Exact Timing (eg. for Frequency Hopping Systems) 

- 256 Byte Micro−programmable FIFO, optionally Supports Packet Sizes > 256 Bytes 

- Three Matching Units for Preamble Byte, Sync−word and Address 

- Ability to store RSSI, Frequency Offset and Data−rate Offset with the Packet Data 

- Multiple Receiver Parameter Sets Allow the Use of more Aggressive Receiver Parameters during Preamble, dramatically Shortening the Required Preamble Length at no Sensitivity Degradation 

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**AX5243** 

## **BLOCK DIAGRAM** 

**==> picture [489 x 368] intentionally omitted <==**

**----- Start of picture text -----**<br>
17 18<br>AX5243<br>Mixer Digital IF De-<br>LNA AGC PGAsIF Filter & ADC channelfilter modulator<br>ANTP 3<br>AGC<br>ANTN 4<br>Modulator<br>PA diff<br>FOUT Chip configuration Communication Controller &<br>Serial Interface<br>POR<br>FXTAL RF Frequency References Registers<br>Generation<br>Subsystem Low Power SPI<br>Oscillator Wake on Radio<br>RF Output 640 Hz/10kHz<br>27 MHz –<br>1.05 GHz<br>Crystal<br>Oscillator Divider<br>typ.<br>16 MHz Voltage<br>Regulator<br>14 15<br>20 19 9 6 7 8 1,5 16 10 11 12 13<br>GPADC1 GPADC2<br>r<br>FIFO<br>rror<br>ion<br> Controlle FIFO<br>Encoder Framing handling<br>Correct dio<br>Forward E Ra timing and packet<br>CLK16P CLK16N<br>SYSCLK FILT L1 L2 VDD_ANA VDD_IO IRQ TCXO_EN SEL CLK MISO MOSI<br>**----- End of picture text -----**<br>


**Figure 1. Functional Block Diagram of the AX5243** 

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**3** 

**AX5243** 

## **Table 1. PIN FUNCTION DESCRIPTIONS** 

|**Symbol**|**Pin(s)**|**Type**|**Description**|
|---|---|---|---|
|VDD_ANA|1|P|Analog power output, decouple to neighboring GND|
|GND|2|P|Ground, decouple to neighboring VDD_ANA|
|ANTP|3|A|Differential antenna input/output|
|ANTN|4|A|Differential antenna input/output|
|VDD_ANA|5|P|Analog power output, decouple to GND|
|FILT|6|A|Optional synthesizer filter|
|L2|7|A|Optional synthesizer inductor, should be shorted with L1 if not used.|
|L1|8|A|Optional synthesizer inductor, should be shorted with L2 if not used.|
|SYSCLK|9|I/O|Default functionality: Crystal oscillator (or divided) clock output<br>Can be programmed to be used as a general purpose I/O pin<br>Selectable internal 65 k�pull−up resistor|
|SEL|10|I|Serial peripheral interface select|
|CLK|11|I|Serial peripheral  interface clock|
|MISO|12|O|Serial peripheral  interface data output|
|MOSI|13|I|Serial peripheral  interface data input|
|IRQ|14|I/O|Default functionality: Transmit and receive interrupt<br>Can be programmed to be used as a general purpose I/O pin<br>Selectable internal 65 k�pull−up resistor|
|TCXO_EN|15|I/O|General purpose I/O pin which can be programmed to enable an<br>external TCXO<br>Selectable internal 65 k�pull−up resistor|
|VDD_IO|16|P|Power supply 1.8 V – 3.3 V|
|GPADC1|17|A|GPADC input, must be connected to GND if not used|
|GPADC2|18|A|GPADC input, must be connected to GND if not used|
|CLK16N|19|A|Crystal oscillator input/output|
|CLK16P|20|A|Crystal oscillator input/output|
|GND|Center pad|P|Ground on center pad of QFN, must be connected|



A = analog input I = digital input signal O = digital output signal I/O = digital input/output signal N = not to be connected P = power or ground 

All digital inputs are Schmitt trigger inputs, digital input and output levels are LVCMOS/LVTTL compatible and 5 V tolerant. 

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**4** 

**AX5243** 

## **Pinout Drawing** 

**==> picture [195 x 187] intentionally omitted <==**

**----- Start of picture text -----**<br>
20 19 18 17 16<br>VDD_ANA 1 15 TCXO_EN<br>GND 2 14 IRQ<br>ANTP 3 AX5243 13 MOSI<br>ANTN 4 12 MISO<br>VDD_ANA 5 11 CLK<br>6 7 8 9 10<br>CLK16P CLK16N GPADC2 GPADC1 VDD_IO<br>FILT L2 L1 SYSCLK SEL<br>**----- End of picture text -----**<br>


**==> picture [167 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
Exposed center pad of the QFN package: GND<br>**----- End of picture text -----**<br>


**Figure 2. Pinout Drawing (Top View)** 

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**5** 

**AX5243** 

## **SPECIFICATIONS** 

**Table 2. ABSOLUTE MAXIMUM RATINGS** 

|**Symbol**|**Description**|**Condition**|**Min**|**Max**|**Units**|
|---|---|---|---|---|---|
|VDD_IO|Supply voltage||−0.5|5.5|V|
|IDD|Supply current|||200|mA|
|Ptot|Total power consumption|||800|mW|
|Pi|Absolute maximum input power at receiver input|ANTP and ANTN<br>pins in RX mode||10|dBm|
|II1|DC current into any pin except ANTP, ANTN||−10|10|mA|
|II2|DC current into pins ANTP, ANTN||−100|100|mA|
|IO|Output Current|||40|mA|
|Via|Input voltage ANTP, ANTN pins||−0.5|5.5|V|
||Input voltage digital pins||−0.5|5.5|V|
|Ves|Electrostatic handling|HBM|−2000|2000|V|
|Tamb|Operating temperature||−40|85|°C|
|Tstg|Storage temperature||−65|150|°C|
|Tj|Junction Temperature|||150|°C|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

1. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 

## **DC Characteristics** 

**Table 3. SUPPLIES** 

|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|TAMB|Operational ambient temperature||−40|27|85|°C|
|VDD_IO|I/O and voltage regulator supply voltage||1.8|3.0|3.6|V|
|VBOUT|Brown−out threshold|Note 1||1.3||V|
|IDSLLEP|Deep Sleep current:<br>All analog and digital functions are<br>powered down|PWRMODE = 0x01||50||nA|
|IPDOWN|Power−down current:<br>Register file contents preserved|PWRMODE = 0x00||400||nA|
|IWOR|Wakeup−on−radio mode:<br>Low power timer and WOR<br>state−machine are running at 640 Hz|PWRMODE = 0x0B||500||nA|
|ISTANBY|Standby−current:<br>All power domains are powered up,<br>crystal oscillator and references are<br>running|PWRMODE = 0x05||230||�A|
|IRX|Current consumption RX<br>PWRMODE = 0x09<br>RF Frequency Subsystem:<br>Internal VCO and internal loop−fiter|868 MHz, datarate 6 kbps||9.5||mA|
|||169 MHz, datarate 6 kbps||6.5|||
|||868 MHz, datarate 100 kbps||11|||
|||169 MHz, datarate 100 kbps||7.5|||
|ITX−DIFF|Current consumption TX|868 MHz, 16 dBm, FSK, Note 2<br>RF Frequency Subsystem:<br>Internal VCO and loop−filter||48||mA|



1. Digital circuitry is functional down to typically 1 V. 

2. Measured with optimized matching networks. 

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**AX5243** 

For information on current consumption in complex modes of operation tailored to your application, see the software AX−RadioLab for AX5243. 

## _Note on current consumption in TX mode_ 

To achieve best output power the matching network has to be optimized for the desired output power and frequency. As a rule of thumb a good matching network produces about 50% efficiency with the AX5243 power amplifier although over 90% are theoretically possible. A typical matching network has between 1 dB and 2 dB loss (Ploss). The PA is internally multiplexed with the LNA on pins ANTP and ANTN. Therefore constraints for the RX matching have to be considered for the PA matching. 

The current consumption can be calculated as 

**==> picture [227 x 24] intentionally omitted <==**

Ioffset is about 6 mA for the fully integrated VCO at 400 MHz to 1050 MHz, and 3 mA for the VCO with external inductor at 169 MHz. The following table shows calculated current consumptions versus output power for Ploss = 1 dB, PAefficiency = 0.5, Ioffset = 6 mA at 868 MHz and Ioffset = 3.5 mA at 169 MHz. 

## **Table 4. CURRENT CONSUMPTION VS. OUTPUT POWER** 

|**POWER**|||
|---|---|---|
|**Pout [dBm]**|**Itxcalc [mA]**||
||**868 MHz**|**169 MHz**|
|0|7.5|4.5|
|1|7.9|4.9|
|2|8.4|5.4|
|3|9.0|6.0|
|4|9.8|6.8|
|5|10.8|7.8|
|6|12.1|9.1|
|7|13.7|10.7|
|8|15.7|12.7|
|9|18.2|15.2|
|10|21.3|18.3|
|11|25.3|22.3|
|12|30.3|27.3|
|13|36.7|33.7|
|14|44.6|41.6|
|15|54.6|51.6|



Both AX5243 power amplifiers run from the regulated VDD_ANA supply and not directly from the battery. This has the advantage that the current and output power do not vary much over supply voltage and temperature. 

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**AX5243** 

## **Table 5. LOGIC** 

|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|**Digital Inputs**|||||||
|VT+|Schmitt trigger low to high threshold point|||1.9||V|
|VT−|Schmitt trigger high to low threshold point|||1.2||V|
|VIL|Input voltage, low||||0.8|V|
|VIH|Input voltage, high||2.0|||V|
|IL|Input leakage current||−10||10|�A|
|Rpullup|Pull−up resistors<br>Pins SYSCLK, IRQ, TCXO_EN|Pull−ups enabled in<br>the relevant pin<br>configuration registers||65||k�|
|**Digital Outputs**|||||||
|IOH|Output Current, high|VDD_IO = 3 V<br>VOH= 2.4 V|4|||mA|
|IOL|Output Current, low|VDD_IO = 3 V<br>VOL= 0.4 V|4|||mA|
|IOZ|Tri−state output leakage current||−10||10|�A|



## **AC Characteristics** 

**Table 6. CRYSTAL OSCILLATOR** 

|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|fXTAL|Crystal frequency|Note 1, 2, 3|10|16|50|MHz|
|gmosc|Oscillator transconductance control range|Self−regulated see Note 4|0.2||20|mS|
|Cosc|Programmable tuning capacitors at pins<br>CLK16N and CLK16P|XTALCAP = 0x00 default||3||pF|
|||XTALCAP = 0x01||8.5||pF|
|||XTALCAP = 0xFF||40||pF|
|Cosc−lsb|Programmable tuning capacitors,<br>increment per LSB of XTALCAP|XTALCAP = 0x01 – 0xFF||0.5||pF|
|fext|External clock input (TCXO)|Note 2, 3, 5|10|16|50|MHz|
|RINosc|Input DC impedance||10|||k�|
|NDIVSYSCLK|Divider ratio fSYSCLK= fXTAL/ NDIVSYSCLK||20|24|210||



1. Tolerances and start−up times depend on the crystal used. Depending on the RF frequency and channel spacing the IC must be calibrated to the exact crystal frequency using the readings of the register TRKFREQ. 

2. The choice of crystal oscillator or TCXO frequency depends on the targeted regulatory regime for TX, see separate documentation on meeting regulatory requirements. 

3. To avoid spurious emission, the crystal or TCXO reference frequency should be chosen so that the RF carrier frequency is not an integer multiple of the crystal or TCXO frequency. 

4. The oscillator transconductance is regulated for fastest start−up time during start−up and for lowest power during steady state oscillation. This means that values will depend on the crystal used. 

5. If an external clock (TCXO) is used, it should be input via an AC coupling at pin CLK16P with the oscillator powered up and XTALCAP = 0x00. For detailed TCXO network recommendations depending on the TCXO output swing refer to the AX5243 Application Note: Use with a TCXO Reference Clock. 

**Table 7. LOW−POWER OSCILLATOR** 

|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|fosc−slow|Oscillator frequency slow mode<br>LPOSC FAST = 0|No calibration|480|640|800|Hz|
|||Internal calibration vs. crystal<br>clock has been performed|630|640|650||
|fosc−fast|Oscillator frequency fast mode<br>LPOSC FAST = 1|No calibration|7.6|10.2|12.8|kHz|
|||Internal calibration vs. crystal<br>clock has been performed|9.8|10.2|10.8||



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**Table 8. RF FREQUENCY GENERATION SUBSYSTEM (SYNTHESIZER)** 

|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|fREF|Reference frequency|The reference frequency must be chosen<br>so that the RF carrier frequency is not an<br>integer multiple of the reference frequency|10|16|50|MHz|
|**Dividers**|||||||
|NDIVref|Reference divider ratio range|Controlled directly with register REFDIV|20||23||
|NDIVm|Main divider ratio range|Controlled indirectly with register FREQ|4.5||66.5||
|NDIVRF|RF divider range|Controlled directly with register RFDIV|1||2||
|**Charge Pump**|||||||
|ICP|Charge pump current|Programmable in increments of 8.5�A via<br>register PLLCPI|8.5||2168|�A|
|**Internal VCO (VCOSEL = 0)**|||||||
|fRF|RF frequency range|RFDIV = 1|400||525|MHz|
|||RFDIV = 0|800||1050||
|fstep|RF frequency step|RFDIV = 1, fxtal= 16.000000 MHz||0.98||Hz|
|BW|Synthesizer loop bandwidth|The synthesizer loop bandwidth and<br>start−up time can be programmed with<br>registers PLLLOOP and PLLCPI.<br>For recommendations see the AX5243<br>Programming Manual, the AX−RadioLab<br>software and AX5243 Application Notes<br>on compliance with regulatory regimes.|50||500|kHz|
|Tstart|Synthesizer start−up time if crystal<br>oscillator and reference are running||5||25|�s|
|PN868|Synthesizer phase noise 868 MHz<br>fREF= 48 MHz|10 kHz offset from carrier||−95||dBc/Hz|
|||1 MHz offset from carrier||−120|||
|PN433|Synthesizer phase noise 433 MHz<br>fREF= 48 MHz|10 kHz offset from carrier||−105||dBc/Hz|
|||1 MHz offset from carrier||−120|||
|**VCO with**|**external inductors (VCOSEL = 1, VCO2INT = 1)**||||||
|fRFrng_lo|RF frequency range<br>For choice of Lextvalues as well as<br>VCO gains see Figure 3 and<br>Figure 4|RFDIV = 1|27||262|MHz|
|fRFrng_hi||RFDIV = 0|54||525||
|PN169|Synthesizer phase noise 169 MHz<br>Lext=47 nH (wire wound 0603)<br>RFDIV = 0, fREF= 16 MHz<br>Note: phase noises can be<br>improved with higher fREF|10 kHz from carrier||−97||dBc/Hz|
|||1 MHz from carrier||−115|||
|**External VCO (VCOSEL = 1, VCO2INT = 0)**|||||||
|fRF|RF frequency range fully external<br>VCO|Note: The external VCO frequency needs<br>to be 2 x fRF|27||1000|MHz|
|Vamp|Differential input amplitude at L1, L2<br>terminals|||0.7||V|
|VinL|Input voltage levels at L1, L2<br>terminals||0||1.8|V|
|Vctrl|Control voltage range|Available at FILT in external loop filter<br>mode|0||1.8|V|



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**AX5243** 

**Figure 3. VCO with External Inductors: Typical Frequency vs. Lext** 

**Figure 4. VCO with External Inductors: Typical KVCO vs. Lext** 

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**AX5243** 

The following table shows the typical frequency ranges for frequency synthesis with external VCO inductor for different inductor values. 

**Table 9.** 

|**Table 9.**||
|---|---|
|**Lext [nH]**<br>**Freq [MHz]**<br>**RFDIV = 0**<br>**Freq [MHz]**<br>**RFDIV = 1**|**PLL Range**|
|8.2<br>482<br>241<br>8.2<br>437<br>219|0<br>15|
|10<br>432<br>216<br>10<br>390<br>195|0<br>15|
|12<br>415<br>208<br>12<br>377<br>189|0<br>15|
|15<br>380<br>190<br>15<br>345<br>173|0<br>15|
|18<br>345<br>173<br>18<br>313<br>157|0<br>15|
|22<br>308<br>154<br>22<br>280<br>140|0<br>14|
|27<br>285<br>143<br>27<br>258<br>129|0<br>15|



|33<br>260<br>130<br>33<br>235<br>118|0<br>15|
|---|---|
|39<br>245<br>123<br>39<br>223<br>112|0<br>14|
|47<br>212<br>106<br>47<br>194<br>97|0<br>14|
|56<br>201<br>101<br>56<br>182<br>91|0<br>15|
|68<br>178<br>89<br>68<br>161<br>81|0<br>15|
|82<br>160<br>80<br>82<br>146<br>73|1<br>14|
|100<br>149<br>75<br>100<br>136<br>68|1<br>14|
|120<br>136<br>68<br>120<br>124<br>62|0<br>14|



For tuning or changing of ranges a capacitor can be added in parallel to the inductor. 

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**AX5243** 

## **Table 10. TRANSMITTER** 

|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|SBR|Signal bit rate||0.1||125|kbps|
|PTX|Transmitter power @ 868 MHz|Differential PA, 50�single<br>ended measurement at an<br>SMA connector behind the<br>matching network, Note 2|−10||16|dBm|
||Transmitter power @ 433 MHz||−10||16||
||Transmitter power @ 169 MHz||−10||16||
|PTX868−step|Programming step size output power|Note 1|||0.5|dB|
|dTXtemp|Transmitter power variation vs.<br>temperature|−40°C to +85°C<br>Note 2||±0.5||dB|
|dTXVdd|Transmitter power variation vs. VDD_IO|1.8 to 3.6 V<br>Note 2||±0.5||dB|
|Padj|Adjacent channel power<br>GFSK BT = 0.5, 500 Hz deviation,<br>1.2 kbps, 25 kHz channel spacing,<br>10 kHz channel BW|868 MHz||−44||dBc|
|||433 MHz||−51|||
|PTX868−harm2|Emission @ 2ndharmonic|868 MHz, Note 2||−40||dBc|
|PTX868−harm3|Emission @ 3rdharmonic|||−60|||
|PTX433−harm2|Emission @ 2ndharmonic|433 MHz, Note 2||−40||dBc|
|PTX433−harm3|Emission @ 3rdharmonic|||−40|||



1. Pout �[TXPWRCOEFFB] 2[12] � 1 � Pmax 

2. 50 � single ended measurements at an SMA connector behind the matching network. For recommended matching networks see section: Application Information. 

## **Table 11. RECEIVER SENSITIVITIES** 

The table lists typical input sensitivities (without FEC) in dBm at the SMA connector with the complete matching network for BER=10[−3] at 433 or 868 MHz. 

|**Data rate**<br>**[kbps]**||**FSK**<br>**h = 0.66**|**FSK**<br>**h = 1**|**FSK**<br>**h = 2**|**FSK**<br>**h = 4**|**FSK**<br>**h = 5**|**FSK**<br>**h = 8**|**FSK**<br>**h = 16**|**PSK**|
|---|---|---|---|---|---|---|---|---|---|
|0.1|Sensitivity [dBm]|−135|−134.5|−132.5|−133|−133.5|−133|−132.5|−138|
||RX Bandwidth [kHz]|0.2|0.2|0.3|0.5|0.6|0.9|2.1|0.2|
||Deviation [kHz]|0.033|0.05|0.1|0.2|0.25|0.4|0.8||
|1|Sensitivity [dBm]|−126|−125|−123|−123.5|−124|−123.5|−122.5|−130|
||RX Bandwidth [kHz]|1.5|2|3|6|7|11|21|1|
||Deviation [kHz]|0.33|0.5|1|2|2.5|4|8||
|10|Sensitivity [dBm]|−117|−116|−113|−114|−113.5|−113||−120|
||RX Bandwidth [kHz]|15|20|30|50|60|110||10|
||Deviation [kHz]|3.3|5|10|20|25|40|||
|100|Sensitivity [dBm]|−107|−105.5||||||−109|
||RX Bandwidth [kHz]|150|200||||||100|
||Deviation [kHz]|33|50|||||||
|125|Sensitivity [dBm]|−105|−104||||||−108|
||RX Bandwidth [kHz]|187.5|200||||||125|
||Deviation [kHz]|42.3|62.5|||||||



1. Sensitivities are equivalent for 1010 data streams and PN9 whitened data streams. 

2. RX bandwidths < 0.9 kHz cannot be achieved with an 48 MHz TCXO. A 16 MHz TCXO was used for all measurements at 0.1 kbps. 

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**AX5243** 

## **Table 12. RECEIVER** 

|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|SBR|Signal bit rate||0.1||125|kbps|
|ISBER868|Input sensitivity at BER = 10−3<br>for 868 MHz operation,<br>continuous data,<br>without FEC|FSK, h = 0.5, 100 kbps||−105||dBm|
|||FSK, h = 0.5, 10 kbps||−116|||
|||FSK, 500 Hz deviation, 1.2 kbps||−126|||
|||PSK, 100 kbps||−109|||
|||PSK, 10 kbps||−120|||
|||PSK, 1 kbps||−130|||
|ISBER868FEC|Input sensitivity at BER = 10−3,<br>for 868 MHz operation,<br>continuous data,<br>with FEC|FSK, h = 0.5, 50 kbps||−111||dBm|
|||FSK, h = 0.5, 5 kbps||−122|||
|||FSK, 0.1 kbps||−137|||
|ISPER868|Input sensitivity at PER = 1%,<br>for 868 MHz operation, 144 bit<br>packet data, without FEC|FSK, h = 0.5, 100 kbps||−103||dBm|
|||FSK, h = 0.5, 10 kbps||−115|||
|||FSK, 500 Hz deviation, 1.2 kbps||−125|||
|ISWOR868|Input sensitivity at PER = 1%<br>for 868 MHz operation, 144 bit<br>packet data, WOR−mode,<br>without FEC|FSK, h = 0.5, 100 kpbs||−102||dBm|
|IL|Maximum input level||||0|dBm|
|CP1dB|Input referred compression point|2 tones separated by 100 kHz||−35||dBm|
|RSSIR|RSSI control range|FSK, 500 Hz deviation, 1.2 kbps|−126||−46|dB|
|RSSIS1|RSSI step size|Before digital channel filter; calculated<br>from register AGCCOUNTER||0.625||dB|
|RSSIS2|RSSI step size|Behind digital channel filter; calculated<br>from registers AGCCOUNTER,<br>TRKAMPL||0.1||dB|
|RSSIS3|RSSI step size|Behind digital channel filter; reading<br>register RSSI||1||dB|
|SEL868|Adjacent channel suppression|25 kHz channels , Note  1||45||dB|
|||100 kHz channels, Note  1||47|||
|BLK868|Blocking at±10 MHz offset|FSK 4.8 kbps, Note 2||78||dB|
|RAFC|AFC pull−in range|The AFC pull−in range can be<br>programmed with the MAXRFOFFSET<br>registers.<br>The AFC response time can be<br>programmed with the FREQGAIND<br>register.|±15|||%|
|RDROFF|Bitrate offset pull−in range|The bitrate pull−in range can be<br>programmed with the MAXDROFFSET<br>registers.|±10|||%|



1. Interferer/Channel @ BER = 10[−3] , channel level is +3 dB above the typical sensitivity, the interfering signal is CW; channel signal is modulated with shaping 

2. Channel/Blocker @ BER = 10[−3] , channel level is +3 dB above the typical sensitivity, the blocker signal is CW; channel signal is modulated with shaping 

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**AX5243** 

**Table 13. RECEIVER AND TRANSMITTER SETTLING PHASES** 

|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|Txtal|XTAL settling time|Powermodes:<br>POWERDOWN to STANDBY<br>Note that Txtaldepends on the specific<br>crystal used.||0.5||ms|
|Tsynth|Synthesizer settling time|Powermodes:<br>STANDBY to SYNTHTX or SYNTHRX||40||�s|
|Ttx|TX settling time|Powermodes:<br>SYNTHTX to FULLTX<br>Ttxis the time used for power ramping, this<br>can be programmed to be 1 x tbit, 2 x tbit,<br>4 x tbitor 8 x tbit.<br>Notes 1, 2|0|1 x tbit|8 x tbit|�s|
|Trx_init|RX initialization time|||150||�s|
|Trx_rssi|RX RSSI acquisition time<br>(after Trx_init)|Powermodes:<br>SYNTHRX to FULLRX<br>Modulation (G)FSK<br>Notes 1, 2||80 +<br>3 x tbit||�s|
|Trx_preamble|RX signal acquisition time to<br>valid data RX at full<br>sensitivity/selectivity<br>(after Trx_init)|||9 x tbit|||



1. tbit  depends on the datarate, e.g. for 10 kbps tbit = 100 � s 

2. In wire mode there is a processing delay of typically 6 x tbit between antenna and DCLK/DATA pins 

**Table 14. OVERALL STATE TRANSITION TIMES** 

|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|Ttx_on|TX startup time|Powermodes:<br>STANDBY to FULLTX<br>Notes 1, 2|40|40 + 1 x tbit||�s|
|Trx_on|RX startup time|Powermodes:<br>STANDBY to FULLRX||190||�s|
|Trx_rssi|RX startup time to valid RSSI|Powermodes:<br>STANDBY to FULLRX<br>Modulation (G)FSK<br>Notes 1, 2||270 +<br>3 x tbit||�s|
|Trx_data|RX startup time to valid data at full<br>sensitivity/selectivity|||190 +<br>9 x tbit||�s|
|Trxtx|RX to TX switching|Powermodes:<br>FULLRX to FULLTX||62||�s|
|Ttxrx|TX to RX switching<br>(to preamble start)|Powermodes:<br>FULLTX to FULLRX||200|||
|Thop|Frequency hop|Switch between frequency<br>defined in  register FREQA and<br>FREQB||30||�s|



1. tbit  depends on the datarate, e.g. for 10 kbps tbit = 100 � s 

2. In wire mode there is a processing delay of typically 6 x tbit between antenna and DCLK/DATA pins 

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**AX5243** 

## **Table 15. SPI TIMING** 

|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|Tss|SEL falling edge to CLK rising edge||10|||ns|
|Tsh|CLK falling edge to SEL rising edge||10|||ns|
|Tssd|SEL falling edge to MISO driving||0||10|ns|
|Tssz|SEL rising edge to MISO high−Z||0||10|ns|
|Ts|MOSI setup time||10|||ns|
|Th|MOSI hold time||10|||ns|
|Tco|CLK falling edge to MISO output||||10|ns|
|Tck|CLK period|Note 1|50|||ns|
|Tcl|CLK low duration||40|||ns|
|Tch|CLK high duration||40|||ns|



1. For SPI access during power−down mode the period should be relaxed to 100 ns 

For a figure showing the SPI timing parameters see section: Serial Peripheral Interface (SPI). 

**Table 16. GENERAL PURPOSE ADC (GPADC)** 

|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|Res|Nominal ADC resolution|||10||bit|
|Fconv|Conversion rate||0.03||1|MS/s|
|DR|Dynamic range|||60||dB|
|INL|Integral nonlinearity|||±1||LSB|
|DNL|Differential nonlinearity|||±1||LSB|
|Zin|Input impedance|||50||k�|
|VDC−IN|Input DC level|||0.8||V|
|VIN−DIFF|Input signal range (differential)||−500||500|mV|
|VIN−SE|Input signal range (single−ended,<br>signal input at pin GPADC1,<br>pin GPADC2 open)||300||1300|mV|



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**15** 

**AX5243** 

## **CIRCUIT DESCRIPTION** 

The AX5243 is a true single chip ultra−low power narrow−band CMOS transceiver for use in licensed and unlicensed bands from 27 and 1050 MHz. The on−chip transceiver consists of a fully integrated RF front−end with modulator, and demodulator. Base band data processing is implemented in an advanced and flexible communication controller that enables user friendly communication via the SPI interface. 

AX5243 can be operated from a 1.8 V to 3.6 V power supply over a temperature range of −40°C to 85°C. It consumes 7 − 48 mA for transmitting at 868 MHz carrier frequency, 4 – 51 mA for transmitting at 169 MHz depending on the output power. In receive operation AX5243 consumes 9 − 11 mA at 868 MHz carrier frequency and 6.5 − 8.5 mA at 169 MHz. 

The AX5243 features make it an ideal interface for integration into various battery powered solutions such as ticketing or as transceiver for telemetric applications e.g. in sensors. As primary application, the transceiver is intended for UHF radio equipment in accordance with the European Telecommunication Standard Institute (ETSI) specification EN 300 220−1 and the US Federal Communications Commission (FCC) standard Title 47 CFR Part 15 as well as Part 90. AX5243 is compliant with respective narrow−band regulations. Additionally AX5243 is suited for systems targeting compliance with Wireless M−Bus standard EN 13757−4:2005. Wireless M−Bus frame support (S, T, R) is built−in. 

AX5243 supports any data rate from 0.1 kbps to 125 kbps for FSK, 4−FSK, GFSK, GMSK, MSK, ASK and PSK. To achieve optimum performance for specific data rates and modulation schemes several register settings to configure the AX5243 are necessary, for details see the AX−RadioLab Software which calculates the necessary register settings and the AX5243 Programming Manual. 

The AX5243 can be operated in two fundamentally different modes. 

Data is sent and received via the SPI port in frames. Pre− and post−ambles as well as checksums can be generated automatically. Interrupts control the data flow between a micro−controller and the AX5243. 

Both transmit and receive use frame mode. In both cases the AX5243 behaves as a SPI slave interface. Configuration of the AX5243 is always done via the SPI interface. 

The receiver and the transmitter support multi−channel operation for all data rates and modulation schemes. 

## **Voltage Regulators** 

The AX5243 uses an on−chip voltage regulator system to create stable supply voltages for the internal circuitry from the primary supply VDD_IO. The I/O level of the digital pins is VDD_IO. 

Pins VDD_ANA are supplied for external decoupling of the power supply used for the on−chip PA. 

The voltage regulator system must be set into the appropriate state before receive or transmit operations can be initiated. This is handled automatically when programming the device modes via the PWRMODE register. 

Register POWSTAT contains status bits that can be read to check if the regulated voltages are ready (bit SVIO) or if VDD_IO has dropped below the brown−out level of 1.3 V (bit SSUM). 

In power−down mode the core supply voltages for digital and analog functions are switched off to minimize leakage power. Most register contents are preserved but access to the FIFO is not possible and FIFO contents are lost. SPI access to registers is possible, but at lower speed. 

In deep−sleep mode all supply voltages are switched off. All digital and analog functions are disabled. All register contents are lost. To leave deep−sleep mode the pin SEL has to be pulled low. This will initiate startup and reset of the AX5243. Then the MISO line should be polled, as it will be held low during initialization and will rise to high at the end of the initialization, when the chip becomes ready for operation. 

## **Crystal Oscillator and TCXO Interface** 

The AX5243 is normally operated with an external TCXO, which is required by most narrow−band regulation with a tolerance of 0.5 ppm to 1.5 ppm depending on the regulation. The on−chip crystal oscillator allows the use of an inexpensive quartz crystal as the RF generation subsystem’s timing reference when possible from a regulatory point of view. 

A wide range of crystal frequencies can be handled by the crystal oscillator circuit. As the reference frequency impacts both the spectral performance of the transmitter as well as the current consumption of the receiver, the choice of reference frequency should be made according to the regulatory regime targeted by the application. For guidelines see the separate Application Notes for usage of AX5243 in compliance with various regulatory regimes. 

The crystal or TCXO reference frequency should be chosen so that the RF carrier frequency is not an integer multiple of the crystal or TCXO frequency. 

The oscillator circuit is enabled by programming the PWRMODE register. At power−up it is enabled. 

To adjust the circuit’s characteristics to the quartz crystal being used, without using additional external components, the tuning capacitance of the crystal oscillator can be programmed. The transconductance of the oscillator is automatically regulated, to allow for fastest start−up times together with lowest power operation during steady−state oscillation. 

The integrated programmable tuning capacitor bank makes it possible to connect the oscillator directly to pins CLK16N and CLK16P without the need for external 

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**AX5243** 

capacitors. It is programmed using bits XTALCAP[5:0] in register XTALCAP. 

To synchronize the receiver frequency to a carrier signal, the oscillator frequency could be tuned using the capacitor bank however, the recommended method to implement frequency synchronization is to make use of the high resolution RF frequency generation sub−system together with the Automatic Frequency Control, both are described further down. 

Alternatively a single ended reference (TXCO, CXO) may be used. For detailed TCXO network recommendations depending on TCXO output swing refer to the AX5243 Application Note: Use with a TCXO Reference Clock. 

## **Low Power Oscillator and Wake−on−Radio (WOR) Mode** 

The AX5243 features an internal lowest power fully integrated oscillator. In default mode the frequency of oscillation is 640 Hz ± 1.5%, in fast mode it is 10.2 kHz ± 1.5%. These accuracies are reached after the internal hardware has been used to calibrate the low power oscillator versus the RF reference clock. This procedure can be run in the background during transmit or receive operations. 

The low power oscillator makes a WOR mode with a power consumption of 500 nA possible. 

If Wake−on−Radio Mode is enabled, the receiver wakes up periodically at a user selectable interval, and checks for a radio signal on the selected channel. If no signal is detected, the receiver shuts down again. If a radio signal is detected, and a valid packet is received, the microcontroller is alerted by asserting an interrupt. 

The AX5243 can thus autonomously poll for radio signals, while the micro−controller can stay powered down, and only wakes up once a valid packet is received. This allows for very low average receiver power, at the expense of longer preambles at the transmitter. 

## **GPIO Pin** 

Pins SYSCLK, IRQ and TCXO_EN can be used as general purpose I/O pins by programming pin configuration registers PINFUNCSYSCLK, PINFUNCIRQ, PINFUNCPWRAMP. Pin input values can be read via register PINSTATE. Pull−ups are disabled if output data is programmed to the GPIO pin. 

**==> picture [240 x 246] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD_IO<br>enable weak pull−up<br>enable output<br>VDD_IO 65 k �<br>output data<br>input data<br>**----- End of picture text -----**<br>


**Figure 5. GPIO Pin** 

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**AX5243** 

## **SYSCLK Output** 

The SYSCLK pin outputs either the reference clock signal divided by a programmable power of two or the low power oscillator clock. Division ratios from 1 to 1024 are possible. For divider ratios > 1 the duty cycle is 50%. Bits SYSCLK[4:0] in the PINFUNCSYSCLK register set the divider ratio. The SYSCLK output can be disabled. 

After power−up SYSCLK outputs 1/16 of the crystal oscillator clock, making it possible to use this clock to boot a micro−controller. 

## **Power−on−Reset (POR)** 

AX5243 has an integrated power−on−reset block. No external POR circuit is required. 

After POR the AX5243 can be reset by first setting the SPI SEL pin to high for at least 100 ns, then setting followed by resetting the bit RST in the PWRMODE register. 

After POR or reset all registers are set to their default values. 

## **RF Frequency Generation Subsystem** 

The RF frequency generation subsystem consists of a fully integrated synthesizer, which multiplies the reference frequency from the crystal oscillator to get the desired RF frequency. The advanced architecture of the synthesizer enables frequency resolutions of 1 Hz, as well as fast settling times of 5 – 50 �s depending on the settings (see section AC Characteristics). Fast settling times mean fast start−up and fast RX/TX switching, which enables low−power system design. 

For receive operation the RF frequency is fed to the mixer, for transmit operation to the power−amplifier. 

The frequency must be programmed to the desired carrier frequency. 

The synthesizer loop bandwidth can be programmed, this serves three purposes: 

1. Start−up time optimization, start−up is faster for higher synthesizer loop bandwidths 

2. TX spectrum optimization, phase−noise at 300 kHz to 1 MHz distance from the carrier improves with lower synthesizer loop bandwidths 

3. Adaptation of the bandwidth to the data−rate. For transmission of FSK and MSK it is required that the synthesizer bandwidth must be in the order of the data−rate. 

## _VCO_ 

An on−chip VCO converts the control voltage generated by the charge pump and loop filter into an output frequency. This frequency is used for transmit as well as for receive operation. The frequency can be programmed in 1 Hz steps in the FREQ registers. For operation in the 433 MHz band, the RFDIV bit in the PLLVCODIV register must be programmed. 

The fully integrated VCO allows to operate the device in the frequency ranges 800 – 1050 MHz and 400 – 525 MHz. 

The carrier frequency range can be extended to 54 – 525 MHz and 27 – 262 MHz by using an appropriate external inductor between device pins L1 and L2. The bit VCO2INT in the PLLVCODIV register must be set high to enter this mode. 

It is also possible to use a fully external VCO by setting bits VCO2INT = 0 and VCOSEL = 1 in the PLLVCODIV register. A differential input at a frequency of double the desired RF frequency must be input at device pins L1 and L2. The control voltage for the VCO can be output at device pin FILT when using external filter mode. The voltage range of this output pin is 0 – 1.8 V. 

This mode of operation is recommended for special applications where the phase noise requirements are not met when using the fully internal VCO or the internal VCO with external inductor. 

## _VCO Auto−Ranging_ 

The AX5243 has an integrated auto−ranging function, which allows to set the correct VCO range for specific frequency generation subsystem settings automatically. Typically it has to be executed after power−up. The function is initiated by setting the RNG_START bit in the PLLRANGINGA or PLLRANGINGB register. The bit is readable and a 0 indicates the end of the ranging process. Setting RNG_START in the PLLRANGINGA register ranges the frequency in FREQA, while setting RNG_START in the PLLRANGINGB register ranges the frequency in FREQB. The RNGERR bit indicates the correct execution of the auto−ranging. 

VCO auto−ranging works with the fully integrated VCO and with the internal VCO with external inductor. 

## _Loop Filter and Charge Pump_ 

The AX5243 internal loop filter configuration together with the charge pump current sets the synthesizer loop band width. The internal loop−filter has three configurations that can be programmed via the register bits FLT[1:0] in registers PLLLOOP or PLLLOOPBOOST the charge pump current can be programmed using register bits PLLCPI[7:0] in registers PLLCPI or PLLCPIBOOST. Synthesizer bandwidths are typically 50 – 500 kHz depending on the PLLLOOP or PLLLOOPBOOST settings, for details see the section: AC Characteristics. The AX5243 can be setup in such a way that when the synthesizer is started, the settings in the registers PLLLOOPBOOST and PLLCPIBOOST are applied first for a programmable duration before reverting to the settings in PLLLOOP and PLLCPI _**.**_ This feature enables automated fastest start−up. 

Setting bits FLT[1:0] = 00 bypasses the internal loop filter and the VCO control voltage is output to an external loop filter at pin FILT. This mode of operation is recommended for achieving lower bandwidths than with the internal loop filter and for usage with a fully external VCO. 

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**AX5243** 

**Table 17. REGISTERS** 

|**Table 17. REGISTERS**|||
|---|---|---|
|**Register**|**Bits**|**Purpose**|
|PLLLOOP<br>PLLLOOPBOOST|FLT[1:0]|Synthesizer loop filter bandwidth and selection of external loop filter, recommended usage is to<br>increase the bandwidth for faster settling time, bandwidth increases of factor 2 and 5 are<br>possible.|
|PLLCPI<br>PLLCPIBOOST||Synthesizer charge pump current, recommended usage is to decrease the bandwidth (and<br>improve the phase−noise) for low data−rate transmissions.|
|PLLVCODIV|REFDIV|Sets the synthesizer reference divider ratio|
||RFDIV|Sets the synthesizer output divider ratio|
||VCOSEL|Selects either the internal or the external VCO|
||VCO2INT|Selects either the internal VCO inductor or an external inductor between pins L1 and L2|
|FREQA, FREQB||Programming of the carrier frequency|
|PLLRANGINGA, PLLRANGINGB||Initiate VCO auto−ranging and check results|



## **RF Input and Output Stage (ANTP/ANTN)** 

The AX5243 antenna interface uses differential pins ANTP and ANTN for both RX and TX. RX/TX switching is handled internally. 

## _LNA_ 

The LNA amplifies the differential RF signal from the antenna and buffers it to drive the I/Q mixer. An external matching network is used to adapt the antenna impedance to the IC impedance. A DC feed to GND must be provided at the antenna pins. For recommendations see section: Application Information. 

## _PA_ 

In TX mode the PA drives the signal generated by the frequency generation subsystem out to either the differential antenna terminals or to the single ended antenna pin. The antenna terminals are chosen via the bits TXDIFF and TXSE in register MODECFGA. 

The output power of the PA is programmed via the register TXPWRCOEFFB. 

The PA can be digitally pre−distorted for high linearity. 

MODECFGA. PA ramping is programmable in increments of the bit time and can be set to 1 – 8 bit times via bits SLOWRAMP in register MODECFGA _**.**_ 

Output power as well as harmonic content will depend on the external impedance seen by the PA, recommendations are given in the section: Application Information. 

## **Digital IF Channel Filter and Demodulator** 

The digital IF channel filter and the demodulator extract the data bit−stream from the incoming IF signal. They must be programmed to match the modulation scheme as well as the data−rate. Inaccurate programming will lead to loss of sensitivity. 

The channel filter offers bandwidths of 995 Hz up to 221 kHz. 

The AX−RadioLab Software calculates the necessary register settings for optimal performance and details can be found in the AX5243 Programming Manual. An overview of the registers involved is given in the following Table 18 as reference. The register setups typically must be done once at power−up of the device. 

The output amplitude can be shaped (raised cosine), this mode is selected with bit AMPLSHAPE in register 

**Table 18. REGISTERS** 

|**Table 18. REGISTERS**||
|---|---|
|**Register**|**Remarks**|
|DECIMATION|This register programs the bandwidth of the digital channel filter.|
|RXDATARATE2…RXDATARATE0|These registers specify the receiver bit rate, relative to the channel filter bandwidth.|
|MAXDROFFSET2…MAXDROFFSET0|These registers specify the maximum possible data rate offset.|
|MAXRFOFFSET2…MAXRFOFFSET0|These registers specify the maximum possible RF frequency offset.|
|TIMEGAIN, DRGAIN|These registers specify the aggressiveness of the receiver bit timing recovery. More<br>aggressive settings allow the receiver to synchronize with shorter preambles, at the<br>expense of more timing jitter and thus a higher bit error rate at a given signal−to−noise<br>ratio.|
|MODULATION|This register selects the modulation to be used by the transmitter and the receiver,<br>i.e. whether ASK, FSK should be used.|
|PHASEGAIN, FREQGAINA, FREQGAINB,<br>FREQGAINC, FREQGAIND, AMPLGAIN|These registers control the bandwidth of the phase, frequency offset and amplitude<br>tracking loops.|



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**19** 

**AX5243** 

## **Table 18. REGISTERS** 

|**Table 18. REGISTERS**||
|---|---|
|**Register**|**Remarks**|
|AGCGAIN|This register controls the AGC (automatic gain control) loop slopes, and thus the<br>speed of gain adjustments. The faster the bit−rate, the faster the AGC loop should be.|
|TXRATE|These registers control the bit rate of the transmitter.|
|FSKDEV|These registers control the frequency deviation of the transmitter in FSK mode. The<br>receiver does not explicitly need to know the frequency deviation, only the channel<br>filter bandwidth has to be set wide enough for the complete modulation to pass.|



## **Encoder** 

The encoder is located between the Framing Unit, the Demodulator and the Modulator. It can optionally transform the bit−stream in the following ways: 

- It can invert the bit stream. 

- It can perform differential encoding. This means that a zero is transmitted as no change in the level, and a one is transmitted as a change in the level. 

- It can perform Manchester encoding. Manchester encoding ensures that the modulation has no DC content and enough transitions (changes from 0 to 1 and from 1 to 0) for the demodulator bit timing recovery to function correctly, but does so at a doubling of the data rate. 

- It can perform spectral shaping (also know as whitening). Spectral shaping removes DC content of the bit stream, ensures transitions for the demodulator bit timing recovery, and makes sure that the transmitted spectrum does not have discrete lines even if the transmitted data is cyclic. It does so without adding additional bits, i.e. without changing the data rate. Spectral Shaping uses a self synchronizing feedback shift register. 

The encoder is programmed using the register ENCODING, details and recommendations on usage are given in the AX5243 Programming Manual. 

## **Framing and FIFO** 

Most radio systems today group data into packets. The framing unit is responsible for converting these packets into a bit−stream suitable for the modulator, and to extract packets from the continuous bit−stream arriving from the demodulator. 

The Framing unit supports two different modes: 

- Packet modes 

- Raw modes 

The micro−controller communicates with the framing unit through a 256 byte FIFO. Data in the FIFO is organized 

in Chunks. The chunk header encodes the length and what data is contained in the payload. Chunks may contain packet data, but also RSSI, Frequency offset, Timestamps, etc. 

The AX5243 contains one FIFO. Its direction is switched depending on whether transmit or receive mode is selected. 

The FIFO can be operated in polled or interrupt driven modes. In polled mode, the microcontroller must periodically read the FIFO status register or the FIFO count register to determine whether the FIFO needs servicing. 

In interrupt mode EMPTY, NOT EMPTY, FULL, NOT FULL and programmable level interrupts are provided. The AX5243 signals interrupts by asserting (driving high) its IRQ line. The interrupt line is level triggered, active high. Interrupts are acknowledged by removing the cause for the interrupt, i.e. by emptying or filling the FIFO. 

Basic FIFO status (EMPTY, FULL, Overrun, Underrun, FIFO fill level above threshold, FIFO free space above threshold) are also provided during each SPI access on MISO while the micro− controller shifts out the register address on MOSI. See the SPI interface section for details. This feature significantly reduces the number of SPI accesses necessary during transmit and receive. 

## _Packet Modes_ 

The AX5243 offers different packet modes. For arbitrary packet sizes HDLC is recommended since the flag and bit−stuffing mechanism. The AX5243 also offers packet modes with fixed packet length with a byte indicating the length of the packet. 

In packet modes a CRC can be computed automatically. 

HDLC Mode is the main framing mode of the AX5243. In this mode, the AX5243 performs automatic packet delimiting, and optional packet correctness check by inserting and checking a cyclic redundancy check (CRC) field. 

NOTE: HDLC mode follows High−Level Data Link Control (HDLC, ISO 13239) protocol. 

The packet structure is given in the following table. 

**Table 19. HDLC PACKET STRUCTURE** 

|**Flag**|**Address**|**Control**|**Information**|**FCS**|**(Optional Flag)**|
|---|---|---|---|---|---|
|8 bit|8 bit|8 or 16 bit|Variable length, 0 or more bits in multiples of 8|16 / 32 bit|8 bit|



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**20** 

**AX5243** 

HDLC packets are delimited with flag sequences of content 0x7E. 

In AX5243 the meaning of address and control is user defined. The Frame Check Sequence (FCS) can be programmed to be CRC−CCITT, CRC−16 or CRC−32. 

The receiver checks the CRC, the result can be retrieved from the FIFO, the CRC is appended to the received data. 

In Wireless M−Bus Mode, the packet structure is given in the following table. 

NOTE: Wireless M−Bus mode follows EN13757−4 

**Table 20. WIRELESS M−BUS PACKET STRUCTURE** 

|**Preamble**|**L**|**C**|**M**|**A**|**FCS**|**Optional Data Block**<br>**(optionally repeated with FCS)**|**FCS**|
|---|---|---|---|---|---|---|---|
|variable|8 bit|8 bit|16 bit|48 bit|16 bit|8 − 96 bit|16 bit|



For details on implementing a HDLC communication as well as Wireless M−Bus please use the AX−RadioLab software and see the AX5243 Programming Manual. 

## _Raw Modes_ 

In Raw mode, the AX5243 does not perform any packet delimiting or byte synchronization. It simply serializes transmit bytes and de−serializes the received bit−stream and groups it into bytes. This mode is ideal for implementing legacy protocols in software. 

Raw mode with preamble match is similar to raw mode. In this mode, however, the receiver does not receive anything until it detects a user programmable bit pattern (called the preamble) in the receive bit−stream. When it detects the preamble, it aligns the de−serialization to it. 

The preamble can be between 4 and 32 bits long. 

## **RX AGC and RSSI** 

AX5243 features three receiver signal strength indicators (RSSI): 

1. RSSI before the digital IF channel filter. The gain of the receiver is adjusted in order to keep the analog IF filter output level inside the working range of the ADC and demodulator. The register AGCCOUNTER contains the current 

value of the AGC and can be used as an RSSI. The step size of this RSSI is 0.625 dB. The value can be used as soon as the RF frequency generation sub−system has been programmed. 

2. RSSI behind the digital IF channel filter. The register RSSI contains the current value of the RSSI behind the digital IF channel filter. The step size of this RSSI is 1 dB. 

3. RSSI behind the digital IF channel filter high accuracy. The demodulator also provides amplitude information in the TRK_AMPLITUDE register. By combining both the AGCCOUNTER and the TRK_AMPLITUDE registers, a high resolution (better than 0.1 dB) RSSI value can be computed at the expense of a few arithmetic operations on the micro−controller. The AX−RadioLab Software calculates the necessary register settings for best performance and details can be found in the AX5243 Programming Manual. 

## **Modulator** 

Depending on the transmitter settings the modulator generates various inputs for the PA: 

## **Table 21. MODULATIONS** 

|**Modulation**|**Bit = 0**|**Bit = 1**|**Main Lobe Bandwidth**|**Max. Bitrate**|
|---|---|---|---|---|
|ASK|PA off|PA on|BW = BITRATE|125 kBit/s|
|FSK/MSK/GFSK/GMSK|�f = −fdeviation|�f = +fdeviation|BW = (1 + h)⋅BITRATE|125 kBit/s|
|PSK|�� = 0°|�� = 180°|BW = BITRATE|125 kBit/s|



- h = modulation index. It is the ratio of the deviation compared to the bit−rate; fdeviation = 0.5⋅h⋅BITRATE, AX5243 can demodulate signals with h < 32. 

- ASK = amplitude shift keying FSK = frequency shift keying 

- MSK= minimum shift keying; MSK is a special case of FSK, where h = 0.5, and therefore fdeviation = 0.25⋅BITRATE; the advantage of MSK over FSK is that it can be demodulated more robustly. 

## PSK = phase shift keying 

All modulation schemes, except 4−FSK, are binary. Amplitude can be shaped using a raised cosine waveform. Amplitude shaping will also be performed for constant amplitude modulation ((G)FSK, (G)MSK) for ramping up and down the PA. Amplitude shaping should always be enabled. 

Frequency shaping can either be hard (FSK, MSK), or Gaussian (GMSK, GFSK), with selectable BT = 0.3 or BT = 0.5. 

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**21** 

**AX5243** 

**Table 22. 4−FSK MODULATION** 

|**Modulation**|**DiBit = 00**|**DiBit = 01**|**DiBit = 11**|**DiBit = 10**|**Main Lobe Bandwidth**|**Max. Bitrate**|
|---|---|---|---|---|---|---|
|4−FSK|�f = −3fdeviation|�f = −fdeviation|�f = +fdeviation|�f = +3fdeviation|BW = (1 + 3 h)⋅BITRATE|115.2 kBit/s|



## 4−FSK Frequency shaping is always hard. 

## **Automatic Frequency Control (AFC)** 

The AX5243 features an automatic frequency tracking loop which is capable of tracking the transmitter frequency within the RX filter band width. On top of that the AX5243 has a frequency tracking register TRKRFFREQ to synchronize the receiver frequency to a carrier signal. For AFC adjustment, the frequency offset can be computed with the following formula: 

**==> picture [101 x 18] intentionally omitted <==**

The pull−in range of the AFC can be programmed with the MAXRFOFFSET Registers. 

## **PWRMODE Register** 

The PWRMODE register controls, which parts of the chip are operating. 

**Table 23. PWRMODE REGISTER** 

|**PWRMODE Register**|**Name**|**Description**|
|---|---|---|
|0000|POWERDOWN|All digital and analog functions, except the register file, are disabled. The core supply<br>voltages are switched off to conserve leakage power. Register contents are preserved and<br>accessible registers via SPI, but at a slower speed.<br>Access to the FIFO is not possible and the contents are not preserved. POWERDOWN<br>mode is only entered once the FIFO is empty.|
|0001|DEEPSLEEP|AX5243 is fully turned off. All digital and analog functions are disabled. All register<br>contents are lost.<br>To leave DEEPSLEEP mode the pin SEL has to be pulled low. This will initiate startup and<br>reset of the AX5243. Then the MISO line should be polled, as it will be held low during<br>initialization and will rise to high at the end of the initialization, when the chip becomes<br>ready for operation.|
|0101|STANDBY|The crystal oscillator and the reference are powered on; receiver and transmitter are off.<br>Register contents are preserved and accessible registers via SPI.<br>Access to the FIFO is not possible and the contents are not preserved. STANDBY is only<br>entered once the FIFO is empty.|
|0110|FIFO|The reference is powered on. Register contents are preserved and accessible registers via<br>SPI.<br>Access to the FIFO is possible and the contents are preserved.|
|1000|SYNTHRX|The synthesizer is running on the receive frequency. Transmitter and receiver are still off.<br>This mode is used to let the synthesizer settle on the correct frequency for receive.|
|1001|FULLRX|Synthesizer and receiver are running.|
|1011|WOR|Receiver wakeup−on−radio mode.<br>The mode the same as POWERDOWN, but the 640 Hz internal low power oscillator is<br>running.|
|1100|SYNTHTX|The synthesizer is running on the transmit frequency. Transmitter and receiver are still off.<br>This mode is used to let the synthesizer settle on the correct frequency for transmit.|
|1101|FULLTX|Synthesizer and transmitter are running. Do not switch into this mode before the<br>synthesizer has completely settled on the transmit frequency (in SYNTHTX mode),<br>otherwise spurious spectral transmissions will occur.|



NOTE: For the corresponding currents see table in section DC Characteristics. 

**Table 24. A TYPICAL PWRMODE SEQUENCE FOR A TRANSMIT SESSION** 

|**Step**|**PWRMODE**|**Remarks**|
|---|---|---|
|1|POWERDOWN||
|2|STANDBY|The settling time is dominated by the crystal used, typical value 3ms.|
|3|FULLTX|Data transmission|
|4|POWERDOWN||



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**22** 

**AX5243** 

**Table 25. A TYPICAL PWRMODE SEQUENCE FOR A RECEIVE SESSION** 

|**Step**|**PWRMODE [3:0]**|**Remarks**|
|---|---|---|
|1|POWERDOWN||
|2|STANDBY|The settling time is dominated by the crystal used, typical value 3ms.|
|3|FULLRX|Data reception|
|4|POWERDOWN||



## **Serial Peripheral Interface** 

The AX5243 can be programmed via a four wire serial interface according SPI using the pins CLK, MOSI, MISO and SEL. Registers for setting up the AX5243 are programmed via the serial peripheral interface in all device modes. 

When the interface signal SEL is pulled low, a configuration data stream is expected on the input signal pin MOSI, which is interpreted as D0...Dx, A0...Ax, R_N/W. Data read from the interface appears on MISO. 

Figure 6 shows a write/read access to the interface. The data stream is built of an address byte including read/write information and a data byte. Depending on the R_N/W bit and address bits A[6..0], data D[7..0] can be written via MOSI or read at the pin MISO. R_N/W = 0 means read mode, R_N/W = 1 means write mode. 

registers are at the beginning of the address space, i.e. at addresses less than 0x70. These registers can be accessed more efficiently using the short address form, which is detailed in Figure 6. 

Some registers are longer than 8 bits. These registers can be accessed more quickly than by reading and writing individual 8 bit parts. This is illustrated in Figure 8. Accesses are not limited by 16 bits either, reading and writing data bytes can be continued as long as desired. After each byte, the address counter is incremented by one. Also, this access form works with long addresses. 

During the address phase of the access, the AX5243 outputs the most important status bits. This feature is designed to speed up the software decision on what to do in an interrupt handler. 

The status bits contain the following information: 

Most registers are 8 bits wide and accessed using the waveforms as detailed in Figure 7. The most important 

**Table 26. SPI STATUS BITS** 

|**SPI Bit Cell**|**Status**|**Meaning / Register Bit**|
|---|---|---|
|0|−|1 (when transitioning out of deep sleep mode, this bit transitions from 0→1 when the power<br>becomes ready)|
|1|S14|PLL LOCK|
|2|S13|FIFO OVER|
|3|S12|FIFO UNDER|
|4|S11|THRESHOLD FREE (FIFOFREE > FIFOTHRESH)|
|5|S10|THRESHOLD COUNT (FIFOCOUNT > FIFOTHRESH)|
|6|S9|FIFO FULL|
|7|S8|FIFO EMPTY|
|8|S7|PWRGOOD (not BROWNOUT)|
|9|S6|PWR INTERRUPT PENDING|
|10|S5|RADIO EVENT PENDING|
|11|S4|XTAL OSCILLATOR RUNNING|
|12|S3|WAKEUP INTERRUPT PENDING|
|13|S2|LPOSC INTERRUPT PENDING|
|14|S1|GPADC INTERRUPT PENDING|
|15|S0|internal|



NOTE: Bit cells 8−15 (S7 … S0) are only available in two address byte SPI access formats. 

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**23** 

**AX5243** 

_SPI Timing_ 

**==> picture [450 x 187] intentionally omitted <==**

**----- Start of picture text -----**<br>
Tss Tck TchTcl Ts Th Tsh<br>SEL<br>CLK<br>MOSI R/ W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0<br>MISO S14 S13 S12 S11 S10 S9 S8 D7 D6 D5 D4 D3 D2 D1 D0<br>Tssd Tco Tssz<br>Figure 6. SPI 8 Bit Read/Write Access with Timing<br>SEL<br>CLK<br>MOSI R/W A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0<br>MISO S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 D7 D6 D5 D4 D3 D2 D1 D0<br>**----- End of picture text -----**<br>


**Figure 7. SPI 8 Bit Long Address Read/Write Access** 

**==> picture [452 x 46] intentionally omitted <==**

**----- Start of picture text -----**<br>
SEL<br>CLK<br>MOSI R/W A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0<br>MISO S14 S13 S12 S11 S10 S9 S8 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0<br>**----- End of picture text -----**<br>


**Figure 8. SPI 16 Bit Long Read/Write Access** 

## **General Purpose ADC (GPADC)** 

The AX5243 features a general purpose ADC. The ADC input pins are GPADC1 and GPADC2. The ADC converts the voltage difference applied between pins GPADC1 and GPADC2. If pin GPADC2 is left open, the ADC converts the difference between an internally generated value of 800 mV and the voltage applied at pin GPADC1. 

The GPADC can only be used if the receiver is disabled. To enable the GPADC write 1 to the GPADC13 bit in the GPADCCTRL register. To start a single conversion, write 1 to the BUSY bit in the GPADCCTRL register. Then wait for the BUSY bit to clear, or the GPADC Interrupt to be asserted. 

The GPADC Interrupt is cleared by reading the result register GPADC13VALUE. 

If continuous sampling is desired, set the CONT bit in register GPADCCTRL. The desired sampling rate can be specified in the GPADCPERIOD register. 

## **�� DAC** 

One digital pin − TCXO_EN − may be used as a �� Digital−to−Analog Converter. A simple RC lowpass filter is needed to smooth the output. The DAC may be used to output RSSI, many demodulator variables, or a constant value under software control. 

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**24** 

**AX5243** 

## **REGISTER BANK DESCRIPTION** 

This section describes the bits of the register bank as reference. The registers are grouped by functional block to facilitate programming. The AX−RadioLab software calculates the necessary register settings for best performance and details can be found in the AX5243 Programming Manual. 

An R in the retention column means that this register’s contents are not lost during power−down mode. 

No checks are made whether the programmed combination of bits makes sense! Bit 0 is always the LSB. 

NOTES: Whole registers or register bits marked as reserved should be kept at their default values. 

All addresses not documented here must not be accessed, neither in reading nor in writing. 

The retention column indicates if the register contents are preserved in power−down mode. 

**Table 27. CONTROL REGISTER MAP** 

|**Add**|**Name**|**Dir**|**Ret**|**Reset**||||**Bit**|**Bit**||||**Description**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||||||**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**||
|**Revis**|**ion & Interface Probing**|||||||||||||
|000|REVISION|R|R|01010001|SILICONREV(7:0)||||||||Silicon Revision|
|001|SCRATCH|RW|R|11000101|SCRATCH(7:0)||||||||Scratch Register|
|**Operating Mode**||||||||||||||
|002|PWRMODE|RW|R|011–0000|RST|XOEN|REFEN|WDS|PWRMODE(3:0)||||Power Mode|
|**Voltage Regulator**||||||||||||||
|003|POWSTAT|R|R|––––––––|SSUM|SREF|SVREF|SVANA|SVMODEM|SBEVANA|SBEVMOD<br>EM|SVIO|Power Management<br>Status|
|004|POWSTICKYST<br>AT|R|R|––––––––|SSSUM|SREF|SSVREF|SSVANA|SSVMODE<br>M|SSBEVANA|SSBEVMO<br>DEM|SSVIO|Power Management<br>Sticky Status|
|005|POWIRQMASK|RW|R|00000000|MPWR<br>GOOD|MSREF|MSVREF|MS VANA|MS<br>VMODEM|MSBE<br>VANA|MSBE<br>VMODEM|MSVIO|Power Management<br>Interrupt Mask|
|**Interrupt Control**||||||||||||||
|006|IRQMASK1|RW|R|––000000|–|–|IRQMASK(13:8)||||||IRQ Mask|
|007|IRQMASK0|RW|R|00000000|IRQMASK(7:0)||||||||IRQ Mask|
|008|RADIOEVENTM<br>ASK1|RW|R|–––––––0|–|–|–|–|–|–|–|RADIO<br>EVENT<br>MASK(8)|Radio Event Mask|
|009|RADIOEVENTM<br>ASK0|RW|R|00000000|RADIO EVENT MASK(7:0)||||||||Radio Event Mask|
|00A|IRQINVERSION<br>1|RW|R|––000000|–|–|IRQINVERSION(13:8)||||||IRQ Inversion|
|00B|IRQINVERSION<br>0|RW|R|00000000|IRQINVERSION(7:0)||||||||IRQ Inversion|
|00C|IRQREQUEST1|R|R|––––––––|–|–|IRQREQUEST(13:8)||||||IRQ Request|
|00D|IRQREQUEST0|R|R|––––––––|IRQREQUEST(7:0)||||||||IRQ Request|
|00E|RADIOEVENTR<br>EQ1|R||––––––––|–|–|–|–|–|–|–|RADIO<br>EVENT<br>REQ(8)|Radio Event Request|
|00F|RADIOEVENTR<br>EQ0|R||––––––––|RADIO EVENT REQ(7:0)||||||||Radio Event Request|
|**Modu**|**lation & Framing**|||||||||||||
|010|MODULATION|RW|R|–––01000|–|–|–|RX HALF<br>SPEED|MODULATION(3:0)||||Modulation|
|011|ENCODING|RW|R|–––00010|–|–|–|ENC<br>NOSYNC|ENC<br>MANCH|ENC<br>SCRAM|ENC DIFF|ENC INV|Encoder/Decoder<br>Settings|
|012|FRAMING|RW|R|–0000000|FRMRX|CRCMODE(2:0)|||FRMMODE(2:0)|||FABORT|Framing settings|
|014|CRCINIT3|RW|R|11111111|CRCINIT(31:24)||||||||CRC Initialisation Data|
|015|CRCINIT2|RW|R|11111111|CRCINIT(23:16)||||||||CRC Initialisation Data|
|016|CRCINIT1|RW|R|11111111|CRCINIT(15:8)||||||||CRC Initialisation Data|
|017|CRCINIT0|RW|R|11111111|CRCINIT(7:0)||||||||CRC Initialisation Data|
|**Forw**|**ard Error Correction**|||||||||||||
|018|FEC|RW|R|00000000|SHORT<br>MEM|RSTVI<br>TERBI|FEC NEG|FEC POS|FECINPSHIFT(2:0)|||FEC ENA|FEC (Viterbi)<br>Configuration|
|019|FECSYNC|RW|R|01100010|FECSYNC(7:0)||||||||Interleaver<br>Synchronisation<br>Threshold|
|01A|FECSTATUS|R|R|––––––––|FEC INV|MAXMETRIC(6:0)|||||||FEC Status|



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**25** 

**AX5243** 

## **Table 27. CONTROL REGISTER MAP** 

|**Add**|**Name**|**Dir**|**Ret**|**Reset**||||**Bit**|**Bit**||||**Description**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||||||**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**||
|**Statu**|**s**|||||||||||||
|01C|RADIOSTATE|R|–|––––0000|–|–|–|–|RADIOSTATE(3:0)||||Radio Controller State|
|01D|XTALSTATUS|R|R|––––––––|–|–|–|–|–|–|–|XTAL<br>RUN|Crystal Oscillator<br>Status|
|**Pin Configuration**||||||||||||||
|020|PINSTATE|R|R|––––––––|–|–|PS PWR<br>AMP|PS ANT<br>SEL|PS IRQ|PS DATA|PS DCLK|PS SYS<br>CLK|Pinstate|
|021|PINFUNCSYSC<br>LK|RW|R|0––01000|PU<br>SYSCLK|–|–|PFSYSCLK(4:0)|||||SYSCLK Pin Function|
|022|PINFUNCDCLK|RW|R|00–––100|PU DCLK|PI DCLK|–|–|–|PFDCLK(2:0)|||DCLK Pin Function|
|023|PINFUNCDATA|RW|R|10–––111|PU DATA|PI DATA|–|–|–|PFDATA(2:0)|||DATA Pin Function|
|024|PINFUNCIRQ|RW|R|00–––011|PU IRQ|PI IRQ|–|–|–|PFIRQ(2:0)|||IRQ Pin Function|
|026|PINFUNCTCXO<br>_EN|RW|R|00––0110|PU<br>TCXO_EN|PI<br>TCXO_EN|–|–|TCXO_EN (3:0)||||TCXO_EN Pin<br>Function|
|027|PWRAMP|RW|R|–––––––0|–|–|–|–|–|–|–|PWRAMP|PWRAMP Control|
|**FIFO**||||||||||||||
|028|FIFOSTAT|R|R|0–––––––|FIFO AUTO<br>COMMIT|–|FIFO FREE<br>THR|FIFO CNT<br>THR|FIFO OVER|FIFO<br>UNDER|FIFO FULL|FIFO<br>EMPTY|FIFO Control|
|||W|R||||FIFOCMD(5:0)|||||||
|029|FIFODATA|RW||––––––––|FIFODATA(7:0)||||||||FIFO Data|
|02A|FIFOCOUNT1|R|R|–––––––0|–|–|–|–|–|–|–|FIFO<br>COUNT(8<br>)|Number of Words<br>currently in FIFO|
|02B|FIFOCOUNT0|R|R|00000000|FIFOCOUNT(7:0)||||||||Number of Words<br>currently in FIFO|
|02C|FIFOFREE1|R|R|–––––––1|–|–|–|–|–|–|–|FIFO<br>FREE(8)|Number of Words that<br>can be written to FIFO|
|02D|FIFOFREE0|R|R|00000000|FIFOFREE(7:0)||||||||Number of Words that<br>can be written to FIFO|
|02E|FIFOTHRESH1|RW|R|–––––––0|–|–|–|–|–|–|–|FIFO<br>THRESH<br>(8)|FIFO Threshold|
|02F|FIFOTHRESH0|RW|R|00000000|FIFOTHRESH(7:0)||||||||FIFO Threshold|
|**Synthesizer**||||||||||||||
|030|PLLLOOP|RW|R|0–––1001|FREQB|–|–|–|DIRECT|FILT EN|FLT(1:0)||PLL Loop Filter<br>Settings|
|031|PLLCPI|RW|R|00001000|PLLCPI||||||||PLL Charge Pump<br>Current (Boosted)|
|032|PLLVCODIV|RW|R|–000–000|–|VCOI MAN|VCO2INT|VCOSEL|–|RFDIV|REFDIV(1:0)||PLL Divider Settings|
|033|PLLRANGINGA|RW|R|00001000|STICKY<br>LOCK|PLL LOCK|RNGERR|RNG<br>START|VCORA(3:0)||||PLL Autoranging|
|034|FREQA3|RW|R|00111001|FREQA(31:24)||||||||Synthesizer Frequency|
|035|FREQA2|RW|R|00110100|FREQA(23:16)||||||||Synthesizer Frequency|
|036|FREQA1|RW|R|11001100|FREQA(15:8)||||||||Synthesizer Frequency|
|037|FREQA0|RW|R|11001101|FREQA(7:0)||||||||Synthesizer Frequency|
|038|PLLLOOPBOOS<br>T|RW|R|0–––1011|FREQB|–|–|–|DIRECT|FILT EN|FLT(1:0)||PLL Loop Filter<br>Settings (Boosted)|
|039|PLLCPIBOOST|RW|R|11001000|PLLCPI||||||||PLL Charge Pump<br>Current|
|03B|PLLRANGINGB|RW|R|00001000|STICKY<br>LOCK|PLL LOCK|RNGERR|RNG<br>START|VCORB(3:0)||||PLL Autoranging|
|03C|FREQB3|RW|R|00111001|FREQB(31:24)||||||||Synthesizer Frequency|
|03D|FREQB2|RW|R|00110100|FREQB(23:16)||||||||Synthesizer Frequency|
|03E|FREQB1|RW|R|11001100|FREQB(15:8)||||||||Synthesizer Frequency|
|03F|FREQB0|RW|R|11001101|FREQB(7:0)||||||||Synthesizer Frequency|
|**Signal Strength**||||||||||||||
|040|RSSI|R|R|––––––––|RSSI(7:0)||||||||Received Signal<br>Strength Indicator|
|041|BGNDRSSI|RW|R|00000000|BGNDRSSI(7:0)||||||||Background RSSI|
|042|DIVERSITY|RW|R|––––––00|–|–|–|–|–|–|ANT SEL|DIV ENA|Antenna Diversity<br>Configuration|
|043|AGCCOUNTER|RW|R|––––––––|AGCCOUNTER(7:0)||||||||AGC Current Value|



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**26** 

**AX5243** 

## **Table 27. CONTROL REGISTER MAP** 

|**Add**|**Name**|**Dir**|**Ret**|**Reset**||||**Bit**|**Bit**||||**Description**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||||||**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**||
|**Rece**|**iver Tracking**|||||||||||||
|045|TRKDATARATE<br>2|R|R|––––––––|TRKDATARATE(23:16)||||||||Datarate Tracking|
|046|TRKDATARATE<br>1|R|R|––––––––|TRKDATARATE(15:8)||||||||Datarate Tracking|
|047|TRKDATARATE<br>0|R|R|––––––––|TRKDATARATE(7:0)||||||||Datarate Tracking|
|048|TRKAMPL1|R|R|––––––––|TRKAMPL(15:8)||||||||Amplitude Tracking|
|049|TRKAMPL0|R|R|––––––––|TRKAMPL(7:0)||||||||Amplitude Tracking|
|04A|TRKPHASE1|R|R|––––––––|–|–|–|–|TRKPHASE(11:8)||||Phase Tracking|
|04B|TRKPHASE0|R|R|––––––––|TRKPHASE(7:0)||||||||Phase Tracking|
|04D|TRKRFFREQ2|RW|R|––––––––|–|–|–|–|TRRFKFREQ(19:16)||||RF Frequency<br>Tracking|
|04E|TRKRFFREQ1|RW|R|––––––––|TRRFKFREQ(15:8)||||||||RF Frequency<br>Tracking|
|04F|TRKRFFREQ0|RW|R|––––––––|TRRFKFREQ(7:0)||||||||RF Frequency<br>Tracking|
|050|TRKFREQ1|RW|R|––––––––|TRKFREQ(15:8)||||||||Frequency Tracking|
|051|TRKFREQ0|RW|R|––––––––|TRKFREQ(7:0)||||||||Frequency Tracking|
|052|TRKFSKDEMO<br>D1|R|R|––––––––|–|–|TRKFSKDEMOD(13:8)||||||FSK Demodulator<br>Tracking|
|053|TRKFSKDEMO<br>D0|R|R|––––––––|TRKFSKDEMOD(7:0)||||||||FSK Demodulator<br>Tracking|
|054|TRKAFSKDEM<br>OD1|R|R|––––––––|TRKAFSKDEMOD(15:8)||||||||AFSK Demodulator<br>Tracking|
|055|TRKAFSKDEM<br>OD0|R|R|––––––––|TRKAFSKDEMOD(7:0)||||||||AFSK Demodulator<br>Tracking|
|**Time**|**r**|||||||||||||
|059|TIMER2|R|–|––––––––|TIMER(23:16)||||||||1 MHz Timer|
|05A|TIMER1|R|–|––––––––|TIMER(15:8)||||||||1 MHz Timer|
|05B|TIMER0|R|–|––––––––|TIMER(7:0)||||||||1 MHz Timer|
|**Wakeup Timer**||||||||||||||
|068|WAKEUPTIMER<br>1|R|R|––––––––|WAKEUPTIMER(15:8)||||||||Wakeup Timer|
|069|WAKEUPTIMER<br>0|R|R|––––––––|WAKEUPTIMER(7:0)||||||||Wakeup Timer|
|06A|WAKEUP1|RW|R|00000000|WAKEUP(15:8)||||||||Wakeup Time|
|06B|WAKEUP0|RW|R|00000000|WAKEUP(7:0)||||||||Wakeup Time|
|06C|WAKEUPFREQ<br>1|RW|R|00000000|WAKEUPFREQ(15:8)||||||||Wakeup Frequency|
|06D|WAKEUPFREQ<br>0|RW|R|00000000|WAKEUPFREQ(7:0)||||||||Wakeup Frequency|
|06E|WAKEUPXOEA<br>RLY|RW|R|00000000|WAKEUPXOEARLY||||||||Wakeup Crystal<br>Oscillator Early|
|**Physical Layer Parameters**<br>**Receiver Parameters**||||||||||||||
|100|IFFREQ1|RW|R|00010001|IFFREQ(15:8)||||||||2nd LO / IF Frequency|
|101|IFFREQ0|RW|R|00100111|IFFREQ(7:0)||||||||2nd LO / IF Frequency|
|102|DECIMATION|RW|R|–0001101|–|DECIMATION(6:0)|||||||Decimation Factor|
|103|RXDATARATE2|RW|R|00000000|RXDATARATE(23:16)||||||||Receiver Datarate|
|104|RXDATARATE1|RW|R|00111101|RXDATARATE(15:8)||||||||Receiver Datarate|
|105|RXDATARATE0|RW|R|10001010|RXDATARATE(7:0)||||||||Receiver Datarate|
|106|MAXDROFFSE<br>T2|RW|R|00000000|MAXDROFFSET(23:16)||||||||Maximum Receiver<br>Datarate Offset|
|107|MAXDROFFSE<br>T1|RW|R|00000000|MAXDROFFSET(15:8)||||||||Maximum Receiver<br>Datarate Offset|
|108|MAXDROFFSE<br>T0|RW|R|10011110|MAXDROFFSET(7:0)||||||||Maximum Receiver<br>Datarate Offset|
|109|MAXRFOFFSET<br>2|RW|R|0–––0000|FREQ<br>OFFS<br>CORR|–|–|–|MAXRFOFFSET(19:16)||||Maximum Receiver RF<br>Offset|
|10A|MAXRFOFFSET<br>1|RW|R|00010110|MAXRFOFFSET(15:8)||||||||Maximum Receiver RF<br>Offset|



**www.onsemi.com** 

**27** 

**AX5243** 

## **Table 27. CONTROL REGISTER MAP** 

|**Add**|**Name**|**Dir**|**Ret**|**Reset**|||||**Bit**|**Bit**|**Bit**|**Bit**|||**Description**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||||||**7**|**6**||**5**|**4**|**3**|**2**||**1**|**0**||
|10B|MAXRFOFFSET<br>0|RW|R|10000111|MAXRFOFFSET(7:0)||||||||||Maximum Receiver RF<br>Offset|
|10C|FSKDMAX1|RW|R|00000000|FSKDEVMAX(15:8)||||||||||Four FSK Rx Deviation|
|10D|FSKDMAX0|RW|R|10000000|FSKDEVMAX(7:0)||||||||||Four FSK Rx Deviation|
|10E|FSKDMIN1|RW|R|11111111|FSKDEVMIN(15:8)||||||||||Four FSK Rx Deviation|
|10F|FSKDMIN0|RW|R|10000000|FSKDEVMIN(7:0)||||||||||Four FSK Rx Deviation|
|110|AFSKSPACE1|RW|R|––––0000|–|–||–|–|AFSKSPACE(11:8)|||||AFSK Space (0)<br>Frequency|
|111|AFSKSPACE0|RW|R|01000000|AFSKSPACE(7:0)||||||||||AFSK Space (0)<br>Frequency|
|112|AFSKMARK1|RW|R|––––0000|–|–||–|–|AFSKMARK(11:8)|||||AFSK Mark (1)<br>Frequency|
|113|AFSKMARK0|RW|R|01110101|AFSKMARK(7:0)||||||||||AFSK Mark (1)<br>Frequency|
|114|AFSKCTRL|RW|R|–––00100|–|–||–|AFSKSHIFT0(4:0)||||||AFSK Control|
|115|AMPLFILTER|RW|R|––––0000|–|–||–|–|AMPLFILTER(3:0)|||||Amplitude Filter|
|116|FREQUENCYLE<br>AK|RW|R|––––0000|–|–||–|–|FREQUENCYLEAK[3:0]|||||Baseband Frequency<br>Recovery Loop<br>Leakiness|
|117|RXPARAMSETS|RW|R|00000000|RXPS3(1:0)|||RXPS2(1:0)||RXPS1(1:0)|||RXPS0(1:0)||Receiver Parameter<br>Set Indirection|
|118|RXPARAMCUR<br>SET|R|R|––––––––|–|–||–|RXSI(2)|RXSN(1:0)|||RXSI(1:0)||Receiver Parameter<br>Current Set|
|**Rece**|**iver Parameter Set 0**|||||||||||||||
|120|AGCGAIN0|RW|R|10110100|AGCDECAY0(3:0)|||||AGCATTACK0(3:0)|||||AGC Speed|
|121|AGCTARGET0|RW|R|01110110|AGCTARGET0(7:0)||||||||||AGC Target|
|122|AGCAHYST0|RW|R|–––––000|−|||||||AGCAHYST0(2:0)|||AGC Digital Threshold<br>Range|
|123|AGCMINMAX0|RW|R|–000–000|−||AGCMAXDA0(2:0)|||−||AGCMINDA0(2:0)|||AGC Digital Min/Max<br>Set Points|
|124|TIMEGAIN0|RW|R|11111000|TIMEGAIN0M|||||TIMEGAIN0E|||||Timing Gain|
|125|DRGAIN0|RW|R|11110010|DRGAIN0M|||||DRGAIN0E|||||Data Rate Gain|
|126|PHASEGAIN0|RW|R|11––0011|FILTERIDX0(1:0)|||–|–|PHASEGAIN0(3:0)|||||Filter Index, Phase<br>Gain|
|127|FREQGAINA0|RW|R|00001111|FREQ LIM0|FREQ<br>MODULO0||FREQ<br>HALFMOD0|FREQ<br>AMPL<br>GATE0|FREQGAINA0(3:0)|||||Frequency Gain A|
|128|FREQGAINB0|RW|R|00–11111|FREQ<br>FREEZE0|FREQ<br>AVG0||–|FREQGAINB0(4:0)||||||Frequency Gain B|
|129|FREQGAINC0|RW|R|–––01010|–|–||–|FREQGAINC0(4:0)||||||Frequency Gain C|
|12A|FREQGAIND0|RW|R|0––01010|RFFREQ<br>FREEZE0|–||–|FREQGAIND0(4:0)||||||Frequency Gain D|
|12B|AMPLGAIN0|RW|R|01––0110|AMPL AVG|AMPL AGC||–|–|AMPLGAIN0(3:0)|||||Amplitude Gain|
|12C|FREQDEV10|RW|R|––––0000|–|–||–|–|FREQDEV0(11:8)|||||Receiver Frequency<br>Deviation|
|12D|FREQDEV00|RW|R|00100000|FREQDEV0(7:0)||||||||||Receiver Frequency<br>Deviation|
|12E|FOURFSK0|RW|R|–––10110|–|–||–|DEV<br>UPDATE0|DEVDECAY0(3:0)|||||Four FSK Control|
|12F|BBOFFSRES0|RW|R|10001000|RESINTB0(3:0)|||||RESINTA0(3:0)|||||Baseband Offset<br>Compensation<br>Resistors|
|**Rece**|**iver Parameter Set 1**|||||||||||||||
|130|AGCGAIN1|RW|R|10110100|AGCDECAY1(3:0)|||||AGCATTACK1(3:0)|||||AGC Speed|
|131|AGCTARGET1|RW|R|01110110|AGCTARGET1(7:0)||||||||||AGC Target|
|132|AGCAHYST1|RW|R|–––––000|−|||||||AGCAHYST1(2:0)|||AGC Digital Threshold<br>Range|
|133|AGCMINMAX1|RW|R|–000–000|−||AGCMAXDA1(2:0)|||−||AGCMINDA1(2:0)|||AGC Digital Min/Max<br>Set Points|
|134|TIMEGAIN1|RW|R|11110110|TIMEGAIN1M|||||TIMEGAIN1E|||||Timing Gain|
|135|DRGAIN1|RW|R|11110001|DRGAIN1M|||||DRGAIN1E|||||Data Rate Gain|
|136|PHASEGAIN1|RW|R|11––0011|FILTERIDX1(1:0)|||–|–|PHASEGAIN1(3:0)|||||Filter Index, Phase<br>Gain|



**www.onsemi.com** 

**28** 

**AX5243** 

## **Table 27. CONTROL REGISTER MAP** 

|**Add**|**Name**|**Dir**|**Ret**|**Reset**||||||**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Description**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||||||**7**||**6**||**5**|**4**|**3**||**2**|**1**|**0**||
|137|FREQGAINA1|RW|R|00001111|FREQ LIM1||FREQ<br>MODULO1||FREQ<br>HALFMOD1|FREQ<br>AMPL<br>GATE1|FREQGAINA1(3:0)|||||Frequency Gain A|
|138|FREQGAINB1|RW|R|00–11111|FREQ<br>FREEZE1||FREQ<br>AVG1||–|FREQGAINB1(4:0)||||||Frequency Gain B|
|139|FREQGAINC1|RW|R|–––01011|–||–||–|FREQGAINC1(4:0)||||||Frequency Gain C|
|13A|FREQGAIND1|RW|R|0––01011|RFFREQ<br>FREEZE1||–||–|FREQGAIND1(4:0)||||||Frequency Gain D|
|13B|AMPLGAIN1|RW|R|01––0110|AMPL AVG1||AMPL1<br>AGC1||–|–|AMPLGAIN1(3:0)|||||Amplitude Gain|
|13C|FREQDEV11|RW|R|––––0000|–||–||–|–|FREQDEV1(11:8)|||||Receiver Frequency<br>Deviation|
|13D|FREQDEV01|RW|R|00100000|FREQDEV1(7:0)|||||||||||Receiver Frequency<br>Deviation|
|13E|FOURFSK1|RW|R|–––11000|–||–||–|DEV<br>UPDATE1|DEVDECAY1(3:0)|||||Four FSK Control|
|13F|BBOFFSRES1|RW|R|10001000|RESINTB1(3:0)||||||RESINTA1(3:0)|||||Baseband Offset<br>Compensation<br>Resistors|
|**Rece**|**iver Parameter Set 2**||||||||||||||||
|140|AGCGAIN2|RW|R|11111111|AGCDECAY2(3:0)||||||AGCATTACK2(3:0)|||||AGC Speed|
|141|AGCTARGET2|RW|R|01110110|AGCTARGET2(7:0)|||||||||||AGC Target|
|142|AGCAHYST2|RW|R|–––––000|−|||||||AGCAHYST2(2:0)||||AGC Digital Threshold<br>Range|
|143|AGCMINMAX2|RW|R|–000–000|−|AGCMAXDA2(2:0)|||||−|AGCMINDA2(2:0)||||AGC Digital Min/Max<br>Set Points|
|144|TIMEGAIN2|RW|R|11110101|TIMEGAIN2M||||||TIMEGAIN2E|||||Timing Gain|
|145|DRGAIN2|RW|R|11110000|DRGAIN2M||||||DRGAIN2E|||||Data Rate Gain|
|146|PHASEGAIN2|RW|R|11––0011|FILTERIDX2(1:0)||||–|–|PHASEGAIN2(3:0)|||||Filter Index, Phase<br>Gain|
|147|FREQGAINA2|RW|R|00001111|FREQ LIM2||FREQ<br>MODULO2||FREQ<br>HALFMOD2|FREQ<br>AMPL<br>GATE2|FREQGAINA2(3:0)|||||Frequency Gain A|
|148|FREQGAINB2|RW|R|00–11111|FREQ<br>FREEZE2||FREQ<br>AVG2||–|FREQGAINB2(4:0)||||||Frequency Gain B|
|149|FREQGAINC2|RW|R|–––01101|–||–||–|FREQGAINC2(4:0)||||||Frequency Gain C|
|14A|FREQGAIND2|RW|R|0––01101|RFFREQ<br>FREEZE2||–||–|FREQGAIND2(4:0)||||||Frequency Gain D|
|14B|AMPLGAIN2|RW|R|01––0110|AMPL AVG2||AMPL<br>AGC2||–|–|AMPLGAIN2(3:0)|||||Amplitude Gain|
|14C|FREQDEV12|RW|R|––––0000|–||–||–|–|FREQDEV2(11:8)|||||Receiver Frequency<br>Deviation|
|14D|FREQDEV02|RW|R|00100000|FREQDEV2(7:0)|||||||||||Receiver Frequency<br>Deviation|
|14E|FOURFSK2|RW|R|–––11010|–||–||–|DEV<br>UPDATE2|DEVDECAY2(3:0)|||||Four FSK Control|
|14F|BBOFFSRES2|RW|R|10001000|RESINTB2(3:0)||||||RESINTA2(3:0)|||||Baseband Offset<br>Compensation<br>Resistors|
|**Rece**|**iver Parameter Set 3**||||||||||||||||
|150|AGCGAIN3|RW|R|11111111|AGCDECAY3(3:0)||||||AGCATTACK3(3:0)|||||AGC Speed|
|151|AGCTARGET3|RW|R|01110110|AGCTARGET3(7:0)|||||||||||AGC Target|
|152|AGCAHYST3|RW|R|–––––000|−|||||||AGCAHYST3(2:0)||||AGC Digital Threshold<br>Range|
|153|AGCMINMAX3|RW|R|–000–000|−|||AGCMAXDA3(2:0)|||−|AGCMINDA3(2:0)||||AGC Digital Min/Max<br>Set Points|
|154|TIMEGAIN3|RW|R|11110101|TIMEGAIN3M||||||TIMEGAIN3E|||||Timing Gain|
|155|DRGAIN3|RW|R|11110000|DRGAIN3M||||||DRGAIN3E|||||Data Rate Gain|
|156|PHASEGAIN3|RW|R|11––0011|FILTERIDX3(1:0)||||–|–|PHASEGAIN3(3:0)|||||Filter Index, Phase<br>Gain|
|157|FREQGAINA3|RW|R|00001111|FREQ LIM3||FREQ<br>MODULO3||FREQ<br>HALFMOD3|FREQ<br>AMPL<br>GATE3|FREQGAINA3(3:0)|||||Frequency Gain A|
|158|FREQGAINB3|RW|R|00–11111|FREQ<br>FREEZE3||FREQ<br>AVG3||–|FREQGAINB3(4:0)||||||Frequency Gain B|
|159|FREQGAINC3|RW|R|–––01101|–||–||–|FREQGAINC3(4:0)||||||Frequency Gain C|



**www.onsemi.com** 

**29** 

**AX5243** 

## **Table 27. CONTROL REGISTER MAP** 

|**Add**|**Name**|**Dir**|**Ret**|**Reset**||||**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Description**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||||||**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**||
|15A|FREQGAIND3|RW|R|0––01101|RFFREQ<br>FREEZE3|–|–|FREQGAIND3(4:0)|||||Frequency Gain D|
|15B|AMPLGAIN3|RW|R|01––0110|AMPL AVG3|AMPL<br>AGC3|–|–|AMPLGAIN3(3:0)||||Amplitude Gain|
|15C|FREQDEV13|RW|R|––––0000|–|–|–|–|FREQDEV3(11:8)||||Receiver Frequency<br>Deviation|
|15D|FREQDEV03|RW|R|00100000|FREQDEV3(7:0)||||||||Receiver Frequency<br>Deviation|
|15E|FOURFSK3|RW|R|–––11010|–|–|–|DEV<br>UPDATE3|DEVDECAY3(3:0)||||Four FSK Control|
|15F|BBOFFSRES3|RW|R|10001000|RESINTB3(3:0)||||RESINTA3(3:0)||||Baseband Offset<br>Compensation<br>Resistors|
|**Trans**|**mitter Parameters**|||||||||||||
|160|MODCFGF|RW|R|––––––00|–|–|–|–|–|–|FREQ SHAPE||Modulator<br>Configuration F|
|161|FSKDEV2|RW|R|00000000|FSKDEV(23:16)||||||||FSK Frequency<br>Deviation|
|162|FSKDEV1|RW|R|00001010|FSKDEV(15:8)||||||||FSK Frequency<br>Deviation|
|163|FSKDEV0|RW|R|00111101|FSKDEV(7:0)||||||||FSK Frequency<br>Deviation|
|164|MODCFGA|RW|R|0000–101|BROWN<br>GATE|PTTLCK<br>GATE|SLOW RAMP||–|AMPL<br>SHAPE|TX SE|TX DIFF|Modulator<br>Configuration A|
|165|TXRATE2|RW|R|00000000|TXRATE(23:16)||||||||Transmitter Bitrate|
|166|TXRATE1|RW|R|00101000|TXRATE(15:8)||||||||Transmitter Bitrate|
|167|TXRATE0|RW|R|11110110|TXRATE(7:0)||||||||Transmitter Bitrate|
|168|TXPWRCOEFF<br>A1|RW|R|00000000|TXPWRCOEFFA(15:8)||||||||Transmitter<br>Predistortion<br>Coefficient A|
|169|TXPWRCOEFF<br>A0|RW|R|00000000|TXPWRCOEFFA(7:0)||||||||Transmitter<br>Predistortion<br>Coefficient A|
|16A|TXPWRCOEFF<br>B1|RW|R|00001111|TXPWRCOEFFB(15:8)||||||||Transmitter<br>Predistortion<br>Coefficient B|
|16B|TXPWRCOEFF<br>B0|RW|R|11111111|TXPWRCOEFFB(7:0)||||||||Transmitter<br>Predistortion<br>Coefficient B|
|16C|TXPWRCOEFF<br>C1|RW|R|00000000|TXPWRCOEFFC(15:8)||||||||Transmitter<br>Predistortion<br>Coefficient C|
|16D|TXPWRCOEFF<br>C0|RW|R|00000000|TXPWRCOEFFC(7:0)||||||||Transmitter<br>Predistortion<br>Coefficient C|
|16E|TXPWRCOEFF<br>D1|RW|R|00000000|TXPWRCOEFFD(15:8)||||||||Transmitter<br>Predistortion<br>Coefficient D|
|16F|TXPWRCOEFF<br>D0|RW|R|00000000|TXPWRCOEFFD(7:0)||||||||Transmitter<br>Predistortion<br>Coefficient D|
|170|TXPWRCOEFF<br>E1|RW|R|00000000|TXPWRCOEFFE(15:8)||||||||Transmitter<br>Predistortion<br>Coefficient E|
|171|TXPWRCOEFF<br>E0|RW|R|00000000|TXPWRCOEFFE(7:0)||||||||Transmitter<br>Predistortion<br>Coefficient E|
|**PLL**|**Parameters**|||||||||||||
|180|PLLVCOI|RW|R|0–010010|VCOIE|–|VCOI(5:0)||||||VCO Current|
|181|PLLVCOIR|RW|R|––––––––|–|–|VCOIR(5:0)||||||VCO Current<br>Readback|
|182|PLLLOCKDET|RW|R|–––––011|LOCKDETDL|YR|–|–|–|LOCK DET<br>DLYM|LOCKDETDLY||PLL Lock Detect Delay|
|183|PLLRNGCLK|RW|R|–––––011|–|–|–|–|–|PLLRNGCLK(2:0)|||PLL Ranging Clock|
|**Crystal Oscillator**||||||||||||||
|184|XTALCAP|RW|R|00000000|XTALCAP(7:0)||||||||Crystal Oscillator Load<br>Capacitance|



**www.onsemi.com** 

**30** 

**AX5243** 

## **Table 27. CONTROL REGISTER MAP** 

|**Add**|**Name**|**Dir**|**Ret**|**Reset**||||**Bit**|**Bit**||||**Description**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||||||**7**|**6**|**5**|**4**|**3**|**2**|**1**|**0**||
|**Base**|**band**|||||||||||||
|188|BBTUNE|RW|R|–––01001|–|–|–|BB TUNE<br>RUN|BBTUNE(3:0)||||Baseband Tuning|
|189|BBOFFSCAP|RW|R|–111–111|–|CAP INT B(2:0)|||–|CAP INT A(2:0)|||Baseband Offset<br>Compensation<br>Capacitors|
|**MAC**<br>**Pack**|**Layer Parameters**<br>**et Format**|||||||||||||
|200|PKTADDRCFG|RW|R|001–0000|MSB FIRST|CRC SKIP<br>FIRST|FEC SYNC<br>DIS|–|ADDR POS(3:0)||||Packet Address Config|
|201|PKTLENCFG|RW|R|00000000|LEN BITS(3:0||||LEN POS(3:0)||||Packet Length Config|
|202|PKTLENOFFSE<br>T|RW|R|00000000|LEN OFFSET(7:0)||||||||Packet Length Offset|
|203|PKTMAXLEN|RW|R|00000000|MAX LEN(7:0)||||||||Packet Maximum<br>Length|
|204|PKTADDR3|RW|R|00000000|ADDR(31:24)||||||||Packet Address 3|
|205|PKTADDR2|RW|R|00000000|ADDR(23:16)||||||||Packet Address 2|
|206|PKTADDR1|RW|R|00000000|ADDR(15:8)||||||||Packet Address 1|
|207|PKTADDR0|RW|R|00000000|ADDR(7:0)||||||||Packet Address 0|
|208|PKTADDRMAS<br>K3|RW|R|00000000|ADDRMASK(31:24)||||||||Packet Address Mask<br>1|
|209|PKTADDRMAS<br>K2|RW|R|00000000|ADDRMASK(23:16)||||||||Packet Address Mask<br>0|
|20A|PKTADDRMAS<br>K1|RW|R|00000000|ADDRMASK(15:8)||||||||Packet Address Mask<br>1|
|20B|PKTADDRMAS<br>K0|RW|R|00000000|ADDRMASK(7:0)||||||||Packet Address Mask<br>0|
|**Patte**|**rn Match**|||||||||||||
|210|MATCH0PAT3|RW|R|00000000|MATCH0PAT(31:24)||||||||Pattern Match Unit 0,<br>Pattern|
|211|MATCH0PAT2|RW|R|00000000|MATCH0PAT(23:16)||||||||Pattern Match Unit 0,<br>Pattern|
|212|MATCH0PAT1|RW|R|00000000|MATCH0PAT(15:8)||||||||Pattern Match Unit 0,<br>Pattern|
|213|MATCH0PAT0|RW|R|00000000|MATCH0PAT(7:0)||||||||Pattern Match Unit 0,<br>Pattern|
|214|MATCH0LEN|RW|R|0––00000|MATCH0<br>RAW|–|–|MATCH0LE|N||||Pattern Match Unit 0,<br>Pattern Length|
|215|MATCH0MIN|RW|R|–––00000|–|–|–|MATCH0MI|N||||Pattern Match Unit 0,<br>Minimum Match|
|216|MATCH0MAX|RW|R|–––11111|–|–|–|MATCH0MA|X||||Pattern Match Unit 0,<br>Maximum Match|
|218|MATCH1PAT1|RW|R|00000000|MATCH1PAT(15:8)||||||||Pattern Match Unit 1,<br>Pattern|
|219|MATCH1PAT0|RW|R|00000000|MATCH1PAT(7:0)||||||||Pattern Match Unit 1,<br>Pattern|
|21C|MATCH1LEN|RW|R|0–––0000|MATCH1<br>RAW|–|–|–|MATCH1LEN||||Pattern Match Unit 1,<br>Pattern Length|
|21D|MATCH1MIN|RW|R|––––0000|–|–|–|–|MATCH1MIN||||Pattern Match Unit 1,<br>Minimum Match|
|21E|MATCH1MAX|RW|R|––––1111|–|–|–|–|MATCH1MAX||||Pattern Match Unit 1,<br>Maximum Match|
|**Pack**|**et Controller**|||||||||||||
|220|TMGTXBOOST|RW|R|00110010|TMGTXBOO|STE||TMGTXBOO|STM||||Transmit PLL Boost<br>Time|
|221|TMGTXSETTLE|RW|R|00001010|TMGTXSETT|LEE||TMGTXSET|TLEM||||Transmit PLL (post<br>Boost) Settling Time|
|223|TMGRXBOOST|RW|R|00110010|TMGRXBOO|STE||TMGRXBOO|STM||||Receive PLL Boost<br>Time|
|224|TMGRXSETTLE|RW|R|00010100|TMGRXSETT|LEE||TMGRXSET|TLEM||||Receive PLL (post<br>Boost) Settling Time|
|225|TMGRXOFFSA<br>CQ|RW|R|01110011|TMGRXOFF|SACQE||TMGRXOFF|SACQM||||Receive Baseband DC<br>Offset Acquisition Time|
|226|TMGRXCOARS<br>EAGC|RW|R|00111001|TMGRXCOA|RSEAGCE||TMGRXCOA|RSEAGCM||||Receive Coarse AGC<br>Time|



**www.onsemi.com** 

**31** 

**AX5243** 

## **Table 27. CONTROL REGISTER MAP** 

|**Add**|**Name**|**Dir**|**Ret**|**Reset**|||||||**Bit**|**Bit**|**Bit**|||**Description**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||||||**7**||**6**||**5**||**4**|**3**|**2**|**1**|**0**||
|227|TMGRXAGC|RW|R|00000000|TMGRXAGC||E||||TMGRXAGC|M||||Receiver AGC Settling<br>Time|
|228|TMGRXRSSI|RW|R|00000000|TMGRXRSSI||E||||TMGRXRSS|IM||||Receiver RSSI Settling<br>Time|
|229|TMGRXPREAM<br>BLE1|RW|R|00000000|TMGRXPRE||AMBLE1E||||TMGRXPRE|AMBLE1M||||Receiver Preamble 1<br>Timeout|
|22A|TMGRXPREAM<br>BLE2|RW|R|00000000|TMGRXPRE||AMBLE2E||||TMGRXPRE|AMBLE2M||||Receiver Preamble 2<br>Timeout|
|22B|TMGRXPREAM<br>BLE3|RW|R|00000000|TMGRXPRE||AMBLE3E||||TMGRXPRE|AMBLE3M||||Receiver Preamble 3<br>Timeout|
|22C|RSSIREFEREN<br>CE|RW|R|00000000|RSSIREFER||ENCE|||||||||RSSI Offset|
|22D|RSSIABSTHR|RW|R|00000000|RSSIABSTH||R|||||||||RSSI Absolute<br>Threshold|
|22E|BGNDRSSIGAI<br>N|RW|R|––––0000|–||–||–||–|BGNDRSSIGAIN||||Background RSSI<br>Averaging Time<br>Constant|
|22F|BGNDRSSITHR|RW|R|––000000|–||–||BGNDRSS|IT|HR|||||Background RSSI<br>Relative Threshold|
|230|PKTCHUNKSIZ<br>E|RW|R|––––0000|–||–||–||–|PKTCHUNKSIZE(3:0)||||Packet Chunk Size|
|231|PKTMISCFLAG<br>S|RW|R|–––00000|–||–||–||WOR<br>MULTI<br>PKT|AGC SETTL<br>DET|BGND<br>RSSI|RXAGC<br>CLK|RXRSSI<br>CLK|Packet Controller<br>Miscellaneous Flags|
|232|PKTSTOREFLA<br>GS|RW|R|–0000000|–||ST ANT<br>RSSI||ST CRCB||ST RSSI|ST DR|ST<br>RFOFFS|ST FOFFS|ST<br>TIMER|Packet Controller Store<br>Flags|
|233|PKTACCEPTFL<br>AGS|RW|R|––000000|–||–||ACCPT<br>LRGP||ACCPT<br>SZF|ACCPT<br>ADDRF|ACCPT<br>CRCF|ACCPT<br>ABRT|ACCPT<br>RESIDUE|Packet Controller<br>Accept Flags|
|**Special Functions**<br>**General Purpose ADC**|||||||||||||||||
|300|GPADCCTRL|RW|R|––000000|BUSY||–||0||0|0|GPADC13|CONT|CH ISOL|General Purpose ADC<br>Control|
|301|GPADCPERIOD|RW|R|00111111|GPADCPERIOD(7:0)|||||||||||GPADC Sampling<br>Period|
|308|GPADC13VALU<br>E1|R||––––––––|–||–||–||–|–|–|GPADC13VALUE(9:8)||GPADC13 Value|
|309|GPADC13VALU<br>E0|R||––––––––|GPADC13VALUE(7:0)|||||||||||GPADC13 Value|
|**Low**|**Power Oscillator Calibration**||||||||||||||||
|310|LPOSCCONFIG|RW||00000000|LPOSC<br>OSC<br>INVERT||LPOS<br>OSC<br>DOUB|C<br>LE|LPOSC<br>CALIBR||LPOSC<br>CALIBF|LPOSC<br>IRQR|LPOSC<br>IRQF|LPOSC<br>FAST|LPOSC<br>ENA|Low Power Oscillator<br>Configuration|
|311|LPOSCSTATUS|R||––––––––|–||–||–||–|–|–|LPOSC<br>IRQ|LPOSC<br>EDGE|Low Power Oscillator<br>Status|
|312|LPOSCKFILT1|RW||00100000|LPOSCKFILT(15:8)|||||||||||Low Power Oscillator<br>Calibration Filter<br>Constant|
|313|LPOSCKFILT0|RW||11000100|LPOSCKFILT(7:0)|||||||||||Low Power Oscillator<br>Calibration Filter<br>Constant|
|314|LPOSCREF1|RW||01100001|LPOSCREF(15:8)|||||||||||Low Power Oscillator<br>Calibration Reference|
|315|LPOSCREF0|RW||10101000|LPOSCREF(7:0)|||||||||||Low Power Oscillator<br>Calibration Reference|
|316|LPOSCFREQ1|RW||00000000|LPOSCFREQ(9:2)|||||||||||Low Power Oscillator<br>Calibration Frequency|
|317|LPOSCFREQ0|RW||0000––––|LPOSCFREQ(1:−2)|||||||–|–|–|–|Low Power Oscillator<br>Calibration Frequency|
|318|LPOSCPER1|RW||––––––––|LPOSCPER(15:8)|||||||||||Low Power Oscillator<br>Calibration Period|
|319|LPOSCPER0|RW||––––––––|LPOSCPER(7:0)|||||||||||Low Power Oscillator<br>Calibration Period|
|**DAC**|||||||||||||||||
|330|DACVALUE1|RW|R|––––0000|–|–||–||–||DACVALUE(11:8)||||DAC Value|
|331|DACVALUE2|RW|R|00000000|DACVALUE(7:0)|||||||||||DAC Value|
|332|DACCONFIG|RW|R|00––0000|DAC<br>PW<br>M|DAC CLK X2||–||–||DACINPUT(3:0)||||DAC Configuration|



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**32** 

**AX5243** 

## **APPLICATION INFORMATION** 

## **Typical Application Diagrams** 

_Match to 50 � for Differential Antenna Pins (868 / 915 / 433 / 169 MHz RX / TX Operation)_ 

**==> picture [468 x 183] intentionally omitted <==**

**----- Start of picture text -----**<br>
LC1 CC1 CF<br>CM1<br>LB1<br>50  �  single−ended<br>equipment or antenna<br>LF<br>CT1 LT1<br>IC antenna<br>pins CT2 LT 2<br>CA CA<br>CB2<br>LC2 CC2 CM2 LB2 Optional filter stage<br>to suppress TX<br>harmonics<br>**----- End of picture text -----**<br>


**Figure 9. Structure of the Differential Antenna Interface for TX/RX Operation to 50 � Single−ended Equipment or Antenna** 

**Table 28. TYPICAL COMPONENT VALUES** 

|**Frequency Band**|**LC1,2**<br>**[nH]**|**CC1,2**<br>**[pF]**|**CT1,2**<br>**[pF]**|**LT1,2**<br>**[nH]**|**CM1**<br>**[pF]**|**CM2**<br>**[pF]**|**LB1,2**<br>**[nH]**|**CB2**<br>**[pF]**|**CF**<br>**[pF]**<br>**optional**|**LF**<br>**[nH]**<br>**optional**|**CA**<br>**[pF]**<br>**optional**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|868 / 915 MHz|18|nc|2.7|18|6.2|3.6|12|2.7|nc|0�|nc|
|433 MHz|100|nc|4.3|43|11|5.6|27|5.1|nc|0�|nc|
|470 MHz|100|nc|3.9|33|4.7|nc|22|4.7|nc|0�|nc|
|169 MHz|150|10|10|120|12|nc|68|12|6.8|30|27|



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**33** 

**AX5243** 

_Using a Dipole Antenna and the Internal TX/RX Switch_ 

**==> picture [318 x 349] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD_ANA<br>GND TCXO_EN<br>ANTP IRQ<br>ANTN AX5243<br>MOSI<br>MISO<br>VDD_ANA CLK<br>CLK16P CLK16N GPADC2 GPADC1 VDD_IO<br>FILT L2 L1 SYSCLK SEL<br>Microcontroller<br>**----- End of picture text -----**<br>


**Figure 10. Typical Application Diagram with Dipole Antenna and Internal TX/RX Switch** 

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**34** 

**AX5243** 

_Using a Single−ended Antenna and the Internal TX/RX Switch_ 

**==> picture [472 x 348] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD_ANA<br>GND TCXO_EN<br>ANTP IRQ<br>ANTN AX5243<br>50  �<br>MOSI<br>MISO<br>VDD_ANA CLK<br>CLK16P CLK16N GPADC2 GPADC1 VDD_IO<br>FILT L2 L1 SYSCLK SEL Microcontroller<br>**----- End of picture text -----**<br>


**Figure 11. Typical Application Diagram with Single−ended Antenna and Internal TX/RX Switch** 

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**35** 

**AX5243** 

_Using an External VCO Inductor_ 

**==> picture [318 x 349] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD_ANA<br>GND TCXO_EN<br>ANTP IRQ<br>ANTN AX5243<br>MOSI<br>MISO<br>VDD_ANA CLK<br>LVCO<br>CLK16P CLK16N GPADC2 GPADC1 VDD_IO<br>FILT L2 L1 SYSCLK SEL Microcontroller<br>**----- End of picture text -----**<br>


**Figure 12. Typical Application Diagram with External VCO Inductor** 

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**36** 

**AX5243** 

_Using an External VCO_ 

**==> picture [318 x 400] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD_ANA<br>GND TCXO_EN (GPIO)<br>ANTP IRQ<br>ANTN AX5243<br>MOSI<br>MISO<br>VDD_ANA CLK<br>VCO<br>CLK16P CLK16N GPADC2 GPADC1 VDD_IO<br>FILT L2 L1 SYSCLK SEL Microcontroller<br>VCTRL OUTP OUTN EN<br>**----- End of picture text -----**<br>


**Figure 13. Typical Application Diagram with External VCO** 

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**37** 

**AX5243** 

_Using a TCXO_ 

**==> picture [327 x 348] intentionally omitted <==**

**----- Start of picture text -----**<br>
EN_TCXO<br>C1_TCXO [1]<br>TCXO<br>C2_TCXO [1]<br>VDD_ANA<br>GND TCXO_EN<br>ANTP IRQ<br>ANTN AX5243<br>MOSI<br>MISO<br>VDD_ANA CLK<br>CLK16P CLK16N GPADC2 GPADC1 VDD_IO<br>FILT L2 L1 SYSCLK SEL<br>Microcontroller<br>**----- End of picture text -----**<br>


Note 1: For detailed TCXO network recommendations depending on TCXO output swing refer to the AX5243 Application Note: Use with a TCXO Reference Clock. 

**Figure 14. Typical Application Diagram with a TCXO** 

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**AX5243** 

## **QFN20 PACKAGE INFORMATION** 

# **QFN20 4x4, 0.5P** CASE 485EE ISSUE A 

**==> picture [447 x 356] intentionally omitted <==**

**----- Start of picture text -----**<br>
NOTES:<br>D A 1. DIMENSIONING AND TOLERANCING PER ASME<br>B EXPOSED Cu MOLD CMPD A3 2. Y14.5M, 1994.CONTROLLING DIMENSION: MILLIMETERS.<br>3. DIMENSION b APPLIES TO PLATED TERMINAL<br>ÇÇ ÉÉÉ<br>PIN ONE AND IS MEASURED BETWEEN 0.15 AND 0.30 MM<br>REFERENCE FROM THE TERMINAL TIP.<br>ÉÉÉ ÇÇÉÉ ÉÉÉÇÇÇ 4. COPLANARITY APPLIES TO THE EXPOSED PAD<br>ÉÉÉ E A1 AS WELL AS THE TERMINALS.<br>2X MILLIMETERS<br>0.10 C DETAIL BALTERNATE DIMA MIN 0.80 MAX 1.00<br>CONSTRUCTIONS<br>2X A1 0.00 0.05<br>0.10 C A3 0.20 REF<br>TOP VIEW b 0.25 0.35<br>L L D 4.00 BSC<br>D2 2.75 2.85<br>DETAIL B A3 A E 4.00 BSC<br>L1 E2 2.75 2.85<br>0.10 C e 0.50 BSC<br>DETAIL A L 0.25 0.35<br>ALTERNATE L1 0.00 0.15<br>0.08 C TERMINAL CONSTRUCTIONS<br>NOTE 4 SIDE VIEW A1 C SEATINGPLANE<br>SOLDERING FOOTPRINT*<br>DETAIL A D2 20X L 4.30 0.5020X<br>6<br>2.95<br>11<br>E2 1<br>1<br>20 20X b 2.95 4.30<br>e 0.10 C A B<br>BOTTOM VIEW 0.05 C NOTE 3 PKG<br>OUTLINE<br>20X<br>0.35<br>0.50<br>PITCH<br>DIMENSIONS: MILLIMETERS<br>**----- End of picture text -----**<br>


*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 

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**39** 

**AX5243** 

## **QFN20 Soldering Profile** 

**==> picture [429 x 255] intentionally omitted <==**

**----- Start of picture text -----**<br>
Preheat Reflow Cooling<br>TP tP<br>TL<br>tL<br>TsMAX<br>TsMIN<br>ts<br>25 ° C<br>T25 ° C to Peak<br>Time<br>Temperature<br>**----- End of picture text -----**<br>


**Figure 15. QFN40 Soldering Profile** 

**Table 29.** 

|**Table 29.**||
|---|---|
|**Profile Feature**|**Pb−Free Process**|
|Average Ramp−Up Rate|3°C/s max.|
|Preheat Preheat<br>Temperature Min<br>TsMIN<br>Temperature Max<br>TsMAX<br>Time (TsMINto TsMAX)<br>ts<br>Time 25°C to Peak Temperature<br>T25°C to Peak|150°C<br>200°C<br>60 – 180 sec<br>8 min max.|
|Reflow Phase<br>Liquidus Temperature<br>TL<br>Time over Liquidus Temperature<br>tL<br>Peak Temperature<br>tp<br>Time within 5°C of actual Peak Temperature<br>Tp|217°C<br>60 – 150 s<br>260°C<br>20 – 40 s|
|Cooling Phase<br>Ramp−down rate|6°C/s max.|



1. All temperatures refer to the top side of the package, measured on the the package body surface. 

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**40** 

**AX5243** 

## **QFN20 Recommended Pad Layout** 

1. PCB land and solder masking recommendations are shown in Figure 16. 

A = Clearance from PCB thermal pad to solder mask opening, 0.0635 mm minimum 

- B = Clearance from edge of PCB thermal pad to PCB land, 0.2 mm minimum 

- C = Clearance from PCB land edge to solder mask opening to be as tight as possible to ensure that some solder mask remains between PCB pads. 

- D = PCB land length = QFN solder pad length + 0.1 mm 

- E = PCB land width = QFN solder pad width + 0.1 mm 

## **Figure 16. PCB Land and Solder Mask Recommendations** 

2. Thermal vias should be used on the PCB thermal pad (middle ground pad) to improve thermal conductivity from the device to a copper ground plane area on the reverse side of the printed circuit board. The number of vias depends on the package thermal requirements, as determined by thermal simulation or actual testing. 

3. Increasing the number of vias through the printed circuit board will improve the thermal conductivity to the reverse side ground plane and external heat sink. In general, adding more metal through the PC board under the IC will improve operational heat transfer, but will require careful attention to uniform heating of the board during assembly. 

## **Assembly Process** 

_Stencil Design & Solder Paste Application_ 

1. Stainless steel stencils are recommended for solder paste application. 

      3. For the PCB thermal pad, solder paste should be printed on the PCB by designing a stencil with an array of smaller openings that sum to 50% of the QFN exposed pad area.  Solder paste should be applied through an array of squares (or circles) as shown in Figure 17. 

      4. The aperture opening for the signal pads should be between 50−80% of the QFN pad area as shown in Figure 18. 

      5. Optionally, for better solder paste release, the aperture walls should be trapezoidal and the corners rounded. 

      6. The fine pitch of the IC leads requires accurate alignment of the stencil and the printed circuit board. The stencil and printed circuit assembly should be aligned to within + 1 mil prior to application of the solder paste. 

      7. No−clean flux is recommended since flux from underneath the thermal pad will be difficult to clean if water−soluble flux is used. 

2. A stencil thickness of 0.125 – 0.150 mm 

   - (5 – 6 mils) is recommended for screening. 

**Figure 17. Solder Paste Application on Exposed Pad** 

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**41** 

**AX5243** 

Minimum 50% coverage 62% coverage Maximum 80% coverage 

## **Figure 18. Solder Paste Application on Pins** 

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**AX5243/D** 

**42**