AX-SFJK-1-01-TB05.

## AX-SFJK, AX-SFJK-API 

## Ultra-Low Power, AT Command / API Controlled, Sigfox Compliant Transceiver IC for Up-Link and Down-Link 

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## **OVERVIEW** 

## **Circuit Description** 

AX−SFJK and AX−SFJK−API are ultra−low power single chip solutions for a node on the Sigfox network with both up− and down−link functionality. The AX−SFJK chip is delivered fully ready for operation and contains all the necessary firmware to transmit and receive data from the Sigfox network in Japan (SIGFOX RCZ3a region). It connects to the customer product using a logic level RS232 UART. AT commands are used to send frames and configure radio parameters. 

The AX−SFJK−API variant is intended for customers wishing to write their own application software based on the AX−SF−LIB−1−GEVK library. 

## **Features** 

Functionality and Ecosystem 

- Sigfox up−link and down−link functionality controlled by AT commands or API 

- The AX−SFJK and AX−SFJK−API ICs are part of a whole development and product ecosystem available from ON Semiconductor for any Sigfox requirement. Other parts of the ecosystem include 

   - ♦ Ready to go development kit DVK−SFJK−[API]−1−GEVK including a 2 year Sigfox subscription 

   - ♦ Sigfox Ready[®] certified reference design for the AX−SFJK and AX−SFJK−API ICs 

## General Features 

- QFN40 5 mm x 7 mm package 

- Supply range 1.8 V * − 3.6 V 

- −40°C to 85°C 

- Temperature sensor 

- Supply voltage measurements 

- 8 GPIO pins 

   - ♦ 2 GPIO pins with selectable voltage measure functionality, differential (1 V or 10 V range) or single ended (1 V range) with 10 bit resolution 

   - ♦ 2 GPIO pins with selectable sigma delta DAC output functionality 

   - ♦ 2 GPIO pins with selectable output clock 

   - ♦ 3 GPIO pins selectable as SPI master interface 

   - ♦ RX/TX switching Control 

## Power Consumption 

- Ultra−low Power Consumption: 

   - ♦ Charge required to send a Sigfox OOB packet at 13 dBm output power: 0.28 C 

   - ♦ Deepsleep mode current: 100 nA 

   - ♦ Sleep mode current: 1.8 A 

   - ♦ Standby mode current: 0.5 mA 

   - ♦ Continuous radio RX−mode  at 922.2 MHz : 15 mA 

   - ♦ Continuous radio TX−mode at 923.2 MHz 45 mA  @ 13 dBm 

High Performance Narrow−band Sigfox RF Transceiver 

- Receiver 

   - ♦ Carrier frequency 922.2 MHz 

   - ♦ Data−rate 600 bps FSK 

   - ♦ Sensitivity 

      - −126 dBm @ 600 bps, 922.2 MHz, GFSK 

   - ♦ 0 dBm maximum input power 

- Transmitter 

   - ♦ Carrier frequency 923.2 MHz 

   - ♦ Data−rate 100 bps PSK 

   - ♦ High efficiency, high linearity integrated power amplifier 

   - ♦ Maximum output power 13 dBm 

*The device is operational from 1.8 V to 3.6 V. However, a supply voltage below 2.0 V is considered an extreme condition. Details see Table 4. 

## **Applications** 

Sigfox networks up−link and down−link. 

Publication Order Number: **AX−SFJK/D** 

**1** 

© Semiconductor Components Industries, LLC, 2017 **June, 2017 − Rev. 3** 

**AX−SFJK, AX−SFJK−API** 

## **BLOCK DIAGRAM** 

**==> picture [434 x 535] intentionally omitted <==**

**----- Start of picture text -----**<br>
AX−SFJK / AX−SFJK−API<br>CLKP TCXO CAL<br>RF synthesis<br>CLKN interface FILT<br>ANTP1 PA Transmit<br>Communication<br>controller<br>ANTP<br>LNA Receive<br>ANTN<br>UARTRX<br>UART<br>UARTTX<br>DAC<br>GPIO[9:4,1:0] GPIO<br>ADC CPU<br>RADIO_LED<br>dedicated<br>CPU_LED<br>status<br>TX_LED<br>outputs<br>RX_LED<br>TX_EN<br>RX_EN<br>Program<br>memory<br>(FLASH)<br>power mode control RAM<br>Sigfox identity (ID, PAC)<br>Sigfox compliant<br>application<br>GND VDD_IO VDD_ANA VTCXO RESET_N<br>**----- End of picture text -----**<br>


**Figure 1. Functional Block Diagram of the AX−SFJK / AX−SFJK−API** 

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**AX−SFJK, AX−SFJK−API** 

## **Table 1. PIN FUNCTION DESCRIPTIONS** 

|**Symbol**|**Pin(s)**|**Type**|**Description**|
|---|---|---|---|
|VDD_ANA|1|P|Analog power output, decouple to neighboring GND|
|GND|2|P|Ground, decouple to neighboring VDD_ANA|
|ANTP|3|A|Differential receive input|
|ANTN|4|A|Differential receive input|
|ANTP1|5|N|Single ended transmit output|
|GND|6|P|Ground, decouple to neighboring VDD_ANA|
|VDD_ANA|7|P|Analog power output, decouple to neighboring GND|
|GND|8|P|Ground|
|FILT|9|A|Synthesizer filter|
|L2|10|A|Must be connected to pin L1|
|L1|11|A|Must be connected to pin L2|
|NC|12|N|Do not connect|
|GPIO8|13|I/O/PU|General purpose IO|
|GPIO7|14|I/O/PU|General purpose IO, selectable SPI functionality (MISO)|
|GPIO6|15|I/O/PU|General purpose IO, selectable SPI functionality (MOSI)|
|GPIO5|16|I/O/PU|General purpose IO, selectable SPI functionality (SCK)|
|GPIO4|17|I/O/PU|General purpose IO, selectable��DAC functionality, selectable dock function-<br>ality|
|CPU_LED|18|O|CPU activity indicator|
|RADIO_LED|19|O|Radio activity indicator|
|VTCXO|20|O|TCXO power|
|GPIO9|21|I/O/PU|General purpose IO, wakeup from deep sleep|
|UARTTX|22|O|UART transmit|
|UARTRX|23|I/PU|UART receive|
|RX_LED|24|O|Receive activity indicator|
|TX_LED|25|O|Transmit activity indicator|
|NC|26|PD|Do not connect|
|RESET_N|27|I/PU|Optional reset pin. Internal pull−up resistor is permanently enabled, neverthe-<br>less it is recommended to connect this pin to VDD_IO if it is not used.|
|GND|28|P|Ground|
|VDD_IO|29|P|Unregulated power supply|
|GPIO0|30|I/O/A/PU|General purpose IO, selectable ADC functionality, selectable��DAC function-<br>ality, selectable clock functionality|
|GPIO1|31|I/O/A/PU|General purpose IO, selectable ADC functionality|
|TX_EN|32|O|Transmitter Enable (to frontend)|
|NC|33|N|Do not connect|
|NC|34|N|Do not connect|
|RX_EN|35|O|Receiver Enable (to frontend)|
|VDD_IO|36|P|Unregulated power supply|
|CAL|37|A|Connect to FILT as shown in the application diagram|
|NC|38|N|Do not connect|
|CLKN|39|A|TCXO interface|



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**AX−SFJK, AX−SFJK−API** 

## **Table 1. PIN FUNCTION DESCRIPTIONS** 

|**Symbol**|**Pin(s)**|**Type**|**Description**|
|---|---|---|---|
|CLKP|40|A|TCXO interface|
|GND|Center pad|P|Ground on center pad of QFN, must be connected|



A = analog input 

I = digital input signal 

O = digital output signal PU = pull−up I/O = digital input/output signal N = not to be connected 

P = power or ground PD = pull−down 

All digital inputs are Schmitt trigger inputs, digital input and output levels are LVCMOS/LVTTL compatible. Pins GPIO[3:0] must not be driven above VDD_IO, all other digital inputs are 5 V tolerant. All GPIO pins and UARTRX start up as input with pull−up. For explanations on how to use the GPIO pins, see chapter “AT Commands”. 

**Table 2.** 

|**Table 2.**||
|---|---|
|**Pin**|**Possible GPIO Modes**|
|GPIO0|0, 1, Z, U, A, T|
|GPIO1|0, 1, Z, U, A|
|GPIO4|0, 1, Z, U, T|
|GPIO5|0, 1, Z, U|
|GPIO6|0, 1, Z, U|
|GPIO7|0, 1, Z, U|
|GPIO8|0, 1, Z, U|
|GPIO9|0, 1, Z, U|



0 = pin drives 

1 = not to be connected 

Z = pin is high impedance input U = pin is input with pull−up A = pin is analog input 

T = pin is driven by clock or DAC 

## **Pinout Drawing** 

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40 39 38 37 36 35 34 33 32 31 30 29<br>VDD_ANA 1 28 GND<br>GND 2 27 RESET_N<br>ANTP 3 26 NC<br>ANTN 4 AX−SFJK / AX−SFJK−API 25 TXLED<br>ANTP1 5 24 RXLED<br>QFN40<br>GND 6 23 UARTRX<br>VDD_ANA 7 22 UARTTX<br>GND 8 21 GPIO9<br>9 10 11 12 13 14 15 16 17 18 19 20<br>CLKP CLKN NC CAL VDD_IO RX_EN NC NC TX_EN GPIO1 GPIO0 VDD_IO<br>FILT L2 L1 NC GPIO8 GPIO7 GPIO6 GPIO5 GPIO4 CPU_LED RADIO_LED VTCXO<br>**----- End of picture text -----**<br>


**Figure 2. Pinout Drawing (Top View)** 

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**AX−SFJK, AX−SFJK−API** 

## **SPECIFICATIONS** 

## **Table 3. ABSOLUTE MAXIMUM RATINGS** 

|**Symbol**|**Description**|**Condition**|**Min**|**Max**|**Units**|
|---|---|---|---|---|---|
|VDD_IO|Supply voltage||−0.5|5.5|V|
|IDD|Supply current|||200|mA|
|Ptot|Total power consumption|||800|mW|
|Pi|Absolute maximum input power at receiver input|ANTP and ANTN<br>pins in RX mode||10|dBm|
|II1|DC current into any pin except ANTP, ANTN, ANTP1||−10|10|mA|
|II2|DC current into pins ANTP, ANTN, ANTP1||−100|100|mA|
|IO|Output Current|||40|mA|
|Via|Input voltage ANTP, ANTN, ANTP1 pins||−0.5|5.5|V|
||Input voltage digital pins||−0.5|5.5|V|
|Ves|Electrostatic handling|HBM|−2000|2000|V|
|Tamb|Operating temperature||−40|85|°C|
|Tstg|Storage temperature||−65|150|°C|
|Tj|Junction Temperature|||150|°C|



Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 

1. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 

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**AX−SFJK, AX−SFJK−API** 

## **DC Characteristics** 

## **Table 4. SUPPLIES** 

Conditions for all current and charge values unless otherwise specified are for the hardware configuration described in the AX−SFJK Application Note: Sigfox Compliant Reference Design. 

|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|TAMB|Operational ambient temperature||−40|27|85|°C|
|VDDIO|I/O and voltage regulator supply<br>voltage||1.8*|3.3|3.6|V|
|VDDIO_R1|I/O voltage ramp for reset activation;<br>Note 1|Ramp starts at VDD_IO≤0.1 V|0.1|||V/ms|
|VDDIO_R2|I/O voltage ramp for reset activation;<br>Note 1|Ramp starts at 0.1 V < VDD_IO < 0.7 V|3.3|||V/ms|
|IDS|Deep sleep mode current; Note 3|AT$P=2||350||nA|
|ISLP|Sleep mode current; Note 3|AT$P=1||1.6||�A|
|ISTDBY|Standby mode current<br>Notes 2, 3|||0.5||mA|
|IRX_CONT|Current consumption continuous<br>RX; Note 3|AT$TM=3,255||10||mA|
|QSFX_OOB_24|Charge to send a Sigfox out of band<br>message, 13 dBm; Note 3|AT$S0||0.28||C|
|QSFX_BIT_24|Charge to send a bit, 13 dBm;<br>Note 3|AT$SB=0||0.21||C|
|QSFX_BITDL_24|Charge to send a bit with downlink<br>receive, 13 dBm; Note 3|AT$SB=0,1||0.56||C|
|QSFX_LFR_24|Charge to send the longest possible<br>Sigfox frame (12 byte) , 13 dBm;<br>Note 3|AT$SF=00112233445566778899aabb||0.34||C|
|QSFX_LFRDL_24|Charge to send the longest possible<br>Sigfox frame (12 byte) with downlink<br>receive, 13 dBm; Note 3|AT$SF=00112233445566778899aabb,1||0.67||C|
|ITXMOD24AVG|Modulated Transmitter Current;<br>Note 3|Pout=13 dBm; average||45||mA|



- *The device is operational from 1.8 V to 3.6 V. However, a supply voltage below 2.0 V is considered an extreme condition and operation can lead to reduced output power and increased spurious emission. 

1. If VDD_IO ramps cannot be guaranteed, an external reset circuit is recommended, see the AX8052 Application Note: Power On Reset 

2. Internal 20 MHz oscillator, voltage conditioning and supervisory circuit running. 

3. Includes Front End Module, TCXO. 

## **Battery Life Examples** 

Scenario: 

- 2 AAA Alkaline batteries in series 

- One OOB frame transmitter per day at Pout=13 dBm 

- Four maximum length frames with downlink receive per day at Pout=13 dBm 

- Device in Sleep 

- Neglecting battery self discharge 

|2 AAA alkaline capacity|1500 mAh * 3600 s/h|5400 C|
|---|---|---|
|Sleep charge per day|1.8�A * 86400 s|0.16 C/day|
|OOB frame transmission||0.34 C/day|
|Frame transmission with downlink|4 * 0.67 C/day|2.68 C/day|
|Total Charge consumption||3.18 C/day|
|Battery life||4.7 Years|



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**AX−SFJK, AX−SFJK−API** 

## **Table 5. LOGIC** 

|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|**Digital Inputs**|||||||
|VT+|Schmitt trigger low to high threshold point|VDD_IO = 3.3 V||1.55||V|
|VT−|Schmitt trigger high to low threshold point|||1.25||V|
|VIL|Input  voltage, low||||0.8|V|
|VIH|Input voltage, high||2.0|||V|
|VIPA|Input voltage range, GPIO[3:0]||−0.5||VDD_IO|V|
|VIPBC|Input voltage range, GPIO[9:4], UARTRX||−0.5||5.5|V|
|IL|Input leakage current||−10||10|�A|
|RPU|Programmable Pull−Up Resistance|||65||k�|
|**Digital Outputs**|||||||
|IOH|Output Current, high<br>Ports GPIO[9:0], UARTTX, TXLED, RXLED,<br>TXLED, CPULED|VOH= 2.4 V|8|||mA|
|IOL|Output Current, low<br>GPIO[9:0], UARTTX, TXLED, RXLED, TXLED,<br>CPULED|VOL= 0.4 V|8|||mA|
|IOZ|Tri−state output leakage current||−10||10|�A|



## **AC Characteristics** 

**Table 6. TCXO REFERENCE INPUT** 

|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|fTCXO|TCXO frequency|A passive network between the TCXO output<br>and the pins CLKP and CLKN is required.<br>For detailed TCXO network recommendations<br>depending on the TCXO output swing refer to<br>the AX5043 Application Note: Use with a<br>TCXO Reference Clock.<br>For TCXO recommendations see the AX−<br>SFJK Application Note: Sigfox Compliant Ref-<br>erence Design||48||MHz|



## **Table 7. TRANSMITTER** 

Conditions for transmitter specifications unless otherwise specified with the antenna network from AX−SFJK Application Note: Sigfox Compliant Reference Design and at 923.2 MHz. 

|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|SBR|Signal bit rate|||100||bps|
|PTX|Highest Transmitter output power|AT$CW=923200000,1||13||dBm|
|dTXtemp|Transmitter power variation vs. tempera-<br>ture|−40°C to +85°C||±0.5||dB|
|dTXVdd|Transmitter power variation vs. VDD_IO|1.8 to 3.6 V||||dB|
|PTXharm2|Emission @ 2ndharmonic|||−50||dBc|
|PTXharm3|Emission @ 3rdharmonic|||−67|||
|PTXharm4|Emission @ 4thharmonic|||−65|||



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**AX−SFJK, AX−SFJK−API** 

**==> picture [501 x 403] intentionally omitted <==**

**----- Start of picture text -----**<br>
* RBW 1 MHz Marker 3 [T1 ]<br>* VBW 3 MHz −65.24 dBm<br>Ref 0 dBm * Att 10 dB * SWT 10 s 3.692307692 GHz<br>0 Marker 1 [T1 ]<br>−50.37 dBm<br>1.846153846 GHz A<br>−10<br>Marker 2 [T1 ]<br>1 P K * −67.09 dBm<br>CLRWR<br>−20 2.769230769 GHz<br>−30<br>ARIB<br>−40<br>1<br>−50<br>3DB<br>−60<br>3<br>2<br>−70<br>−80<br>−90<br>−100<br>Center 3 GHz 400 MHz/ Span 4 GHz<br>**----- End of picture text -----**<br>


**Figure 3. Typical Spectrum with Harmonics at 13 dBm Output Power** 

## **Table 8. RECEIVER** 

Conditions for transmitter specifications unless otherwise specified with the antenna network from AX−SFJK Application Note: Sigfox Compliant Reference Design and at 922.2 MHz. 

|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|SBR|Signal bit rate|||600||bps|
|ISBER905||AT$SB=x,1, AT$SF=x,1,<br>AT$TM=3,x PER < 0.1||−126||dBm|
|BLK905|Blocking at±10 MHz<br>offset|Channel/Blocker @ PER = 0.1, wanted signal<br>level is +3 dB above the typical sensitivity, the<br>blocker signal is CW||78||dB|



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**AX−SFJK, AX−SFJK−API** 

## **Table 9. ADC / TEMPERATURE SENSOR** 

|**Symbol**|**Description**|**Condition**|**Min**|**Typ**|**Max**|**Units**|
|---|---|---|---|---|---|---|
|ADCRES|ADC resolution|||10||Bits|
|VADCREF|ADC reference voltage||0.95|1|1.05|V|
|ZADC00|Input capacitance||||2.5|pF|
|DNL|Differential nonlinearity|||±1||LSB|
|INL|Integral nonlinearity|||±1||LSB|
|OFF|Offset|||3||LSB|
|GAIN_ERR|Gain error|||0.8||%|
|**ADC in Differential Mode**|||||||
|VABS_DIFF|Absolute voltages & common mode voltage in<br>differential mode at each input||0||VDD_IO|V|
|VFS_DIFF01|Full swing input for differential signals|Gain x1|−500||500|mV|
|VFS_DIFF10||Gain x10|−50||50|mV|
|**ADC in Single Ended Mode**|||||||
|VMID_SE|Mid code input voltage in single ended mode|||0.5||V|
|VIN_SE00|Input voltage in single ended mode||0||VDD_IO|V|
|VFS_SE01|Full swing input for single ended signals|Gain x1|0||1|V|
|**Temperature**|**Sensor**||||||
|AT$RLNG|Temperature range|AT$T?|−40||85|°C|
|TERR_CAL|Temperature error|AT$T?|−2||2|°C|



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**AX−SFJK, AX−SFJK−API** 

## **COMMAND INTERFACE** 

## **General Information** 

The chapter “Command Interface” is a documentation of the AT−Command set for devices which do not have an API−interface. To see whether the device is capable of receiving AT−Commands, please refer to chapter “Part Numbers”. If the device has been shipped with the API−Interface, please refer to the SW manual and “apiexample” code delivered with AX−SF−LIB−1−GEVK for an introduction on how to setup a project and how to use the API−Interface. 

mode can be activated with **AT$P=2** . To wake−up from Deep Sleep mode, GPIO9 is pulled to GND. 

When using Deep Sleep mode, keep two things in mind: Everything is turned off, timers are not running at all and all settings will be lost (use **AT$WR** to save settings to flash before entering Deep Sleep mode). Out−of−band messages will therefore not be sent. The pins states are frozen in Deep Sleep mode. The user must ensure that this will not result in condition which would draw a lot of current. 

## **AT Commands** 

## **Serial Parameters: 9600, 8, N, 1** 

The AX−SFJK uses the UART (pins UARTTX, UARTRX) to communicate with a host and uses a bitrate of **9600 baud** , no parity, 8 data bits and one stop bit. 

## **Power Modes** 

**==> picture [203 x 124] intentionally omitted <==**

_Standby_ 

After Power−Up and after finishing a SIGFOX transmission, AX−SFJK enters Standby mode. In Standby mode, AX−SFJK listens on the UART for commands from the host. Also, OOB frames are transmitted whenever the OOB timer fires. To conserve power, the AX−SFJK can be put into Sleep or turned off (Deep Sleep) completely. 

## _Sleep_ 

The command **AT$P=1** is used to put the AX−SFJK into Sleep mode. In this mode, only the wakeup timer for out−of−band messages is still running. To wake the AX−SFJK up from Sleep mode toggle the serial UARTRX pin, e.g. by sending a break (break is an RS232 framing violation, i.e. at least 10 bit durations low). When an Out of Band (OOB) message is due, AX−SFJK automatically wakes up to transmit the message, and then returns to Sleep mode. 

## _Deep Sleep_ 

In Deep Sleep mode, the AX−Sigfox is completely turned off and only draws negligible leakage current. Deep Sleep 

## _Numerical Syntax_ 

hexdigit ::= [0−9A−Fa−f] hexnum ::= “0x” hexdigit+ decnum ::= “0” | [1−9] [0−9]* octnum ::= “0” [0−7]+ binnum ::= “0b” [01]+ bit ::= [01] optnum ::= “−1” frame ::= (hexdigit hexdigit)+ uint ::= hexnum | decnum | octnum | binnum uint_opt ::= uint | optnum 

## _Command Syntax_ 

A command starts with ‘AT’ (everything is case sensitive!), continues with the actual command followed by parameters (if any) and ends with any kind of whitespace (space, tab, newline etc.) 

If incorrect syntax is detected (“parsing error”) all input is ignored up until the next whitespace character. 

Also note that any number can be entered in any format (Hexadecimal, Decimal, Octal and binary) by adding the corresponding prefix (‘0x’, ‘0’, ‘0b’). The only exception is the ‘Send Frame’ command (AT$SF) which expects a list of hexadecimal digits without any prefix. 

## _Return Codes_ 

A successful command execution is indicated by sending ‘OK’. If a command returns a value (e.g. by querying a register) only the value is returned. 

## _Examples_ 

Bold text is sent to AX−SFJK. 

**AT$I=0** AXSEM AT Command Interface 

Here, we execute command ‘I’ to query some general information. 

## **AT$SF=aabb1234** 

OK 

This sends a Sigfox frame containing { 0x00 : 0x11 : 0x22 : 0x33 : 0x44 }, then waits for a downlink response telegram, which in this example contains { 0xAA : 0xBB : 0xCC : 0xDD }. 

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## **AX−SFJK, AX−SFJK−API** 

**AT$CB=0011223344,1** OK RX=AA BB CC DD 

This sends a Sigfox frame containing { 0xAA : 0xBB : 0x12 : 0x34 } without waiting for a response telegram. 

**AT$CB=0xAA,1** OK 

The ‘CB’ command sends out a continuous pattern of bits, in this case 0xAA = 0b10101010. 

**AT$P=1** 

## OK 

This transitions the device into sleep mode. Out−of−band transmissions will still be triggered. The UART is powered down. The device can be woken up by a low level on the UART signal, i.e. by sending break. 

**Table 10. COMMANDS** 

|**Table 10. COMMANDS**|||
|---|---|---|
|**Command**|**Name**|**Description**|
|AT|Dummy Command|Just returns ‘OK’ and does nothing else. Can be used to check<br>communication.|
|AT$SB=bit[,bit]|Send Bit|Send a bit status (0 or 1). Optional bit flag indicates if AX−SFJK<br>should receive a downlink frame.|
|AT$SF=frame[,bit]|Send Frame|Send payload data, 1 to 12 bytes. Optional bit flag indicates if<br>AX−SFJK should receive a downlink frame.|
|AT$SO|Manually send out of band<br>message|Send the out−of−band message.|
|AT$TR?|Get the transmit repeat|Returns the number of transmit repeats. Default: 2|
|AT$TR=?|Get transmit range|Returns the allowed range of transmit repeats.|
|AT$TR=uint|Get transmit repeat|Sets the transmit repeat.|
|ATSuint?|Get Register|Query a specific configuration register’s value. See chapter<br>“Registers” for a list of registers.|
|ATSuint=uint|Set Register|Change a configuration register.|
|ATSuint=?|Get Register Range|Returns the allowed range of transmit repeats.|
|AT$IF=uint|Set TX Frequency|Set the output carrier macro channel for Sigfox frames.|
|AT$IF?|Get TX Frequency|Get the currently chosen TX frequency.|
|AT$DR=uint|Set RX Frequency|Set the reception carrier macro channel for Sigfox frames.|
|AT$DR?|Get RX Frequency|Get the currently chosen RX frequency.|
|AT$CW=uint,bit[,uint_opt]|Continuous Wave|To run emission tests for Sigfox certification it is necessary to send a<br>continuous wave, i.e. just the base frequency without any modula-<br>tion. Parameters:<br>**Name**<br>**Range**<br>**Description**<br>Frequency<br>800000000−<br>Continuous wave frequency in Hz.<br>999999999, 0 Use 923200000 for Sigfox<br>Mode<br>0, 1<br>Enable or disable carrier wave.<br>Power<br>14<br>dBm of signal  |  Default: 14|
|AT$CB=uint_opt,bit|Test Mode: TX constant byte|For emission testing it is useful to send a specific bit pattern. The<br>first parameter specifies the byte to send. Use ‘−1’ for a<br>(pseudo−)random pattern. Parameters:<br>**Name**<br>**Range**<br>**Decsription**<br>Pattern<br>0−255, −1<br>Byte to send. Use ‘−1’ for a<br>(pseudo−)random pattern.<br>Mode<br>0, 1<br>Enable or disable pattern test mode.|
|AT$T?|Get Temperature|Measure internal temperature and return it in 1/10thof a degree<br>Celsius.|
|AT$V?|Get Voltages|Return current voltage and voltage measured during the last<br>transmission in mV.|



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## **Table 10. COMMANDS** 

|**Table 10. COMMANDS**|||
|---|---|---|
|**Command**|**Name**|**Description**|
|AT$I=uint|Information|Display various product information:<br>0: Software Name & Version<br>Example Response: AX−Sigfox 1.1 RCZ3<br>1: Contact Details<br>Example Response: support@axsem.com<br>2: Silicon revision lower byte<br>Example Response: 8F<br>3: Silicon revision upper byte<br>Example Response: 51<br>4: Major Firmware Version<br>Example Response: 1<br>5: Minor Firmware Version<br>Example Response: 1<br>7: Firmware Variant (Frequency Band etc. (EU/US))<br>Example Response: RCZ3<br>9: SIGFOX Library Version<br>Example Response: UDL1−1.8.9<br>10: Device ID<br>Example Response: 00012345<br>11:  PAC<br>Example Response: 0123456789ABCDEF|
|AT$P=uint|Set Power Mode|To conserve power, the AX−SFJK can be put to sleep manually.<br>Depending on power mode, you will be responsible for waking up the<br>AX−SFJK again!<br>0: software reset (settings will be reset to values in flash)<br>1: sleep (send a break to wake up)<br>2: deep sleep (toggle GPIO9 or RESET_N pin to wake up;<br>the AX−SFJK is not running and all settings will be reset!)|
|AT$WR|Save Config|Write all settings to flash (RX/TX frequencies, registers) so they<br>survive reset/deep sleep or loss of power.<br>Use AT$P=0 to reset the AX−SFJK and load settings from flash.|
|AT:Pn?|Get GPIO Pin|Return the setting of the GPIO Pin_n_;_n_can range from 0 to 9.<br>A character string is returned describing the mode of the pin,<br>followed by the actual value. If the pin is configured as analog pin,<br>then the voltage (range 0…1 V) is returned. The mode characters<br>have the following meaning:<br>**Mode**<br>**Description**<br>0<br>Pin drives low<br>1<br>Pin drives high<br>Z<br>Pin is high impedance input<br>U<br>Pin is input with pull−up<br>A<br>Pin is analog input (GPIO pin 0…3 only)<br>T<br>Pin is driven by clock or DAC (GPIO pin 0 and 4 only)<br>The default mode after exiting reset is U on all GPIO pins.|
|AT:Pn=?|Get GPIO Pin Range|Print a list of possible modes for a pin. The table below lists the<br>response.<br>**Pin**<br>**Modes**<br>P0<br>0, 1, Z, U, A, T<br>P1<br>0, 1, Z, U, A<br>P4<br>0, 1, Z, U, T<br>P5<br>0, 1, Z, U<br>P6<br>0, 1, Z, U<br>P7<br>0, 1, Z, U<br>P8<br>0, 1, Z, U<br>P9<br>0, 1, Z, U|
|AT:Pn=mode|Set GPIO Pin|Set the GPIO pin mode.<br>For a list of the modes see the command AT:Pn?|



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**AX−SFJK, AX−SFJK−API** 

## **Table 10. COMMANDS** 

|**Table 10. COMMANDS**|||
|---|---|---|
|**Command**|**Name**|**Description**|
|AT:ADC Pn[−Pn[(1V|10V)]]?|Get GPIO Pin Analog Voltage|Measure the voltage applied to a GPIO pin. The command also<br>allows measurement of the voltage difference across two GPIO pins.<br>In differential mode, the full scale range may also be specified as 1 V<br>or 10 V. Note however that the pin input voltages must not exceed<br>the range 0..VDD_IO. The command returns the result as fraction of<br>the full scale range (1 V if none is specified). The GPIO pins<br>referenced should be initialized to analog mode before issuing this<br>command.|
|AT:SPI[(A|B|C|D)]=bytes|SPI Transaction|This command clocks out_bytes_on the SPI port. The clock frequency is<br>312.5 kHz. The command returns the bytes read on MISO during out-<br>put. Optionally the clocking mode may be specified (default is A):<br>**Mode**<br>**Clock Inversion**<br>**Clock Phase**<br>A<br>normal<br>normal<br>B<br>normal<br>alternate<br>C<br>inverted<br>normal<br>D<br>inverted<br>alternate<br>Note that SEL, if needed, is not generated by this command,<br>and must instead be driven using standard GPIO commands<br>(AT:Pn=0|1).|
|AT:CLK=freq,reffreq|Set Clock Generator|Output a square wave on the pin(s) set to T mode. The frequency of<br>the square wave is (freq / 216)×reffreq. Possible values for reffreq<br>are 20000000, 10000000, 5000000, 2500000, 1250000, 625000,<br>312500, 156250. Possible values if freq are 0…65535.|
|AT:CLK=OFF|Turn off Clock Generator|Switch off the clock generator|
|AT:CLK?|Get Clock Generator|Return the settings of the clock generator. Two numbers are<br>returned, freq and reffreq.|
|AT:DAC=value|Set��DAC|Output a��DAC value on the pin(s) set to T mode. Parameter<br>value may be in the range −32768…32767. The average output<br>voltage is (1/2 + value / 217)×VDD.<br>An external low pass filter is needed to get smooth output voltages.<br>The modulation frequency is 20 MHz. A possible low pass filter<br>choice is a simple RC low pass filter with R = 10 k�and C = 1�F.|
|AT:DAC=OFF|Turn off��DAC|Switch off the DAC|
|AT:DAC?|Get��DAC|Return the DAC value|



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**AX−SFJK, AX−SFJK−API** 

## **Table 10. COMMANDS** 

|**Table 10. COMMANDS**|||
|---|---|---|
|**Command**|**Name**|**Description**|
|AT$TM=mode,config|Activates the Sigfox Testmode|Available test modes:<br>0. TX BPSK<br>Send only BPSK with Synchro Bit + Synchro frame +<br>PN sequence: No hopping centered on the TX_frequency.<br>Config bits 0 to 6 define the number of repetitions. Bit 7 of config<br>defines if a delay is applied of not in the loop<br>1. TX Protocol:<br>Tx mode with full protocol with Sigfox key: Send Sigfox protocol<br>frames with initiate downlink flag = True. Config defines the<br>number of repetitions.<br>2. RX Protocol:<br>This mode tests the complete downlink protocol in Downlink only.<br>Config defines the number of repetitions.<br>3. RX GFSK:<br>RX mode with known pattern with SB + SF + Pattern on<br>RX_frequency (internal comparison with received frame⇔known<br>pattern = AA AA B2 27 1F 20 41 84 32 68 C5 BA AE 79 E7 F6 DD<br>9B. Config defines the number of repetitions. Config defines the<br>number of repetitions.<br>4. RX Sensitivity:<br>Does uplink + downlink frame with Sigfox key and specific timings.<br>This test is specific to SIGFOX’s test equipments & softwares.<br>5. TX Synthesis:<br>Does one uplink frame on each Sigfox channel to measure<br>frequency synthesis step|
|AT$SE|Starts AT$TM=3,255 indefinitely|Convenience command for sensitivity tests|
|AT$SL[=frame]|Send local loop|Sends a local loop frame with optional payload of 1 to 12 bytes.<br>Default payload: 0x84, 0x32, 0x68, 0xC5, 0xBA, 0x53, 0xAE, 0x79,<br>0xE7, 0xF6, 0xDD, 0x9B.|
|AT$RL|Receive local loop|Starts listening for a local loop.|



## **Table 11. REGISTERS** 

|**Number**|**Name**|**Description**|**Default**|**Range**|**Units**|
|---|---|---|---|---|---|
|300|Out Of Band<br>Period|AX−SFJK sends periodic static<br>messages to indicate that they are<br>alive. Set to 0 to disable.|24|0−24|hours|
|400|LBT Mask|LBT configurations to be used.|<1><br><15000><br><0>,0|||
|410|Encryption Key<br>Configuration|Set to zero for normal operation. Set<br>to one for use with the SIGFOX<br>Network Emulator Kit (SNEK)|0|0−1|0: private key<br>1: public key|
|800|LBT RSSI Offset|Shifts the carrier sense threshold.<br>Positive values result in a lower<br>threshold.|0|−128−127|dB|



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**AX−SFJK, AX−SFJK−API** 

## **APPLICATION INFORMATION** 

## **Typical Application Diagrams** 

_Typical AX−SFJK / AX−SFJK−API Application Diagram_ 

**==> picture [67 x 53] intentionally omitted <==**

**Figure 4. Typical Application Diagram** 

For detailed application configuration and BOM see the AX−SFJK Application Note: Sigfox Compliant Reference Design. 

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**15** 

## **AX−SFJK, AX−SFJK−API** 

## **QFN40 PACKAGE INFORMATION** 

# **QFN40 7x5, 0.5P** CASE 485EG ISSUE A 

**==> picture [476 x 376] intentionally omitted <==**

**----- Start of picture text -----**<br>
NOTES:<br>D A B L L 1. DIMENSIONING AND TOLERANCING PER<br>ASME Y14.5M, 1994.<br>PIN ONE 2. CONTROLLING DIMENSIONS: MILLIMETERS.<br>REFERENCE ÉÉ L1 3. TERMINAL AND IS MEASURED BETWEENDIMENSION b APPLIES TO PLATED<br>0.25 AND 0.30mm FROM TERMINAL<br>ÉÉ DETAIL A 4. COPLANARITY APPLIES TO THE EXPOSED<br>E ALTERNATE TERMINAL PAD AS WELL AS THE TERMINALS.<br>CONSTRUCTIONS<br>MILLIMETERS<br>DIM MIN MAX<br>2X 0.15 C A 0.80 1.00<br>A1 0.00 0.05<br>EXPOSED Cu MOLD CMPD A3 0.20 REF<br>2X 0.15 C b 0.18 0.30<br>TOP VIEW ÉÉ D 7.00 BSC<br>D2 5.30 5.50<br>DETAIL B (A3) ÇÇ E 5.00 BSC<br>0.10 C A DETAIL BALTERNATE E2Le 0.303.300.50 BSC3.500.50<br>0.08 C A1 CONSTRUCTION L1 −−− 0.15<br>NOTE 4 SIDE VIEW C SEATINGPLANE<br>D2 RECOMMENDED<br> DETAIL A 40X L SOLDERING FOOTPRINT*<br>9<br>7.30<br>21<br>5.60 40X<br>E2 40X b PACKAGE 0.60<br>0.10 C A B OUTLINE 1<br>1 0.05 C NOTE 3<br>40 29<br>e 3.60 5.30<br>e/2<br>BOTTOM VIEW<br>0.50 40X<br>PITCH 0.32<br>DIMENSIONS: MILLIMETERS<br>*For additional information on our Pb−Free strategy and soldering<br>details, please download the ON Semiconductor Soldering and<br>Mounting Techniques Reference Manual, SOLDERRM/D.<br>**----- End of picture text -----**<br>


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**AX−SFJK, AX−SFJK−API** 

## **QFN40 Soldering Profile** 

**==> picture [429 x 255] intentionally omitted <==**

**----- Start of picture text -----**<br>
Preheat Reflow Cooling<br>TP tP<br>TL<br>tL<br>TsMAX<br>TsMIN<br>ts<br>25 ° C<br>T25 ° C to Peak<br>Time<br>Temperature<br>**----- End of picture text -----**<br>


**Figure 5. QFN40 Soldering Profile** 

**Table 12.** 

|**Table 12.**||
|---|---|
|**Profile Feature**|**Pb−Free Process**|
|Average Ramp−Up Rate|3°C/s max.|
|Preheat Preheat<br>Temperature Min<br>TsMIN<br>Temperature Max<br>TsMAX<br>Time (TsMINto TsMAX)<br>ts<br>Time 25°C to Peak Temperature<br>T25°C to Peak|150°C<br>200°C<br>60 – 180 sec<br>8 min max.|
|Reflow Phase<br>Liquidus Temperature<br>TL<br>Time over Liquidus Temperature<br>tL<br>Peak Temperature<br>tp<br>Time within 5°C of actual Peak Temperature<br>Tp|217°C<br>60 – 150 s<br>260°C<br>20 – 40 s|
|Cooling Phase<br>Ramp−down rate|6°C/s max.|



1. All temperatures refer to the top side of the package, measured on the the package body surface. 

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**AX−SFJK, AX−SFJK−API** 

## **QFN40 Recommended Pad Layout** 

1. PCB land and solder masking recommendations are shown in Figure 6. 

A = Clearance from PCB thermal pad to solder mask opening, 0.0635 mm minimum 

B = Clearance from edge of PCB thermal pad to PCB land, 0.2 mm minimum 

- C = Clearance from PCB land edge to solder mask opening to be as tight as possible to ensure that some solder mask remains between PCB pads. 

- D = PCB land length = QFN solder pad length + 0.1 mm 

- E = PCB land width = QFN solder pad width + 0.1 mm 

## **Figure 6. PCB Land and Solder Mask Recommendations** 

2. Thermal vias should be used on the PCB thermal pad (middle ground pad) to improve thermal conductivity from the device to a copper ground plane area on the reverse side of the printed circuit board. The number of vias depends on the package thermal requirements, as determined by thermal simulation or actual testing. 

3. Increasing the number of vias through the printed circuit board will improve the thermal conductivity to the reverse side ground plane and external heat sink. In general, adding more metal through the PC board under the IC will improve operational heat transfer, but will require careful attention to uniform heating of the board during assembly. 

## **Assembly Process** 

_Stencil Design & Solder Paste Application_ 

1. Stainless steel stencils are recommended for solder paste application. 

      3. For the PCB thermal pad, solder paste should be printed on the PCB by designing a stencil with an array of smaller openings that sum to 50% of the QFN exposed pad area.  Solder paste should be applied through an array of squares (or circles) as shown in Figure 7. 

      4. The aperture opening for the signal pads should be between 50−80% of the QFN pad area as shown in Figure 8. 

      5. Optionally, for better solder paste release, the aperture walls should be trapezoidal and the corners rounded. 

      6. The fine pitch of the IC leads requires accurate alignment of the stencil and the printed circuit board. The stencil and printed circuit assembly should be aligned to within + 1 mil prior to application of the solder paste. 

      7. No−clean flux is recommended since flux from underneath the thermal pad will be difficult to clean if water−soluble flux is used. 

2. A stencil thickness of 0.125 – 0.150 mm 

   - (5 – 6 mils) is recommended for screening. 

**Figure 7. Solder Paste Application on Exposed Pad** 

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**18** 

**AX−SFJK, AX−SFJK−API** 

Minimum 50% coverage 62% coverage Maximum 80% coverage 

## **Figure 8. Solder Paste Application on Pins** 

**Life Support Applications** This product is not designed for use in life support appliances, devices, or in systems where malfunction of this product can reasonably be expected to result in personal injury. ON Semiconductor customers using or selling this product for use in such applications do so at their own risk 

and agree to fully indemnify ON Semiconductor for any damages resulting from such improper use or sale. 

## **Device Information** 

The following device information can be queried using the AT−Commands AT$I=4, AT$I=5 for the APP version and AT$I=2, AT$I=3 for the chip version. 

**Table 13. DEVICE VERSIONS** 

|**Product**|**Part Number**|**APP Version**|**APP Version**|**Chip Version**|**Chip Version**|
|---|---|---|---|---|---|
|||**[0]**|**[1]**|**[0]**|**[1]**|
|AX−SFJK|AX−SFJK−1−01−XXXX1|0x01|0x01|0x8F|0x51|
|AX−SFJK−API|AX−SFJK−API−1−01−XXXX1|0x01|0x01|0x8F|0x51|



1. TB05 for Reel 500, TX30 for Reel 3000 reel 

Sigfox and Sigfox Ready are registered trademarks of Sigfox SARL. 

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## **LITERATURE FULFILLMENT** : 

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**19**