AUIRLS3036-7P

## **AUTOMOTIVE GRADE** 

## **Features** 

Advanced Process Technology Ultra Low On-Resistance Logic Level Gate Drive Dynamic dv/dt Rating 175°C Operating Temperature Fast Switching Repetitive Avalanche Allowed up to Tjmax Lead-Free, RoHS Compliant Automotive Qualified * 

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|---|---|---|
|HEXFET|®|Power MOSFET|
|D|VDSS|60V|
|RDS(on)   typ.|1.5m|
|max.|1.9m|
|G|
|ID (Silicon Limited)|300A|
|S|ID (Package Limited)|240A|

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## **Description** 

Specifically designed for Automotive applications, this HEXFET[®] Power MOSFET utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area.  Additional features of this design  are a 175°C junction operating temperature, fast switching speed and improved repetitive avalanche rating . These features combine to make this design an extremely efficient and reliable device for use in Automotive applications and a wide variety of other applications. 

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|---|---|---|
|G|D|S|
|Gate|Drain|Source|

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|---|---|---|---|---|
|Standard Pack|
|Base Part Number|Package Type|Orderable Part Number|
|Form|Quantity|
|Tube|50|AUIRLS3036-7P|
|AUIRLS3036-7P|D2Pak 7 Pin|Tape and Reel Left|800|AUIRLS3036-7TRL|
|Tape and Reel Right|800|AUIRLS3036-7TRR|

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## **Absolute Maximum Ratings** 

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.   These are stress ratings  only; and functional operation of the device at these or any other condition beyond those indicated in the specifications is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Ambient temperature (TA) is 25°C, unless otherwise specified. 

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|---|---|---|---|---|---|---|---|
|Symbol|Parameter|Max.|Units|
|ID|@ TC|= 25°C|ee|Continuous Drain Current, VGS @ 10V  (Silicon Limited)|©|300|
|ID @ TC = 100°C|a|Continuous Drain Current, VGS @ 10V   (Silicon Limited)|210|
|A|
|ID @ TC = 25°C|a|Continuous Drain Current, VGS @ 10V (Package Limited)|240|
|IDM|Pulsed Drain Current|1000|
|—<——_——————|ae|
|PD|@TC|= 25°C|a|Maximum Power Dissipation|380|W|
|a|Linear Derating Factor|2.5|W/°C|
|VGS|a|Gate-to-Source Voltage|± 16|V|
|EAS|Single Pulse Avalanche Energy|(Thermally Limited)|300|mJ|
|IAR|po|Avalanche Current|A|
|See Fig. 14, 15, 22a, 22b|
|EAR|a|Repetitive Avalanche Energy|mJ|
|dv/dt|Peak Diode Recovery|8.1|V/ns|
|a|
|TJ|Operating Junction and|
|-55  to + 175|
|TSTG|Storage Temperature Range|°C|
|pf|Soldering Temperature, for 10 seconds (1.6mm from case)|300|
|Thermal Resistance|
|Symbol|Parameter|Typ.|Max.|Units|
|R|θ|JC|<a|Junction-to-Case|–––|0.40|°C/W|
|R|θ|JA|Junction-to-Ambient (PCB Mount, steady state)|–––|40|
|Ce|

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HEXFET[®] is a registered trademark of International Rectifier. ***** Qualification standards can be found at http://www.irf.com/ 

## ������������� 

## **Static Electrical Characteristics @ TJ = 25°C (unless otherwise specified)** 

|**Symbol**|**Parameter**|**Min. **|**Typ. **|**Max. **|**Units**|**Units**|**Conditions**||
|---|---|---|---|---|---|---|---|---|
|V(BR)DSS|Drain-to-Source Breakdown Voltage|60|–––|–––|V||VGS= 0V, ID= 250μA||
|ΔV(BR)DSS/ΔTJ|Breakdown Voltage Temp. Coefficient|–––|0.059|–––|V/°C||Reference to 25°C, ID= 5mA�||
|RDS(on)|Static Drain-to-Source On-Resistance|–––<br>–––|1.5<br>1.7|1.9<br>2.2|mΩ||VGS= 10V, ID= 180A�<br>VGS= 4.5V, ID= 150A�||
|VGS(th)|Gate Threshold Voltage|1.0|–––|2.5|V||VDS= VGS, ID= 250μA||
|gfs|Forward Transconductance|390|–––|–––|S||VDS= 10V,ID= 180A||
|RG(int)|Internal Gate Resistance|–––|1.9|–––|Ω||||
|IDSS|Drain-to-Source Leakage Current|–––<br>–––|–––<br>–––|20<br>250|μA||VDS= 60V, VGS= 0V<br>VDS= 60V, VGS= 0V, TJ= 125°C||
|IGSS|Gate-to-Source Forward Leakage<br>Gate-to-Source Reverse Leakage|–––<br>–––|–––<br>–––|100<br>-100|nA||VGS= -16V<br>VGS= 16V||
|**Dynamic Electrical Characteristics @ TJ = 25°C(unless otherwise specified)**|||||||||
|**Symbol**|**Parameter**|**Min. **|**Typ. **|**Max. **|**Units**||**Conditions**||
|Qg|Total Gate Charge|–––|110|160|||ID= 180A||
|Qgs<br>Qgd|Gate-to-Source Charge<br>Gate-to-Drain("Miller")Charge|–––<br>–––|33<br>53|–––<br>–––|nC||VDS= 30V<br>VGS= 4.5V�||
|Qsync|Total Gate Charge Sync.(Qg - Qgd)|–––|57|–––|||ID= 180A, VDS=0V, VGS= 4.5V||
|td(on)|Turn-On DelayTime|–––|81|–––|||VDD= 39V||
|tr|Rise Time|–––|540|–––|||ID= 180A||
|td(off)|Turn-Off DelayTime|–––|89|–––|ns||RG= 2.1Ω||
|tf|Fall Time|–––|170|–––|||VGS= 4.5V�||
|Ciss|Input Capacitance|–––|11270|–––|||VGS= 0V||
|Coss|Output Capacitance|–––|1025|–––|||VDS= 50V||
|Crss|Reverse Transfer Capacitance|–––|520|–––|pF||ƒ= 1.0MHz||
|Cosseff. (ER)|Effective Output Capacitance(EnergyRelated)�|�–––|1460|–––|||VGS= 0V, VDS= 0V to 48V�||
|Cosseff. (TR)|Effective Output Capacitance(Time Related) �|–––|1630|–––|||VGS= 0V, VDS= 0V to 48V�||



## **Diode Characteristics** 

|**Symbol**|**Parameter**|**Min. **|**Typ. **|**Max. **|**Units**|**Conditions**|
|---|---|---|---|---|---|---|
|IS|Continuous Source Current<br>(BodyDiode)|–––|–––|300|A|S<br>D<br>G<br>showing  the<br>MOSFET symbol<br>integral reverse<br>p-njunction diode.|
|ISM|Pulsed Source Current<br>(BodyDiode)��|–––|–––|1000|||
|VSD|Diode Forward Voltage|–––|–––|1.3|V|TJ= 25°C, IS= 180A, VGS= 0V�|
|trr|Reverse Recovery Time|–––|57|–––|ns|TJ= 25°C<br>VR= 51V,<br>TJ= 125°C<br>IF= 180A<br>TJ= 25°C<br>di/dt = 100A/μs�<br>TJ= 125°C<br>TJ= 25°C|
|||–––|60|–––|||
|Qrr|Reverse Recovery Charge|–––|140|–––|nC||
|||–––|160|–––|||
|IRRM|Reverse RecoveryCurrent|–––|4.6|–––|A||
|ton|Forward Turn-On Time|Intrinsic turn-on time is negligible(turn-on is dominated byLS+LD)|||||



## **������** 

- Calcuted continuous current based on maximum allowable junction temperature Bond wire current limit is 195A. Note that current limitation arising from heating of the device leds may occur with some lead mounting arrangements. 

- Repetitive rating;  pulse width limited by max. junction temperature. 

- Limited by TJmax, starting TJ = 25°C, L = 0.018mH RG = 25 Ω , IAS = 180A, VGS =10V. Part not recommended for use above this value . 

- ISD ≤ 180A, di/dt ≤ 1070A/μs, VDD ≤ V(BR)DSS, TJ ≤ 175°C. 

- Pulse width ≤ 400μs; duty cycle ≤ 2%. 

- Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. 

- Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS. 

- When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended   footprint and soldering techniquea refer to applocation note # AN-  994 echniques refer to application note #AN-994. 

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1000<br>VGS<br>Peta TOP           15V<br>10V<br>4.5V<br>reel 4.0V<br>100 P74Ze 585 eesSat 3.5V3.3V<br>3.0V<br>Sat BOTTOM 2.7V<br>re<br>10 a ee aa<br>1 email PFET<br>Pn 2.7V Pa Hy<br>EEF ≤  60μs PULSE WIDTH<br>Tj = 25°C<br>PT Et anil<br>0.1<br>0.1 1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>Fig 1.   Typical Output Characteristics<br>1000<br>esee. eee<br>TJ = 175°C<br>n/n<br>100<br>eei 448 ey eeeee eeeee<br>T J  = 25°C<br>10<br>pf V DS  = 25V<br>≤  60μs PULSE WIDTH<br>1 lane<br>2.0 3.0 4.0 5.0<br>VGS, Gate-to-Source Voltage (V)<br>ID, Drain-to-Source Current (A)<br>) (Α<br>ID, Drain-to-Source Current<br>**----- End of picture text -----**<br>


**Fig 3.** Typical Transfer Characteristics 

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20000<br>VGS   = 0V,       f = 100 kHz<br>Ciss   = Cgs + Cgd,  Cds SHORTED<br>C  = C<br>rss   gd<br>15000 C oss   = C ds  + C gd<br>Ciss<br>10000<br>5000<br>Coss<br>Crss<br>a Sl<br>0<br>1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>C, Capacitance (pF)<br>**----- End of picture text -----**<br>


**Fig 5.** Typical Capacitance vs. Drain-to-Source Voltage 

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1000<br>VGS<br>PA TOP           15V<br>10V<br>4.5V<br>ema pail 4.0V<br>PW<br>WG 3.5V 3.3V<br>3.0V<br>|A BOTTOM 2.7V<br>YY iit omen<br>100 Yen| TT<br>VASO<br>earfs 2.7V ≤  60μs PULSE WIDTH tm LI<br>Tj = 175°C<br>ania |<br>10<br>0.1 1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>Fig 2.   Typical Output Characteristics<br>2.5<br>ID = 180A<br>VGS = 10V<br>2.0<br>1.5 /<br>1.0 pA<br>nae<br>0.5<br>-60 -40 -20 0 20 40 60 80 100 120 140 160 180<br>TJ , Junction Temperature (°C)<br>Fig 4.   Normalized On-Resistance vs. Temperature<br>5<br>ID= 180A VDS= 48V<br>VDS= 30V<br>4<br>3<br>2<br>1<br>0<br>0 20 40 60 80 100 120 140<br> QG  Total Gate Charge (nC)<br>VGS, Gate-to-Source Voltage (V)<br>ID, Drain-to-Source Current (A)<br>RDS(on) , Drain-to-Source On Resistance                        (Normalized)<br>**----- End of picture text -----**<br>


**Fig 4.** Normalized On-Resistance vs. Temperature 

**Fig 6.** Typical Gate Charge vs. Gate-to-Source Voltage 

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1000<br>TJ = 175°CJ = 175°C= 175°C<br>100<br>TJ = 25°CJ = 25°C= 25°C<br>10<br>1<br>VGS = 0VGS = 0V= 0V<br>0.1<br>0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6<br>VSD, Source-to-Drain Voltage (V)<br>ISD, Reverse Drain Current (A)<br>**----- End of picture text -----**<br>


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10000<br>OPERATION IN THIS AREA<br>LIMITED BY R DS(on)<br>TJ = 175°CJ = 175°C= 175°C 1000<br>100<br>100μsec<br>100<br>TJ = 25°CJ = 25°C= 25°C<br>10 1msec<br>LIMITED BY PACKAGE<br>10<br>10msec<br>1<br>1 Tc = 25°C<br>Tj = 175°C DC<br>VGS = 0VGS = 0V= 0V Single Pulse<br>0.1 0.1<br>0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0.1 1 10 100<br>VSD, Source-to-Drain Voltage (V) VDS, Drain-toSource Voltage (V)<br>Fig 7.   Typical Source-Drain Diode Fig 8.   Maximum Safe Operating Area<br>Forward Voltage<br>300 80<br>LIMITED BY PACKAGE ID = 5mA<br>250 =<br>IN<br>200 rTENCENC 70<br>150<br>100 TOCE NE NE<br>TEE 60<br>50 CEE<br>0<br>50<br>25 50 75 100 125 150 175<br>-60 -40 -20 0 20 40 60 80 100 120 140 160 180<br> TC , Case Temperature (°C)<br>TJ , Junction Temperature (°C)<br>Fig 9.   Maximum Drain Current vs. Fig 10.   Drain-to-Source Breakdown Voltage<br>Case Temperature<br>4.0 1200<br>                 I D<br>TOP          22A<br>1000<br>                37A<br>3.0 BOTTOM   180A<br>TELL. Soo<br>800<br>CLEA awe<br>2.0 / 600 PEEL<br>400<br>aaa T<br>1.0<br>200<br>Cai}ca NAERSSRESE<br>0.0 0<br>0 10 20 30 40 50 60 70 25 50 75 100 125 150 175<br>VDS, Drain-to-Source Voltage (V) Starting TJ, Junction Temperature (°C)<br>ID , Drain Current (A)<br>ID,  Drain-to-Source Current (A)<br>V(BR)DSS , Drain-to-Source Breakdown Voltage<br>Energy (μJ)<br>EAS, Single Pulse Avalanche Energy (mJ)<br>**----- End of picture text -----**<br>


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300<br>LIMITED BY PACKAGE<br>250 =<br>IN<br>200<br>rTENCENC<br>150<br>100 TOCE NE NE<br>TEE<br>50 CEE<br>0<br>25 50 75 100 125 150 175<br> TC , Case Temperature (°C)<br>ID , Drain Current (A)<br>**----- End of picture text -----**<br>


**Fig 10.** Drain-to-Source Breakdown Voltage 

**Fig 11.** Typical COSS Stored Energy 

**Fig 12.** Maximum Avalanche Energy Vs. DrainCurrent 

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1<br>D = 0.50<br>0.1 0.20<br>0.10<br>0.05 R1 R1 R2 R2 R3 R 3 Ri (°C/W) τι (sec)<br>0.01 0.020.01 τ J τ J τ 1 τ 1 τ 2 τ 2 τ 3 τ 3 τ C τ 0.1037310.196542 0.0001840.001587<br>Ci= Ci=  τ i /τ Rii / Ri 0.098271 0.006721<br>0.001 SINGLE PULSE<br>( THERMAL RESPONSE )<br>Notes:<br>1. Duty Factor D = t1/t2<br>2. Peak Tj = P dm x Zthjc + Tc<br>0.0001<br>1E-006 1E-005 0.0001 0.001 0.01 0.1<br>t1 , Rectangular Pulse Duration (sec)<br>Thermal Response ( Z thJC )<br>**----- End of picture text -----**<br>


**Fig 13.** Maximum Effective Transient Thermal Impedance, Junction-to-Case 

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1000<br>Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche<br>pulsewidth, tav, assuming  Δ Tj = 150°C and<br>Tstart =25°C (Single Pulse)<br>100<br>0.01<br>0.05<br>0.10<br>10<br>Allowed avalanche Current vs avalanche<br>pulsewidth, tav, assuming  ΔΤ j = 25 ° C and<br>Tstart = 150°C.<br>1<br>1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01<br>tav (sec)<br>Fig 14.   Typical Avalanche Current vs.Pulsewidth<br>300 Notes on Repetitive Avalanche Curves , Figures 14, 15:<br>TOP          Single Pulse                 (For further info, see AN-1005 at www.irf.com)<br>250 BOTTOM   1% Duty Cycle I D  = 180A 1. Avalanche failures assumption:Purely a thermal phenomenon and failure occurs at a temperature far in<br>excess of Tjmax. This is validated for every part type.jmax. This is validated for every part type.. This is validated for every part type.<br>200 2. Safe operation in Avalanche is allowed as long asTjmaxjmax is not exceeded.<br>3. Equation below based on circuit and waveforms shown in Figures 22a, 22b.<br>4. PD (ave) = Average power dissipation per single avalanche pulse.<br>150 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase<br>during avalanche).<br>6. Iav = Allowable avalanche current.<br>100 7.  Δ T = Allowable rise in junction temperature, not to exceed = Allowable rise in junction temperature, not to exceedAllowable rise in junction temperature, not to exceed Tjmax jmax (assumed as<br>25°C in Figure 14, 15).<br>tav = Average time in avalanche.<br>50<br>D = Duty cycle in avalanche =  tav ·f<br>ZthJC(D, tav) = Transient thermal resistance, see Figures 13)<br>0<br>25 50 75 100 125 150 175 PD (ave) = 1/2 ( 1.3·BV·Iav) = � T/ ZthJC<br>Iav = 2 � T/ [1.3·BV·Zth]<br>Starting TJ , Junction Temperature (°C)<br>EAR , Avalanche Energy (mJ)<br>Avalanche Current (A)<br>**----- End of picture text -----**<br>


- Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type.jmax. This is validated for every part type.. This is validated for every part type. 

2. Safe operation in Avalanche is allowed as long asTjmaxjmax is not exceeded. 

3. Equation below based on circuit and waveforms shown in Figures 22a, 22b. 

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 

7. Δ T = Allowable rise in junction temperature, not to exceed = Allowable rise in junction temperature, not to exceedAllowable rise in junction temperature, not to exceed Tjmax jmax (assumed as 25°C in Figure 14, 15). 

**EAS (AR) = PD (ave)·tav** 

**Fig 15.** Maximum Avalanche Energy vs. Temperature 

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3.0<br>ID = 1.0A<br>ID = 1.0mA<br>2.5 ID = 250μA<br>\<br>2.0<br>1.5<br>1.0<br>-75 -50 -25 0 25 50 75 100 125 150 175<br>TJ , Temperature ( °C )<br>VGS(th) Gate threshold Voltage (V)<br>**----- End of picture text -----**<br>


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24<br>18<br>12<br>IF = 120A<br>6<br>VR = 51V<br>T  = 125°C<br>J<br>TJ =  25°C<br>0<br>100 200 300 400 500 600 700 800 900<br>dif / dt - (A / μs)<br>IRRM - (A)<br>**----- End of picture text -----**<br>


**Fig 16.** Threshold Voltage Vs. Temperature 

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24 yd Le<br>18<br>12 a<br>|oeq I | F = 180A<br>6<br>VR = 51V<br>T  = 125°C<br>J<br>TJ =  25°C<br>0<br>100 200 300 400 500 600 700 800 900<br>dif / dt - (A / μs)<br>IRRM - (A)<br>**----- End of picture text -----**<br>


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1000<br>800<br>LLL LL<br>600<br>7<br>400<br>[AlZO IF = 120A<br>200 “?— VR = 51V<br>TJ = 125°C<br>T  =  25°C<br>J<br>0<br>100 200 300 400 500 600 700 800 900<br>dif / dt - (A / μs)<br>QRR - (nC)<br>**----- End of picture text -----**<br>


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1000<br>IF = 180A<br>VR = 51V<br>800 TJ = 125 ° C<br>T  =  25°C<br>J<br>600<br>400<br>BRREEAE<br>ee<br>200<br>| |<br>0<br>100 200 300 400 500 600 700 800 900<br>dif / dt - (A / μs)<br>QRR - (nC)<br>**----- End of picture text -----**<br>


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Driver Gate Drive<br>P.W.<br>D.U.T + { P.W. + Period ——— + D = —— Period<br>) [©)]    •  CircuitLow LayoutStray InductConsiderations | V t t GS=10<br> •<br>- •   CurrentLow LeakageTransformerInductance @ D.U.T. ISD Waveform<br>+<br>= ReverseRecovery Body Diode Forward \<br>- a - ® + Current r Current di/dt /<br>® D.U.T. VDS Waveform Diode Recoverydv/dt ‘<br>00 > VDD<br>ma<br>•   Re-Applied<br>•   Driver same type as D.U.T. + Voltage Body Diode  Forward Drop<br>Ro (A •   dv/dt controlled by Rg Vp p -<br>•<br>D.U.T. - Device Under Test SCO |<br>Ripple  ≤ 5% ISD<br>Isp controlled by Duty Factor "D" @\ t<br>* Vag = 5V for Logic Level Devices<br>Fig 21.  Peak Diode Recovery dv/dt Test Circuit for N-Channel<br>HEXFET ® Power MOSFETs<br>V(BR)DSS<br>15V << tp -—><br>VDS L DRIVER<br>RG D.U.T +<br>- [V][DD]<br>IAS A<br>gy 2V0VGS dk<br>tp 0.01 Ω IAS<br> Unclamped Inductive Test Circuit Fig 22b.   Unclamped Inductive Waveforms<br>Rp<br>VDSDS<br>90%<br>Ves I<br>+<br>“ 1 D.U.T. - Vop<br>10%<br>) [Ves]<br>Pulse Width ≤ 1  ys VGSGS | KSSp<br>Duty Factor ≤ 0.1 % l| v l > | p l<br>td(on)d(on) trr td(off)d(off)<br>  Switching Time Test Circuit Fig 23b.   Switching Time Waveforms<br>Current Regulator Id<br>Same Type as D.U.T. Vds<br>50K Ω Vgs<br>! 12V .2 μ F .3 μ F ||| i<br>+<br>D.U.T. -VDSVDSDS<br>Vgs(th)<br>VGSGS<br>3mA<br>IGG IDD<br>Current Resistors Qgs1 Qgs2 Qgd Qgodr<br>**----- End of picture text -----**<br>


**Fig 22b.** Unclamped Inductive Waveforms 

**Fig 22a.** Unclamped Inductive Test Circuit 

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VDSDS<br>90%<br>I<br>10% /\<br>VGSGS l| v l > | KSSp l<br>td(on)d(on) trr td(off)d(off) tf<br>**----- End of picture text -----**<br>


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Fig 23a.   Switching Time Test Circuit<br>**----- End of picture text -----**<br>


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Current Regulator<br>Same Type as D.U.T.<br>50K Ω<br>12V .2 μ F<br>.3 μ F |||<br>+<br>D.U.T. -VDSVDSDS<br>VGSGS<br>3mA<br>IGG IDD<br>Current Sampling Resistors<br>**----- End of picture text -----**<br>


**Fig 24a.** Gate Charge Test Circuit 

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Fig 24b.    Gate Charge Waveform<br>Submit Datasheet Feedback<br>**----- End of picture text -----**<br>


D[2] Pak - 7 Pin Package Outline Dimensions are shown in millimeters (inches) 

## D[2] Pak - 7 Pin Part Marking Information 

## D[2] Pak - 7 Pin Tape and Reel 

## **†** 

## **Qualification Information** 

## **Qualification Level** 

Automotive (per AEC-Q101)[††] Comments: This part number(s) passed Automotive qualification. IR’s Industrial and Consumer qualification level is granted by extension of the higher Automotive level. 

|**Moisture Sensitivity Level**|**Moisture Sensitivity Level**|**Moisture Sensitivity Level**|D2Pak 7 Pin|MSL1|
|---|---|---|---|---|
|||Machine Model||Class M4 (+/- 800V)†††|
|||||AEC-Q101-002|
|**ESD**||Human Body Model||Class H3A (+/- 6000V)†††<br>AEC-Q101-001|
|||Charged Device Model||Class C5 (+/- 2000V)†††|
|||||AEC-Q101-005|
|**RoHS Compliant**||||Yes|



http//www.irf.com/ 

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Unless specifically designated for the automotive market, International Rectifier Corporation and its subsidiaries (IR) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or services without notice. Part numbers designated with the “AU” prefix follow automotive industry and / or customer specific requirements with regards to product discontinuance and process change notification. All products are sold subject to IR’s terms and conditions of sale supplied at the time of order acknowledgment. 

IR warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with IR’s standard warranty.  Testing and other quality control techniques are used to the extent IR deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. 

IR assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using IR components. To minimize the risks with customer products and applications, customers should provide adequate design and operating safeguards. 

Reproduction of IR information in IR data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices.  Reproduction of this information with alterations is an unfair and deceptive business practice. IR is not responsible or liable for such altered documentation.  Information of third parties may be subject to additional restrictions. 

Resale of IR products or serviced with statements different from or beyond the parameters stated by IR for that product or service voids all express and any implied warranties for the associated IR product or service and is an unfair and deceptive business practice.  IR is not responsible or liable for any such statements. 

IR products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of the IR product could create a situation where personal injury or death may occur.  Should Buyer purchase or use IR products for any such unintended or unauthorized application, Buyer shall indemnify and hold International Rectifier and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that IR was negligent regarding the design or manufacture of the product. 

Only products certified as military grade by the Defense Logistics Agency (DLA) of the US Department of Defense, are designed and manufactured to meet DLA military specifications required by certain military, aerospace or other applications. Buyers acknowledge and agree that any use of IR products not certified by DLA as military-grade, in applications requiring military grade products, is solely at the Buyer’s own risk and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. 

IR products are neither designed nor intended for use in automotive applications or environments unless the specific IR products are designated by IR as compliant with ISO/TS 16949 requirements and bear a part number including the designation “AU”.  Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, IR will not be responsible for any failure to meet such requirements. 

For technical support, please contact IR’s Technical Assistance Center http://www.irf.com/technical-info/ 

## **WORLD HEADQUARTERS:** 

101 N. Sepulveda Blvd., El Segundo, California 90245 

Tel: (310) 252-7105 

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## **Revision History** 

|**Revision Historyy**||
|---|---|
|**Date**|**Comments**|
|4/2/2014|•Added  "Logic Level Gate Drive" bullet in the features section on page 1<br>•Updated  part marking  on page 8<br>•Updated typo on the fig.19 and fig.20, unit of y-axis from "A" to "nC" on page 6.<br>•Updated data sheet with new IR corporate template|