AUIRFS8409

**AUTOMOTIVE GRADE** 

## **Features** 

Advanced Process Technology New Ultra Low On-Resistance 175°C Operating Temperature Fast Switching Repetitive Avalanche Allowed up to Tjmax Lead-Free, RoHS Compliant ° . Automotive Qualified * 

## **Description** 

Specifically designed for Automotive applications, this HEXFET® Power MOSFET utilizes the latest processing techniques to achieve extremely low on-resistance per silicon area. Additional features of this design are a 175°C junction operating temperature, fast switching speed and improved repetitive avalanche rating. These features combine to make this design an extremely efficient and reliable device for use in Automotive applications and wide variety of other applications. 

## **Applications** 

Electric Power Steering (EPS) Battery Switch Start/Stop Micro Hybrid Heavy Loads DC-DC Applications 

HEXFET Power MOSFET 

**==> picture [257 x 212] intentionally omitted <==**

**----- Start of picture text -----**<br>
D VDSS 40V<br>RDS(on) (SMD)   typ. 0.97m Ω<br>OL                          max. —— 1.2m Ω<br>G<br>eee ID (Silicon Limited) eon 409A<br>S ee ID (Package Limited) 195A  ee<br>D<br>D D<br>S<br>D S S D<br>G G G<br>TO-220AB D [2] Pak TO-262<br>AUIRFB8409 AUIRFS8409 AUIRFSL8409<br>**----- End of picture text -----**<br>


|**G**<br>Gate|**D**<br>Drain|**S**<br>Source|
|---|---|---|



|**Base part number**|**Package Type**|**Standard Pack**|**Standard Pack**|**Orderable Part Number**|
|---|---|---|---|---|
|||**Form**|**Quantity**||
|AUIRFB8409|TO-220|Tube|**Quantity**<br>50|AUIRFB8409|
|AUIRFS8409|D2-Pak|Tube|50|AUIRFS8409|
|AUIRFS8409|D2-Pak|Tape and Reel Left|800|AUIRFS8409TRL|
|AUIRFSL8409|TO-262|Tube|50|AUIRFSL8409|



## **Absolute Maximum Ratings** 

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.   These are stress ratings only; and functional operation of the device at these or any other condition beyond those indicated in the specifications is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. Ambient temperature (TA) is 25°C, unless otherwise specified. 

|**Symbol**|**Parameter**<br>~~ee ee~~|**Max.**<br>~~ee~~|**Units**<br>~~ee~~|
|---|---|---|---|
|ID@ TC= 25°C|Continuous Drain Current,VGS@ 10V(Silicon Limited)<br>~~ss~~<br>~~ee ee~~|409<br>~~ss~~<br>~~ee~~|A<br>~~ee~~|
|ID@ TC= 100°C|Continuous Drain Current,VGS@ 10V(Silicon Limited)<br>~~ee ee~~|289<br>~~ee~~||
|ID@ TC= 25°C|Continuous Drain Current,VGS@ 10V(Package Limited)<br>~~ee ee~~<br>~~ee~~|195<br>~~ee~~<br>~~ee~~||
|IDM<br>~~TT~~|Pulsed Drain Current<br>~~ee ee~~<br>~~OOF~~<br>~~TT~~<br>~~—>o~~|1524<br>~~ee~~<br>~~OOF~~<br>~~—>o~~||
|PD@TC= 25°C<br>~~TT~~|Maximum Power Dissipation<br>~~ee ee~~<br>~~TT~~<br>~~—>o~~|375<br>~~ee~~<br>~~—>o~~|W<br>~~ee~~|
|~~TT~~|Linear DeratingFactor<br>~~TT~~<br>~~—>o~~<br>~~Se~~|2.5<br>~~—>o~~<br>~~Se~~<br>~~ee~~|W/°C<br>~~Se~~|
|VGS|Gate-to-Source Voltage<br>~~Se~~<br>~~a~~|± 20<br>~~Se~~<br>~~a~~<br>~~ee~~|V<br>~~Se~~<br>~~a~~|
|EAS|Single Pulse Avalanche Energy (ThermallyLimited)<br>~~a~~<br>~~ee~~<br>~~ee~~|760<br>~~a~~<br>~~ee~~<br>~~ee~~<br>~~ee~~|mJ<br>~~a~~<br>~~ee~~|
|EAS (tested)<br>~~i~~|Single Pulse Avalanche EnergyTested Value<br>~~ee~~<br>~~i~~<br>~~eee~~|1360<br>~~ee~~<br>~~eee~~||
|AS (tested)<br>IAR<br>~~i~~|Avalanche Current<br>~~i~~<br>~~eee~~|See Fig. 14, 15, 24a, 24b<br>~~eee~~|A|
|EAR<br>~~i~~|Repetitive Avalanche Energy<br>~~i~~<br>~~eee~~||mJ|
|TJ<br>TSTG<br>~~i~~|Operating Junction and<br>Storage Temperature Range<br>~~i~~<br>~~eee~~<br>~~ee~~|-55  to + 175<br>~~eee~~<br>~~ee~~|°C<br>~~ee~~|
||SolderingTemperature,for 10 seconds(1.6mm from case)<br>~~ee~~|300<br>~~ee~~||
||Mountingtorque,6-32 or M3 screw<br>~~Se~~|10lbf in(1.1N m)<br>~~Se~~|~~Se~~|



***** Qualification standards can be found at http://www.irf.com/ 

## AUIRFB/S/SL8409 

## **Thermal Resistance** 

|**Symbol**||**Parameter**||||**Typ.**|**Typ.**|**Typ.**|**Max.**|**Units**|
|---|---|---|---|---|---|---|---|---|---|---|
|RθJC||Junction-to-Case��||||–––|||0.40|°C/W|
|RθCS||Case-to-Sink,Flat Greased Surface||||0.50|||–––||
|RθJA||Junction-to-Ambient(PCB Mount) �||||–––|||62||
|**Static @ TJ =**|**25°C(unless otherwise specified)**||||||||||
|**Symbol**|**Parameter**||**Min.**|**Typ.**|**Max. **||**Units**|**Conditions**|||
|V(BR)DSS|Drain-to-Source Breakdown Voltage||40|–––|–––||V|VGS= 0V,ID= 250µA|||
|∆V(BR)DSS/∆TJ|Breakdown Voltage Temp. Coefficient||–––|0.014|–––||V/°C|Reference to 25°C,ID= 1.0mA�|||
|RDS(on)SMD|Static Drain-to-Source On-Resistance||–––|0.97|1.2||mΩ|VGS= 10V,ID= 100A�|||
|RDS(on)TO-220|||–––|1.0|1.3|||VGS= 10V,ID= 100A�|||
|VGS(th)|Gate Threshold Voltage||2.2|–––|3.9||V|VDS= VGS,ID= 250µA|||
|IDSS|Drain-to-Source Leakage Current||–––|–––|1.0||µA|VDS= 40V,VGS= 0V|||
||||–––|–––|150|||VDS= 40V,VGS= 0V,TJ= 125°C|||
|IGSS|Gate-to-Source Forward Leakage||–––|–––|100||nA|VGS= 20V|||
||Gate-to-Source Reverse Leakage||–––|–––|-100|||VGS= -20V|||
|RG|Internal Gate Resistance||–––|2.1|–––||Ω||||
|**Dynamic @ TJ = 25°C(unless otherwise specified)**|||||||||||
|**Symbol**|**Parameter**||**Min.**|**Typ.**|**Max. **||**Units**|**Conditions**|||
|gfs|Forward Transconductance||150|–––|–––||S|VDS= 10V,ID= 100A|||
|Qg|Total Gate Charge||–––|300|450||nC|VGS= 10V�<br>VDS=20V<br>ID= 100A|||
|Qgs|Gate-to-Source Charge||–––|77|–––||||||
|Qgd|Gate-to-Drain("Miller")Charge||–––|98|–––||||||
|Qsync|Total Gate Charge Sync.(Qg- Qgd)||–––|202|–––|||ID= 100A,VDS=0V,VGS= 10V|||
|td(on)|Turn-On DelayTime||–––|32|–––||ns|VDD= 20V<br>ID= 30A<br>RG= 2.7Ω<br>VGS= 10V�|||
|tr|Rise Time||–––|105|–––||||||
|td(off)|Turn-Off DelayTime||–––|160|–––||||||
|tf|Fall Time||–––|100|–––||||||
|Ciss|Input Capacitance||–––|14240|–––||pF|VGS= 0V<br>VDS= 25V<br>ƒ= 1.0 MHz|||
|Coss|Output Capacitance||–––|2130|–––||||||
|Crss|Reverse Transfer Capacitance||–––|1460|–––||||||
|Cosseff.(ER)|Effective Output Capacitance(EnergyRelated)||–––|2605|–––|||VGS= 0V,VDS= 0V to 32V�|||
|Cosseff.(TR)|Effective Output Capacitance(Time Related)||–––|2920|–––|||VGS= 0V,VDS= 0V to 32V�|||



## **Diode Characteristics** 

|**Symbol**|**Parameter**|**Min.**|**Typ.**|**Max. **|**Units**|**Conditions**|
|---|---|---|---|---|---|---|
|IS|Continuous Source Current<br>(Body Diode)|–––|–––|409�|A|S<br>D<br>G<br>integral reverse<br>p-n junction diode.<br>MOSFET symbol<br>showing  the|
|ISM|Pulsed Source Current<br>(Body Diode)��|–––|–––|1576|||
|VSD|Diode Forward Voltage|–––|0.86|1.2|V|TJ= 25°C,IS= 100A,VGS= 0V�|
|dv/dt|Peak Diode Recovery �|–––|2.7|–––|V/ns|TJ= 175°C,IS= 100A,VDS= 40V|
|trr|Reverse Recovery Time|–––|52|–––|ns|TJ= 25°C<br>VR= 34V,<br>TJ= 125°C<br>IF= 100A<br>TJ= 25°C<br>di/dt = 100A/µs�<br>TJ= 125°C<br>TJ= 25°C|
|||–––|52|–––|||
|Qrr|Reverse Recovery Charge|–––|97|–––|nC||
|||–––|97|–––|||
|IRRM|Reverse RecoveryCurrent|–––|2.3|–––|A||
|ton|Forward Turn-On Time|Intrinsic turn-on time is negligible(turn-on is dominated byLS+LD)|||||



## **������** 

- Calculated continuous current based on maximum allowable junction temperature. Bond wire current limit is 195A. Note that current limitations arising from heating of the device leads may occur with some lead mounting arrangements. ������������������ 

- Repetitive rating;  pulse width limited by max. junction temperature. 

- Limited by TJmax, starting TJ = 25°C, L = 0.15mH, RG = 50 Ω , IAS = 100A, VGS =10V. Part not recommended for use  above this value. 

- ISD ≤ 100A, di/dt ≤ 990A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C. 

- Pulse width ≤ 400µs; duty cycle ≤ 2%. 

- Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS. 

- Coss eff. (ER) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 to 80% VDSS. 

- When mounted on 1" square PCB (FR-4 or G-10 Material). For recommended footprint and soldering techniques refer to application note #AN-994. 

- �θ ������������������������������������� 

- �θ JC ���������������������������� 

������������������������������������������������������������������������������������������������������������������������������������� 

� 

AUIRFB/S/SL8409 ~~CT~~ 

**==> picture [215 x 664] intentionally omitted <==**

**----- Start of picture text -----**<br>
1000<br>VGS<br>TOP           15V<br>10V<br>fa 8.0V<br>7.0V<br>6.0V<br>ff 5.5V<br>100 V AZaeael 4.8V<br>BOTTOM 4.5V<br>s<br> | ia a<br>10<br>T— err |<br>4.5V a<br>≤ 60µs PULSE WIDTH<br>Tj = 25°C<br>1<br>0.1 1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>Fig 1.   Typical Output Characteristics<br>1000<br>ee ee ee 7 eee ee<br>y/o<br>100<br>T = 25°C<br>J<br>a<br>Py Af<br>10 e TJ = 175°C al<br>ree| ff eo<br>VDS = 25V<br>≤ 60µs PULSE WIDTH<br>1.0 - Et<br>2 3 4 5 6 7<br>VGS, Gate-to-Source Voltage (V)<br>Fig 3.   Typical Transfer Characteristics<br>100000<br>VGS   = 0V,       f = 1 MHZ<br>= Ciss   = C gs + Cgd,  C ds SHORTED<br>C  = C<br>= rss   gd<br>Coss   = Cds + Cgd<br>-<br>E Ciss S<br>10000<br>Sa Coss n nell<br>P C EE<br>rss<br>PO SBA TH<br>} | Nt<br>P enPE<br>1000 ><br>1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>C, Capacitance (pF)<br>ID, Drain-to-Source Current (A)<br>ID, Drain-to-Source Current (A)<br>**----- End of picture text -----**<br>


**Fig 5.** Typical Capacitance vs. Drain-to-Source Voltage 

**==> picture [209 x 200] intentionally omitted <==**

**----- Start of picture text -----**<br>
1000<br>VGS<br>TOP           15V<br>10V<br>8.0V<br>a fa<br>7.0V<br>6.0V<br>nny /4ae> 5.5V<br>ma Zant 4.8V<br>BOTTOM 4.5V<br>100<br>|) WY | eae<br>4.5V<br>a a<br>V7 7 7<br>≤ 60µs PULSE WIDTH<br>Tj = 175°C<br>10<br>0.1 1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>ID, Drain-to-Source Current (A)<br>**----- End of picture text -----**<br>


**Fig 2.** Typical Output Characteristics 

**==> picture [214 x 201] intentionally omitted <==**

**----- Start of picture text -----**<br>
2.0<br>ID = 100A<br>1.8 V GS = 10V<br>1.6 Ht| Le> Z)<br>1.41.2 P EE EL<br>LLLy [O]<br>1.0 L AL|  LEE<br>0.8<br>0.6 ATCEE<br>-60 -40 -20 0 20 40 60 80 100120140160180<br>TJ , Junction Temperature (°C)<br>RDS(on) , Drain-to-Source On Resistance                        (Normalized)<br>**----- End of picture text -----**<br>


**Fig 4.** Normalized On-Resistance vs. Temperature 

**==> picture [214 x 201] intentionally omitted <==**

**----- Start of picture text -----**<br>
14.0<br>ID= 100A<br>P t<br>12.0<br>V EL DS= 32V LL<br>10.0 Z C e OT VDS= 20V SYA<br>8.0<br>B annan<br>6.0<br>|<br>4.0<br>E e= ane<br>V<br>2.0 A TE<br>| |<br>0.0 Jill titi<br>0 50 100 150 200 250 300 350 400<br> QG,  Total Gate Charge (nC)<br>VGS, Gate-to-Source Voltage (V)<br>**----- End of picture text -----**<br>


**Fig 6.** Typical Gate Charge vs. Gate-to-Source Voltage 

AUIRFB/S/SL8409 ~~as~~ 

**==> picture [211 x 681] intentionally omitted <==**

**----- Start of picture text -----**<br>
1000<br>T = 175°C<br>J<br>100<br>10<br>T = 25°C<br>J<br>1<br>VGS = 0V<br>0.1<br>0.0 0.5 1.0 1.5 2.0 2.5<br>VSD, Source-to-Drain Voltage (V)<br>Fig 7.   Typical Source-Drain Diode<br>Forward Voltage<br>500<br>Limited By Package<br>400<br>TILL<br>ma T Ty<br>300200 wae.<br>100 TTT TT<br>P itt LA\<br>0<br>25 50 75 100 125 150 175<br> TC , Case Temperature (°C)<br>Fig 9.   Maximum Drain Current vs.<br>Case Temperature<br>2.5<br>VDS= 0V to 32V<br>2.0 TL<br>1.5 T T<br>1.0 a aa<br>0.5 T A T JTT7<br>EL ) ELLE<br>0.0<br>0 5 10 15 20 25 30 35 40 45<br>VDS, Drain-to-Source Voltage (V)<br>Fig 11.   Typical COSS Stored Energy<br>ISD, Reverse Drain Current (A)<br>Energy (µJ)<br>ID,  Drain Current (A)<br>**----- End of picture text -----**<br>


**==> picture [227 x 446] intentionally omitted <==**

**----- Start of picture text -----**<br>
10000<br>OPERATION IN THIS AREA<br>LIMITED BY R DS(on)<br>1000 100µsec<br>1 ms ec<br>100<br>10msec<br>Limited by package<br>10<br>1 DC<br>Tc = 25°C<br>Tj = 175°C<br>Single Pulse<br>0.1<br>0.1 1 10 100<br>VDS, Drain-toSource Voltage (V)<br>Fig 8.   Maximum Safe Operating Area<br>47<br>Id = 1.0mA<br>46<br>S eUanEREDEEE<br>45<br>B RRRRDZAGnne<br>P ELE<br>44<br>43<br>ALL LLL<br>42<br>AB EPZ0R0R000LE<br>41<br>40 AP L E EE ELLLE<br>-60 -40 -20 0 20 40 60 80 100120140160180<br>TJ , Temperature ( °C )<br>Fig 10.   Drain-to-Source Breakdown Voltage<br>V(BR)DSS, Drain-to-Source Breakdown Voltage (V)<br>ID,  Drain-to-Source Current (A)<br>**----- End of picture text -----**<br>


**==> picture [215 x 201] intentionally omitted <==**

**----- Start of picture text -----**<br>
3500<br>ID<br>3000 TOP         26A<br>T TT<br>52A<br>2500 BOTTOM 100A<br>N OE<br>2000<br>1500 E NG<br>1000<br>SP ENGHEEREEEDNEN TTT TT<br>500<br>S COOS CARSSSSOT ST<br>0<br>25 50 75 100 125 150 175<br>Starting TJ , Junction Temperature (°C)<br>EAS , Single Pulse Avalanche Energy (mJ)<br>**----- End of picture text -----**<br>


**Fig 12.** Maximum Avalanche Energy vs. DrainCurrent 

AUIRFB/S/SL8409 

**==> picture [481 x 673] intentionally omitted <==**

**----- Start of picture text -----**<br>
1<br>D = 0.50<br>0.1 0.20<br>0.10<br>0.05<br>0.01 0.02<br>0.01<br>0.001<br>Notes:<br>SINGLE PULSE<br>1. Duty Factor D = t1/t2<br>( THERMAL RESPONSE )<br>2. Peak Tj = P dm x Zthjc + Tc<br>0.0001<br>1E-006 1E-005 0.0001 0.001 0.01 0.1<br>t1 , Rectangular Pulse Duration (sec)<br>Fig 13.   Maximum Effective Transient Thermal Impedance, Junction-to-Case<br>1000<br>Allowed avalanche Current vs avalanche<br>pulsewidth, tav, assuming  ∆ Tj = 150°C and<br>Tstart =25°C (Single Pulse)<br>100<br>10<br>Allowed avalanche Current vs avalanche<br>pulsewidth, tav, assuming  ∆Τ j = 25°C and<br>Tstart = 150°C.<br>1<br>1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01<br>tav (sec)<br>Fig 14.   Typical Avalanche Current vs.Pulsewidth<br>800 Notes on Repetitive Avalanche Curves , Figures 14, 15<br>TOP          Single Pulse                 (For further info, see AN-1005 at www.irf.com)<br>1. Avalanche failures assumption:<br>700 BOTTOM   1.0% Duty Cycle<br>Purely a thermal phenomenon and failure occurs at a temperature far in<br>ID = 100A excess of Tjmax. This is validated for every part type.jmax. This is validated for every part type.. This is validated for every part type.<br>600<br>2. Safe operation in Avalanche is allowed as long asTjmaxjmax is not exceeded.<br>3. Equation below based on circuit and waveforms shown in Figures 24a, 24b.<br>500 4. PD (ave) = Average power dissipation per single avalanche pulse.<br>5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase<br>400 during avalanche).<br>6. Iav = Allowable avalanche current.<br>300 7.  ∆ T = Allowable rise in junction temperature, not to exceed = Allowable rise in junction temperature, not to exceedAllowable rise in junction temperature, not to exceed Tjmax jmax (assumed as<br>25°C in Figure 14, 15).<br>200 tav = Average time in avalanche.<br>D = Duty cycle in avalanche =  tav ·f<br>100 ZthJC(D, tav) = Transient thermal resistance, see Figures 13)<br>0 PD (ave) = 1/2 ( 1.3·BV·Iav) = � T/ ZthJC<br>25 50 75 100 125 150 175 Iav = 2 � T/ [1.3·BV·Zth]<br>Starting TJ , Junction Temperature (°C) EAS (AR) = PD (ave)·tav<br>EAR , Avalanche Energy (mJ)<br>Avalanche Current (A)<br>Thermal Response ( Z thJC ) °C/W<br>**----- End of picture text -----**<br>


- Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type.jmax. This is validated for every part type.. This is validated for every part type. 

2. Safe operation in Avalanche is allowed as long asTjmaxjmax is not exceeded. 

3. Equation below based on circuit and waveforms shown in Figures 24a, 24b. 

5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 

7. ∆ T = Allowable rise in junction temperature, not to exceed = Allowable rise in junction temperature, not to exceedAllowable rise in junction temperature, not to exceed Tjmax jmax (assumed as 25°C in Figure 14, 15). 

**Fig 15.** Maximum Avalanche Energy vs. Temperature 

� 

������������������������������������������������������������������������������������������������������������������������������������ 

AUIRFB/S/SL8409 ~~|~~ 

**==> picture [212 x 672] intentionally omitted <==**

**----- Start of picture text -----**<br>
6.0<br>ID = 100A<br>4.0<br>|<br>T = 125°C<br>2.0 | J<br>TJ = 25°C<br>0.0 seePT<br>4 6 8 10 12 14 16 18 20<br>VGS, Gate -to -Source Voltage  (V)<br>Fig 16.  On-Resistance vs. Gate Voltage<br>12<br>IF = 60A<br>10 VR = 34V E =<br>TJ = 25°C<br>8 TJ = 125°C _ Ba<br>V Y<br>WA<br>6 x | | |<br>4<br>y l | [<br>2<br>7 | tt<br>0<br>0 200 400 600 800 1000<br>diF /dt (A/µs)<br>Fig. 18 - Typical Recovery Current vs.<br>12<br>IF = 100A<br>10 VR = 34V<br>TJ = 25°C<br>8 TJ = 125°C<br>6<br>‘20<br>4<br>y7 l| |<br>2<br>0<br>0 200 400 600 800 1000<br>diF /dt (A/µs)<br>)  Ω<br>RDS(on),  Drain-to -Source On Resistance (m<br>IRRM (A)<br>IRRM (A)<br>**----- End of picture text -----**<br>


**==> picture [209 x 201] intentionally omitted <==**

**----- Start of picture text -----**<br>
4.0<br>PEN ET<br>3.5 <a =e<br>A SN<br>3.0<br>J<br>NWP<br>BALD<br>2.5<br>ID = 250µA ZENG<br>ID = 1.0mA<br>CLLNNL<br>2.0 ID = 1.0A<br>1.5<br>PEELELLL EEEEN<br>1.0<br>-75 -50 -25 0 25 50 75 100 125 150 175<br>TJ , Temperature ( °C )<br>VGS(th), Gate threshold Voltage (V)<br>**----- End of picture text -----**<br>


**Fig 17.** Threshold Voltage vs. Temperature 

**==> picture [216 x 434] intentionally omitted <==**

**----- Start of picture text -----**<br>
300<br>IF = 60A<br>VR = 34V e S<br>250<br>TJ = 25°C<br>TJ = 125°C L —|<br>5am<br>200<br>¢<br>Wa<br>‘ff<br>150<br>oy<br>100<br>E ar<br>50<br>0 200 400 600 800 1000<br>diF /dt (A/µs)<br>Fig. 19 - Typical Stored Charge vs. dif/dt<br>260<br>IF = 100A<br>VR = 34V<br>220<br>TJ = 25°C<br>TJ = 125°C<br>180<br>¢<br>a<br>f a |<br>140<br>¢<br>100 4 a a<br>60<br>0 200 400 600 800 1000<br>diF /dt (A/µs)<br>QRR (nC)<br>QRR (nC)<br>**----- End of picture text -----**<br>


AUIRFB/S/SL8409 ~~|~~ 

**==> picture [211 x 201] intentionally omitted <==**

**----- Start of picture text -----**<br>
6.0<br>VGS = 5.5V<br>VGS = 6.0V<br>VGS = 7.0V<br>4.0 l oa VGS = 8.0V n<br>VGS =10V<br>ie |_| |My<br>2.0<br>ae<br>0.0<br>0 200 400 600 800 1000 1200<br>ID, Drain Current (A)<br>) Ω<br>RDS(on),  Drain-to -Source On Resistance (m<br>**----- End of picture text -----**<br>


**Fig 22.** Typical On-Resistance vs. Drain Current 

## AUIRFB/S/SL8409 

**==> picture [415 x 346] intentionally omitted <==**

**----- Start of picture text -----**<br>
Driver Gate Drive<br>P.W.<br>D.U.T + {$$ P.W. Period — — D = —— Period<br>) [©)]    •  Circuit Layout Considerations ] V |t GS=10<br>| — -  •   GroundLow StrayPlane Inductance<br> •   CurrentLow LeakageTransformerInductance 2) D.U.T. ISD Waveform<br>+<br>Reverse<br>@ - a | = - ® + RecoveryCurrent r Body Diode ForwardCurrent di/dt /\ ——<br>@ D.U.T. VDS Waveform Diode Recoverydv/dt ‘ '<br>00 we VDD<br>iv<br>•   Re-Applied<br>•   Driver same type as D.U.T. + Voltage Body Diode  Forward Drop<br>Re ( 4 •   Ispdv/dt controlledcontrolled by byDuty RgFactor "D" Vpp - ® t<br>•<br>D.U.T. - Device Under Test Ripple  ≤ 5% e s ISD ee<br>* Vg = 5V for Logic Level Devices<br>Fig 23.  Peak Diode Recovery dv/dt Test Circuit for N-Channel<br>HEXFET ® Power MOSFETs<br>V(BR)DSS<br>15V ~— tp -><br>VDS L DRIVER<br>RG D.U.T +<br>- [V][DD]<br>IAS A<br>yp 20VVGS dk<br>tp 0.01 WA Ω IAS oe<br>**----- End of picture text -----**<br>


**==> picture [173 x 136] intentionally omitted <==**

**----- Start of picture text -----**<br>
Fig 24a.   Unclamped Inductive Test<br>Circuit<br>Rp<br>Ves D.U.T.<br>Re<br>+<br>-<br>i [Ves]<br>Pulse Width ≤ 1  us<br>Duty Factor ≤ 0.1 %<br>**----- End of picture text -----**<br>


**==> picture [167 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
Fig 25a.   Switching Time Test Circuit<br>**----- End of picture text -----**<br>


**==> picture [136 x 132] intentionally omitted <==**

**----- Start of picture text -----**<br>
Current Regulator<br>.| Same Type as D.U.T. |<br>! 50K Ω |<br>fd 12V .2 µ F |<br>.3 µ F<br>Thao<br>+<br>D.U.T. -VDS<br>VGS<br>3mA<br>IG ID<br>Current Sampling Resistors<br>**----- End of picture text -----**<br>


**Fig 26a.** Gate Charge Test Circuit 

**Fig 24b.** Unclamped Inductive Waveforms 

**==> picture [192 x 121] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDS<br>90%<br>WN<br>10%<br>[\_<br>VGS |l vl >|ey,Lael<br>td(on) tr td(off) tf<br>**----- End of picture text -----**<br>


**==> picture [167 x 10] intentionally omitted <==**

**----- Start of picture text -----**<br>
Fig 25b.   Switching Time Waveforms<br>**----- End of picture text -----**<br>


**==> picture [162 x 131] intentionally omitted <==**

**----- Start of picture text -----**<br>
Id<br>Vds<br>Vgs<br>i<br>|<br>Vgs(th)<br>Qgs1 Qgs2 Qgd Qgodr<br>**----- End of picture text -----**<br>


**Fig 26b.** Gate Charge Waveform 

AUIRFB/S/SL8409 

TO-220AB packages are not recommended for Surface Mount Application. 

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ 

AUIRFB/S/SL8409 

## TO-262 Package Outline Dimensions are shown in millimeters (inches) 

## TO-262 Part Marking Information 

AUIRFB/S/SL8409 

Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ 

AUIRFB/S/SL8409 ~~—~~ 

Dimensions are shown in millimeters (inches) 

**==> picture [438 x 182] intentionally omitted <==**

**----- Start of picture text -----**<br>
TRR<br>o0° Oo<br>1.60 (.063)<br>1.50 (.059)<br>1.60 (.063)<br>4.10 (.161)<br>3.90 (.153) 1.50 (.059) 0.368 (.0145)<br>| Wey | Lo : ~T 0.342 (.0135)<br>o—______+ ooo SO 4) -<br>FEED DIRECTION 1.85 (.073) 11.60 (.457)<br>1.65 (.065) 11.40 (.449) 24.30 (.957)<br>15.42 (.609)<br>23.90 (.941)<br>15.22 (.601)<br>TRL<br>| XN<br>1.75 (.069)<br>10.90 (.429) 1.25 (.049)<br>10.70 (.421) 4.72 (.136)<br>16.10 (.634) 4.52 (.178)<br>15.90 (.626)<br>a i | ir<br>**----- End of picture text -----**<br>


FEED DIRECTION 

**==> picture [428 x 196] intentionally omitted <==**

**----- Start of picture text -----**<br>
13.50 (.532) 27.40 (1.079)<br>‘ 12.80 (.504) 23.90 (.941)<br>4<br>330.00 60.00 (2.362)<br>7) (14.173) al g       MIN.<br>  MAX.<br>‘<br>30.40 (1.197)<br>NOTES :       MAX.<br>1.   COMFORMS TO EIA-418.<br>2.   CONTROLLING DIMENSION: MILLIMETER. 26.40 (1.039)24.40 (.961) TE 4<br>3.   DIMENSION MEASURED @ HUB.<br>3<br>**----- End of picture text -----**<br>


4.   INCLUDES FLANGE DISTORTION @ OUTER EDGE. 

AUIRFB/S/SL8409 

## **† Qualification Information** 

|**Qualification Information**<br>**†**|**Qualification Information**<br>**†**|||
|---|---|---|---|
|**Qualification Level**||Automotive<br>(per AEC-Q101)||
|||Comments: This part number(s) passed Automotive qualification. IR’s<br>Industrial and Consumer qualification level is granted by extension of the<br>higher Automotive level.||
|||D<br>2PAK|MSL1|
|||TO-220|N/A|
|||TO-262||
|**ESD**|Machine Model|Class M4 (+/- 600V)<br>††<br>AEC-Q101-002||
||Human Body Model|Class H3A (+/- 6000V)<br>††<br>AEC-Q101-001||
||Charged Device Model|Class C5 (+/- 2000V)<br>††<br>AEC-Q101-005||
|**RoHS Compliant**||Yes||



AUIRFB/S/SL8409 

## **����������������** 

Unless specifically designated for the automotive market, International Rectifier Corporation and its subsidiaries (IR) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or services without notice. Part numbers designated with the “AU” prefix follow automotive industry and / or customer specific requirements with regards to product discontinuance and process change notification. All products are sold subject to IR’s terms and conditions of sale supplied at the time of order acknowledgment. 

IR warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with IR’s standard warranty.  Testing and other quality control techniques are used to the extent IR deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. 

IR assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using IR components. To minimize the risks with customer products and applications, customers should provide adequate design and operating safeguards. 

Reproduction of IR information in IR data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices.  Reproduction of this information with alterations is an unfair and deceptive business practice.  IR is not responsible or liable for such altered documentation.  Information of third parties may be subject to additional restrictions. 

Resale of IR products or serviced with statements different from or beyond the parameters stated by IR for that product or service voids all express and any implied warranties for the associated IR product or service and is an unfair and deceptive business practice.  IR is not responsible or liable for any such statements. 

IR products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or in other applications intended to support or sustain life, or in any other application in which the failure of the IR product could create a situation where personal injury or death may occur.  Should Buyer purchase or use IR products for any such unintended or unauthorized application, Buyer shall indemnify and hold International Rectifier and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that IR was negligent regarding the design or manufacture of the product. 

Only products certified as military grade by the Defense Logistics Agency (DLA) of the US Department of Defense, are designed and manufactured to meet DLA military specifications required by certain military, aerospace or other applications. Buyers acknowledge and agree that any use of IR products not certified by DLA as military-grade, in applications requiring military grade products, is solely at the Buyer’s own risk and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. 

IR products are neither designed nor intended for use in automotive applications or environments unless the specific IR products are designated by IR as compliant with ISO/TS 16949 requirements and bear a part number including the designation “AU”. Buyers acknowledge and agree that, if they use any non-designated products in automotive applications, IR will not be responsible for any failure to meet such requirements. 

For technical support, please contact IR’s Technical Assistance Center 

http://www.irf.com/technical-info/ 

## **WORLD HEADQUARTERS:** 

101 N. Sepulveda Blvd., El Segundo, California 90245 

Tel: (310) 252-7105 

������������������������������������������������������������������������������������������������������������������������������������� 

��