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AUIRFB3806
Power MOSFET, N Channel, 60 V, 43 A, 0.0126 ohm, TO-220AB, Through Hole
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- Manufacturer: INFINEON
- Product type: Single MOSFETs
- No. of Pins: 3Pins
- Channel Type: N Channel
- Power Dissipation: 71W
- Transistor Mounting: Through Hole
- Transistor Polarity: N Channel
- Power Dissipation Pd: 71W
- Rds(on) Test Voltage: 10V
- On Resistance Rds(on): 0.0126ohm
- Transistor Case Style: TO-220AB
- Drain Source Voltage Vds: 60V
- Operating Temperature Max: 175°C
- Continuous Drain Current Id: 43A
- Drain Source On State Resistance: 0.0126ohm
- Gate Source Threshold Voltage Max: 2V
| Delivery and price | |
|---|---|
| Units per pack | 1 |
| Price | 0.258 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
## PD IRFB3806PbF IRFS3806PbF IRFSL3806PbF
## **Applications**
High Efficiency Synchronous Rectification in SMPS
HEXFET Power MOSFET
Uninterruptible Power Supply High Speed Power Switching
|||D||**VDSS**||**60V**|
|---|---|---|---|---|---|---|
||||||||
|||||**RDS(on) typ.**|**typ.**|**12.6m**Ω|
|G||||**max.**|**max.**|**15.8m**Ω|
|||S||**ID **||**43A**|
Hard Switched and High Frequency Circuits
## **Benefits**
Improved Gate, Avalanche and Dynamic dv/dt Ruggedness Fully Characterized Capacitance and Avalanche SOA Enhanced body diode dV/dt and dI/dt Capability
|**Benefits**<br>Improved Gate, Avalanche and Dynamic<br>dv/dt Ruggedness<br>Fully Characterized Capacitance and<br>S<br>**ID **<br>**43**|**3**|**3A**|
|---|---|---|
|Fully Characterized Capacitance and<br>Avalanche SOA<br>D<br>D<br>D|||
|Enhanced body diode dV/dt and dI/dt|||
|Capability<br>S<br>S||S<br>D|
|G<br>D<br>G||G|
|TO-220AB<br>D2Pak||TO-262|
|IRFB3806PbF<br>IRFS3806PbF<br>IRFSL3806PbF|||
||||
|**G**<br>**D**<br>**S**|||
|Gate<br>Drain<br>Source|||
|**Absolute Maximum Ratings**<br>**Symbol**<br>**Parameter**<br>**Units**<br>ID@ TC= 25°C<br>Continuous Drain Current,VGS @ 10V<br>ID@ TC= 100°C<br>Continuous Drain Current, VGS@ 10V<br>A<br>IDM<br>Pulsed Drain Current<br>PD@TC= 25°C<br>Maximum Power Dissipation<br>W<br>Linear DeratingFactor<br>W/°C<br>VGS<br>Gate-to-Source Voltage<br>V<br>dv/dt<br>Peak Diode Recovery<br>V/ns<br>**Max.**<br>43<br>31<br>170<br>71<br>24<br>± 20<br>0.47<br>~~so..nnwn”’-- See~~<br>~~owg~EZ~~<br>~~es~~<br>~~ef~~<br>~~CT~~<br>~~ee~~<br>~~es~~<br>~~esS(O~~<br>~~Ef~~<br>~~ae~~<br>~~I Sn~~<br>~~(I~~|||
|TJ<br>Operating Junction and<br>-55 to + 175||°C|
|TSTG<br>Storage Temperature Range|||
|Soldering Temperature, for 10 seconds<br>300|||
|(1.6mm from case)|||
|Mountingtorque,6-32 or M3 screw<br>**Avalanche Characteristics**<br>10lb in(1.1N m)<br>~~es~~<br>~~I (RU~~|||
|EAS(Thermallylimited)<br>Single Pulse Avalanche Energy<br>mJ<br>IAR<br>Avalanche Current<br>A<br>EAR<br>Repetitive Avalanche Energy<br>mJ<br>73<br>25<br>7.1<br>~~SS~~<br>~~ee~~<br>~~es Rn~~<br>~~es~~|||
|**Thermal Resistance**<br>**Symbol**<br>**Parameter**<br>**Typ.**<br>**Max.**<br>RθJC<br>Junction-to-Case<br>–––<br>2.12<br>RθCS<br>Case-to-Sink,Flat Greased Surface,TO-220<br>0.50<br>–––<br>RθJA<br>Junction-to-Ambient,TO-220<br>–––<br>62<br>RθJA<br>Junction-to-Ambient (PCB Mount) , D2Pak<br>–––<br>40<br>~~Le~~<br>~~PC~~<br>~~Oe~~<br>~~esRe~~<br>~~Pe~~<br>~~fe~~<br>~~c}tntrxy*."~~||**Units**<br>°C/W|
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02/29/08
**Static @ TJ = 25°C (unless otherwise specified)**
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||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|(QO|Symbol|Parameter|Min.|Typ.|Max.|Units|Conditions|
|Rs|V(BR)DSS|(DQG|Drain-to-Source Breakdown Voltage|60|OD|–––|GOO|–––|V|VGS = 0V, ID = 250µA|
|∆V(BR)DSS/∆TJ|Breakdown Voltage Temp. Coefficient|–––|0.075|–––|V/°C|Reference to 25°C, ID = 5mA|
|Re|QO|
|es|RDS(on)|GOGO|Static Drain-to-Source On-Resistance|QO|–––|OG|12.6|GO|15.8|QO|mΩ|VGS = 10V, I|©|D = 25A|
|sD|VGS(th)|Gate Threshold Voltage|GOOD|2.0|–––|GO|4.0|CO|V|VDS = VGS, ID = 50µA|
|IDSS|Drain-to-Source Leakage Current|–––|–––|20|µA|VDS = 60V, VGS = 0V|
|=Pt|–––|–––|250|VDS = 48V, VGS = 0V, TJ = 125°C|
|IGSS|Gate-to-Source Forward Leakage|–––|–––|100|nA|VGS = 20V|
|——————————————es|Gate-to-Source Reverse Leakage|–––|es|–––|es|-100|VGS = -20V|
|Dynamic @ TJ = 25°C (unless otherwise specified)|
|Symbol|Parameter|Min.|Typ.|Max.|Units|Conditions|
|asGD|
|Rs|gfs|en|Forward Transconductance|41|–––|GO|–––|GO|S|VDS = 10V, ID = 25A|
|Qg|Total Gate Charge|–––|22|30|nC|ID = 25A|
|es|Gn|nDGO|GO|
|Qgs|Gate-to-Source Charge|–––|5.0|–––|VDS = 30V|
|esee|
|Qgd|Gate-to-Drain ("Miller") Charge|–––|6.3|–––|VGS = 10V|
|esee|
|Qsync|Total Gate Charge Sync. (Qg - Qgd)|–––|28.3|–––|ID = 25A, VDS =0V, VGS = 10V|
|es|ee|@|
|Rs|RG(int)|en|Internal Gate Resistance|ee|–––|0.79|–––|Ω|
|td(on)|Turn-On Delay Time|–––|6.3|–––|ns|VDD = 39V|
|es|Gn|nDGO|GO|
|tr|Rise Time|–––|40|–––|ID = 25A|
|aeee|
|td(off)|Turn-Off Delay Time|–––|49|–––|RG = 20Ω|
|ee|
|tf|Fall Time|–––|47|–––|VGS = 10V|
|ee|@|
|Ciss|Input Capacitance|–––|1150|–––|VGS = 0V|
|ee|
|Coss|Output Capacitance|–––|130|–––|VDS = 50V|
|ee|
|Crss|Reverse Transfer Capacitance|–––|67|–––|pF|ƒ = 1.0MHz|
|esee|
|Coss eff. (ER)|Effective Output Capacitance (Energy Related)|–––|190|–––|VGS = 0V, VDS = 0V to 60V|
|ee>|
|Coss eff. (TR)|Effective Output Capacitance (Time Related)|–––|230|–––|VGS = 0V, VDS = 0V to 60V|
|ee|ee|PO|
|Diode Characteristics|
|(QO|Symbol|Parameter|Min.|Typ.|GOO|Max.|Units|Conditions|
|IS|Continuous Source Current|–––|–––|43|A|MOSFET symbol|D|
|(Body Diode)|showing the|
|ISM|Pulsed Source Current|–––|–––|170|integral reverse|G|
|(Body Diode)|p-n junction diode.|S|
|ee|VSD|Diode Forward Voltage|–––|–––|1.3|V|TJ = 25°C, IS = 25A, VGS = 0V|
|trr|Reverse Recovery Time|–––|22|33|ns|TJ = 25°C|VR = 51V,|
|aPT|–––|26|39|TJ = 125°C|IF = 25A|
|Qrr|Reverse Recovery Charge|–––|17|26|nC|TJ = 25°C|di/dt = 100A/µs|
|=o|–––|24|36|TJ = 125°C|:|
|IRRM|Reverse Recovery Current|–––|1.4|–––|A|TJ = 25°C|
|es|PT|
|es|ton|QRee|Forward Turn-On Time|Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)|
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> Notes: ~~®©~~ Repetitive rating; pulse width limited by max. junction Coss eff. (TR) is a fixed capacitance that gives the same charging time eff. (TR) is a fixed capacitance that gives the same charging time
Repetitive rating; pulse width limited by max. junction temperature.
Coss eff. (TR) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80% VDSS.
@ Limited by TJmax, starting TJ = 25°C, L = 0.23mH ©
Coss eff. (ER) is a fixed capacitance that gives the same energy as
RG = 25Ω, IAS = 25A, VGS =10V. Part not recommended for use above this value.
Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom mended footprint and soldering techniques refer to application note #AN-994. Rθ is measured at TJ approximately 90°C.
ISD ≤ 25A, di/dt ≤ 1580A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C. Pulse width ≤ 400µs; duty cycle ≤ 2%.
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1000<br>VGS<br>TOP 15V<br>10V =a<br>8.0V<br>6.0V<br>5.5V<br>5.0V<br>100 4.8V immaiiil<br>BOTTOM 4.5V<br>10<br>4.5V<br>Ce ee<br>≤60µs PULSE WIDTH<br>Tj = 25°C<br>1 nail<br>0.1 1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>Fig 1. Typical Output Characteristics<br>1000<br>es es ee ee ee<br>100 T He<br>a<br>TJ = 175°C<br>10 n /a<br>TJ = 25°C<br>1 A 7 L<br>VDS = 25V<br>≤60µs PULSE WIDTH<br>0.1 Pp i<br>2 3 4 5 6 7 8 9<br>VGS, Gate-to-Source Voltage (V)<br>Fig 3. Typical Transfer Characteristics<br>10000<br>VGS = 0V, f = 1 MHZ<br>Ciss = Cgs + Cgd, Cds SHORTED<br>Crss = Cgd<br>= Coss = Cds + Cgd<br>Ciss<br>1000<br>=<br>Coss<br>Sai t Crss Salli<br>100<br>P ETRTT<br>H ee TS ll<br>10 EAI LLL<br>1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>ID, Drain-to-Source Current (A)<br>ID, Drain-to-Source Current (A)<br>C, Capacitance (pF)<br>**----- End of picture text -----**<br>
**Fig 5.** Typical Capacitance vs. Drain-to-Source Voltage
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1000<br>VGS<br>TOP 15V<br>10V =<br>8.0V<br>6.0V<br>5.5V<br>5.0V<br>100 4.8V AE<br>BOTTOM 4.5V<br>4.5V<br>10<br>jo |<br>≤60µs PULSE WIDTH<br>Tj = 175°C<br>1 coil TU<br>0.1 1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>Fig 2. Typical Output Characteristics<br>2.5<br>ID = 25A<br>VGS = 10V<br># 86<br>2.0<br>A TT<br>1.5 F LEE LELELVEL LI<br>1.0 H LTpat<br>OpeATLLcnnnanneELL<br>0.5<br>-60 -40 -20 0 20 40 60 80 100120140160180<br>TJ , Junction Temperature (°C)<br>Fig 4. Normalized On-Resistance vs. Temperature<br>12.0<br>ID= 25A<br>10.0 VDS= 48V<br>VDS= 30V {|<br>8.0 VDS= 12V<br>S f<br>6.0<br>a w<br>4.0<br>a e<br>2.0<br>0.0 JY | |[|]<br>0 5 10 15 20 25<br> QG, Total Gate Charge (nC)<br>ID, Drain-to-Source Current (A)<br>RDS(on) , Drain-to-Source On Resistance (Normalized)<br>VGS, Gate-to-Source Voltage (V)<br>**----- End of picture text -----**<br>
**Fig 4.** Normalized On-Resistance vs. Temperature
**Fig 6.** Typical Gate Charge vs. Gate-to-Source Voltage
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1000<br>OPERATION IN THIS AREA<br>LIMITED BY RDS(on)<br>= =<br>100 na 100µsec<br>rs<br>1msec<br>MTR cecil ea FE<br>10<br>10msec<br>1<br>So<br>Tc = 25°C DC ieee<br>Tj = 175°C<br>Single Pulse<br>PS.<br>0.1<br>1 10 100<br>VDS, Drain-to-Source Voltage (V)<br>Fig 8. Maximum Safe Operating Area<br>80<br>Id = 5mA<br>L LY4<br>75<br>T ELL<br>70<br>va<br>A AT.<br>65<br>iV<br>60 ALq LEL ELLE<br>-60 -40 -20 0 20 40 60 80 100120140160180<br>TJ , Temperature ( °C )<br>V(BR)DSS, Drain-to-Source Breakdown Voltage (V)<br>ID, Drain-to-Source Current (A)<br>**----- End of picture text -----**<br>
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1000<br>S SS =<br>100 R g<br>e e<br>TJ = 175°C ees ae eee<br>10<br>TJ = 25°C<br>1<br>ff<br>ee es<br>VGS = 0V<br>P ff t<br>0.1<br>0.0 0.5 1.0 1.5 2.0<br>VSD, Source-to-Drain Voltage (V)<br>ISD, Reverse Drain Current (A)<br>**----- End of picture text -----**<br>
**Fig 7.** Typical Source-Drain Diode Forward Voltage
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45<br>40<br>35 PS OMELRE<br>30<br>25<br>O PN<br>20<br>e e ee eee<br>15<br>P N<br>10 r ey<br>5<br>0 TTTPNEL TN<br>25 50 75 100 125 150 175<br> TC , Case Temperature (°C)<br>ID, Drain Current (A)<br>**----- End of picture text -----**<br>
**Fig 10.** Drain-to-Source Breakdown Voltage
**Fig 9.** Maximum Drain Current vs. Case Temperature
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0.4 300<br>ID<br>0.3 TOP 2.8A<br>250<br>5.1A<br>0.3 BOTTOM 25A<br>T T LL L. 200 N T<br>0.2 pA<br>| a | 150 A<br>0.2<br>100<br>0.1<br>CoE \<br>0.1 fA 50 N ENT<br>| B RE<br>0.0 P e 0 T P BSS<br>-10 0 10 20 30 40 50 60 70 25 50 75 100 125 150 175<br>Starting TJ , Junction Temperature (°C)<br>VDS, Drain-to-Source Voltage (V)<br>EAS , Single Pulse Avalanche Energy (mJ)<br>**----- End of picture text -----**<br>
**Fig 12.** Maximum Avalanche Energy vs. DrainCurrent
**Fig 11.** Typical COSS Stored Energy
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10<br>1 e D = 0.50 e ee ee ——— |<br>e eeee<br>0.20<br>__es a 0.10 ane eneE e ect eeeee]<br>0.1 0.05 R1 R 1 R2 R 2 R3R3 Ri (°C/W) τi (sec)<br>0.02 τJ τJ τCτ 0.6086 0.00026<br>0.01 τ1τ1 τ2 τ2 τ3τ3 0.9926 0.001228<br>— aS ae | | Al<br>r T i | Ci= R τi/Ri RB o 0.5203 0.00812 e<br>0.01 2 cel |e Ci τi/Ri ee<br>Notes:<br>SINGLE PULSE<br>1. Duty Factor D = t1/t2<br>( THERMAL RESPONSE )<br>2. Peak Tj = P dm x Zthjc + Tc<br>co e ||<br>0.001<br>1E-006 1E-005 0.0001 0.001 0.01 0.1<br>t1 , Rectangular Pulse Duration (sec)<br>Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case<br>100<br>FOa EmMmane Duty Cycle = Single Pulse OeHP|ETTTT<br>= 0.01 Allowed avalanche Current vs avalanche |<br>ALUN pulsewidth, tav, assuming ∆Tj = 150°C and nll<br>Tstart =25°C (Single Pulse)<br>10 T TR IK LIP br Hill<br>0.05<br>— LSS I<br>0.10 I NOSE EE<br>COTA RN<br>1 A SS PP<br>ee ee ee es <i en iGo cc ce ee<br>Fae ee A) ee<br>| Allowed avalanche Current vs avalanche ee<br>pulsewidth, tav, assuming ∆Τj = 25°C and<br>Tstart = 150°C.<br>PEaO En|ETI rrr|__| | | | | {|<br>0.1<br>1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01<br>tav (sec)<br>Fig 14. Typical Avalanche Current vs.Pulsewidth<br>80 Notes on Repetitive Avalanche Curves , Figures 14, 15:<br>TOP Single Pulse (For further info, see AN-1005 at www.irf.com)<br>BOTTOM 1.0% Duty Cycle 1. Avalanche failures assumption:<br>ID = 25A Purely a thermal phenomenon and failure occurs at a temperature far in<br>60 N E excess of Tjmax. This is validated for every part type.jmax. This is validated for every part type.. This is validated for every part type.<br>2. Safe operation in Avalanche is allowed as long asTjmaxjmax is not exceeded.<br>3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.<br>4. PD (ave) = Average power dissipation per single avalanche pulse.D (ave) = Average power dissipation per single avalanche pulse.= Average power dissipation per single avalanche pulse.<br>40 AANOSNNO TLE 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase<br>during avalanche).<br>6. Iav = Allowable avalanche current.<br>7. ∆T = Allowable rise in junction temperature, not to exceed∆T = Allowable rise in junction temperature, not to exceedT = Allowable rise in junction temperature, not to exceed = Allowable rise in junction temperature, not to exceedAllowable rise in junction temperature, not to exceed Tjmax jmax (assumed as<br>20 TLENN N UEL 25°C in Figure 14, 15).<br>tav = Average time in avalanche.<br>D = Duty cycle in avalanche = tav ·f<br>ZthJC(D, tav) = Transient thermal resistance, see Figures 13)<br>ELLENNA<br>0<br>PD (ave) = 1/2 ( 1.3·BV·Iav) =D (ave) = 1/2 ( 1.3·BV·Iav) = = 1/2 ( 1.3·BV·Iav) =av) =) = | T/ ZthJCthJC<br>25 50 75 100 125 150 175<br>Iav =av == 2 A T/ [1.3·BV·Zth]th]]<br>Starting TJ , Junction Temperature (°C) EAS (AR) = PD (ave)·tavAS (AR) = PD (ave)·tav = PD (ave)·tavD (ave)·tav·tavav<br>EAR , Avalanche Energy (mJ)<br> thJC ) °C/W<br>Thermal Response ( Z<br>Avalanche Current (A)<br>**----- End of picture text -----**<br>
- Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type.jmax. This is validated for every part type.. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmaxjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.D (ave) = Average power dissipation per single avalanche pulse.= Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche).
7. ∆T = Allowable rise in junction temperature, not to exceed∆T = Allowable rise in junction temperature, not to exceedT = Allowable rise in junction temperature, not to exceed = Allowable rise in junction temperature, not to exceedAllowable rise in junction temperature, not to exceed Tjmax jmax (assumed as 25°C in Figure 14, 15).
**PD (ave) = 1/2 ( 1.3·BV·Iav) =D (ave) = 1/2 ( 1.3·BV·Iav) = = 1/2 ( 1.3·BV·Iav) =av) =) =** | **T/ ZthJCthJC Iav =av == 2** A **T/ [1.3·BV·Zth]th]] EAS (AR) = PD (ave)·tavAS (AR) = PD (ave)·tav = PD (ave)·tavD (ave)·tav·tavav**
**Fig 15.** Maximum Avalanche Energy vs. Temperature
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4.0<br>—<br>3.5<br>3.0<br>S SS<br>PO PN IN<br>2.5 I D = 50µA<br>PSL<br>ID = 250µA<br>2.0 I D = 1.0mA ERNE<br>ID = 1.0A<br>1.5<br>L EE EEH E EENNS<br>1.0<br>-75 -50 -25 0 25 50 75 100 125 150 175 200<br>TJ , Temperature ( °C )<br>VGS(th), Gate threshold Voltage (V)<br>**----- End of picture text -----**<br>
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14<br>IF = 17A<br>12 V R = 51V<br>TJ = 25°C<br>10<br>TJ = 125° C<br>Pe<br>8<br>So e<br>6<br>4 e e<br>2<br>4i mmna<br>0<br>0 200 400 600 800 1000<br>diF /dt (A/µs)<br>IRR (A)<br>**----- End of picture text -----**<br>
**Fig 16.** Threshold Voltage vs. Temperature
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14<br>IF = 25A<br>12 V R = 51V<br>TJ = 25°C<br>10<br>TJ = 125° C<br>8<br>6 ae<br>P T | el<br>4 e t<br>2<br>oe<br>| | |<br>T T<br>0<br>0 200 400 600 800 1000<br>diF /dt (A/µs)<br>IRR (A)<br>**----- End of picture text -----**<br>
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260<br>IF = 17A<br>VR = 51V<br>210<br>TJ = 25°C<br>TJ = 125° C<br>160<br>E RE<br>110<br>y<br>e<br>60<br>a e4n<br>aI<br>e T<br>10<br>|<br>0 200 400 600 800 1000<br>diF /dt (A/µs)<br>QRR (A)<br>**----- End of picture text -----**<br>
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260<br>IF = 25A<br>VR = 51V<br>210<br>TJ = 25°C<br>TJ = 125° C<br>160<br>110<br>60 e T<br>10<br>0 200 400 600 800 1000<br>diF /dt (A/µs)<br>QRR (A)<br>**----- End of picture text -----**<br>
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Driver Gate Drive<br>P.W.<br>Period D =<br>D.U.T + [{ P.W. n d — Period<br>) [©)] • Circuit Layout Considerations lt V | GS=10V<br> •<br>| —| - LowGround Stray Pla I n eductance<br> • CurrentLow LeakageTransformerInductance 2) D.U.T. ISD Waveform<br>+<br>= ReverseRecovery Body Diode Forward \<br>- a - ® + Current r Current di/dt /<br>1) D.U.T. VDS Waveform Diode Recoverydv/dt ‘<br>00 = VDD<br>ma<br>• Re-Applied<br>• Driver same type as D.U.T. + Voltage Body Diode Forward Drop<br>Re ( aA • dv/dt controlled by Rg Vpp -<br>•<br>D.U.T. - Device Under Test er ae<br>Ripple ≤ 5% ISD<br>Isp controlled by Duty Factor "D" @ t<br>* Veg = 5V for Logic Level Devices<br>Fig 20. Peak Diode Recovery dv/dt Test Circuit for N-Channel<br>HEXFET ® Power MOSFETs<br>V(BR)DSS<br>15V < tp ><br>VDS L DRIVER<br>RG D.U.T +<br>- [V][DD]<br>IAS A<br>20VVGS<br>tp O- A 0.01 \A Ω IAS f :<br> Unclamped Inductive Test Circuit Fig 21b. Unclamped Inductive Waveforms<br>LDD<br>VDSDS VDS<br>90%<br>+<br>VDDDD -<br>D.U.T 10%<br>VGSGS VGS<br>Pulse Width < 1µs 1 yay 1<br>Duty Factor < 0.1% td(on) tr td(off) tf<br> Switching Time Test Circuit Fig 22b. Switching Time Waveforms<br>Id<br>Vds<br>Vgs<br>L<br>VCC<br>DUT<br>Vgs(th)<br>1K<br>a: Qgs1 l ey! Qgs2 Qgd Qgodr<br> Gate Charge Test Circuit Fig 23b. Gate Charge Waveform<br>**----- End of picture text -----**<br>
**Fig 21b.** Unclamped Inductive Waveforms
**Fig 21a.** Unclamped Inductive Test Circuit
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LDD<br>VDSDS<br>+<br>VDDDD -<br>D.U.T<br>VGSGS<br>Pulse Width < 1µs<br>Duty Factor < 0.1%<br>Fig 22a. Switching Time Test Circuit<br>L<br>VCC<br>DUT<br>0<br>1K<br>a:<br>**----- End of picture text -----**<br>
**Fig 22a.** Switching Time Test Circuit
**Fig 23a.** Gate Charge Test Circuit
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**Note:** "P" in assembly line position indicates "Lead-Free"
TO-220AB packages are not recommended for Surface Mount Application.
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## TO-262 Package Outline
Dimensions are shown in millimeters (inches)
## TO-262 Part Marking Information
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Dimensions are shown in millimeters (inches)
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TRR<br>1.60 (.063)<br>1.50 (.059)<br>1.60 (.063)<br>4.10 (.161)<br>1.50 (.059)<br>3.90 (.153) 0.368 (.0145)<br>0.342 (.0135)<br>FEED DIRECTION 1.85 (.073) 11.60 (.457)<br>1.65 (.065) 11.40 (.449) 24.30 (.957)<br>15.42 (.609)<br>23.90 (.941)<br>15.22 (.601)<br>TRL<br>1.75 (.069)<br>10.90 (.429) 1.25 (.049)<br>10.70 (.421) 4.72 (.136)<br>16.10 (.634) 4.52 (.178)<br>15.90 (.626)<br>FEED DIRECTION<br>13.50 (.532) 27.40 (1.079)<br>12.80 (.504) 23.90 (.941)<br>4<br>330.00 60.00 (2.362)<br>(14.173) MIN.<br> MAX.<br>30.40 (1.197)<br>NOTES : MAX.<br>1. COMFORMS TO EIA-418.<br>26.40 (1.039) 4<br>2. CONTROLLING DIMENSION: MILLIMETER. 24.40 (.961)<br>3. DIMENSION MEASURED @ HUB.<br>3<br>4. INCLUDES FLANGE DISTORTION @ OUTER EDGE.<br>**----- End of picture text -----**<br>
Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR’s Web site.
**IR WORLD HEADQUARTERS:** 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information **.** 02/08
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Updated at February 9, 2023
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