ADXL380-2BCCZ-RL7

MEMS Accelerometer, ± 4g, ± 8g, ± 16g, X, Y, Z, I2C, LGA, 14 Pins

⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
Manufacturer: ANALOG DEVICES
Product type: MEMS Accelerometers
SVHC: No SVHC (04-Feb-2026)
No. of Pins: 14Pins
Supply Voltage Max: 3.6V
Supply Voltage Min: 2.25V
Operating Temperature Max: 85°C
Operating Temperature Min: -40°C
Sensing Range - Accelerometer: ± 4g, ± 8g, ± 16g
Delivery and price
Units per pack	500
Price	7.04 €
Current stock	1000+
Lead time	30 days
Datasheet
Data Sheet 

**ADXL380** 

**==> picture [111 x 32] intentionally omitted <==**

## Low Noise, Low Power, Wide Bandwidth, 3-Axis MEMS Accelerometer 

## **FEATURES** 

- Ultralow noise density: 20 µ _g_ /√Hz (XY) and 27 µ _g_ /√Hz (Z) 

- Low power consumption 

- High performance: 340 µA 

- Ultra-low power: 33 µA 

- Wide bandwidth: 4 kHz 

- Relative flatness with equalization: <0.5 dB 

- Relative flatness without equalization: <2 dB 

- Low latency: group delay <110 µs 

- Digital features 

- 16-bit ADC 

- Multiprotocol serial interfaces: SPI or I[2] C 

- Multiprotocol audio data output: I[2] S, TDM, and PDM 

- Programmable LPF and HPF 

- Data synchronous or asynchronous sampling 

- Output FIFO: 320 word 

- Built-in features for system-level power savings 

- Single tap, double tap, and triple tap detection 

- Activity and inactivity detection 

- Configurable interrupt modes 

- Integrated temperature sensor 

- Voltage range options 

- VS with internal regulators: 2.25 V to 3.6 V (or V1P8 at 1.8 V) 

- VDDIO: 1.14 V to 3.6 V (1.62 V to 3.6 V for full temperature range) 

- Electromechanical self test 

- 10,000 _g_ mechanical shock survival 

- RoHS compliant 

- Operating temperature range: −40°C to +85°C 

## **GENERAL DESCRIPTION** 

The ADXL380 is a low noise density, low power, 3-axis accelerometer with selectable measurement ranges. The ADXL380 supports the ±4 _g_ , ±8 _g_ , and ±16 _g_ ranges. 

The ADXL380 offers industry leading noise, enabling precision applications with minimal calibration. The low noise and low power ADXL380 enables accurate measurements of audio signals or heart sounds even in high vibration environments. 

The ADXL380 multifunction pin names may be referenced only by their relevant function for either the serial peripheral interface (SPI) or inter-IC(I[2] C) interface, or these pin names can be referenced by their audio function (pulse density modulation (PDM), inter-IC sound (I[2] S), or time division multiplexing (TDM)). 

In addition to its low power consumption, the ADXL380 has many features to enable true system level performance. These features include a built-in micropower temperature sensor, singletap, double tap, and triple tap detection, and a state machine to prevent false triggering. In addition, the ADXL380 has provisions for external control of the sampling time and/or an external clock. 

The ADXL380 operates on a wide, 2.25 V to 3.6 V supply range (or 1.8 V supply) and can interface, if necessary, to a host operating on a separate supply voltage. The ADXL380 is available in a 14-terminal, 2.9 mm × 2.8 mm × 0.87 mm, LGA package. 

## **APPLICATIONS** 

   - Audio and active noise cancellation (ANC) 

   - Robotics 

   - Wearables and low power motion detection 

   - Seismic imaging 

   - Condition-based monitoring 

- 14-terminal, 2.9 mm × 2.8 mm × 0.87 mm, LGA package 

## **FUNCTIONAL BLOCK DIAGRAM** 

**==> picture [358 x 140] intentionally omitted <==**

_**Figure 1. Functional Block Diagram**_ 

Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 

**Rev. 0** 

**DOCUMENT FEEDBACK TECHNICAL SUPPORT** 

Data Sheet 

**ADXL380** 

## **TABLE OF CONTENTS** 

Features................................................................ 1 General Description...............................................1 Applications........................................................... 1 Functional Block Diagram......................................1 Specifications........................................................ 4 Timing Specifications......................................... 7 Digital Timing Diagrams................................... 10 Absolute Maximum Ratings.................................12 Thermal Resistance......................................... 12 Recommended Soldering Profile......................12 ESD Caution.....................................................12 Pin Configuration and Function Descriptions...... 13 Typical Performance Characteristics...................14 Theory of Operation.............................................22 Mechanical Device Operation.......................... 22 Operating Modes..............................................22 Standby Mode.................................................. 22 Measurement Mode......................................... 22 Selectable Measurement Ranges.................... 22 Digital Output....................................................22 Temperature Sensor.........................................23 Axes of Acceleration Sensitivity....................... 23 Power Sequencing........................................... 23 Power Supply Description................................ 24 Overrange Protection....................................... 24 Self Test............................................................24 Filter................................................................. 25 Noise................................................................ 29 Power Savings Features..................................... 30 Operating Modes..............................................30 Motion Detection.............................................. 31 Activity Detection..............................................31 Inactivity Detection........................................... 31 Linking Activity and Inactivity Detection........... 32 FIFO.................................................................... 33 System-Level Power Savings...........................33 Data Recording and Event Context..................33 FIFO Configuration...........................................34 FIFO Modes..................................................... 34 FIFO Interrupts.................................................34 FIFO Watermark...............................................34 FIFO Ready......................................................34 FIFO Overrun................................................... 34 FIFO Full.......................................................... 34 Communications..................................................35 SPI Instructions................................................ 35 I[2] C Interface..................................................... 35 I[2] S/TDM Interface.............................................36 PDM Interface.................................................. 38 

Additional Features..............................................40 Free Fall Detection...........................................40 Tap Detection................................................... 40 External Clock.................................................. 41 External Trigger................................................41 External Synchronization..................................41 Self Test............................................................45 User Register Protection.................................. 45 Concurrent Operating Modes...........................45 Interrupts.......................................................... 45 Status Flags and Error Handling...................... 45 Latency................................................................47 Low Latency Mode........................................... 47 Serial Communications........................................49 SPI Bus Sharing...............................................49 Register Map....................................................... 50 Analog Devices Device ID Register................. 52 Analog Devices MEMS Device ID Register......53 Part ID Register................................................53 Part ID and Revision ID Register..................... 53 Serial Number 0 Register.................................53 Serial Number 1 Register.................................54 Serial Number 2 Register.................................54 Serial Number 3 Register.................................54 Serial Number 4 Register.................................55 Serial Number 5 Register.................................55 Serial Number 6 Register.................................55 Device Sensor Parameter Registers................56 Status 0 Register (Clear on Read)................... 57 Status 1 Register (Clear on Read)................... 58 Status 2 Register (Clear on Read)................... 59 Status 3 Register (Clear on Read)................... 60 X Axis Data Output Read (High Byte, Bits[15:8]) Register.........................................60 X Axis Data Output Read (Low Byte, Bits[7:0]) Register...........................................61 Y Axis Data Output Read (High Byte, Bits[15:8]) Register.........................................61 Y Axis Data Output Read (Low Byte, Bits[7:0]) Register...........................................61 Z Axis Data Output Read (High Byte, Bits[15:8]) Register.........................................61 Z Axis Data Output Read (Low Byte, Bits[7:0]) Register...........................................62 Temperature Data Output Read (High Byte) Register..........................................................62 Temperature Data Output Read (Low Byte) and Sensor DSM Register..............................62 FIFO Read Data (from FIFO Block) Register...63 

**Rev. 0 | 2 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **TABLE OF CONTENTS** 

FIFO Status Registers......................................63 Miscellaneous 0 (Read Only) Register.............63 Miscellaneous 1 (Read Only) Register.............64 Sensor DSM Register.......................................64 Clock Control Register..................................... 65 OP_MODE Register.........................................65 Digital Enable Register.....................................66 Data Ready and I[2] C Communication Port Configuration Register....................................67 NVM (EFUSE) User Control Register.............. 68 Register Reset..................................................69 Interrupt Pin 0 Enables MAP0 Register............69 Interrupt Pin 0 Enables MAP1 Register............70 Interrupt Pin 1 Enables MAP0 Register............71 Interrupt Pin 1 Enables MAP1 Register............72 FIFO Configuration 0 Register......................... 73 FIFO Configuration 1 Register......................... 74 Serial Port Configuration 0 Register.................74 Serial Port Configuration 1 Register.................75 Serial Port Configuration 2 Register.................75 SYNC and Serial Port Configuration Register..76 PDM Configuration Register.............................77 Activity, Inactivity, and PDM Control Register.. 77 Activity and Inactivity and Self-Test Control Register..........................................................78 Activity Threshold (High Byte) Register............79 Activity Threshold (Low Byte) Register............ 79 Timed Activity (High Byte, Bits[23:16]) Register..........................................................80 Timed Activity (Mid Byte, Bits[15:7]) Register.. 80 Timed Activity (Low Byte, Bits[7:0]) Register... 80 Inactivity Threshold (High Byte) Register.........81 Inactivity Threshold (Low Byte) Register..........81 Timed Inactivity (High Byte, Bits[23:16]) Register..........................................................81 Timed Inactivity (Mid Byte, Bits[15:8]) Register..........................................................82 Timed Inactivity (Low Byte, Bits[7:0]) Register..........................................................82 

Tap Threshold Register.................................... 82 Tap Duration Register.......................................83 Tap Latency Wait Time Register.......................83 Tap Window Register....................................... 83 Tap Configuration Register...............................84 Undervoltage and Overrange Configuration Register..........................................................85 SAR Trigger and Digital Filter Configuration Register..........................................................86 X-Axis SAR User Offset Register.....................87 Y-Axis SAR User Offset Register..................... 87 Z-Axis SAR User Offset Register..................... 87 X-Axis DSM User Offset Register.................... 87 Y-Axis DSM User Offset Register.....................88 Z-Axis DSM User Offset Register.....................88 Digital Filter Configuration Register..................88 User Temperature Sensor Control Registers... 90 MISO and Gain Scaler Configuration Register..........................................................91 SOUT0 Pad Control Register............................. 91 MCLK Pad Register..........................................92 BCLK Pad Register.......................................... 92 FSYNC Pad and Resync Configuration Register..........................................................93 INT0 Pad Control Register............................... 94 INT1 Pad Control Register............................... 95 Applications Information...................................... 96 Application Examples.......................................96 Device Configuration........................................96 Power Supply Requirements..........................100 Interrupts........................................................ 101 Using an External Clock.................................102 Mechanical Considerations for Mounting....... 102 PCB Footprint.................................................102 Outline Dimensions........................................... 103 Ordering Guide...............................................103 Models, Measurement Range, and Communications Interface............................103 Evaluation Boards.......................................... 103 

## **REVISION HISTORY** 

## **8/2024—Revision 0: Initial Version** 

**Rev. 0 | 3 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **SPECIFICATIONS** 

TA = 25°C, supply voltage (VS) = 3.3 V, x-axis and y-axis acceleration = 0 _g_ , z-axis acceleration = 1 _g_ , and full-scale range = ±4 _g,_ , and high performance (HP) mode, unless otherwise noted. 

_**Table 1. Specifications**_ 

|**_Table 1. Specifications_**|**_Table 1. Specifications_**|**_Table 1. Specifications_**|**_Table 1. Specifications_**|
|---|---|---|---|
|**Parameter**<br>**Test Conditions/**<br>**Comments**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**||||
|SENSOR INPUT<br>Full-Scale Range (FSR)<br>Nonlinearity1,2<br>Total Harmonic Distortion (THD)<br>Cross-Axis Sensitivity3<br>Sensor Resonant Frequency4<br>Quality Factor4|Each axis<br>User selectable<br>Percentage of full<br>scale range (FSR)<br>±4_g_, ±8_g_<br>±16_g_<br>3.57_g_at 1 kHz<br>X-axis and Y-axis<br>Z-axis<br>X-axis and Y-axis<br>Z-axis|±4, ±8, ±16<br>±0.1<br>±0.4<br>0.1<br>±2<br>±2.5<br>5.1<br>3.8<br>2.2<br>1.2|g<br>%FSR<br>%FSR<br>%FSR<br>%<br>kHz<br>kHz|
|SENSITIVITY<br>Sensitivity<br>Scale Factor<br>Sensitivity Error at 25°C<br>Sensitivity Change due to Temperature|Each axis<br>±4_g_<br>±8_g_<br>±16_g_<br>±4_g_<br>±8_g_<br>±16_g_<br>X-axis and Y-axis<br>Z-axis<br>TA= −40°C to +85°C|7500<br>3750<br>1875<br>133.3<br>266.7<br>533.3<br>±1.6<br>±1.8<br>±0.02|LSB/_g_<br>LSB/_g_<br>LSB/_g_<br>µ_g_/LSB<br>µ_g_/LSB<br>µ_g_/LSB<br>%<br>%<br>%/°C|
|OUTPUT RESOLUTION<br>All_g_Ranges|Each axis<br>Σ-Δ modulator, DSM<br>(high performance)<br>SAR (low power)5|16<br>12|Bits<br>Bits|
|0_g_OFFSET<br>0_g_Output for XOUT, YOUT, and ZOUT<br>1,6<br>0_g_Offset vs. Temperature<br>Bias Repeatability7<br>Vibration Rectification Error (VRE)|Each axis<br>TA= −40°C to +85°C<br>X-axis and Y-axis<br>Z-axis<br>Offset due to 2.5_g_<br>RMS vibration, in 1_g_<br>field|−250<br>±60<br>+250<br>1.0<br>100<br>120<br>28|m_g_<br>m_g_/°C<br>µ_g_<br>µ_g_<br>m_g_|
|NOISE PERFORMANCE<br>Noise Density<br>High Performance (HP) Mode8<br>Reduced Bandwidth (RBW) Mode<br>Low Power (LP) Mode<br>Very Low Power (VLP) Mode|X-axis and Y-axis<br>Z-axis<br>X-axis and Y-axis<br>Z-axis<br>X-axis and Y-axis<br>Z-axis<br>X-axis and Y-axis<br>Z-axis|20<br>27<br>23<br>29<br>39<br>49<br>94<br>97|µ_g_/√Hz<br>µ_g_/√Hz<br>µg/√Hz<br>µ_g_/√Hz<br>µ_g_/√Hz<br>µ_g_/√Hz<br>µ_g_/√Hz<br>µ_g_/√Hz|



**Rev. 0 | 4 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **SPECIFICATIONS** 

_**Table 1. Specifications (Continued)**_ 

|**_Table 1. Specifications(Continued)_**|**_Table 1. Specifications(Continued)_**|**_Table 1. Specifications(Continued)_**|**_Table 1. Specifications(Continued)_**|
|---|---|---|---|
|**Parameter**<br>**Test Conditions/**<br>**Comments**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**||||
|Ultra-Low Power (ULP) Mode<br>HS Mode<br>Output Noise9<br>HP Mode<br>RBW Mode<br>LP Mode<br>VLP Mode<br>ULP Mode<br>Heart Sounds (HS) Mode<br>Velocity Random Walk (VRW)<br>Bias Stability|X-axis and Y-axis<br>Z-axis<br>X-axis and Y-axis<br>Z-axis<br>X-axis and Y-axis<br>Z-axis<br>X-axis and Y-axis<br>Z-axis<br>X-axis and Y-axis<br>Z-axis<br>X-axis and Y-axis<br>Z-axis<br>X-axis and Y-axis<br>Z-axis<br>X-axis and Y-axis<br>Z-axis<br>X-axis and Y-axis<br>Z-axis<br>All axes|160<br>160<br>66<br>71<br>1.3<br>1.7<br>1.0<br>1.3<br>1.2<br>1.5<br>2.1<br>2.2<br>1.2<br>1.2<br>1.5<br>1.6<br>10<br>12<br>6.5|µ_g_/√Hz<br>µ_g_/√Hz<br>µ_g_/√Hz<br>µ_g_/√Hz<br>m_g_RMS<br>m_g_RMS<br>m_g_RMS<br>m_g_RMS<br>m_g_RMS<br>m_g_RMS<br>m_g_RMS<br>m_g_RMS<br>m_g_RMS<br>m_g_RMS<br>m_g_RMS<br>m_g_RMS<br>mm/sec/√hr<br>mm/sec/√hr<br>μ_g_|
|BANDWIDTH<br>Bandwidth (−3 dB Corner)<br>HP Mode<br>RBW Mode<br>LP Mode<br>VLP Mode<br>ULP Mode<br>HS Mode<br>Relative Flatness<br>HP Mode<br>Without Digital Correction (<2.5 kHz)<br>With Digital Correction (<3.8 kHz)<br>RBW Mode<br>Without Digital Correction (<2 kHz)|All configurable filters<br>set to default<br>X-axis and Y-axis<br>Z-axis<br>X-axis and Y-axis<br>Z-axis<br>X-axis and Y-axis<br>Z-axis|4000<br>2000<br>1000<br>500<br>50<br>400<br>2<br>2<br>0.5<br>0.5<br>0.5<br>1|Hz<br>Hz<br>Hz<br>Hz<br>Hz<br>Hz<br>dB<br>dB<br>dB<br>dB<br>dB<br>dB|
|SELF TEST<br>Self-Test Delta (STΔ)10|X-axis and Y-axis<br>Z-axis|2.5<br>4.0<br>5.5<br>2.0<br>3.0<br>3.8|_g_<br>_g_|
|POWER SUPPLY<br>Operating Voltage Range (VS)<br>Input and Output Voltage Range (VDDIO)<br>V1P8with Internal Low Dropout Regulator (LDO) Bypassed<br>Supply Reset Threshold (VRESET)<br>Hold Time|TA= −25°C to +85°C<br>TA= −40°C to +85°C<br>VSUPPLY= 0 V|2.25<br>3.6<br>1.14<br>3.6<br>1.62<br>3.6<br>1.62<br>1.8<br>1.98<br>1.2<br>1|V<br>V<br>V<br>V<br>V<br>ms|



**Rev. 0 | 5 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **SPECIFICATIONS** 

_**Table 1. Specifications (Continued)**_ 

|**_Table 1. Specifications(Continued)_**|**_Table 1. Specifications(Continued)_**|**_Table 1. Specifications(Continued)_**|**_Table 1. Specifications(Continued)_**|
|---|---|---|---|
|**Parameter**<br>**Test Conditions/**<br>**Comments**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**||||
|Rise Time<br>Supply Current11<br>HP Mode<br>RBW Mode<br>LP Mode<br>VLP Mode<br>ULP Mode<br>HS Mode<br>Standby<br>Turn-On Time12<br>Standby to Valid Data Time<br>Power-Up to Standby|0 V to 90% of VS<br>LDO enabled|4<br>340<br>250<br>140<br>44<br>33<br>32<br>6.8<br>2<br>3|ms<br>µA<br>µA<br>µA<br>µA<br>µA<br>µA<br>µA<br>ms<br>ms|
|CLOCK<br>Internal Oscillator||512|kHz|
|DELAYS<br>Group Delay<br>Default Mode<br>Low Latency Mode13|X-axis and Y-axis<br>Z-axis<br>X-axis and Y-axis<br>Z-axis|710<br>750<br>95<br>110|µs<br>µs<br>µs<br>µs|
|TEMPERATURE SENSOR1,14<br>Output at 25°C<br>Sensitivity<br>Sensitivity Error||550<br>10.2<br>0.06|LSB<br>LSB/°C<br>%|
|ENVIRONMENTAL<br>Operating Temperature Range||−40<br>+85|°C|



- 1 Typical value based on characterization, not tested in production. 

- 2 Nonlinearity is measured with a DC input stimulus. 

- 3 Cross-axis sensitivity is defined as coupling between any two axes. Typical value based on characterization, not tested in production. 

- 4 Typical value defined based on design and simulation. It is not tested in production. 

- 5 Note that the lower 4 bits of the SAR are zeros, which is to match the 16-bit DSM. 

- 6 Different supplies and measurement range settings can cause a shift in performance. 

- 7 Repeatability provides an estimate for long-term drift in the bias, as observed during 500 hours of high-temperature operating life (HTOL) at 105°C and 1000 cycles of temperature cycle testing (TCT). Repeatability represents the root sum square (RSS) of the bias drift associated with HTOL and TCT. 

- 8 Noise density values with equalization filter enabled. 

- 9 RMS noise with default bandwidth setting used for each power mode. 

- 10 Self-test change is defined as the positive self-test output (when the positive beam deflection is asserted) minus the negative self-test output (when the negative beam deflection is asserted). Different supplies and _g_ ranges cause different self-test changes. 

- 11 Supply current is measured with default configurations with XYZ channels enabled. Supply current may increase when additional features (temperature sensor, first in, first out (FIFO), or external analog-to-digital converter (ADC) for example) are enabled. 

- 12 Refer to the Power Supply Requirements section for the minimum supply rise time requirement. 

- 13 Low latency mode bypasses optional filters. See the Latency section for more information including configuration settings. 

- 14 Nominal values for temperature sensor output with HIGH_GAIN_TEMP = 0. 

**Rev. 0 | 6 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **SPECIFICATIONS** 

## **TIMING SPECIFICATIONS** 

_**Table 2. I[2] C Input and Output Levels and Timing (TA = 25°C, VS = 3.3 V, and VDDIO = 3.3 V)[1]**_ 

|**_Table 2. I2C Input and Output Levels and Timing (TA = 25°C, VS = 3.3_**|**_Table 2. I2C Input and Output Levels and Timing (TA = 25°C, VS = 3.3_**|**_Table 2. I2C Input and Output Levels and Timing (TA = 25°C, VS = 3.3_**|**_V, and VDDIO = 3.3 V) 1_**|**_V, and VDDIO = 3.3 V) 1_**|**_V, and VDDIO = 3.3 V) 1_**|
|---|---|---|---|---|---|
|**Parameter**<br>**Symbol**<br>**Test Conditions/**<br>**Comments**|||**I2C_HSM_EN = 0**<br>**(Fast Mode)**<br>**I2C_HSM_EN = 1**<br>**(High Speed Mode)**|||
||||**Min**<br>**Max**<br>**Min**<br>**Max**<br>**Unit**|||
|DC INPUT LEVELS<br>Input Voltage<br>Low Level<br>High Level<br>Hysteresis of Schmitt Trigger<br>Inputs<br>Input Current|VIL<br>VIH<br>VHYS<br>IIL|0.1 × VDDIO< VIN<<br>0.9 × VDDIO|0.3 × VDDIO<br>0.7 × VDDIO<br>0.05 × VDDIO<br>−10<br>+10|0.3 × VDDIO<br>0.7 × VDDIO<br>0.1 × VDDIO|V<br>V<br>V<br>µA|
|DC OUTPUT LEVELS<br>Output Voltage<br>Low Level<br>Output Current<br>Low Level|VOL<br>VOL1<br>VOL2<br>VIH<br>IOL|Low level current<br>(IOL) = 7 mA<br>VDDIO> 2 V<br>VDDIO≤ 2 V<br>VOL= 0.4 V<br>VOL= 0.6 V|0.4<br>0.2 × VDDIO<br>0.7 × VDDIO<br>20<br>6|0.7 × VDDIO|V<br>V<br>V<br>mA<br>mA|
|AC INPUT LEVELS<br>SCL Frequency<br>SCL High Time<br>SCL Low Time<br>Start Setup Time<br>Start Hold Time<br>SDA Setup Time<br>SDA Hold Time<br>Stop Setup Time<br>Bus Free Time<br>SCL Input Rise Time<br>SCL Input Fall Time<br>SDA Input Rise Time<br>SDA Input Fall Time<br>Width of Spike to Suppress|tHIGH<br>tLOW<br>tSUSTA<br>tHDSTA<br>tSUDAT<br>tHDDAT<br>tSUSTO<br>tBUF<br>tRCL<br>tFCL<br>tRDA<br>tFDA<br>tSP|Not shown in Figure|0.01<br>1<br>260<br>500<br>260<br>260<br>50<br>0<br>360<br>500<br>120<br>120<br>120<br>120<br>50|0.01<br>3.4<br>60<br>160<br>160<br>160<br>10<br>0<br>160<br>80<br>80<br>160<br>160<br>10|MHz<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns|
|AC OUTPUT LEVELS<br>Propagation Delay<br>Data<br>Acknowledge<br>Output Fall Time|tVDDAT<br>tVDACK<br>tF|Load capacitance<br>(CLOAD) = 500 pF<br>Not shown in Figure|97<br>450<br>450<br>20 × (VDDIO/5.5)<br>120|27<br>135|ns<br>ns<br>ns|



> 1 Timing may be different with I2C_SDA_SLOW enabled. 

**Rev. 0 | 7 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **SPECIFICATIONS** 

_**Table 3. SPI Digital Input and Output (TA = 25°C, VS = 3.3 V, and VDDIO = 3.3 V)**_ 

|**_Table 3. SPI Digital Input and Output(TA = 25°C, VS = 3.3 V, and VDDIO = 3.3 V)_**|**_Table 3. SPI Digital Input and Output(TA = 25°C, VS = 3.3 V, and VDDIO = 3.3 V)_**|**_Table 3. SPI Digital Input and Output(TA = 25°C, VS = 3.3 V, and VDDIO = 3.3 V)_**|||
|---|---|---|---|---|
|**Parameter**<br>**Symbol**<br>**Test Conditions/Comments**|||**Limit1**<br>**Unit**<br>**Min**<br>**Max**||
|DIGITAL INPUT<br>Low Level Input Voltage<br>High Level Input Voltage<br>Low Level Input Current<br>High Level Input Current|VIL<br>VIH<br>IIL<br>IIH|Input voltage (VIN) = VDDIO<br>VIN= 0 V|0.3 × VDDIO<br>0.7 × VDDIO<br>−0.1<br>0.1|V<br>V<br>µA<br>µA|
|DIGITAL OUTPUT<br>Low Level Output Voltage<br>High Level Output Voltage<br>Low Level Output Current<br>High Level Output Current|VOL<br>VOH<br>IOL<br>IOH|IOL= IOL, MIN<br>IOH= IOH, MAX<br>VOL= VOL, MAX<br>VOH= VOH, MIN|0.2 × VDDIO<br>0.8 × VDDIO<br>1<br>−2|V<br>V<br>mA<br>mA|



> 1 Limits based on characterization results, not production tested. 

_**Table 4. SPI Timing (TA = 25°C, VS = 3.3 V, and VDDIO = 3.3 V)**_ 

|**Parameter**|**Limit1, 2, 3**<br>**Unit**<br>**Description**<br>**Min**<br>**Max**|**Limit1, 2, 3**<br>**Unit**<br>**Description**<br>**Min**<br>**Max**|**Limit1, 2, 3**<br>**Unit**<br>**Description**<br>**Min**<br>**Max**|
|---|---|---|---|
|fCLK<br>tCSS<br>tCSH<br>tCSD<br>tSU<br>tHD<br>tHIGH<br>tLOW<br>tCLE<br>tV<br>tDIS|0.1<br>8<br>100<br>0.02<br>1000<br>20<br>20<br>20<br>50<br>50<br>25<br>0<br>50<br>0<br>25|MHz<br>ns<br>µs<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns|Clock frequency<br>CS setup time<br>CS hold time<br>CS disable time<br>Data setup time<br>Data hold time<br>Clock high time<br>Clock low time<br>Clock enable time<br>Output valid from clock low (not shown in timing diagrams)<br>Output disable time (not shown in timing diagrams)|



> 1 Limits based on design targets; not production tested. 

- 2 The timing values are measured corresponding to the input thresholds (VIL and VIH) given in Table 3. 

- 3 Maximum loading should not exceed 12 pF. 

_**Figure 2. SPI Timing Diagram–Single-Byte Read**_ 

_**Figure 3. SPI Timing Diagram–Single-Byte Write**_ 

**Rev. 0 | 8 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **SPECIFICATIONS** 

**==> picture [245 x 60] intentionally omitted <==**

_**Figure 4. SPI Timing Diagram–Multibyte Read**_ 

**==> picture [245 x 60] intentionally omitted <==**

_**Figure 5. SPI Timing Diagram–Multibyte Write**_ 

_**Table 5. I[2] S, TDM, and PDM Timing (TA = 25°C, VS = 3.3 V, and VDDIO = 3.3 V)**_ 

|**_Table 5. I2S, TDM, and PDM Timing (TA = 25°C, VS = 3.3 V, and VDDIO = 3.3 V)_**|**_Table 5. I2S, TDM, and PDM Timing (TA = 25°C, VS = 3.3 V, and VDDIO = 3.3 V)_**|**_Table 5. I2S, TDM, and PDM Timing (TA = 25°C, VS = 3.3 V, and VDDIO = 3.3 V)_**|**_Table 5. I2S, TDM, and PDM Timing (TA = 25°C, VS = 3.3 V, and VDDIO = 3.3 V)_**|
|---|---|---|---|
|**Parameter**<br>**Min**<br>**Max**<br>**Unit**<br>**Description**||||
|SERIAL PORT<br>tBL<br>tBH<br>fBCLK<br>tLS<br>tLH<br>fSYNC<br>tTS<br>tSOD<br>tSOTD<br>tSOTX|18<br>18<br>0.512<br>12.288<br>3<br>5<br>2<br>48<br>6<br>0<br>30<br>0<br>80<br>0<br>15<br>0<br>15|ns<br>ns<br>MHz<br>ns<br>ns<br>kHz<br>ns<br>ns<br>ns<br>ns<br>ns|BCLK low pulse width (controller and subordinate modes)<br>BCLK high pulse width (controller and subordinate modes)<br>BCLK frequency<br>FSYNC setup, time to BCLK rising (subordinate mode)<br>FSYNC hold, time from BCLK rising (subordinate mode)<br>FSYNC frequency<br>BCLK falling to FSYNC timing skew (controller mode)<br>SOUTxdelay, time from BCLK falling (controller and subordinate modes), VDDIO<br>at 1.62 V minimum<br>SOUTxdelay, time from BCLK falling (controller and subordinate modes), VDDIO<br>at 1.14 V minimum<br>BCLK falling to SOUTxdriven in tristate mode<br>BCLK falling to SOUTxtristated in tristate mode|
|PDM OUTPUT<br>fPDM_CLK<br>tHOLD|0.512<br>12.288<br>35<br>46|MHz<br>ns|PDM clock frequency<br>PDM data hold time|



**Rev. 0 | 9 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **SPECIFICATIONS** 

## **DIGITAL TIMING DIAGRAMS** 

**==> picture [41 x 48] intentionally omitted <==**

**==> picture [252 x 117] intentionally omitted <==**

_**Figure 6. I[2] S/TDM Serial Output Port Timing Diagram**_ 

_**Figure 7. SPI Port Timing Diagram**_ 

_**Figure 8. Timing Diagram for SPI Send Instructions**_ 

_**Figure 9. I[2] C Port Timing Diagram**_ 

**Rev. 0 | 10 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **SPECIFICATIONS** 

**==> picture [296 x 33] intentionally omitted <==**

_**Figure 10. PDM Output Timing Diagram**_ 

**Rev. 0 | 11 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **ABSOLUTE MAXIMUM RATINGS** 

_**Table 6. Absolute Maximum Ratings**_ 

|**_Table 6. Absolute Maximum Ratings_**|**_Table 6. Absolute Maximum Ratings_**|
|---|---|
|**Parameter**<br>**Rating**||
|Mechanical Shock (Any Axis, 0.2 ms)<br>VS<br>VDDIO<br>V1P8Configured as Input<br>Digital Inputs(FSYNC, SCLK/SCL, SDI/SDA,<br>SDO/ASEL0,<br>CS/ASEL1, SOUT0, SOUT1/MCLK,<br>and BCLK)<br>Temperature Range (Storage)|10,000_g_<br>−0.3 V to +4.0 V<br>−0.3 V to +4.0 V<br>−0.3 V to +2.0 V<br>−0.3 V to VDDIO+ 0.3 V<br>−55°C to +150°C|



Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. 

## **THERMAL RESISTANCE** 

Thermal performance is directly linked to PCB design and operating environment. Careful attention to PCB thermal design is required. 

Thermal resistance values specified in Table 7 are simulated based on JEDEC specs (unless specified otherwise) and should be used in compliance with JESD51-12. 

θJA is the natural convection junction-to-ambient thermal resistance measured in a one cubic foot sealed enclosure, θJC is the junction-to-case thermal resistance, ΨJT is the junction-to-top of the package thermal resistance, and ΨJB is the junction-to-bottom of the package thermal resistance. 

_**Table 7. Package Characteristics**_ 

|**_Table 7. Package Characteristics_**|**_Table 7. Package Characteristics_**|**_Table 7. Package Characteristics_**|**_Table 7. Package Characteristics_**|**_Table 7. Package Characteristics_**|**_Table 7. Package Characteristics_**|
|---|---|---|---|---|---|
|**Package Type**<br>**θJA**<br>**θJC**<br>**ΨJT**<br>**ΨJB**<br>**Unit**||||||
|CC-14-3|71.3|46.0|2.9|47.0|°C/W|



## **RECOMMENDED SOLDERING PROFILE** 

Figure 11 and Table 8 provide details about the recommended soldering profile. 

**==> picture [205 x 116] intentionally omitted <==**

_**Figure 11. Recommended Soldering Profile**_ 

_**Table 8. Recommended Soldering Profile**_ 

|**Profile Feature**|**Condition**|**Condition**|
|---|---|---|
||**Sn63/Pb37**<br>**Pb-Free**||
|Average Ramp Rate (TLto TP)<br>Preheat<br>Minimum Temperature (TSMIN)<br>Maximum Temperature (TSMAX)<br>Time (TSMINto TSMAX)(tS)<br>TSMAXto TLRamp-Up Rate<br>Time Maintained Above<br>Liquidous (TL)<br>Liquidous Temperature (TL)<br>Time (tL)<br>Peak Temperature (TP)<br>Time Within 5°C of Actual Peak<br>Temperature (tP)<br>Ramp-Down Rate<br>Time 25°C to Peak Temperature|3°C/sec maximum<br>100°C<br>150°C<br>60 sec to 120 sec<br>3°C/sec maximum<br>183°C<br>60 sec to 150 sec<br>240 + 0/−5°C<br>10 sec to 30 sec<br>6°C/sec maximum<br>6 minutes maximum|3°C/sec maximum<br>150°C<br>200°C<br>60 sec to 180 sec<br>3°C/sec maximum<br>217°C<br>60 sec to 150 sec<br>260 + 0/−5°C<br>20 sec to 40 sec<br>6°C/sec maximum<br>8 minutes max|



## **ESD CAUTION** 

**ESD (electrostatic discharge) sensitive device** . Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. 

**Rev. 0 | 12 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **PIN CONFIGURATION AND FUNCTION DESCRIPTIONS** 

**==> picture [121 x 136] intentionally omitted <==**

_**Figure 12. Pin Configuration (Top View)**_ 

_**Table 9. Pin Function Descriptions**_ 

|**Pin No.**<br>**Mnemonic**|**Pin No.**<br>**Mnemonic**|**Description**|**Description**|**Description**|**Description**|
|---|---|---|---|---|---|
|||**SPI**<br>**I2S/TDM**<br>**I2C**<br>**PDM**||||
|1<br>2<br>3<br>4<br>5<br>6<br>7<br>8<br>9<br>10<br>11<br>12<br>13<br>14|FSYNC<br>SCLK/SCL<br>SDI/SDA<br>SDO/ASEL0<br>CS/ASEL1<br>INT0<br>INT1<br>V1P8<br>GND<br>VS<br>VDDIO<br>SOUT0<br>SOUT1/ MCLK<br>BCLK|Interrupt Input in FIFO Trigger<br>Mode (Optional)<br>SPI, Clock (SCLK)<br>SPI, Serial Data Input (SDI)<br>SPI, Serial Data Output (SDO)<br>SPI, Chip Select<br>Interrupt 0<br>Interrupt 1<br>Internally Regulated Voltage<br>(External 1.8 V When VS<br>Grounded)<br>Ground<br>Supply Voltage<br>Input and Output Supply<br>Not Applicable<br>Not Applicable<br>Not Applicable|Frame Sync (FSYNC)<br>Not Applicable<br>Not Applicable<br>Not Applicable<br>Not Applicable<br>Interrupt 0<br>Interrupt 1<br>Internally Regulated Voltage<br>(External 1.8 V When VS<br>Grounded)<br>Ground<br>Supply Voltage<br>Input and Output Supply<br>Data Channel 0 (SOUT0)<br>MCLK or Data Channel 1 (SOUT1)<br>Bit Clock (BCLK)|Interrupt Input in FIFO Trigger<br>Mode (Optional)<br>I2C, Serial Clock (SCL)<br>I2C, Serial Data (SDA)<br>I2C, Address Select 0 (ASEL0)<br>I2C, Address Select 1 (ASEL1)<br>Interrupt 0<br>Interrupt 1<br>Internally Regulated Voltage<br>(External 1.8 V When VS<br>Grounded)<br>Ground<br>Supply Voltage<br>Input and Output Supply<br>Not Applicable<br>Not Applicable<br>Not Applicable|SOUT1<br>Not Applicable<br>Not Applicable<br>Not Applicable<br>Not Applicable<br>Interrupt 0<br>Interrupt 1<br>Internally Regulated Voltage<br>(External 1.8 V When VS<br>Grounded)<br>Ground<br>Supply Voltage<br>Input and Output Supply<br>Data Channel 0 (SOUT0)<br>Not Applicable<br>Bit Clock (BCLK)|



**Rev. 0 | 13 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

TA = 25°C, VS = 3.3 V, x-axis and y-axis acceleration = 0 _g_ , z-axis acceleration = 1 _g_ , full-scale range = ±4 _g_ , and default settings for other registers, unless otherwise noted. 

**==> picture [198 x 163] intentionally omitted <==**

_**Figure 13. X-Axis Zero g Offset at 25°C, VS = 3.3 V**_ 

**==> picture [196 x 163] intentionally omitted <==**

_**Figure 16. X-Axis Sensitivity at 25°C, VS = 3.3 V, ±4 g Range**_ 

**==> picture [199 x 164] intentionally omitted <==**

_**Figure 14. Y-Axis Zero g Offset at 25°C, VS = 3.3 V**_ 

**==> picture [196 x 164] intentionally omitted <==**

_**Figure 17. Y-Axis Sensitivity at 25°C, VS = 3.3 V, ±4g Range**_ 

**==> picture [198 x 165] intentionally omitted <==**

_**Figure 15. Z-Axis Zero g Offset at 25°C, VS = 3.3 V**_ 

**==> picture [196 x 164] intentionally omitted <==**

_**Figure 18. Z-Axis Sensitivity at 25°C, VS = 3.3 V, ±4 g Range**_ 

**Rev. 0 | 14 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

**TYPICAL PERFORMANCE CHARACTERISTICS** 

**==> picture [183 x 162] intentionally omitted <==**

_**Figure 19. X-Axis Offset vs. Temperature at 25°C, VS = 3.3 V**_ 

**==> picture [183 x 163] intentionally omitted <==**

_**Figure 20. Y-Axis Offset vs. Temperature at 25°C, VS = 3.3 V**_ 

**==> picture [183 x 163] intentionally omitted <==**

**==> picture [190 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 21. Z-Axis Offset vs. Temperature at 25°C, VS = 3.3 V<br>**----- End of picture text -----**<br>


**==> picture [201 x 164] intentionally omitted <==**

_**Figure 22. X-Axis Sensitivity Change vs. Temperature at 25°C, VS = 3.3 V**_ 

**==> picture [201 x 164] intentionally omitted <==**

_**Figure 23. Y-Axis Sensitivity Change vs. Temperature at 25°C, VS = 3.3 V**_ 

**==> picture [201 x 164] intentionally omitted <==**

_**Figure 24. Z-Axis Sensitivity Change vs. Temperature at 25°C, VS = 3.3 V**_ 

**Rev. 0 | 15 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

**TYPICAL PERFORMANCE CHARACTERISTICS** 

**==> picture [202 x 163] intentionally omitted <==**

_**Figure 25. X-Axis Frequency Response at 25°C, VS = 3.3 V**_ 

**==> picture [202 x 163] intentionally omitted <==**

_**Figure 26. Y-Axis Frequency Response at 25°C, VS = 3.3 V**_ 

**==> picture [202 x 163] intentionally omitted <==**

**==> picture [186 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 27. Z-Axis Frequency Response at 25°C, VS = 3.3 V<br>**----- End of picture text -----**<br>


**==> picture [202 x 163] intentionally omitted <==**

_**Figure 28. X-Axis PDM Frequency Response at 25°C, VS = 3.3 V**_ 

**==> picture [202 x 163] intentionally omitted <==**

_**Figure 29. Y-Axis PDM Frequency Response at 25°C, VS = 3.3 V**_ 

**==> picture [202 x 163] intentionally omitted <==**

**==> picture [202 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 30. Z-Axis PDM Frequency Response at 25°C, VS = 3.3 V<br>**----- End of picture text -----**<br>


**Rev. 0 | 16 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

_**Figure 31. X-axis ±4 g Nonlinearity at 25°C, VS = 3.3 V**_ 

_**Figure 32. Y-Axis ±4 g Nonlinearity at 25°C, VS = 3.3 V**_ 

_**Figure 33. Z-Axis ±4 g Nonlinearity at 25°C, VS = 3.3 V**_ 

_**Figure 34. X-Axis ±8 g Nonlinearity at 25°C, VS = 3.3 V**_ 

_**Figure 35. Y-Axis ±8 g Nonlinearity at 25°C, VS = 3.3 V**_ 

_**Figure 36. Z-Axis ±8 g Nonlinearity at 25°C, VS = 3.3 V**_ 

**Rev. 0 | 17 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

_**Figure 37. X-Axis ±16 g Nonlinearity at 25°C, VS = 3.3 V**_ 

_**Figure 38. Y-Axis ±16 g Nonlinearity at 25°C, VS = 3.3 V**_ 

_**Figure 39. Z-Axis ±16 g Nonlinearity at 25°C, VS = 3.3 V**_ 

_**Figure 40. X-Axis Vibration Rectification Error, X-Axis in +1 g Field, ±4 g Range, VS = 3.3 V**_ 

_**Figure 41. Y-Axis Vibration Rectification Error, Y-Axis in +1 g Field, ±4 g Range, VS = 3.3 V**_ 

_**Figure 42. Z-Axis Vibration Rectification Error, Z-Axis in +1 g Field, ±4 g Range, VS = 3.3 V**_ 

**Rev. 0 | 18 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

**==> picture [203 x 162] intentionally omitted <==**

_**Figure 43. X-Axis Root Allan Variance at 25°C, VS = 3.3 V**_ 

**==> picture [203 x 162] intentionally omitted <==**

_**Figure 44. Y-Axis Root Allan Variance at 25°C, VS = 3.3 V**_ 

**==> picture [203 x 162] intentionally omitted <==**

_**Figure 45. Z-Axis Root Allan Variance at 25°C, VS = 3.3 V**_ 

**==> picture [200 x 163] intentionally omitted <==**

_**Figure 46. X-Axis Self-Test Magnitude at 25°C, VS = 3.3 V**_ 

**==> picture [200 x 163] intentionally omitted <==**

_**Figure 47. Y-Axis Self-Test Magnitude at 25°C, VS = 3.3 V**_ 

**==> picture [199 x 165] intentionally omitted <==**

_**Figure 48. Z-Axis Self-Test Magnitude at 25°C, VS = 3.3 V**_ 

**Rev. 0 | 19 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

**==> picture [195 x 162] intentionally omitted <==**

_**Figure 49. Clock Deviation from Nominal at 25°C, VS = 3.3 V**_ 

**==> picture [199 x 162] intentionally omitted <==**

_**Figure 50. HP Mode Supply Current at 25°C, 3-Axis, VS = 3.3 V**_ 

**==> picture [199 x 164] intentionally omitted <==**

_**Figure 51. RBW Mode Supply Current at 25°C, 3-Axis, VS = 3.3 V**_ 

**==> picture [199 x 162] intentionally omitted <==**

_**Figure 52. LP Mode Supply Current at 25°C, 3-Axis, VS = 3.3 V**_ 

**==> picture [199 x 164] intentionally omitted <==**

_**Figure 53. VLP Mode Supply Current at 25°C, 3-Axis, VS = 3.3 V**_ 

**==> picture [199 x 162] intentionally omitted <==**

_**Figure 54. ULP Mode Supply Current at 25°C, 3-Axis, VS = 3.3 V**_ 

**Rev. 0 | 20 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

**==> picture [199 x 162] intentionally omitted <==**

_**Figure 55. HS Mode Supply Current at 25°C, 1-Axis, VS = 3.3 V**_ 

**==> picture [199 x 162] intentionally omitted <==**

_**Figure 56. Standby Mode Supply Current at 25°C, VS = 3.3 V**_ 

**==> picture [198 x 164] intentionally omitted <==**

_**Figure 57. Temperature Sensor Output at 25°C, HIGH_GAIN_TEMP = 0, VS = 3.3 V**_ 

**Rev. 0 | 21 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **THEORY OF OPERATION** 

The ADXL380 is a complete 3-axis acceleration measurement system. The device measures both dynamic accelerations resulting from motion, shock, and vibration as well as static acceleration such as tilt. Acceleration is reported digitally from the device using SPI or I[2] C protocols and/or I[2] S/TDM/PDM. Built-in digital logic enables autonomous operation and implements functionality that enhances system level power savings. 

The micromachined, sensing elements are fully differential, comprising the lateral x-axis and y-axis sensor and the vertical, teeter totter z-axis sensors. The x-axis and y-axis sensors and the z-axis sensors go through separate signal paths that minimize offset drift and noise. 

The ADXL380 include anti-aliasing filters before the high resolution Σ-Δ ADC and a decimation filter after. The following two signal paths are supported: 

- High performance using the 16-bit DSM 

- Low power using the 12-bit SAR 

These signal paths can be used independently or concurrently (see the Concurrent Operating Modes section for more information). User-selectable ODR and filter corners are provided. 

## **MECHANICAL DEVICE OPERATION** 

The moving component of the sensor is a polysilicon surface-micromachined structure that is built on top of a silicon wafer. Polysilicon springs suspend the structure over the surface of the wafer and provide a resistance against acceleration forces. 

Deflection of the structure is measured using differential capacitors that consist of independent fixed plates and plates attached to the moving mass. Acceleration deflects the structure and unbalances the differential capacitor, resulting in a sensor output whose amplitude is proportional to acceleration. Phase sensitive demodulation determines the magnitude and polarity of the acceleration. 

## **OPERATING MODES** 

The ADXL380 has seven primary operating modes with more modes available when operating concurrently (see the Concurrent Operating Modes section for more information). 

_**Table 10. Operating Modes**_ 

|**Mode**|**Signal Path**|
|---|---|
|Standby<br>High Performance (HP)<br>Reduce Bandwidth (RBW)<br>Low Power (LP)<br>Very Low Power (VLP)<br>Ultra-Low Power (ULP)<br>Heart Sounds (HS)|Not applicable<br>16-bit DSM (high performance signal chain)<br>16-bit DSM (high performance signal chain)<br>16-bit DSM (high performance signal chain)<br>12-bit SAR (low power signal chain)<br>12-bit SAR (low power signal chain)<br>12-bit SAR (low power signal chain)|



## **STANDBY MODE** 

Placing the ADXL380 in standby suspends measurement and reduces current consumption to 6.8 µA (typical). Standby mode is used for power conservation and device configuration. FIFO data is preserved and no new interrupts are generated (see Interrupts section for more details). 

The ADXL380 powers up in standby with all sensor functions turned off. Note that any changes to the device configuration must be made with the device in standby. If changes are made while the ADXL380 is in measurement mode, these changes may be effective for only part of a measurement. Ensure that a change of the data capture configuration only occurs in standby mode. 

## **MEASUREMENT MODE** 

Measurement mode refers to any of the operating modes that use the DSM or SAR signal path (every mode except standby mode in Table 10). When operating in measurement mode, the user can choose between several power consumption modes or operate in concurrent mode (one DSM mode and one SAR mode operating concurrently). 

Note that after entering measurement mode, a 2 ms wait time must be observed before reading acceleration data to allow the output time to settle after entering measurement mode. 

## **SELECTABLE MEASUREMENT RANGES** 

The ADXL380 has selectable measurement ranges of ±4 _g_ , ±8 _g_ , and ±16 _g_ . Acceleration samples are always converted by an ADC; therefore, sensitivity scales with _g_ range. Ranges and corresponding sensitivity values are listed in Table 1. When the input exceeds the full-scale range, the output data may not be accurate temporarily. The sensor is not damaged as long as the acceleration remains less than the absolute maximum rating. Table 6 lists the absolute maximum ratings for acceleration, indicating the acceleration level that can cause permanent damage to the ADXL380. 

## **DIGITAL OUTPUT** 

Figure 58 shows the ADXL380 application circuit. The communications interface is either SPI or I[2] C for the configuration, and the serial data interface is either SPI/I[2] C, I[2] S, or PDM (see the Serial Communications section for additional information). 

The ADXL380 includes an internal configurable digital band-pass filter. Both the high-pass and low-pass poles of the filter are adjustable, as detailed in the Filter section. The ADXL380 powers up in standby mode. A particular mode can be chosen by setting the OP_MODE register (Register 0x26). 

Figure 58 shows a 0.1 µF capacitor on the VS, VDDIO, and V1P8 pins. If the power supply is noisy, additional filtering may be required. An additional 1 µF capacitor can be added to the VS and VDDIO supplies in parallel with the 0.1 µF capacitors. 

**Rev. 0 | 22 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **THEORY OF OPERATION** 

**==> picture [213 x 132] intentionally omitted <==**

_**Figure 58. ADXL380 Application Circuit**_ 

**==> picture [116 x 47] intentionally omitted <==**

## **TEMPERATURE SENSOR** 

The ADXL380 includes an integrated 12-bit temperature sensor, which the system designer can use to monitor the internal system temperature or to improve the temperature stability of the device via calibration. 

The temperature sensor built in the ADXL380 is trimmed at room temperature before shipping; therefore, it can even be used to monitor the absolute temperature. To get even better accuracy, users can measure and calibrate the initial bias of the ADXL380 at some known temperature in mass production. 

To use the temperature sensor for calibration of the acceleration signal, it is sufficient to correlate acceleration to temperature sensor output, rather than to absolute temperature. In this case, it is not necessary to convert the temperature reading to an absolute temperature; therefore, calibration of the initial bias is not required. 

The designer can configure the device to save data from the temperature sensor in the FIFO. Temperature samples, whether read from the output registers or from the FIFO, update concurrently with acceleration (and ADC) samples, unless these samples are turned off. When the temperature channel is enabled, the ODR is always 100 Hz. If the ODR is faster than this on the other channels (x-axis, y-axis, or z-axis channels), temperature data is repeated until a new temperature sample is available. 

## **AXES OF ACCELERATION SENSITIVITY** 

Figure 59 shows the axes of acceleration sensitivity. Note that the digital output increases when accelerated along the sensitive axis. 

_**Figure 59. Axes of Acceleration Sensitivity**_ 

**==> picture [83 x 81] intentionally omitted <==**

_**Figure 60. Output Response vs. Orientation to Gravity**_ 

## **POWER SEQUENCING** 

The ADXL380 uses internal LDO regulators to generate the 1.8 V power for the internal analog and digital supplies. This 1.8 V regulated voltage is sent to the V1P8 pin as an output. When using the LDO regulator, connect VS to a voltage source between 2.25 V and 3.6 V. 

To disable the internal LDO regulators, tie VS to ground before using an external 1.8 V supply to power V1P8. Refer to the Power Supply Requirements section for more information. 

If necessary V1P8 and VDDIO can be powered from the same external 1.8 V supply so that both are powered at the same time. In this case, proper decoupling and low frequency isolation are important to maintain the noise performance of the sensor. 

VS, VDDIO, and V1P8 (if enabled as inputs) can be powered up in any sequence. 

**Rev. 0 | 23 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **THEORY OF OPERATION** 

## **POWER SUPPLY DESCRIPTION** 

The ADXL380 have three different power supply domains: VS, V1P8, and VDDIO. The internal analog and digital circuitry operates at 1.8 V nominal. 

## **VS** 

VS is 2.25 V to 3.6 V, which is the input range to the two LDO regulators that generate the nominal 1.8 V outputs for V1P8 (which requires a 100 nF capacitor). Connect VS to ground to disable the LDO regulators, which allows driving V1P8 from an external source. 

## **V1P8** 

V1P8 is the supply voltage for the internal logic circuitry. A separate LDO regulator decouples the digital supply noise from the analog signal path. If this is driven by an external supply, it must be 1.8 V ± 10%, and VS must be grounded. 

## **VDDIO** 

The VDDIO value determines the logic high level for communication interface ports, as well as the interrupt pins. 

VDDIO can operate as low as 1.14 V min (−25°C to +85°C) and 1.62 V min (for the full temperature range). 

## **OVERRANGE PROTECTION** 

To avoid electrostatic capture of the proof mass when the accelerometer is subject to input acceleration beyond its full-scale range, all sensor drive clocks turn off for 0.5 ms. The overrange protection activates when the input acceleration exceeds the threshold (see Table 11). Note that this threshold may vary from part to part (±25% from the nominal value). 

When an overrange event occurs, the response is determined by the DIG_OUT_DURING_OR bits in Register 0x48. During an overrange event, the data can be configured to remain at full-scale with the correct sign, hold the previous data before the overrange event, or do nothing to the data. The overrange protection can be disabled if desired (DIS_OR_PROTECTION = 1). Overrange detection still occurs, but no active protection occurs. To disable detection completely, set DIS_OR_DETECTION equal to 1. 

## **SELF TEST** 

The ADXL380 incorporates a self test feature that effectively tests the mechanical and electronic system. Enabling self test stimulates the sensor electrostatically to produce an output corresponding to the test signal applied as well as the mechanical force exerted. This feature must be enabled in the ±8 _g_ range. 

Take the following steps to run a self-test measurement: 

**1.** Set the ADXL380 operational mode (HP, RBW, LP, VLP, ULP, or HS) and configure the device in the ±8 _g_ range. Both OP_MODE and RANGE bits are in the OP_MODE register (Register 0x26). 

**2.** Enable the X, Y, and Z axes by setting the MODE_CHANNE_EN bits in the Register DIG_EN register (Register 0x27). In HS operational mode, only enable a singular axis (X, Y, or Z). 

**3.** Enable the positive self-test force (STPOSITIVE) by setting the ST_MODE bit and ST_FORCE bit to b’1 in the SNSR_AXIS_EN register (Register 0x38). 

**4.** Read the acceleration data for at least 25 samples. The user must record the acceleration data value. 

**5.** Enable the negative self test force (STNEGATIVE) by changing self-test direction, setting the ST_DIR, ST_FORCE, and ST_MODE bits to b’1 in the SNSR_AXIS_EN register (Register 0x38). 

**6.** Read the acceleration data for at least 25 samples. The user must record the acceleration data value. 

**7.** Subtract the data collected in Step 6 from the data collected in Step 5 to determine the magnitude of the self-test delta: STΔ = STPOSITIVE − STNEGATIVE. 

**8.** Compare the STΔ magnitude to the limits in Table 1. If the magnitudes are within the minimum and maximum specifications, the ADXL380 passed the self test. Otherwise, the ADXL380 failed and must be flagged for further investigation. 

_**Table 11. Overrange Protection Threshold**_ 

|**_Table 11. Overrange Protection Threshold_**|**_Table 11. Overrange Protection Threshold_**|**_Table 11. Overrange Protection Threshold_**|
|---|---|---|
|**Range (****_g_)**<br>**X/Y Nominal Threshold (****_g_)**<br>**Z Nominal Threshold (****_g_)**|||
|4<br>8<br>16|20<br>40<br>70|10<br>20<br>50|



**Rev. 0 | 24 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **THEORY OF OPERATION** 

## **FILTER** 

The ADXL380 provides digital filtering options to maintain optimal noise performance. The user has access to seven different filter options for maximized user configurability. The filters available include the equalizer filter, digital low-pass filter, digital high-pass filter, low latency infinite impulse response filter, and decimation filters (sinc filter, droop compensation filter (DCF), and infinite impulse response filter). 

The filter signal path is shown in Figure 61. Table 12 summarizes filters availability by operational modes. Refer to the Latency section for information on filter latency. 

_**Table 12. ADXL380 Filter Options by Operational Mode**_ 

|**_Table 12. ADXL380 Filter Options by Operational Mode_**|**_Table 12. ADXL380 Filter Options by Operational Mode_**|
|---|---|
|**Filter**<br>**Operational Mode Supported**||
|Equalizer (EQ) Filter<br>Low-Pass Filter (LPF)<br>High-Pass Filter (HPF)<br>First-Order Infinite Impulse Response<br>Filter (IIR1)<br>Sinc Filter<br>Droop Compensation Filter (DCF)<br>Seventh-Order Infinite Impulse Response<br>Filter (IIR7)|HP<br>HP, RBW, or LP<br>HP, RBW, LP, VLP, ULP, or HS<br>HP, RBW, or LP<br>HP, RBW, or LP<br>HP, RBW, or LP<br>HP, RBW, or LP|



**==> picture [487 x 227] intentionally omitted <==**

_**Figure 61. ADXL380 Filter Path**_ 

**Rev. 0 | 25 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **THEORY OF OPERATION** 

## **Fourth-Order Equalizer Filter (EQ)** 

The ADXL380 includes a fourth-order digital equalizer filter designed to flatten the sensor frequency response to increase the sensing bandwidth up to 4 kHz (see Figure 62). 

The EQ feature is only available when operating in HP mode. The EQ is automatically bypassed in other operational modes. The EQ, IIR1, and LPF cannot be used concurrently. 

the FILTER register (Register 0x50, Bits[5:4]) to b’00 and set the IIR1_EN bit in the TRIG_CFG register (Register 0x49, Bit 5) to b’0 prior to enabling the EQ (default configuration). The EQ_BYPASS bit in Register FILTER (Register 0x50, Bit 6) is set to b’0 by default to enable EQ. The user must set the EQ_BYPASS bit to b’1 to bypass the EQ. The EQ is automatically bypassed in all other operational modes. 

The FILTER register (Register 0x50) is used to disable the EQ. In HP operational mode, the user must set the LPF_MODE bits in 

**==> picture [226 x 196] intentionally omitted <==**

**==> picture [226 x 196] intentionally omitted <==**

_**Figure 62. ADXL380 Filter Frequency Response—Equalizer Effect**_ 

**Rev. 0 | 26 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **THEORY OF OPERATION** 

## **Digital LPF** 

The digital LPF in the ADXL380 provides an improved noise performance in a reduced bandwidth setting. The LPF is a secondorder infinite impulse response filter that supports three different user-configurable cutoff frequencies: ¼ × ODR, 1/8 × ODR, and 1/16 × ODR. The LPF is disabled by default. 

The LPF feature is only available when operating in the high-performance signal chain (HP, RBW, and LP operational modes). The EQ, IIR1, and LPF cannot be used concurrently. 

The FILTER register (Register 0x50) is used to enable the LPF. In HP operational mode, the user must set the EQ_BYPASS bit in the FILTER register (Register 0x50) to b’1 and set the IIR1_EN bit to b’0 in the TRIG_CFG register (Register 0x49) prior to enabling the LPF. In RBW and LP operational modes, the user must set the IIR1_EN bit in the TRIG_CFG register (Register 0x49) to b’0 prior to enabling the LPF. 

The LPF is then enabled by setting the LPF_MODE bits in the FILTER register (Register 0x50) to the desired value: 

- No low-pass filtering (b'00) 

- Cutoff frequency is 1/4 × ODR (b'01) 

- Cutoff frequency is 1/8 × ODR (b'10) 

- Cutoff frequency is 1/16 × ODR (b'11) 

## **Digital HPF** 

The digital HPF in the ADXL380 includes a programmable corner frequency. The HPF is disabled by default. 

The FILTER register (Register 0x50) is used to enable the HPF. The HPF_PATH bit in the FILTER register must be set to the desired signal path. When the HPF_PATH bit is set to b’0, the HPF is set to the low power signal chain, and when the HPF_PATH bit is set to b’1, the HPF is set to the high performance signal chain. Refer to the Operating Modes section for more details on high performance modes (DSM signal path) and low power modes (SAR signal chain). Once the HPF_PATH bit is set, the HPF_CORNER bits are set to the desired value. Table 13 shows the different available values for the HPF corner frequency. 

_**Table 13. HPF Corner Frequency Values**_ 

|**_Table 13. HPF Corner Frequency Values_**|**_Table 13. HPF Corner Frequency Values_**|
|---|---|
|**HPF_CORNER Bits Value**<br>**Corner Frequency Value (Hz)**||
|b'000<br>b'001<br>b'010<br>b'011<br>b'100<br>b'101<br>b'110|Not applicable (no high-pass filtering)<br>24.7E-4 × ODR<br>6.2084E-4 × ODR<br>1.5545E-4 × ODR<br>0.3862E-4 × ODR<br>0.0954E-4 × ODR<br>0.0238E-4 × ODR|



## **First-Order Low Latency Infinite Impulse Response Filter (IIR1)** 

The first-order IIR1 in the ADXL380 provides an improved noise performance in a low group delay setting. The IIR1 supports a 5 kHz cutoff frequency and is disabled by default. Refer to the Latency section for more information on the latency with various filters enabled. 

The IIR1 feature is only supported for the high performance signal chain (HP, RBW, or LP operational modes). The EQ, IIR1, and LPF cannot be used concurrently. 

The TRIG_CFG register (Register 0x49) is used to enable the IIR1. In HP operational mode, the user must set the EQ_BYPASS bit to b’1 and the LPF_MODE bits to b’00 in the FILTER register (Register 0x50) prior to enabling the IIR1. In RBW or LP operational modes, the user must set the LPF_MODE bits in the FILTER register (Register 0x50) to b’00 prior to enabling the IIR1. 

The IIR1 is then enabled by setting the IIR1_EN bit in the TRIG_CFG register (Register 0x49) to b’1. 

## **Decimation Filters** 

The decimation filters in the ADXL380 provide an improved noise performance to the customer. The ADC output is first decimated by a third-order sinc filter. Then, the DCF, a second-order FIR, is designed to correct for the drooping effect of the sinc filter. The signal is further decimated by a seven-order IIR filter. The output of the decimation filters is a variable ODR in function of the decimation occurring previously in the signal path. Note that the rounding method is configurable. Use the FLOOR rounding method to improve DC performance when using the HPF. The FLOOR rounding method minimizes the DC offset that is introduced when truncating the data to 16 bits and is defined as follows: 

- If the signal is negative, it increments the data value by 1. 

- If the signal is positive, the data is left unchanged. 

Table 14 lists the ODR as a function of the different decimation filter settings. Table 14 also mentions the DOUBLE_SPEED bit feature in the DIG_EN register (Register 0x27, Bit 2) that affects the system clock of the ADXL380, and therefore, influences the final ODR. Refer to the Low Latency Mode section for more details, including register settings. 

The decimation filters are only supported for the high-performance signal chain (HP, RBW, and LP operational modes). 

**==> picture [210 x 53] intentionally omitted <==**

_**Figure 63. Decimation Filter Architecture**_ 

**Rev. 0 | 27 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **THEORY OF OPERATION** 

_**Table 14. ADXL380 Decimation Filter–HP Mode**_ 

|**DOUBLE**<br>**_SPEED**<br>**Bit,Register**<br>**0x27, Bit 2**<br>**A (kHz)**|**DOUBLE**<br>**_SPEED**<br>**Bit,Register**<br>**0x27, Bit 2**<br>**A (kHz)**|**SINC _RATE**<br>**Bit, Register**<br>**0x49, Bit 6**<br>**B**<br>**(kHz)**|**SINC _RATE**<br>**Bit, Register**<br>**0x49, Bit 6**<br>**B**<br>**(kHz)**|**DEC_2X_BYP**<br>**ASS Bit,**<br>**Register**<br>**0x49, Bit 7**<br>**C (kHz),**<br>**ODR**|**DEC_2X_BYP**<br>**ASS Bit,**<br>**Register**<br>**0x49, Bit 7**<br>**C (kHz),**<br>**ODR**|
|---|---|---|---|---|---|
|b’0|512|b’0 (32×)|16|b’0|8|
|||||b’1|16|
|||b’1 (16×)|32|Not applicable|32|
|b’1|1024|b’0 (32×)|32|b’0|16|
|||||b’1|32|
|||b’1 (16×)|64|Not applicable|64|



## **Third-Order Sinc Filter (SINC)** 

The third-order sinc filter is designed to reduce the quantization noise of the Σ-Δ ADC. The sinc filter can be set either to 32× (default) or 16×. The user shall use the DCF filter to compensate for the droop of the SINC filter. 

The TRIG_CFG register (Register 0x49) is used to change the decimation of the sinc filter. By default, the SINC_RATE bit in the TRIG_CFG register (Register 0x49, Bit 6) is set to b’0 for a 32× decimation. The user must set the SINC_RATE bit to b’1 to set the sinc filter to 16× decimation (see Table 14). When the SINC_RATE bit is set to b’1, the IIR7 is bypassed automatically. 

## **Droop Compensation Filter (DCF)** 

The DCF is designed to compensate the droop of the sinc filter. The DCF is optimized for the 32× decimation of the sinc filter. Bypass the DCF if the sinc filter is set to a 16× decimation. 

The FILTER register (Register 0x50) is used to disable the DCF. By default, the DCF_BYPASS bit in the FILTER register (Register 0x50, Bit 7) is set to b’0 to compensate the droop of the sinc filter. The user must set the DCF_BYPASS bit in the FILTER register to b’1 to bypass the DCF. 

## **Seventh-Order Infinite Impulse Response Filter (IIR7)** 

The IIR7 is designed to provide an improved noise performance to the customer. The IIR7 is a 2× decimation filter. 

The TRIG_CFG register (Register 0x49) is used to disable the IIR7. By default, the DEC_2X_BYPASS bit in the TRIG_CFG register (Register 0x49, Bit 7) is set to b’0 for a 2× decimation. The user must set the DEC_2X_BYPASS bit to b’1 to bypass the IIR7 (see Table 14). When the SINC_RATE bit in the TRIG_CFG (Register 0x49, Bit 6) is set to b’1, the IIR7 is bypassed automatically. 

**Rev. 0 | 28 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **THEORY OF OPERATION** 

## **NOISE** 

The ADXL380 has several operating modes and dynamic range options. Each of these impacts noise performance (see Table 15). 

The ADXL380 offers many options for controlling the tradeoff between power consumption, dynamic range, and noise performance. 

_**Table 15. Noise Performance vs. Dynamic Range and Operating Mode**_ 

|**Operational Mode**<br>**Dynamic Range (****_g_)**|**Operational Mode**<br>**Dynamic Range (****_g_)**|**Noise Density (µ****_g_/√Hz)**<br>**RMS Output Noise (m****_g_)**|**Noise Density (µ****_g_/√Hz)**<br>**RMS Output Noise (m****_g_)**|**Noise Density (µ****_g_/√Hz)**<br>**RMS Output Noise (m****_g_)**|**Noise Density (µ****_g_/√Hz)**<br>**RMS Output Noise (m****_g_)**|
|---|---|---|---|---|---|
|||**XY**<br>**Z**<br>**XY**<br>**Z**||||
|High Performance (HP)|4<br>8<br>16|20<br>22<br>28|27<br>28<br>30|1.3<br>1.4<br>1.8|1.7<br>1.8<br>1.9|
|Reduced Bandwidth (RBW)|4<br>8<br>16|23<br>27<br>37|29<br>30<br>34|1.0<br>1.2<br>1.7|1.3<br>1.4<br>1.5|
|Low Power (LP)|4<br>8<br>16|39<br>44<br>57|49<br>51<br>56|1.2<br>1.4<br>1.8|1.5<br>1.6<br>1.8|
|Very Low Power (VLP)|4<br>8<br>16|94<br>170<br>340|97<br>180<br>270|2.1<br>3.7<br>7.5|2.2<br>3.9<br>6.1|
|Ultra-Low Power (ULP)|4<br>8<br>16|160<br>310<br>620|160<br>390<br>580|1.2<br>2.2<br>4.4|1.2<br>2.8<br>4.2|
|Heart Sound Mode (1-Axis)|4<br>8<br>16|66<br>110<br>210|71<br>120<br>190|1.5<br>2.6<br>4.7|1.6<br>2.7<br>4.4|



**Rev. 0 | 29 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **POWER SAVINGS FEATURES** 

The ADXL380 includes several features (as described in the following sections) for enabling power savings at the system level, as well as at the device level. 

## **OPERATING MODES** 

The ADXL380 has seven standard operating modes: 

- Standby 

- High performance (HP) 

- Reduced bandwidth (RBW) 

- Low power (LP) 

- Very low power (VLP) 

- Ultra-low power (ULP) 

- Heart sounds (HS) 

When using modes concurrently, the 13 unique operating mode are available (for example, HP mode and ULP mode: OP_MODE = 4’b1110). See the OP_MODE bits, Bits[3:0] in the OP_MODE register (Register 0x26) for more details about each mode. 

The ADXL380 supports seven modes of operation to prioritize performance, low power, or bandwidth depending on the needs of the application. These modes are configured through the use of the four bits within the OP_MODE bits. 

Switching between any two modes must be first done by transitioning through standby mode, which must be done explicitly through register commands because the ADXL380 does not manage this aspect. Switching to standby ensures all clocks and datapaths are correctly configured and flushed to a known state. 

_**Table 16. Modes of Operation**_ 

|**_Table 16. Modes of Operation_**|**_Table 16. Modes of Operation_**|**_Table 16. Modes of Operation_**|**_Table 16. Modes of Operation_**|**_Table 16. Modes of Operation_**|**_Table 16. Modes of Operation_**|**_Table 16. Modes of Operation_**|**_Table 16. Modes of Operation_**|
|---|---|---|---|---|---|---|---|
|**Operational Mode**<br>**Bandwidth1**<br>**Signal Path**<br>**System Clock**<br>**FIFO**<br>**SPI/I2C**<br>**TDM**<br>**OP_MODE (Register 0x26, Bits[3:0])**||||||||
|Standby<br>HS (1-Axis)<br>ULP<br>VLP<br>LP<br>RBW<br>HP|Not applicable<br>400 Hz<br>50 Hz<br>500 Hz<br>1000 Hz<br>2000 Hz<br>4000 Hz|Not applicable<br>SAR<br>SAR<br>SAR<br>Σ-Δ<br>Σ-Δ<br>Σ-Δ|Not applicable<br>256 kHz<br>256 kHz<br>256 kHz<br>512 kHz<br>512 kHz<br>512 kHz|No<br>Yes<br>Yes<br>Yes<br>Yes<br>Yes<br>Yes|Yes<br>Yes<br>Yes<br>Yes<br>Yes<br>Yes<br>Yes|No<br>No<br>No<br>No<br>Yes<br>Yes<br>Yes|4’b0000<br>4’b0001<br>4’b0010<br>4’b0011<br>4’b0100<br>4’b1000<br>4’b1100|



> 1 Bandwidth with DEC_2X_BYPASS = 0, SINC_RATE = 0, and LPF disabled. 

**Rev. 0 | 30 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **POWER SAVINGS FEATURES** 

## **MOTION DETECTION** 

The ADXL380 features built-in logic that detects activity (presence of acceleration above a threshold) and inactivity (lack of acceleration above a threshold). Activity and inactivity events can be used as triggers to manage the accelerometer mode of operation, trigger an interrupt to a host processor, and/or autonomously drive a motion switch. 

Detection of an activity or inactivity event is indicated in the STATUSx registers (Register 0x11 through Register 0x14) and can be configured to generate an interrupt. Note that motion detection (activity, inactivity, or tap detection) are only functional for the low power operational modes (VLP, ULP, and HS modes). 

## **ACTIVITY DETECTION** 

An activity event is detected when acceleration remains more than a specified threshold for a specified time period on any of the axes. If any axis exceeds the threshold, an activity event occurs unless that axis is disabled. 

## **Referenced and Absolute Configurations** 

Activity detection can be configured as referenced or absolute. 

When using absolute activity detection, acceleration samples are compared to a user set threshold to determine whether motion is present. For example, if a threshold of 0.5 _g_ is set, and the acceleration on the z-axis is 1 _g_ for longer than the user defined activity time, the activity status asserts. 

In many applications, it is advantageous for activity detection not to be based on an absolute threshold but to be based on a deviation from a reference point or orientation, which is particularly useful because it removes the effect on activity detection of the static 1 _g_ imposed by gravity. When an accelerometer is stationary, its output can reach 1 _g_ , even when it is not moving. In absolute activity, when the threshold is set to less than 1 _g_ , activity is immediately detected in this case. 

In the referenced configuration, activity is detected when acceleration samples are at least a user set amount more than an internally defined reference for the user defined amount of time, as described in the following equation: 

## ABS Acceleration ‐ Reference > Threshold 

(1) 

Consequently, activity is detected only when acceleration has deviated sufficiently from the initial orientation. The reference for activity detection is calculated when activity detection is engaged in the following scenarios: 

- When the activity function is turned on and measurement mode is engaged 

- If link mode is enabled when inactivity is detected and activity detection begins 

- If link mode is not enabled when activity is detected and activity detection repeats 

The referenced configuration results in a sensitive activity detection that detects even the most subtle motion events. 

When using the referenced configuration, it is important to note that the ADXL380 still uses the absolute thresholds when it first enters measurement mode, which becomes important if an inactivity threshold <1 _g_ is desired. In this case, the device must enter measurement mode with a threshold greater than 1 _g_ . The inactivity threshold can then be lowered to the desired level (while still in measurement mode), which allows the ADXL380 to set the thresholds around the 1 _g_ offset on the z-axis. 

## **Fewer False Positives** 

Ideally, the intent of activity detection is to wake up a system only when motion is intentional, ignoring noise or small, unintentional movements. In addition to being sensitive to subtle motion events, the ADXL380 activity detection algorithm is designed to be robust in filtering out undesired triggers. 

The ADXL380 activity detection functionality includes a timer to filter out unwanted motion and ensure that only sustained motion is recognized as activity. The duration of this timer, as well as the acceleration threshold, are user adjustable from one sample (that is, no timer) to up to 20 seconds of motion. 

## **INACTIVITY DETECTION** 

An inactivity event is detected when acceleration remains less than a specified threshold for a specified time on all the axes. All three axes (if enabled) must be less than the inactivity thresholds for an inactivity event to occur. Inactivity detection is also configurable as referenced or absolute. 

When using absolute inactivity detection, acceleration samples are compared to a user set threshold for the user set time to determine the absence of motion. Inactivity is detected when enough consecutive samples are all less than the threshold. The absolute configuration of inactivity must be used for implementing free fall detection. 

When using referenced inactivity detection, inactivity is detected when acceleration samples are within a user specified amount of an internally defined reference for a user defined amount of time, as described in the following equation: 

## ABS Acceleration ‐ Reference < Threshold 

(2) 

The reference for inactivity detection is calculated when: 

- The inactivity function is turned on, and the ADXL380 enters measurement mode. 

- An inactivity event is detected. 

Each time an inactivity event is detected, the reference is updated, which becomes important when using an inactivity timer. The reference is not updated until the timer expires. In dynamic environments, the reference not being updated until the timer expires can 

**Rev. 0 | 31 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **POWER SAVINGS FEATURES** 

lead to the ADXL380 becoming stuck in a state where it is looking for inactivity, but the acceleration is outside the threshold limits. 

## **LINKING ACTIVITY AND INACTIVITY DETECTION** 

The activity and inactivity detection functions can be used concurrently and processed manually by a host processor, or these functions can be configured to interact in several other ways, which is explained in further detail in the following sections. 

## **Default Mode** 

The user must enable the activity and inactivity functions because these functions are not automatically enabled by default. After the user enables the activity and inactivity functions, the ADXL380 exhibits the following behavior when it enters default mode: both activity and inactivity detection remain enabled, and all interrupts must be serviced by a host processor; that is, a processor must read each interrupt before it is cleared and can be used again. 

Default mode operation is illustrated in the flowchart in Figure 64. 

**==> picture [58 x 42] intentionally omitted <==**

**==> picture [58 x 42] intentionally omitted <==**

**==> picture [73 x 42] intentionally omitted <==**

**==> picture [73 x 42] intentionally omitted <==**

**==> picture [58 x 42] intentionally omitted <==**

**==> picture [58 x 42] intentionally omitted <==**

_**Figure 64. Flowchart Illustrating Activity and Inactivity Operation in Default Mode**_ 

## **Linked Mode** 

In linked mode, activity and inactivity detection are linked to each other in a way so that only one of the functions is enabled at any given time. As soon as activity is detected, the ADXL380 is assumed to be moving and stops looking for activity. Inactivity is expected as the next event. Therefore, only inactivity detection operates. 

Similarly, when inactivity is detected, the ADXL380 is assumed to be stationary. Therefore, activity is expected as the next event, and only activity detection operates. 

In linked mode, an activity interrupt is enabled first after power-up. Each interrupt must be serviced by a host processor before the next interrupt is enabled. Linked mode operation is shown in the flowchart in Figure 65. 

**==> picture [58 x 43] intentionally omitted <==**

**==> picture [58 x 43] intentionally omitted <==**

**==> picture [73 x 43] intentionally omitted <==**

**==> picture [73 x 43] intentionally omitted <==**

**==> picture [58 x 43] intentionally omitted <==**

**==> picture [58 x 43] intentionally omitted <==**

_**Figure 65. Activity and Inactivity Operation in Linked Mode**_ 

In standby mode, linked mode must always be enabled. Switching from default mode to linked mode while in another operating mode (for example, HP, ULP, and so on) can cause the state machine to enter a fuzzy state where it is searching for both activity and inactivity simultaneously. 

## **Loop Mode** 

In loop mode, motion detection operates as described in the Linked Mode section; however, interrupts must not be serviced by a host processor. This configuration simplifies the implementation of commonly used motion detection and enhances power savings by reducing the amount of power used in bus communications. 

Similar to linked mode, activity interrupt is enabled first after powerup in loop mode, which means the ADXL380 is currently waiting for an activity event. For immediate inactivity measurement, set a low activity threshold (for example, <1 m _g_ ). Then, adjust the threshold to the desired level for the application without going back to standby mode, which prevents the ADXL380 from getting stuck searching for activity upon power-up. 

Loop mode operation is shown in the flowchart in Figure 66. 

**==> picture [58 x 42] intentionally omitted <==**

**==> picture [58 x 42] intentionally omitted <==**

**==> picture [73 x 42] intentionally omitted <==**

**==> picture [73 x 42] intentionally omitted <==**

**==> picture [57 x 42] intentionally omitted <==**

**==> picture [57 x 42] intentionally omitted <==**

_**Figure 66. Activity and Inactivity in Loop Mode**_ 

**Rev. 0 | 32 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **FIFO** 

The ADXL380 includes a 320-word FIFO buffer. The FIFO provides benefits primarily in two ways: system-level power savings and data recording and event context. 

## **SYSTEM-LEVEL POWER SAVINGS** 

Appropriate use of the FIFO enables system-level power savings by enabling the host processor to sleep for extended periods of time while the accelerometer collects data. Alternatively, using the FIFO to collect data can unburden the host while it tends to other tasks. 

## **DATA RECORDING AND EVENT CONTEXT** 

The FIFO can be used in a triggered mode to record all data leading up to an activity detection event, thereby providing context for the event. In the case of a system that identifies impact events, for example, the accelerometer can keep the entire system off while it stores acceleration data in its FIFO and looks for an activity event. When the impact event occurs, data that was collected prior to the event is frozen in the FIFO. The accelerometer can then wake the rest of the system and transfer this data to the host processor, thereby providing context for the impact event. 

Generally, the more context available, the more intelligent decisions a system can achieve, making a deep FIFO especially useful. While operating in ULP mode (50 Hz output data rate), the ADXL380 FIFO can store up to more than 2.1 seconds of data, providing a clear picture of events prior to an activity trigger. 

All FIFO modes of operation, as well as the structure of the FIFO and instructions for retrieving data from it, are described in further detail in the FIFO Modes section. Note that when retrieving data from the FIFO, all axes (also known as the whole sample size) of interest must be read in a burst (or multibyte) read operation to avoid data loss or misalignment. 

The FIFO size changes to accommodate the number of enabled channels. If only three channels are enabled, the FIFO size is 318 instead of 320 (see Table 17), which ensures that the data stored in the FIFO is a whole data set (for example, the x-axis, y-axis, and z-axis and the temperature data). The address auto-increment function disables when the FIFO_DATA address (Register 0x1D) is used, so that data can be read continuously from the FIFO as a multibyte transaction. In cases where the starting address of a multibyte transaction is less than the FIFO address, the address auto-increments until reaching the FIFO address, and then stops at the FIFO address. 

_**Table 17. FIFO Location vs. Enabled Channels**_ 

|**SRAM**<br>**Address**|**Enabled Channels1**|**Enabled Channels1**|**Enabled Channels1**|**Enabled Channels1**|**Enabled Channels1**|**Enabled Channels1**|
|---|---|---|---|---|---|---|
||**X**<br>**X/Y**<br>**X/T**<br>**X/Y/Z**<br>**X/Y/T**<br>**X/Y/Z/T**||||||
|0<br>1<br>2<br>3<br>4<br>…|X<br>X<br>X<br>X<br>X<br>…|X<br>Y<br>X<br>Y<br>X<br>…|X<br>T<br>X<br>T<br>X<br>…|X<br>Y<br>Z<br>X<br>Y<br>…|X<br>Y<br>T<br>X<br>Y<br>…|X<br>Y<br>Z<br>T<br>X<br>…|



_**Table 17. FIFO Location vs. Enabled Channels (Continued)**_ 

|**SRAM**<br>**Address**|**Enabled Channels1**|**Enabled Channels1**|**Enabled Channels1**|**Enabled Channels1**|**Enabled Channels1**|**Enabled Channels1**|
|---|---|---|---|---|---|---|
||**X**<br>**X/Y**<br>**X/T**<br>**X/Y/Z**<br>**X/Y/T**<br>**X/Y/Z/T**||||||
|315<br>316<br>317<br>318<br>319|X<br>X<br>X<br>X<br>X|Y<br>X<br>Y<br>X<br>Y|T<br>X<br>T<br>X<br>T|X<br>Y<br>Z<br>Unused<br>Unused|X<br>Y<br>T<br>Unused<br>Unused|T<br>X<br>Y<br>Z<br>T|



> 1 X is the X-axis, Y is the Y-axis, Z is the Z-Axis, and T is temperature. 

The FIFO also has a channel ID function that can be enabled in Register 0x30 (FIFO_CFG0), Bit 6 (FIFO_CH_ID). This channel ID precedes each data sample with a 2-bit identification describing what channel the next data sample is. The channel ID for each axis is shown in Table 18. This channel ID does not take up a FIFO SRAM location and can be read by reading Register 0x1D (FIFO_DATA). A multibyte read of Register 0x1D gives the channel ID followed by the data sample for all enabled channels (see Table 19). 

_**Table 18. FIFO Channel ID Description**_ 

|**_Table 18. FIFO Channel ID Description_**|**_Table 18. FIFO Channel ID Description_**|**_Table 18. FIFO Channel ID Description_**|
|---|---|---|
|**Channel**<br>**Abbreviation**<br>**Channel ID**|||
|X-Axis Acceleration<br>Y-Axis Acceleration<br>Z-Axis Acceleration<br>Temperature|X<br>Y<br>Z<br>T|0b00<br>0b01<br>0b10<br>0b11|



_**Table 19. FIFO Location vs. Enabled Channels with Channel ID Enabled**_ 

|**SRAM Address**|**Enabled Channels with Channel ID Enabled**|**Enabled Channels with Channel ID Enabled**|
|---|---|---|
||**X/Y/Z**<br>**X/Y/Z/T**||
|Not Applicable<br>0<br>Not Applicable<br>1<br>Not Applicable<br>2<br>Not Applicable<br>3<br>…<br>Not Applicable<br>315<br>Not Applicable<br>316<br>Not Applicable<br>317<br>Not Applicable<br>318<br>Not Applicable<br>319|X ID<br>X<br>Y ID<br>Y<br>Z ID<br>Z<br>X ID<br>X<br>…<br>X ID<br>X<br>Y ID<br>Y<br>Z ID<br>Z<br>Not applicable<br>Unused<br>Not applicable<br>Unused|X ID<br>X<br>Y ID<br>Y<br>Z ID<br>Z<br>X ID<br>X<br>…<br>T ID<br>T<br>X ID<br>X<br>Y ID<br>Y<br>Z ID<br>Z<br>T ID<br>T|



**Rev. 0 | 33 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **FIFO** 

## **FIFO CONFIGURATION** 

The FIFO can be configured by writing to the FIFO configuration registers, FIFO_CFG0 and FIFO_CRG1 (Register 0x30 and Register 0x31). The FIFO mode, number of FIFO entries, and channel ID enable can all be configured to optimize performance in various applications. 

## **FIFO MODES** 

The ADXL380 has the following FIFO modes: 

- FIFO disabled 

- Normal (also referred to as oldest saved or First N) 

- Stream (also referred to as Last N) 

- Trigger 

When the FIFO is disabled (Register 0x30, Bits[5:4] (FIFO_MODE) = 0b00), no data samples are stored, and a FIFO read returns 0. 

When in normal mode (Register 0x30, Bits[5:4] (FIFO_MODE) = 0b01), the FIFO accumulates data until it is full and then stops, which is indicated by FIFO_FULL (Register 0x11, Bit 1) = 1. Additional data is only collected when space is made available by reading samples out of the FIFO buffer. 

When in stream mode (Register 0x30, Bits[5:4] (FIFO_MODE) = 0b10), new data is continuously written to the FIFO whether it is full or not. When the FIFO is full, the oldest data set (for example, the X, Y, Z, and T data sample) is discarded to make room for the new data set. In this way, the most recent data is always preserved in the FIFO buffer. Stream mode is useful for unburdening a host processor. The processor can tend to other tasks while data is being collected in the FIFO. When the FIFO fills to a certain number of samples (specified by FIFO_SAMPLES in Register 0x30, Bit 0 and Register 0x31, Bits[7:0]), it triggers a FIFO watermark interrupt (if this interrupt is enabled). At this point, the host processor can read the contents of the entire FIFO and then return to its other tasks as the FIFO fills again. 

When in trigger mode (Register 0x30, Bits[5:4] (FIFO_MODE) = 0b11), the FIFO saves samples before and after a trigger event. This trigger event can be either an activity event or an external interrupt. In this mode, new data samples are collected continuously whether the FIFO is full or not (similar to stream mode). Once a trigger event occurs (either an activity event or an external interrupt), the FIFO continues to collect a set number of data samples. The number of data samples it collects after the trigger event is set by the value in the FIFO_SAMPLES bits (Register 0x30, Bit 0 and Register 0x31, Bits[7:0]). 

## **FIFO INTERRUPTS** 

The FIFO has several interrupts that can be mapped to the INT0 and INT1 pins. Interrupt mapping is controlled by using Register 0x2B (INT0_MAP0) through Register 0x2E (INT1_MAP1). 

## **FIFO WATERMARK** 

The FIFO_WATERMARK bit (Register 0x11, Bit 3) is set when the number of samples stored in the FIFO is equal to or exceeds the number of samples specified by the FIFO_SAMPLES bits (Register 0x30, Bit 0 and Register 0x31, Bits[7:0]). In order for an interrupt to be triggered, the ADXL380 must be in either FIFO normal mode or FIFO stream mode, and the FIFO_WATERMARK bit must be mapped to INT0 or INT1. 

The FIFO_WATERMARK bit is cleared automatically when enough samples are read from the FIFO so that the number of samples remaining is lower than the value set by the user in the FIFO_SAMPLES bits. 

## **FIFO READY** 

The FIFO_READY bit (Register 0x11, Bit 4) asserts if there is at least one valid sample available in the FIFO output buffer. This bit is cleared when no valid data is available in the FIFO. 

## **FIFO OVERRUN** 

The FIFO_OVERRUN bit (Register 0x11, Bit 2) is set when the FIFO has overrun or overflow, indicating that new data has replaced unread data, which may indicate a full FIFO that has not yet been emptied or a clocking error caused by a slow SPI transaction. The FIFO_OVERRUN bit is only available for FIFO normal mode and trigger mode. 

The FIFO_OVERRUN bit is cleared automatically when the contents of the FIFO are read. Likewise, when the FIFO is disabled, the FIFO_OVERRUN bit is cleared. 

## **FIFO FULL** 

The FIFO_FULL bit (Register 0x11, Bit 1) is set when the FIFO collects 320 samples (or 318 samples if exactly three channels are enabled; see Table 17). 

To enable an external interrupt triggered FIFO mode, set the FIFO_EXT_TRIG bit (Register 0x30, Bit 3) to 1. Once this bit is set to 1, an external interrupt sent to the FSYNC pin triggers a FIFO capture. 

**Rev. 0 | 34 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **COMMUNICATIONS** 

## **SPI INSTRUCTIONS** 

The digital interface of the ADXL380 is implemented with systemlevel power savings in mind. The following features enhance power savings: 

- Burst reads and writes reduce the number of SPI communication cycles required to configure the ADXL380 and retrieve data. 

- Concurrent operation of activity and inactivity detection enables set and forget operation. Loop mode further reduces communications power by enabling the clearing of interrupts without processor intervention. 

- The FIFO is implemented such that consecutive samples can be read continuously via a multibyte read of unlimited length; therefore, a one read FIFO instruction can clear the entire contents of the FIFO. In many other accelerometers, each read instruction retrieves a single sample only. 

For this device, the clock polarity and clock phase are both zero (CPOL = CPHA = 0), which means that data bits must be read on the rising clock edge, and data bits are transitioned on the falling clock edge. The chip select pin, CS, activates the SPI. As long as CS is high, the ADXL380 ignores any signals present on the SCLK or SDI pins, and the output SDO is in a high impedance state. When CS is in a low logic state, data can be transferred to and from the microcontroller. During transitions of CS from high to low or vice versa, SCLK is set to low by the microcontroller, ensuring that proper communication is initiated with the ADXL380. 

## **I[2] C INTERFACE** 

The ADXL380 conforms to the _UM10204 I2C-Bus Specification and User Manual_ , Rev. 03—19 June 2007, available from NXP Semiconductor. 

With the ASEL0 and ASEL1 pins high, the 7-bit I[2] C address is 0x54 as shown in Figure 67. The I[2] C address is followed by the R/W bit as shown in Figure 68. This translates to 0xA6 for a write and 0xA7 for a read. Alternate I[2] C addresses are shown in Table 20. 

**==> picture [208 x 137] intentionally omitted <==**

_**Figure 67. I[2] C Example Connection Diagram (Address 0x54)**_ 

_**Table 20. I[2] C Address Selection**_ 

|**ASEL0**|**ASEL0**|**ASEL1**|**I2C Address**|
|---|---|---|---|
||Low|Low|0x1D|
||High|Low|0x53|
||Low|High|0x54|
||High|High|0x55|



If other devices are connected to the same I[2] C bus, the nominal operating voltage level of these other devices cannot exceed VDDIO by more than 0.3 V. External pull-up resistors, RP, are necessary for proper I[2] C operation (see Figure 67). Refer to the _UM10204 I[2] C-Bus Specification and User Manual_ , Rev. 03—19 June 2007, when selecting pull-up resistor values to ensure proper operation. 

**==> picture [422 x 106] intentionally omitted <==**

_**Figure 68. I[2] C Device Addressing (Read from Data Registers)**_ 

**Rev. 0 | 35 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **COMMUNICATIONS** 

## **I[2] S/TDM INTERFACE** 

The ADXL380 constantly streams data out of the I[2] S port. This protocol is suitable for obtaining high speed, synchronous accelerometer data. The ADXL380 can act as either a controller or a subordinate on the I[2] S bus. When operating as a controller, the BCLK and FSYNC pins are configured as output pins (see Figure 69). When operating as a subordinate, the BCLK and FSYNC pins are configured as input pins (see Figure 70). 

**==> picture [82 x 116] intentionally omitted <==**

**==> picture [86 x 116] intentionally omitted <==**

_**Figure 69. I[2] S/TDM Wiring Diagram with ADXL380 in Controller Mode**_ 

**==> picture [81 x 116] intentionally omitted <==**

**==> picture [87 x 116] intentionally omitted <==**

_**Figure 70. I[2] S/TDM Wiring Diagram with ADXL380 in Subordinate Mode**_ 

## **Controller Mode (Internal Clock)** 

When in controller mode, the ADXL380 operates at a nominal clock speed of 512 kHz with a nominal frame frequency of 8 kHz. The BCLK and FYSNC pins are provided as outputs for other devices on the I[2] S bus. In this mode, the device supports a word width of 16 bits, 24 bits, or 32 bits. TDM2 and TDM4 are also supported. See Table 21 for a list of supported controller modes. 

_**Table 21. ADXL380 Supported Controller Modes (BCLK and FSYNC Are Outputs)**_ 

|**Output Format **|**Power Mode**|**BCLK Frequency**<br>**FSYNC Frequency**<br>**Word Width**<br>**Output Data Rate**<br>**Data Output Pins**|**BCLK Frequency**<br>**FSYNC Frequency**<br>**Word Width**<br>**Output Data Rate**<br>**Data Output Pins**|**BCLK Frequency**<br>**FSYNC Frequency**<br>**Word Width**<br>**Output Data Rate**<br>**Data Output Pins**|**BCLK Frequency**<br>**FSYNC Frequency**<br>**Word Width**<br>**Output Data Rate**<br>**Data Output Pins**|**BCLK Frequency**<br>**FSYNC Frequency**<br>**Word Width**<br>**Output Data Rate**<br>**Data Output Pins**|
|---|---|---|---|---|---|---|
|I2S or TDM2|HP|512 kHz|16 kHz|16 bit|8 kHz|SOUT0and SOUT1|
|||512 kHz|8 kHz|32 bit|8 kHz|SOUT0and SOUT1|
|||256 kHz|8 kHz|16 bit|8 kHz|SOUT0and SOUT1|
||RBW|256 kHz|8 kHz|16 bit|4 kHz|SOUT0and SOUT1|
|||256 kHz|4 kHz|32 bit|4 kHz|SOUT0and SOUT1|
|||128 kHz|4 kHz|16 bit|4 kHz|SOUT0and SOUT1|
||LP|128 kHz|4 kHz|16 bit|2 kHz|SOUT0and SOUT1|
|||128 kHz|2 kHz|32 bit|2 kHz|SOUT0and SOUT1|
|||64 kHz|2 kHz|16 bit|2 kHz|SOUT0and SOUT1|
|TDM4|HP|512 kHz|8 kHz|16 bit|8 kHz|SOUT0or SOUT1|
||RBW|256 kHz|4 kHz|16 bit|4 kHz|SOUT0or SOUT1|
||LP|128 kHz|2 kHz|16 bit|2 kHz|SOUT0or SOUT1|



**Rev. 0 | 36 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **COMMUNICATIONS** 

## **Subordinate Mode (External Clocks)** 

When in subordinate mode, BCLK and FSYNC must be provided as inputs on their respective pins. The BCLK frequency must be an integer multiple of 512 kHz such that it can be divided down to 512 kHz by setting the EXT_CLK_RATE bits in the CLK_CTRL register (Register 0x25, Bits[7:4]). 

In this mode, the device supports a word width of 16 bits, 24 bits, or 32 bits. TDM2, TDM4, and TDM8 are also supported. See Table 22 for a list of example subordinate modes. Note that there are 

many more configurations that are also supported by the ADXL380. Table 22 is a list of a few examples for reference. If another combination of BCLK and FSYNC is required, the following rules must be followed: 

- If BCLK is used as the system clock, it must be divisible to the required 512 kHz for the system clock. 

- The supported FSYNC rates of 8 kHz, 16 kHz, 24 kHz, or 48 kHz (in HP mode) must be used. When using RBW or LP mode, note that, FSYNC scales. 

_**Table 22. ADXL380 Example Subordinate Modes with No Empty Data Slots[1] (BCLK and FSYNC Are Inputs)**_ 

|**Output Format2**|**Power Mode**|**BCLK Frequency3**<br>**FSYNC Frequency4**<br>**Word Width**<br>**Output Data Rate5**<br>**Data Output Pins**|**BCLK Frequency3**<br>**FSYNC Frequency4**<br>**Word Width**<br>**Output Data Rate5**<br>**Data Output Pins**|**BCLK Frequency3**<br>**FSYNC Frequency4**<br>**Word Width**<br>**Output Data Rate5**<br>**Data Output Pins**|**BCLK Frequency3**<br>**FSYNC Frequency4**<br>**Word Width**<br>**Output Data Rate5**<br>**Data Output Pins**|**BCLK Frequency3**<br>**FSYNC Frequency4**<br>**Word Width**<br>**Output Data Rate5**<br>**Data Output Pins**|
|---|---|---|---|---|---|---|
|I2S or TDM2|HP|3072 kHz|48 kHz|32 bit|8 kHz|SOUT0and SOUT1|
||HP/RBW|1536 kHz|24 kHz|32 bit|8 kHz, 4 kHz|SOUT0and SOUT1|
|||1024 kHz|16 kHz|32 bit|8 kHz, 4 kHz|SOUT0and SOUT1|
|||512 kHz|16 kHz|16 bit|8 kHz, 4 kHz|SOUT0and SOUT1|
||HP/RBW/LP|512 kHz|8 kHz|32 bit|8 kHz, 4 kHz, 2 kHz|SOUT0and SOUT1|
|TDM4|HP|3072 kHz|24 kHz|32 bit|8 kHz, 4 kHz|SOUT0or SOUT1|
||HP/RBW|1536 kHz|12 kHz|32 bit|8 kHz|SOUT0or SOUT1|
|||1024 kHz|8 kHz|32 bit|4 kHz|SOUT0or SOUT1|
|||512 kHz|8 kHz|16 bit|2 kHz|SOUT0or SOUT1|
|TDM8|HP|4096 kHz|16 kHz|32 bit|8 kHz, 4 kHz|SOUT0or SOUT1|
||HP/RBW|2048 kHz|8 kHz|32 bit|8 kHz|SOUT0or SOUT1|
|||1024 kHz|8 kHz|16 bit|4 kHz, 2 kHz|SOUT0or SOUT1|



- 1 X-axis, y-axis, z-axis, and temperature data enabled in Register 0x27. Note that this table is not a comprehensive list. This table represents example configurations with no empty data slots. 

- 2 Note that TDM2, TDM4, and TDM8 are examples. The ADXL380 TDM protocol supports anywhere from 1 to 8 channels. 

- 3 BCLK must be provided externally on the BCLK pin. The frequency must be an integer multiple of 512 kHz such that it can be divided down to 512 kHz by setting the EXT_CLK_RATE bit (Register 0x25, Bits[7:4]). 

- 4 FSYNC must be provided externally on the FSYNC pin. 

- 5 Maximum ADXL380 output data rate for HP, RBW, and LP modes are 16 kHz, 8 kHz, and 4 kHz, respectively. 

**Rev. 0 | 37 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **COMMUNICATIONS** 

## **Signals** 

The ADXL380 uses a 3-wire or 4-wire I[2] S/TDM interface, comprising one continuous serial clock, one synchronization signal, and two serial data channels. There are numerous naming conventions for these channels. The ADXL380 uses the same terminology and symbols as the A[2] B family of transceivers from Analog Devices, Inc. See Table 23 for a comparison of the names used in the I[2] S specification against the names used in the ADXL380. 

_**Table 23. I[2] S Signal Names**_ 

|**_Table 23. I2S Signal Names_**|**_Table 23. I2S Signal Names_**|**_Table 23. I2S Signal Names_**|**_Table 23. I2S Signal Names_**|
|---|---|---|---|
|**I2S Specification**<br>**ADXL380**||||
|**Full Name**<br>**Symbol**<br>**Pin Description**<br>**Mnemonic**||||
|Continuous Serial Clock<br>Word Select<br>Serial Data|SCLK<br>WS<br>SD|Bit clock<br>Frame sync<br>Data transmit|BCLK<br>FSYNC<br>SOUT0and<br>SOUT1|



## **BCLK** 

The bit clock (BCLK) line controls the timing of transactions between the controller (A[2] B transceiver or another controller) and subordinate (ADXL380). This clock can be supplied externally to the BCLK pin (Pin 14) or driven internally from the device. The incoming clock frequency must be a number such that it can be divided down to the expected internal clock for the ADXL380. Set the external clock divide factor (EXT_CLK_RATE in Register 0x25, Bits[7:4]) such that the incoming clock frequency can be divided to 512 kHz. 

## **Sync (FSYNC) Signal** 

In I[2] S, the FSYNC signal indicates the start of a new acceleration sample. The signal alternates between high and low states (with a 50% duty cycle) to indicate whether the sample is for the left or right channel. In TDM mode, the FSYNC signal has a single pulse that is one BCLK cycle wide (set SPT_FSYNC_MODE in the FIFO_CFG0 register (Register 0x32, Bit 3) = 1). This pulse is then followed by up to eight data slots depending on the number of BCLK cycles sent and word width chosen. 

## **Data Transmit (SOUTx) Signal** 

In I[2] S mode, data is sent over both of the SOUT0 and SOUT1 pins. If enabled, SOUT0 contains the x-axis and y-axis data. If enabled, SOUT1 contains the z-axis and temperature data. 

In TDM2 mode, data is sent over both of the SOUT0 and SOUT1 pins. In other TDM modes (for example, TDM4 or TDM8), data is sent over only one data pin (either the SOUT0 or SOUT1 pin, which is configured in the SPT_SOUT_SEL bit in the SPT_CFG2 register (Register 0x34, Bit 7)). In this case, four data slots are required if the x-axis, y-axis, z-axis, and temperature data are enabled (see Register 0x27, DIG_EN). 

## **PDM INTERFACE** 

The ADXL380 PDM port uses a 3-wire interface (see Figure 71): one clock line and two data lines. The two data lines are high performance, 1-bit PDM outputs (SOUT0 and FSYNC). The one-bit data is asserted on the data line on either the rising or falling edge of the system clock to allow the user to stream data from all three acceleration channels (x-axis, y-axis, and z-axis). As shown in Figure 72 (the example PDM data slot configuration), the SOUT0 pin contains the x-axis and y-axis data, and the FSYNC pin contains the z-axis data. Note that, in this example, there is no data on the falling edge for the FSYNC pin, and the output is set to high impedance. 

**==> picture [81 x 116] intentionally omitted <==**

**==> picture [87 x 116] intentionally omitted <==**

_**Figure 71. PDM Wiring Diagram with ADXL380**_ 

**==> picture [200 x 82] intentionally omitted <==**

_**Figure 72. Example PDM Port Data Format**_ 

The pulse density indicates acceleration magnitude and sign. For example, if the ADXL380 is configured in 4 _g_ mode, a 0% PDM density indicates a negative full-scale range (−4 _g_ ). A 50% PDM density indicates 0 _g_ and a 100% PDM density indicates a positive full scale range (+4 _g_ ). The PDM_POL bit (Register 0x37, Bit 7) inverts the polarity of the data so that 0% PDM density is a positive full-scale range. 

The PDM data slots are configurable in Register 0x36 (PDM_CFG). Slot B corresponds to the rising edge on BCLK, and Slot A corresponds to the falling edge on BCLK. The PDM_SOUT0_SLOTB and PDM_SOUT0_SLOTA bits configure which channels are enabled on the SOUT0 pin. The PDM_SOUT1_SLOTA and PDM_SOUT1_SLOTB bits configure which channels are enabled on the FSYNC pin. For example, to match the configuration shown in Figure 72, set Register 0x36 to a value of 0x31, which maps the x-axis to Slot B and the y-axis to Slot A on the SOUT0 pin, and the 

**Rev. 0 | 38 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **COMMUNICATIONS** 

z-axis to Slot B on the FSYNC pin. See Figure 10 for the PDM timing requirements. 

For PDM, the clock provided on the BLCK pin must meet the requirements in Table 5 for fPDM_CLK, and the external clock divider must be set to a value that sets the ADXL380 clock to a valid value (either 512 kHz or 768 kHz). Because latency is often important in audio applications, it is most common to set the system clock to 768 kHz as described in the Low Latency Mode section. 

If the BCLK is 3.072 MHz, set the EXT_CLK_RATE bits (Register 0x25, Bits[7:4]) to 0’b0011, which divides the 3.072 MHz clock by 4 to get to the 768 kHz system clock that the ADXL380 can operate at with low latency. Note that it is important to configure the device in low latency mode if using a 768 kHz system clock. See the Low Latency Mode section for more details. 

**Rev. 0 | 39 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **ADDITIONAL FEATURES** 

## **FREE FALL DETECTION** 

Many digital output accelerometers include a built-in free fall detection feature. In the ADXL380, this function can be implemented using an inactivity interrupt. Refer to the Example: Implementing Free Fall Detection section for more details, including suggested threshold and timing values. 

## **TAP DETECTION** 

The tap interrupt function is capable of detecting either single, double, or triple taps. 

Note that when using a tap threshold less than 1 _g_ , tilting the ADXL380 may also result in a tap event. The following parameters are shown in Figure 73 for a valid single, double, and triple tap event, respectively: 

- The TAP_THRESH register (Register 0x43) sets the acceleration threshold for a tap detection event. 

- The maximum tap duration time is defined by the TAP_DUR register (Register 0x44). The tap duration time represents the maximum time that an event must be more than the tap threshold set in TAP_THRESH register (Register 0x43) to qualify as a tap event. 

- The tap wait time is defined as the time where an event must be less than the threshold to be registered as a tap event. The tap wait time is 2.5 ms. 

- The tap latency time is defined by the TAP_LATENT register (Register 0x45). It is the waiting period from the end of the first tap until the start of the time window where a second tap can be detected. 

- The TAP_WINDOW register (Register 0x46) is the tap duration time where an additional tap can be detected (second or third tap). Although a second tap must begin after the latency time has expired, it does not have to finish before the end of the time defined by the TAP_WINDOW register. If only a singular tap is required, set TAP_WINDOW to 0. 

Additionally, triple tap detection can be enabled by setting the TRIPLE_TAP_EN bit (Register 0x47, TAP_CFG, Bit 2) to b’1. Tap detection can only be implemented on one axis. The tap detection axis is set by the TAP_AXIS bits in the TAP_CFG register (Register 0x47, Bits[1:0]). 

The tap detection status is read with the SINGLE_TAP, DOUBLE_TAP, and TRIPLE_TAP bits located in the STATUS1 register (Register 0x12, Bit 0, Bit 1 and Bit 2, respectively). The tap detection behaves as follow: 

- If only the single tap function is in use, the single tap interrupt is triggered when the acceleration goes to less than the threshold, if the value of time stored in the TAP_DUR register (Register 0x44) has not been exceeded. 

- If both single tap and double tap functions are in use, the single tap interrupt is triggered when the double tap event is either validated or invalidated. 

- If single tap, double tap, and triple tap functions are in use, the single tap and double tap interrupts are triggered when the triple tap event is either validated or invalidated. 

**==> picture [441 x 192] intentionally omitted <==**

_**Figure 73. Tap Interrupt Function with Valid Single Tap, Double Tap, and Triple Tap**_ 

**Rev. 0 | 40 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **ADDITIONAL FEATURES** 

## **EXTERNAL CLOCK** 

The ADXL380 has a nominal clock frequency of 512 kHz that, by default, serves as the time base for internal operations. 

An external clock can be used to improve clock frequency accuracy. To achieve tighter tolerances, a more accurate clock can be provided externally. Additionally, external clock is commonly used with features such as external sync. 

The external clock can be provided on either MCLK or BCLK. This clock can range from 512 kHz to 12.288 MHz for the ADXL380. The clock must be an integer multiple of the nominal clock such that it can be divided down to fit the intended nominal clock frequency by setting the internal divider (EXT_CLK_RATE bits, Register 0x25, Bits[7:4]). The external clock must be divided down to the expected system clock (512 kHz if using HP, RBW, or LP modes or 256 kHz if using VLP, ULP, or HS modes). See Table 16 for more information. 

Note that the external clock must only be configured when in standby mode, and this clock must be set before setting a mode of operation. 

Refer to the Using an External Clock section for more details, including register settings and recommended external clock values. 

## **EXTERNAL TRIGGER** 

For applications that require a precisely timed acceleration measurement, the ADXL380 features an option to synchronize acceleration sampling to an external trigger. This feature is only supported for the low power signal chain (VLP, ULP, and HS operational modes). The external trigger can be used with either an internal or external clock. 

When an external trigger pulse is sent, the ADXL380 outputs one sample data. The user can use this feature to sample data intermittently, which can enable system-level power savings. 

The TRIG_CFG register (Register 0x49) is used to set the external trigger features. The external trigger can be provided on either FSYNC or INT1 by using the TRIG_SRC bit (Bit 1, Register 0x49). The external trigger feature is enabled by setting the TRIG_MODE bit (Register 0x49, Bit 0) to 1. 

- There is no minimum sampling frequency. However, to avoid aliasing, the user must not sample lower than the Nyquist frequency. 

## **EXTERNAL SYNCHRONIZATION** 

For applications that require a precisely timed acceleration measurement, the ADXL380 features an option to synchronize acceleration sampling to an external synchronization signal. This feature is only supported for the high-performance signal chain (HP, RBW, or LP operational modes). External synchronization can be used with either an internal or external clock. 

When an external synchronization frequency is set, the ADXL380 shifts the phase of the data ready (DRDY) signal to match the external synchronization signal. The user can use this feature for systems requiring multiple sensors to have precisely synchronized data sampling. Furthermore, the user can use the interpolation feature to oversample or undersample with improved accuracy. 

The SYNC_CFG register (Register 0x35) is used to set the external synchronization features. The external synchronization signal can be provided on either FSYNC or INT1 by using the SYNC_SRC bit in Register 0x35, Bit 6. The external synchronization feature is set by setting the SYNC_MODE bit (Register 0x35, Bits[5:4]) to the desired value. External synchronization may require an external clock and DRDY. Refer to the External Clock section and the Interrupts section to map the DRDY signal to an interrupt pin. 

The three possible synchronization options for the ADXL380 are no external synchronization (SYNC_MODE = b’00), external synchronization (SYNC_MODE = b’01), and external synchronization with an interpolation filter (SYNC_MODE = b’10). 

Because of internal timing requirements of the ADXL380, the external synchronization signal applied must meet the following criteria: 

- The external synchronization signal must be active high. 

- The pulse width of the external synchronization signal must be at least 5.7 μs. 

- Two consecutive pulses must be at least 5.7 μs apart. 

When external triggering is enabled, it is up to the user to ensure that the sampling frequency meets system requirements. 

Because of the internal timing requirements, the trigger signal applied must meet the following criteria: 

- The trigger signal must be active high. 

- When using the internal oscillator clock, the pulse width of the trigger signal must be at least 5.7 μs. 

- Two consecutive trigger pulses must be at least 5.7 μs apart. 

- The maximum sampling frequency that is supported must be equal to the maximum ODR. 

**Rev. 0 | 41 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **ADDITIONAL FEATURES** 

## **No External Synchronization or Interpolation (SYNC_MODE = b’00)** 

When SYNC_MODE bits in the SYNC_CFG register (Register 0x35, Bits[5:4]) are set to 0, the ADXL380 is in its default external synchronization mode. The ADXL380 has no external synchronization and does not require an external signal to synchronize to. The ADXL380 data sampling is synchronized to the system clock. This 

mode supports an internal or external clock by using the CLK_SRC bits in the CLK_CTRL register (Register 0x25, Bits[1:0]). 

This mode is commonly used when an external processor retrieves the data from the ADXL380 asynchronously. The device samples the data and outputs a DRDY signal each time a new sample becomes available (see Figure 74). 

**==> picture [33 x 65] intentionally omitted <==**

_**Figure 74. No External Synchronization (SYNC_MODE = b'00)**_ 

**Rev. 0 | 42 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **ADDITIONAL FEATURES** 

## **External Synchronization with External Clock (SYNC_MODE = b’01)** 

External synchronization requires an external synchronization signal to align the decimation filter output to a specific clock edge, which provides full external synchronization. In this mode, ODR must be an integer multiple of the synchronization signal frequency. The DRDY signal synchronizes with the external synchronization pulse (see Figure 75). 

The user must provide an external clock that meets the timing requirements (see Table 120). Refer to the Using an External Clock section for more details on how to set up an external clock, including register settings and recommended external clock values. 

The ADXL380 is synchronized to every sync pulse it receives, which means the sync signal can have a lower frequency than the internal ODR. 

**==> picture [37 x 59] intentionally omitted <==**

_**Figure 75. External Synchronization with External Clock (SYNC_MODE = b'01)**_ 

**Rev. 0 | 43 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **ADDITIONAL FEATURES** 

## **External Synchronization with Interpolation (SYNC_MODE = b’10)** 

calculation delay of the interpolation filter is equal to 2.15 μs (see Figure 77). 

Synchronization with the interpolation filter enabled (SYNC_MODE = b'10, Register 0x36, Bits[5:4]) allows the user to sample asynchronously, oversample, or undersample with improved accuracy. This mode is commonly used when syncing is required, but no external clock can be provided. While not being required, an external clock can be used to improve clock frequency accuracy. 

The data interpolation is calculated by computing a linear average between the previous two data samples at the time a sync pulse is active high (see Figure 76). Interpolation increases group delay relative to external sync with external clock mode; however, it guarantees a fixed 1/ODR delay (see Figure 77). The interpolation 

_**Figure 76. Data Interpolation Scheme**_ 

**==> picture [33 x 67] intentionally omitted <==**

_**Figure 77. External Synchronization with Interpolation (SYNC_MODE = b'10)**_ 

**Rev. 0 | 44 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **ADDITIONAL FEATURES** 

## **SELF TEST** 

The ADXL380 incorporates a self-test feature that effectively tests its mechanical and electronic systems simultaneously. When the self-test function is invoked, an electrostatic force is applied to the mechanical sensor. This electrostatic force moves the mechanical sensing element in the same manner as acceleration, and it is an additive to the acceleration experienced by the ADXL380. 

## **USER REGISTER PROTECTION** 

The ADXL380 supports a single event upset (SEU) detection feature for user register protection. When the parity enable register bit (PARITY_ERR, Register 0x20, Bit 5) is set high, the SEU detection feature is enabled on all controllable and /writable register bits (by iterating through all register addresses to calculate the 1-bit sum of all of the register bit positions). If there is a mismatch between the old (stored and valid) parity bit and the current (calculated and valid) parity bit, an SEU parity error generates. 

Either a sticky event bit (PARITY_ERR_STICKY, Register 0x11, Bit 0) or a live event bit (PARITY_ERR, Register 0x20, Bit 5) can be mapped to an interrupt pin if desired. 

An internal 100 Hz clock is used to generate a periodic SEU detection event. Each of these events triggers a parity calculation if the PARITY_EN bit (Register 0x27, Bit 0) is set high. The current and old parity bit are stored for comparison. If there is any mismatch between the valid current parity and the valid old parity, a parity error generates. 

If a parity error occurs, perform a software or hardware reset. 

## **CONCURRENT OPERATING MODES** 

The SAR paths modes (ULP and VLP) can be combined with any one of the Σ-Δ modes (HP, RBW, and LP) for concurrent data sampling. In concurrent mode, the HP, RBW, and LP data is only available on the audio port (I[2] S/TDM/PDM) and the ULP and VLP data is accessed via the control port (SPI or I[2] C). 

Note that the HPF is selectable for either the DSM or SAR signal path, but it is not available for both signal paths in concurrent mode. 

It is possible to use external synchronization pulses (SYNC_MODE (Register 0x35, Bits[5:4]) = 0b01 or 0b10) for the low noise signal path (HP, RBW, and LP modes), and the FIFO_EXT_TRIG bit (Register 0x30, Bit 3) pulses for the low power signal path (ULP, VLP, and HS modes) at the same time. Further details regarding this can be found in the External Trigger section. 

## **INTERRUPTS** 

Several of the built-in functions of the ADXL380 can trigger interrupts to alert the host processor of certain status conditions. Interrupts can be mapped to either (or both) of the two designated output pins, INT0 and INT1, by setting any of the appropriate bits in Register 0x2B to Register 0x2E. All functions can be used 

simultaneously. If multiple interrupts are mapped to one pin, the OR combination of the interrupts determines the status of the pin. 

If no functions are mapped to an interrupt pin, that pin is automatically configured to a high impedance (high-Z) state. These INTx pins are also placed in a high-Z state when reset. 

The INTx pins can be connected to the interrupt input of a host processor where interrupts are responded to with an interrupt routine. 

Because multiple functions can be mapped to the same pin, the STATUSx registers (Register 0x11 to Register 0x14) can be used to determine which condition caused the interrupt to trigger. 

Clear interrupts by one of the following ways: 

- Reading the STATUSx registers clears interrupts (for example, activity, inactivity, undervoltage flag sticky, or parity error sticky). 

- Reading from the data registers, Register 0x14 to Register 0x1B, clears the DRDY interrupt. Note that every enabled channel must be read to clear the interrupt 

- Reading enough data from the FIFO buffer so that interrupt conditions are no longer met clears the FIFO ready and FIFO overrun interrupts. To clear the FIFO_WATERMARK interrupt, the user must also read the FIFO_WATERMARK bit in the STATUS0 register (Register 0x11, Bit 3) and de-assert the chip select line if using SPI communication 

Both interrupt pins are push and pull low impedance pins and have bus keepers when the pins are not internally driven. 

To prevent interrupts from being falsely triggered during configuration, disable interrupts while their settings, such as thresholds, timings, or other values, are configured. 

## **STATUS FLAGS AND ERROR HANDLING** 

The ADXL380 supports several error and status flags that give information about register health, NVM status, FIFO status, activity and inactivity, tap detection, and mechanical overrange and undervoltage monitoring (STATUS0 to STATUS3, Registers 0x11 to Register 0x14). 

## **NVM Status** 

The EFUSE_BUSY_REGERR_STICKY bit in the STATUS0 register (Register 0x11, Bit 5) indicates that a register write has occurred while the NVM was still busy. This bit stays asserted until the STATUS0 register is read. A software or hardware reset is required to clear this error. 

The PARITY_ERR_STICKY bit in the STATUS0 register (Register 0x11, Bit 0) indicates that a SEU error has occurred. See the User Register Protection section for more information on handling this error. 

The NVM_IRQ bit in the STATUS1 register (Register 0x12, Bit 7) indicates that an uncorrectable error has been detected from 

**Rev. 0 | 45 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **ADDITIONAL FEATURES** 

the EFUSE controller checker or the external check enable. The NVM_IRQ bit is an accumulation interrupt status of the EFUSE controller error or with the user NVM_ECC_DET bit and the user NVM_CRC_ERR bit interrupts in the STATUS2 register (Register 0x13, Bit 5 and Bit3, respectively); a user can invoke an EFUSE refresh, an error correcting code (ECC) check, and/or a cyclic redundancy check (CRC) using NVM_CTL register (Register 0x29). A result of any errors can trigger interrupt alarm in the STATUS0 and STATUS2 registers. 

An NVM error can be cleared by reading the STATUSx registers or performing a software or hardware reset. 

## **Overrange** 

Two bits are related to overrange protection on the ADXL380: OVER_RANGE and OVER_RANGE_STICKY in the STATUS1 register (Register 0x12, Bit 3 and Bit 4, respectively). The OVER_RANGE bit indicates that the acceleration input is currently exceeding the overrange threshold. This bit is live and asserts and de-asserts automatically. The OVER_RANGE_STICKY bit indicates that an overrange event has occurred at some point since the last time the STATUS1 register was read. Reading the STATUS1 regis- 

ter clears this bit. See the Overrange Protection section for more information about this protection and the overrange thresholds. 

There are several configuration options for overrange protection (see Table 24). To disable this feature completely, set the DIS_OR_DETECTION bit in the OR_CFG register (Register 0x48, Bit 3) to 1 . To disable the active overrange protection, but keep the overrange detection, set the DIS_OR_PROTECTION bit in the OR_CFG register (Register 0x48, Bit 2) to 1 . 

The user can also configure what happens to the data output during an overrange event as follows: 

- Full-scale code with correct sign (data is railed in the same direction as the input acceleration) 

- Hold previous data value before overrange event (data is frozen at the value just before the overrange event occurred) 

- Do nothing to the data 

Note that when using PDM communication, the data always defaults to full-scale code with the same sign as the input acceleration. 

_**Table 24. Overrange Protection Options**_ 

|**_Table 24. Overrange Protection Options_**|**_Table 24. Overrange Protection Options_**|**_Table 24. Overrange Protection Options_**|**_Table 24. Overrange Protection Options_**|
|---|---|---|---|
|**Settings**<br>**Overrange Protection?**<br>**Overrange Detection?**<br>**Register Configuration**||||
|Completely Enable (Default)<br>Completely Disable<br>Detection Only|Yes<br>No<br>No|Yes<br>No<br>Yes|Register 0x48, Bits[2:3] = 00<br>Register 0x48, Bit 3 = 1<br>Register 0x48, Bit 2 = 1|



**Rev. 0 | 46 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **LATENCY** 

The ADXL380 offer several options for controlling the trade-off between output noise and latency (or group delay) to accommodate a wide range of system requirements. 

There are several filters that can be enabled or bypassed to optimize latency. Using a filter with a lower cutoff frequency introduces more delay to the signal chain but improves output noise. Conversely, less aggressive filtering results in more output noise but less delay. The optimal compromise between these two parameters depends on system implementation. 

Figure 78 shows three different configurations to optimize latency: default configuration, low latency + IIR1, and low latency mode. Note that Figure 78 shows the latency of the entire signal chain up to the last digital filter. When streaming data using I[2] S or TDM, there is also a serial port delay of up to one frame. For example, a 48 kHz FSYNC results in a serial port delay of up to 20.8 µs. 

## **LOW LATENCY MODE** 

The ADXL380 offers an option to lower latency by running the device at 768 kHz instead of 512 kHz. This mode is only supported with the use of an external clock. Refer to the Using an External Clock section for more details, including register settings. Low latency mode allows the ODR to go up to 48 kHz. Ensure that the provided BCLK and FSYNC signals are fast enough to support this data rate (for example, BCLK = 3.072 MHz and FSYNC = 48 kHz). Low latency mode increases power consumption; however, it significantly decreases latency. 

To enable this mode on the ADXL380, set the DOUBLE_SPEED bit in the DIG_EN register (Register 0x27, Bit 2) to b’1, set the SINC_RATE bit in the TRIG_CFG register (Register 0x49, Bit 6) to b’1, and bypass the following filters: EQ, DCF, IIR7, and IIR1 (optional). 

**==> picture [385 x 279] intentionally omitted <==**

_**Figure 78. ADXL380 Latency vs. Filter Options**_ 

_**Table 25. Filter Latency in HP Mode**_ 

|**System Clock**|**MEMS and AFE (µs)**|**MEMS and AFE (µs)**|**SINC (µs),**<br>**SINC_RATE**|**SINC (µs),**<br>**SINC_RATE**|**EQ (µs)1**<br>**IIR1 (µs)1**<br>**LPF (µs)1**<br>**DCF (µs)**<br>**IIR7 (µs)**<br>**HPF (µs)**|**EQ (µs)1**<br>**IIR1 (µs)1**<br>**LPF (µs)1**<br>**DCF (µs)**<br>**IIR7 (µs)**<br>**HPF (µs)**|**EQ (µs)1**<br>**IIR1 (µs)1**<br>**LPF (µs)1**<br>**DCF (µs)**<br>**IIR7 (µs)**<br>**HPF (µs)**|**EQ (µs)1**<br>**IIR1 (µs)1**<br>**LPF (µs)1**<br>**DCF (µs)**<br>**IIR7 (µs)**<br>**HPF (µs)**|**EQ (µs)1**<br>**IIR1 (µs)1**<br>**LPF (µs)1**<br>**DCF (µs)**<br>**IIR7 (µs)**<br>**HPF (µs)**|**EQ (µs)1**<br>**IIR1 (µs)1**<br>**LPF (µs)1**<br>**DCF (µs)**<br>**IIR7 (µs)**<br>**HPF (µs)**|**EQ (µs)1**<br>**IIR1 (µs)1**<br>**LPF (µs)1**<br>**DCF (µs)**<br>**IIR7 (µs)**<br>**HPF (µs)**|
|---|---|---|---|---|---|---|---|---|---|---|---|
||||**0**<br>**1**|||||||||
|512 kHz|X/Y|25|100|60|X/Y|190|160|SeeTable 26|65|270|SeeTable 26|
||Z|40|100|60|Z|205|160|SeeTable 26|65|270|SeeTable 26|
|768 kHz|X/Y|25|70|40|X/Y|40|55|SeeTable 26|45|180|SeeTable 26|
||Z|40|70|40|Z|50|55|SeeTable 26|45|180|SeeTable 26|



> 1 The EQ, IIR1, and LPF filters all share the same filter engine. Only one can be enabled at a time. 

**Rev. 0 | 47 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **LATENCY** 

_**Table 26. LPF and HPF Latency in HP Mode**_ 

|**System Clock**|**LPF (µs), LPF_MODE**<br>**HPF (µs), HPF_CORNER**|**LPF (µs), LPF_MODE**<br>**HPF (µs), HPF_CORNER**|**LPF (µs), LPF_MODE**<br>**HPF (µs), HPF_CORNER**|**LPF (µs), LPF_MODE**<br>**HPF (µs), HPF_CORNER**|**LPF (µs), LPF_MODE**<br>**HPF (µs), HPF_CORNER**|**LPF (µs), LPF_MODE**<br>**HPF (µs), HPF_CORNER**|**LPF (µs), LPF_MODE**<br>**HPF (µs), HPF_CORNER**|**LPF (µs), LPF_MODE**<br>**HPF (µs), HPF_CORNER**|**LPF (µs), LPF_MODE**<br>**HPF (µs), HPF_CORNER**|**LPF (µs), LPF_MODE**<br>**HPF (µs), HPF_CORNER**|**LPF (µs), LPF_MODE**<br>**HPF (µs), HPF_CORNER**|
|---|---|---|---|---|---|---|---|---|---|---|---|
||**0**<br>**1**<br>**2**<br>**3**<br>**0**<br>**1**<br>**2**<br>**3**<br>**4**<br>**5**<br>**6**|||||||||||
|512 kHz<br>768 kHz|Not<br>applicable<br>Not<br>applicable|175<br>60|270<br>90|505<br>170|Not<br>applicable<br>Not<br>applicable|3.3<br>2.2|0.8<br>0.6|0.2<br>0.1|0.05<br>0.04|0.01<br>0.009|0.003<br>0.002|



**Rev. 0 | 48 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **SERIAL COMMUNICATIONS** 

_**Table 27. SPI Write Command in Half Duplex**_ 

|**Command**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**15**<br>**14**<br>**13**<br>**12**<br>**11**<br>**10**<br>**9**<br>**8**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**||||||||||||||||
|SDI|A6|A5|A4|A3|A2|A1|A0|0|D7|D6|D5|A4|D3|D2|D1|D0|
|SDO|High-Z|High-Z|High-Z|High-Z|High-Z|High-Z|High-Z|High-Z|High-Z|High-Z|High-Z|High-Z|High-Z|High-Z|High-Z|High-Z|



_**Table 28. SPI Read Command in Half Duplex**_ 

|**Command**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|**Bit**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
||**15**<br>**14**<br>**13**<br>**12**<br>**11**<br>**10**<br>**9**<br>**8**<br>**7**<br>**6**<br>**5**<br>**4**<br>**3**<br>**2**<br>**1**<br>**0**||||||||||||||||
|SDI|A6|A5|A4|A3|A2|A1|A0|1|NE|NE|NE|NE|NE|NE|NE|NE|
|SDO|High-Z|High-Z|High-Z|High-Z|High-Z|High-Z|High-Z|High-Z|D7|D6|D5|A4|D3|D2|D1|D0|



_**Table 29. SDO Command Bit Definitions**_ 

|**_Table 29. SDO Command Bit Definitions_**|**_Table 29. SDO Command Bit Definitions_**|**_Table 29. SDO Command Bit Definitions_**|**_Table 29. SDO Command Bit Definitions_**|**_Table 29. SDO Command Bit Definitions_**|**_Table 29. SDO Command Bit Definitions_**|
|---|---|---|---|---|---|
|**Bit Name**<br>**Position**<br>**Description**<br>**Definition**||||||
|A[6:0]|15 … 9|Address field||Defines the address of the register from which data is read or to which data is written.||
|R/W|8|Read/write bit||Differentiates the SDI command as either read or write.<br>1: read<br>0: write||
|D[7:0]|7 … 0|Data field||Write command: contains data to be written to the register at the [A6:A0] bits.<br>Read command: no function, contents are ignored.||
|**_Table 30. SDO Response Bit Definitions_**||||||
|**Bit Name**<br>**Position**<br>**Description**<br>**Definition**||||||
|High-Z[7:0]|15 … 8||High impedance||Undriven bits.|
|D[7:0]|7 … 0||Data field||This 8-bit data field contains the data from the register address in Bits[A6:A0].|



## **SPI BUS SHARING** 

When using the ADXL380 on the same SPI bus as another sensor, additional protection may be needed to maintain ultralow noise performance, which is especially important if the other device uses a SPI clock of 15 MHz or greater. 

**Rev. 0 | 49 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

_**Table 31. ADXL380 Register Summary**_ 

|**_Table 31. ADXL380 Register Summary_**|**_Table 31. ADXL380 Register Summary_**|**_Table 31. ADXL380 Register Summary_**|**_Table 31. ADXL380 Register Summary_**|**_Table 31. ADXL380 Register Summary_**|**_Table 31. ADXL380 Register Summary_**|**_Table 31. ADXL380 Register Summary_**|**_Table 31. ADXL380 Register Summary_**|**_Table 31. ADXL380 Register Summary_**|**_Table 31. ADXL380 Register Summary_**|**_Table 31. ADXL380 Register Summary_**|**_Table 31. ADXL380 Register Summary_**|**_Table 31. ADXL380 Register Summary_**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Reg**<br>**Name**<br>**Bits**<br>**Bit 7**<br>**Bit 6**<br>**Bit 5**<br>**Bit 4**<br>**Bit 3**<br>**Bit 2**<br>**Bit 1**<br>**Bit 0**<br>**Reset**<br>**R/W**|||||||||||||
|0x00|DEVID_AD|[7:0]|DEVID_AD||||||||0xAD|R|
|0x01|DEVID_MST|[7:0]|DEVID_MST||||||||0x1D|R|
|0x02|PART_ID|[7:0]|PART_ID[11:4]||||||||0x17|R|
|0x03|PART_ID_REV_I<br>D|[7:0]|PART_ID[3:0]||||REV_ID||||0xC2|R|
|0x04|SERIAL_NUMBE<br>R_0|[7:0]|FAB|||ASCII0[5:1]|||||0x00|R|
|0x05|SERIAL_NUMBE<br>R_1|[7:0]|ASCII0[0]|ASCII1||||||ASCII2[5]|0x00|R|
|0x06|SERIAL_NUMBE<br>R_2|[7:0]|ASCII2[4:0]|||||BCD[6:4]|||0x00|R|
|0x07|SERIAL_NUMBE<br>R_3|[7:0]|BCD[3:0]||||WAFER[4:1]||||0x00|R|
|0x08|SERIAL_NUMBE<br>R_4|[7:0]|WAFER[0]|XCO|||||||0x00|R|
|0x09|SERIAL_NUMBE<br>R_5|[7:0]|YCO|||||||PARITY|0x00|R|
|0x0A|SERIAL_NUMBE<br>R_6|[7:0]|SN6_RESERVED||||||||0x00|R|
|0x0B|DEV_DELTA_Q_<br>X|[7:0]|DEV_DELTA_Q_X||||||||0x00|R|
|0x0C|DEV_DELTA_Q_<br>Y|[7:0]|DEV_DELTA_Q_Y||||||||0x00|R|
|0x0D|DEV_DELTA_Q_<br>Z|[7:0]|DEV_DELTA_Q_Z||||||||0x00|R|
|0x0E|DEV_DELTA_F0<br>_X|[7:0]|DEV_DELTA_F0_X||||||||0x00|R|
|0x0F|DEV_DELTA_F0<br>_Y|[7:0]|DEV_DELTA_F0_Y||||||||0x00|R|
|0x10|DEV_DELTA_F0<br>_Z|[7:0]|DEV_DELTA_F0_Z||||||||0x00|R|
|0x11|STATUS0|[7:0]|NVM_BUSY<br>_STATUS|NVM_DONE|EFUSE_BU<br>SY_REGER<br>R_STICKY|FIFO_READ<br>Y|FIFO_WATE<br>RMARK|FIFO_OVER<br>RUN|FIFO_FULL|PARITY_ER<br>R_STICKY|0x80|R|
|0x12|STATUS1|[7:0]|NVM_IRQ|INACT|ACT|OVER_RAN<br>GE_STICKY|OVER_RAN<br>GE|TRIPLE_TA<br>P|DOUBLE_T<br>AP|SINGLE_TA<br>P|0x00|R|
|0x13|STATUS2|[7:0]|NVM_ECC_<br>DONE|RESERVED|NVM_ECC_<br>DET|NVM_CRC_<br>DONE|NVM_CRC_<br>ERR|RESERVED|UV_FLAG_<br>STICKY|UV_FLAG|0x04|R|
|0x14|STATUS3|[7:0]|RESERVED|||||||DATA_REA<br>DY|0x00|R|
|0x15|XDATA_H|[7:0]|XDATA_H||||||||0x00|R|
|0x16|XDATA_L|[7:0]|XDATA_L||||||||0x00|R|
|0x17|YDATA_H|[7:0]|YDATA_H||||||||0x00|R|
|0x18|YDATA_L|[7:0]|YDATA_L||||||||0x00|R|
|0x19|ZDATA_H|[7:0]|ZDATA_H||||||||0x00|R|
|0x1A|ZDATA_L|[7:0]|ZDATA_L||||||||0x00|R|
|0x1B|TDATA_H|[7:0]|TDATA_H||||||||0x00|R|
|0x1C|TDATA_L|[7:0]|TDATA_L||||XSENS_DSM||||0x00|R|
|0x1D|FIFO_DATA|[7:0]|FIFO_DATA||||||||0x00|R|
|0x1E|FIFO_STATUS0|[7:0]|FIFO_ENTRIES[7:0]||||||||0x00|R|



**Rev. 0 | 50 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

_**Table 31. ADXL380 Register Summary (Continued)**_ 

|**_Table 31. ADXL380 Register Summary (Continued)_**|**_Table 31. ADXL380 Register Summary (Continued)_**|**_Table 31. ADXL380 Register Summary (Continued)_**|**_Table 31. ADXL380 Register Summary (Continued)_**|**_Table 31. ADXL380 Register Summary (Continued)_**|**_Table 31. ADXL380 Register Summary (Continued)_**|**_Table 31. ADXL380 Register Summary (Continued)_**|**_Table 31. ADXL380 Register Summary (Continued)_**|**_Table 31. ADXL380 Register Summary (Continued)_**|**_Table 31. ADXL380 Register Summary (Continued)_**|**_Table 31. ADXL380 Register Summary (Continued)_**|**_Table 31. ADXL380 Register Summary (Continued)_**|**_Table 31. ADXL380 Register Summary (Continued)_**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Reg**<br>**Name**<br>**Bits**<br>**Bit 7**<br>**Bit 6**<br>**Bit 5**<br>**Bit 4**<br>**Bit 3**<br>**Bit 2**<br>**Bit 1**<br>**Bit 0**<br>**Reset**<br>**R/W**|||||||||||||
|0x1F|FIFO_STATUS1|[7:0]|RESERVED|||||||FIFO_ENTR<br>IES[8]|0x00|R|
|0x20|MISC0|[7:0]|XL382|PARITY_RE<br>G|PARITY_ER<br>R|GAIN_SCALER_XY|||||0x00|R|
|0x21|MISC1|[7:0]|RESERVED|||GAIN_SCALER_Z|||||0x00|R|
|0x24|SENS_DSM|[7:0]|YSENS_DSM||||ZSENS_DSM||||0x00|R|
|0x25|CLK_CTRL|[7:0]|EXT_CLK_RATE||||RESERVED||CLK_SRC||0x00|R/W|
|0x26|OP_MODE|[7:0]|RANGE||PDM_MOD<br>E|AUDIO_MO<br>DE|OP_MODE||||0x00|R/W|
|0x27|DIG_EN|[7:0]|MODE_CHANNEL_EN||||FIFO_EN|DOUBLE_S<br>PEED|INT01_EVE<br>NT|PARITY_EN|0x00|R/W|
|0x28|SAR_I2C|[7:0]|I2C_BYPAS<br>S|I2C_HSM_E<br>N|I2C_SDA_S<br>LOW|RESERVED||||DRDY_SEL|0x00|R/W|
|0x29|NVM_CTL|[7:0]|NVM_CTL_<br>ECC_CHEC<br>K|NVM_CTL_<br>CRC_CHEC<br>K|RESERVED||||||0x00|R/W|
|0x2A|REG_RESET|[7:0]|RESERVED||||||SOFT_RES<br>ET|RESERVED|0x00|R/W|
|0x2B|INT0_MAP0|[7:0]|NVM_BUSY<br>_INT0|INACT_INT0|ACT_INT0|RESERVED|FIFO_WATE<br>RMARK_IN<br>T0|FIFO_OVER<br>RUN_INT0|FIFO_FULL<br>_INT0|DATA_RDY_<br>INT0|0x80|R/W|
|0x2C|INT0_MAP1|[7:0]|NVM_DONE<br>_INT0|NVM_IRQ_I<br>NT0|UV_FLAG_I<br>NT0|OVER_RAN<br>GE_INT0|PARITY_ER<br>R_INT0|TRIPLE_TA<br>P_INT0|DOUBLE_T<br>AP_INT0|SINGLE_TA<br>P_INT0|0x00|R/W|
|0x2D|INT1_MAP0|[7:0]|NVM_BUSY<br>_INT1|INACT_INT1|ACT_INT1|RESERVED|FIFO_WATE<br>RMARK_IN<br>T1|FIFO_OVER<br>RUN_INT1|FIFO_FULL<br>_INT1|DATA_RDY_<br>INT1|0x00|R/W|
|0x2E|INT1_MAP1|[7:0]|NVM_DONE<br>_INT1|NVM_IRQ_I<br>NT1|UV_FLAG_I<br>NT1|OVER_RAN<br>GE_INT1|PARITY_ER<br>R_INT1|TRIPLE_TA<br>P_INT1|DOUBLE_T<br>AP_INT1|SINGLE_TA<br>P_INT1|0x80|R/W|
|0x30|FIFO_CFG0|[7:0]|FIFO_READ<br>_RESET|FIFO_CH_I<br>D|FIFO_MODE||FIFO_EXT_<br>TRIG|RESERVED||FIFO_SAMP<br>LES[8]|0x00|R/W|
|0x31|FIFO_CFG1|[7:0]|FIFO_SAMPLES[7:0]||||||||0x00|R/W|
|0x32|SPT_CFG0|[7:0]|SPT_SLOT_WIDTH||SPT_BCLK_<br>POL|SPT_FSYN<br>C_POL|SPT_FSYN<br>C_MODE|SPT_DATA_FORMAT|||0x00|R/W|
|0x33|SPT_CFG1|[7:0]|SPT_XTRA_<br>SAMP|SPT_TRI_S<br>TATE|SPT_Y_SLOT|||SPT_X_SLOT|||0x08|R/W|
|0x34|SPT_CFG2|[7:0]|SPT_SOUT<br>_SEL|SPT_DUAL_<br>MODE|SPT_TEMP_SLOT|||SPT_Z_SLOT|||0x1A|R/W|
|0x35|SYNC_CFG|[7:0]|RESERVED|SYNC_SRC|SYNC_MODE||BCLK_SRC||FSYNC_SRC||0x00|R/W|
|0x36|PDM_CFG|[7:0]|PDM_FSYNC_SLOTB||PDM_FSYNC_SLOTA||PDM_SOUT0_SLOTB||PDM_SOUT0_SLOTA||0x00|R/W|
|0x37|ACT_INACT_CT<br>L|[7:0]|PDM_POL|ACT_INACT<br>_HPF|LINKLOOP||INACT_EN||ACT_EN||0x00|R/W|
|0x38|SNSR_AXIS_EN|[7:0]|ST_MODE|ST_FORCE|ST_DIR|RESERVED||ACT_INACT_AXIS_EN|||0x00|R/W|
|0x39|THRESH_ACT_H|[7:0]|RESERVED|||||THRESH_ACT[10:8]|||0x00|R/W|
|0x3A|THRESH_ACT_L|[7:0]|THRESH_ACT[7:0]||||||||0x00|R/W|
|0x3B|TIME_ACT_H|[7:0]|TIME_ACT[23:16]||||||||0x00|R/W|
|0x3C|TIME_ACT_M|[7:0]|TIME_ACT[15:8]||||||||0x00|R/W|
|0x3D|TIME_ACT_L|[7:0]|TIME_ACT[7:0]||||||||0x00|R/W|
|0x3E|THRESH_INACT<br>_H|[7:0]|RESERVED|||||THRESH_INACT[10:8]|||0x00|R/W|
|0x3F|THRESH_INACT<br>_L|[7:0]|THRESH_INACT[7:0]||||||||0x00|R/W|



**Rev. 0 | 51 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

_**Table 31. ADXL380 Register Summary (Continued)**_ 

|**_Table 31. ADXL380 Register Summary (Continued)_**|**_Table 31. ADXL380 Register Summary (Continued)_**|**_Table 31. ADXL380 Register Summary (Continued)_**|**_Table 31. ADXL380 Register Summary (Continued)_**|**_Table 31. ADXL380 Register Summary (Continued)_**|**_Table 31. ADXL380 Register Summary (Continued)_**|**_Table 31. ADXL380 Register Summary (Continued)_**|**_Table 31. ADXL380 Register Summary (Continued)_**|**_Table 31. ADXL380 Register Summary (Continued)_**|**_Table 31. ADXL380 Register Summary (Continued)_**|**_Table 31. ADXL380 Register Summary (Continued)_**|**_Table 31. ADXL380 Register Summary (Continued)_**|**_Table 31. ADXL380 Register Summary (Continued)_**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**Reg**<br>**Name**<br>**Bits**<br>**Bit 7**<br>**Bit 6**<br>**Bit 5**<br>**Bit 4**<br>**Bit 3**<br>**Bit 2**<br>**Bit 1**<br>**Bit 0**<br>**Reset**<br>**R/W**|||||||||||||
|0x40|TIME_INACT_H|[7:0]|TIME_INACT[23:16]||||||||0x00|R/W|
|0x41|TIME_INACT_M|[7:0]|TIME_INACT[15:8]||||||||0x00|R/W|
|0x42|TIME_INACT_L|[7:0]|TIME_INACT[7:0]||||||||0x00|R/W|
|0x43|TAP_THRESH|[7:0]|TAP_THRESH_PRESCALE||||||||0x00|R/W|
|0x44|TAP_DUR|[7:0]|TAP_DUR||||||||0x00|R/W|
|0x45|TAP_LATENT|[7:0]|TAP_LATENT||||||||0x00|R/W|
|0x46|TAP_WINDOW|[7:0]|TAP_WINDOW||||||||0x00|R/W|
|0x47|TAP_CFG|[7:0]|RESERVED|||||TRIPLE_TA<br>P_EN|TAP_AXIS||0x00|R/W|
|0x48|OR_CFG|[7:0]|RESERVED|||DIS_UV_DE<br>T|DIS_OR_DE<br>TECTION|DIS_OR_PR<br>OTECTION|DIG_OUT_DURING_OR||0x00|R/W|
|0x49|TRIG_CFG|[7:0]|DEC_2X_B<br>YPASS|SINC_RATE|IIR1_EN|RESERVED||ROUND_M<br>ODE|TRIG_SRC|TRIG_MOD<br>E|0x00|R/W|
|0x4A|X_SAR_OFFSET|[7:0]|X_SAR_OFFSET||||||||0x00|R/W|
|0x4B|Y_SAR_OFFSET|[7:0]|Y_SAR_OFFSET||||||||0x00|R/W|
|0x4C|Z_SAR_OFFSET|[7:0]|Z_SAR_OFFSET||||||||0x00|R/W|
|0x4D|X_DSM_OFFSET|[7:0]|X_DSM_OFFSET||||||||0x00|R/W|
|0x4E|Y_DSM_OFFSET|[7:0]|Y_DSM_OFFSET||||||||0x00|R/W|
|0x4F|Z_DSM_OFFSET|[7:0]|Z_DSM_OFFSET||||||||0x00|R/W|
|0x50|FILTER|[7:0]|DCF_BYPA<br>SS|EQ_BYPAS<br>S|LPF_MODE||HPF_PATH|HPF_CORNER|||0x00|R/W|
|0x55|USER_TEMP_S<br>ENS_0|[7:0]|RESERVED||USER_TEMP_OFFSET||||||0x00|R/W|
|0x56|USER_TEMP_S<br>ENS_1|[7:0]|USER_TEM<br>P_TRIM_EN|HIGH_GAIN<br>_TEMP|RESERVED|USER_TEMP_SENS|||||0x00|R/W|
|0x58|MISO|[7:0]|RESERVED|GAIN_SCAL<br>ER_BYPAS<br>S|RESERVED||||MISO_ASEL<br>0_PD|MISO_ASEL<br>0_DRV|0x00|R/W|
|0x59|SOUT0|[7:0]|RESERVED||||||SOUT0_PD|SOUT0_DR<br>V|0x00|R/W|
|0x5A|MCLK|[7:0]|RESERVED||||||MCLK_PD|MCLK_DRV|0x00|R/W|
|0x5B|BCLK|[7:0]|RESERVED||||||BCLK_PD|BCLK_DRV|0x00|R/W|
|0x5C|FSYNC|[7:0]|SYNC_RES<br>YNC|RESERVED|||||FSYNC_PD|FSYNC_DR<br>V|0x00|R/W|
|0x5D|INT0|[7:0]|INT0_POL|RESERVED|||||INT0_PD|INT0_DRV|0x00|R/W|
|0x5E|INT1|[7:0]|INT1_POL|RESERVED|||||INT1_PD|INT1_DRV|0x00|R/W|



## **ANALOG DEVICES DEVICE ID REGISTER** 

**Address: 0x00, Reset: 0xAD, Name: DEVID_AD** 

_**Table 32. Bit Descriptions for DEVID_AD**_ 

|**_Table 32. Bit Descriptions for DEVID_AD_**|**_Table 32. Bit Descriptions for DEVID_AD_**|**_Table 32. Bit Descriptions for DEVID_AD_**|**_Table 32. Bit Descriptions for DEVID_AD_**|**_Table 32. Bit Descriptions for DEVID_AD_**|**_Table 32. Bit Descriptions for DEVID_AD_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|DEVID_AD||This register contains the Analog Devices device ID.|0xAD|R|



**Rev. 0 | 52 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

## **ANALOG DEVICES MEMS DEVICE ID REGISTER** 

## **Address: 0x01, Reset: 0x1D, Name: DEVID_MST** 

## _**Table 33. Bit Descriptions for DEVID_MST**_ 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|DEVID_MST||This register contains the Analog Devices MEMS device ID.|0x1D|R|



## **PART ID REGISTER** 

**Address: 0x02, Reset: 0x17, Name: PART_ID** 

## _**Table 34. Bit Descriptions for PART_ID**_ 

|**Bits**|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|---|
||[7:0]|PART_ID[11:4]||This register contains the device ID (380 = 17C in hex).|0x17|R|



## **PART ID AND REVISION ID REGISTER** 

## **Address: 0x03, Reset: 0xC2, Name: PART_ID_REV_ID** 

_**Table 35. Bit Descriptions for PART_ID_REV_ID**_ 

|[7:4]|PART_ID[3:0]||This register contains the device ID (380 = 17C in hex).|0xC|R|
|---|---|---|---|---|---|
|[3:0]|REV_ID||This register contains the product revision ID.|0x2|R|



## **SERIAL NUMBER 0 REGISTER** 

## **Address: 0x04, Reset: 0x00, Name: SERIAL_NUMBER_0** 

_**Table 36. Bit Descriptions for SERIAL_NUMBER_0**_ 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:5]|FAB||Fab Code. This register is part of a 56-bit product serial number. The fab code is an upper case<br>alphabetic character that represents the wafer fabrication facility. Four binary bits are used to support<br>up to 8 wafer fabrication facilities, the fourth bit is always 0. 0b0000 = A = TSMC-Fab 8. 0b0001 = B<br>= TSMC-Fab 3. All other codes are undefined.|0x0|R|
|[4:0]|ASCII0[5:1]||Serial Number Second ASCII Character. This register is part of a 56-bit product serial number. An<br>upper case A through Z alphabetic character or 0 through 9 numeric character is represented by a<br>6-bit binary field. Coding starts at 0b000000 = 0 up to 0b001001 = 9, 0b001010 = A up to 0b100011<br>= Z, and 0b100100 to 0b111111 are not used.|0x0|R|



**Rev. 0 | 53 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

## **SERIAL NUMBER 1 REGISTER** 

## **Address: 0x05, Reset: 0x00, Name: SERIAL_NUMBER_1** 

**==> picture [309 x 57] intentionally omitted <==**

_**Table 37. Bit Descriptions for SERIAL_NUMBER_1**_ 

|**_Table 37. Bit Descriptions for SERIAL_NUMBER_1_**|**_Table 37. Bit Descriptions for SERIAL_NUMBER_1_**|**_Table 37. Bit Descriptions for SERIAL_NUMBER_1_**|**_Table 37. Bit Descriptions for SERIAL_NUMBER_1_**|**_Table 37. Bit Descriptions for SERIAL_NUMBER_1_**|**_Table 37. Bit Descriptions for SERIAL_NUMBER_1_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|7|ASCII0[0]|Serial<br>upper<br>6-bit<br>Z, an|Number Second ASCII Character. This register is part of a 56-bit product serial number. An<br>case A through Z alphabetic character or 0 through 9 numeric character is represented by a<br>binary field. Coding starts at 0b000000 = 0 up to 0b001001 = 9, 0b001010 = A up to 0b100011 =<br>d 0b100100 to 0b111111 are not used.|0x0|R|
|[6:1]|ASCII1|Serial<br>case<br>binar<br>and 0|Number Third ASCII Character. This register is part of a 56-bit product serial number. An upper<br>A through Z alphabetic character or 0 through 9 numeric character is represented by a 6-bit<br>y field. Coding starts at 0b000000 = 0 up to 0b001001 = 9, 0b001010 = A up to 0b100011 = Z,<br>b100100 to 0b111111 are not used.|0x0|R|
|0|ASCII2[5]|Serial<br>upper<br>6-bit<br>Z, an|Number Fourth ASCII Character. This register is part of a 56-bit product serial number. An<br>case A through Z alphabetic character or 0 through 9 numeric character is represented by a<br>binary field. Coding starts at 0b000000 = 0 up to 0b001001 = 9, 0b001010 = A up to 0b100011 =<br>d 0b100100 to 0b111111 are not used.|0x0|R|



## **SERIAL NUMBER 2 REGISTER** 

**Address: 0x06, Reset: 0x00, Name: SERIAL_NUMBER_2** 

**==> picture [247 x 35] intentionally omitted <==**

_**Table 38. Bit Descriptions for SERIAL_NUMBER_2**_ 

|**_Table 38. Bit Descriptions for SERIAL_NUMBER_2_**|**_Table 38. Bit Descriptions for SERIAL_NUMBER_2_**|**_Table 38. Bit Descriptions for SERIAL_NUMBER_2_**|**_Table 38. Bit Descriptions for SERIAL_NUMBER_2_**|**_Table 38. Bit Descriptions for SERIAL_NUMBER_2_**|**_Table 38. Bit Descriptions for SERIAL_NUMBER_2_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:3]|ASCII2[4:0]|Seri<br>upp<br>6-bit<br>= Z,|al Number Fourth ASCII Character. This register is part of a 56-bit product serial number. An<br>er case A through Z alphabetic character or 0 through 9 numeric character is represented by a<br>binary field. Coding starts at 0b000000 = 0 up to 0b001001 = 9, 0b001010 = A up to 0b100011<br>and 0b100100 to 0b111111 are not used.|0x0|R|
|[2:0]|BCD[6:4]|Seri<br>repr<br>a ra<br>eve|al Number BCD Digits. This register is part of a 56-bit product serial number. This field<br>esents a three-digit decimal number. All three digits are treated as one decimal number having<br>nge of 000 to 999 using a 10-bit binary field. All numbers are padded to the left by zeroes in the<br>nt that the three-digit number is less than Decimal 100.|0x0|R|



## **SERIAL NUMBER 3 REGISTER** 

**Address: 0x07, Reset: 0x00, Name: SERIAL_NUMBER_3** 

**==> picture [243 x 36] intentionally omitted <==**

**Rev. 0 | 54 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

_**Table 39. Bit Descriptions for SERIAL_NUMBER_3**_ 

|**_Table 39. Bit Descriptions for SERIAL_NUMBER_3_**|**_Table 39. Bit Descriptions for SERIAL_NUMBER_3_**|**_Table 39. Bit Descriptions for SERIAL_NUMBER_3_**|**_Table 39. Bit Descriptions for SERIAL_NUMBER_3_**|**_Table 39. Bit Descriptions for SERIAL_NUMBER_3_**|**_Table 39. Bit Descriptions for SERIAL_NUMBER_3_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:4]|BCD[3:0]||Serial Number BCD Digits. This register is part of a 56-bit product serial number. This field<br>represents a three-digit decimal number. All three digits are treated as one decimal number having<br>a range of 000 to 999 using a 10-bit binary field. All numbers are padded to the left by zeroes in the<br>event that the three-digit number is less than Decimal 100.|0x0|R|
|[3:0]|WAFER[4:1]||Wafer ID Number. This register is part of a 56-bit product serial number. It is a 1 through 31 decimal<br>number. A 5-bit binary value is used to support this field. Wafer Number 0 is not supported.|0x0|R|



## **SERIAL NUMBER 4 REGISTER** 

## **Address: 0x08, Reset: 0x00, Name: SERIAL_NUMBER_4** 

**==> picture [220 x 36] intentionally omitted <==**

_**Table 40. Bit Descriptions for SERIAL_NUMBER_4**_ 

|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|
|---|---|---|---|---|---|
|7|WAFER[0]||Wafer ID Number. This register is part of a 56-bit product serial number. It is a 1 through 31 decimal<br>number. A 5-bit binary value is used to support this field. Wafer Number 0 is not supported.|0x0|R|
|[6:0]|XCO||X Die Coordinate. This register is part of a 56-bit product serial number. It is the XCO[8:2] X die<br>coordinate, and has nine bits for Integer −256 to Integer +256.|0x0|R|



## **SERIAL NUMBER 5 REGISTER** 

## **Address: 0x09, Reset: 0x00, Name: SERIAL_NUMBER_5** 

**==> picture [199 x 37] intentionally omitted <==**

## _**Table 41. Bit Descriptions for SERIAL_NUMBER_5**_ 

|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|
|---|---|---|---|---|---|
|[7:1]|YCO||Y Die Coordinate. This register is part of a 56-bit product serial number.|0x0|R|
|0|PARITY||Parity Bit. This register is part of a 56-bit product serial number.|0x0|R|



## **SERIAL NUMBER 6 REGISTER** 

## **Address: 0x0A, Reset: 0x00, Name: SERIAL_NUMBER_6** 

**==> picture [187 x 44] intentionally omitted <==**

## _**Table 42. Bit Descriptions for SERIAL_NUMBER_6**_ 

|**_Table 42. Bit Descriptions for SERIAL_NUMBER_6_**|**_Table 42. Bit Descriptions for SERIAL_NUMBER_6_**|**_Table 42. Bit Descriptions for SERIAL_NUMBER_6_**|**_Table 42. Bit Descriptions for SERIAL_NUMBER_6_**|**_Table 42. Bit Descriptions for SERIAL_NUMBER_6_**|**_Table 42. Bit Descriptions for SERIAL_NUMBER_6_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|SN6_RESERVED||Serial Number 6 Register (Reserved for Used). This register is part of a 56-bit product serial<br>number. [7:5] = YCO[2:0] = Y Die Coordinate. It has nine bits for Integer −256 to Integer<br>+256. [3:0] = CRC[3:0] = 4 bit CRC for the content of the 51-bit serial number value.|0x0|R|



**Rev. 0 | 55 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

## **DEVICE SENSOR PARAMETER REGISTERS** 

## **Address: 0x0B, Reset: 0x00, Name: DEV_DELTA_Q_X** 

**==> picture [190 x 36] intentionally omitted <==**

## _**Table 43. Bit Descriptions for DEV_DELTA_Q_X**_ 

|**_Table 43. Bit Descriptions for DEV_DELTA_Q_X_**|**_Table 43. Bit Descriptions for DEV_DELTA_Q_X_**|**_Table 43. Bit Descriptions for DEV_DELTA_Q_X_**|**_Table 43. Bit Descriptions for DEV_DELTA_Q_X_**|**_Table 43. Bit Descriptions for DEV_DELTA_Q_X_**|**_Table 43. Bit Descriptions for DEV_DELTA_Q_X_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|DEV_DELTA_Q_X||Sensor Parameter. Deviation of X sensor quality factor from the nominal value. Data<br>in twos complement format. Resolution = 0.007. The sensor quality factor at ambient<br>temperature can be calculated by Q_XL380 = Q_NOMINAL + 0.007 × DEV_DELTA_Q.|0x0|R|



## **Address: 0x0C, Reset: 0x00, Name: DEV_DELTA_Q_Y** 

**==> picture [190 x 36] intentionally omitted <==**

## _**Table 44. Bit Descriptions for DEV_DELTA_Q_Y**_ 

|**_Table 44. Bit Descriptions for DEV_DELTA_Q_Y_**|**_Table 44. Bit Descriptions for DEV_DELTA_Q_Y_**|**_Table 44. Bit Descriptions for DEV_DELTA_Q_Y_**|**_Table 44. Bit Descriptions for DEV_DELTA_Q_Y_**|**_Table 44. Bit Descriptions for DEV_DELTA_Q_Y_**|**_Table 44. Bit Descriptions for DEV_DELTA_Q_Y_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|DEV_DELTA_Q_Y||Sensor Parameter. Deviation of Y sensor quality factor from the nominal value. Data<br>in twos complement format. Resolution = 0.007. The sensor quality factor at ambient<br>temperature can be calculated by Q_XL380 = Q_NOMINAL + 0.007 × DEV_DELTA_Q.|0x0|R|



## **Address: 0x0D, Reset: 0x00, Name: DEV_DELTA_Q_Z** 

**==> picture [190 x 36] intentionally omitted <==**

_**Table 45. Bit Descriptions for DEV_DELTA_Q_Z**_ 

|**_Table 45. Bit Descriptions for DEV_DELTA_Q_Z_**|**_Table 45. Bit Descriptions for DEV_DELTA_Q_Z_**|**_Table 45. Bit Descriptions for DEV_DELTA_Q_Z_**|**_Table 45. Bit Descriptions for DEV_DELTA_Q_Z_**|**_Table 45. Bit Descriptions for DEV_DELTA_Q_Z_**|**_Table 45. Bit Descriptions for DEV_DELTA_Q_Z_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|DEV_DELTA_Q_Z||Sensor Parameter. Deviation of Z sensor quality factor from the nominal value. Data<br>in twos complement format. Resolution = 0.003. The sensor quality factor at ambient<br>temperature can be calculated by Q_XL380 = Q_NOMINAL + 0.003 × DEV_DELTA_Q.|0x0|R|



## **Address: 0x0E, Reset: 0x00, Name: DEV_DELTA_F0_X** 

**==> picture [192 x 36] intentionally omitted <==**

_**Table 46. Bit Descriptions for DEV_DELTA_F0_X**_ 

|**_Table 46. Bit Descriptions for DEV_DELTA_F0_X_**|**_Table 46. Bit Descriptions for DEV_DELTA_F0_X_**|**_Table 46. Bit Descriptions for DEV_DELTA_F0_X_**|**_Table 46. Bit Descriptions for DEV_DELTA_F0_X_**|**_Table 46. Bit Descriptions for DEV_DELTA_F0_X_**|**_Table 46. Bit Descriptions for DEV_DELTA_F0_X_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|DEV_DELTA_F0_X||Sensor Parameter. Deviation of X sensor resonant frequency from the nominal value.<br>Data in twos complement format. Resolution = 10 Hz. Refer toTable 1for the Nominal<br>F0 value. The sensor resonant frequency can be calculated by F0_XL380 (Hz) =<br>F0_NOMINAL (Hz) + 10 Hz × DEV_DELTA_F0.|0x0|R|



**Rev. 0 | 56 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

## **Address: 0x0F, Reset: 0x00, Name: DEV_DELTA_F0_Y** 

**==> picture [192 x 36] intentionally omitted <==**

## _**Table 47. Bit Descriptions for DEV_DELTA_F0_Y**_ 

|**_Table 47. Bit Descriptions for DEV_DELTA_F0_Y_**|**_Table 47. Bit Descriptions for DEV_DELTA_F0_Y_**|**_Table 47. Bit Descriptions for DEV_DELTA_F0_Y_**|**_Table 47. Bit Descriptions for DEV_DELTA_F0_Y_**|**_Table 47. Bit Descriptions for DEV_DELTA_F0_Y_**|**_Table 47. Bit Descriptions for DEV_DELTA_F0_Y_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|DEV_DELTA_F0_Y|S<br>D<br>F<br>F|ensor Parameter. Deviation of Y sensor resonant frequency from the nominal value.<br>ata in twos complement format. Resolution = 10 Hz. Refer toTable 1for the Nominal<br>0 value. The sensor resonant frequency can be calculated by F0_XL380 (Hz) =<br>0_NOMINAL (Hz) + 10 Hz × DEV_DELTA_F0.|0x0|R|



## **Address: 0x10, Reset: 0x00, Name: DEV_DELTA_F0_Z** 

**==> picture [192 x 36] intentionally omitted <==**

_**Table 48. Bit Descriptions for DEV_DELTA_F0_Z**_ 

|**_Table 48. Bit Descriptions for DEV_DELTA_F0_Z_**|**_Table 48. Bit Descriptions for DEV_DELTA_F0_Z_**|**_Table 48. Bit Descriptions for DEV_DELTA_F0_Z_**|**_Table 48. Bit Descriptions for DEV_DELTA_F0_Z_**|**_Table 48. Bit Descriptions for DEV_DELTA_F0_Z_**|**_Table 48. Bit Descriptions for DEV_DELTA_F0_Z_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|DEV_DELTA_F0_Z|S<br>D<br>F<br>F|ensor Parameter. Deviation of Z sensor resonant frequency from the nominal value.<br>ata in twos complement format. Resolution = 7 Hz. Refer toTable 1for the Nominal<br>0 value. The sensor resonant frequency can be calculated by F0_XL380 (Hz) =<br>0_NOMINAL (Hz) + 7 Hz × DEV_DELTA_F0.|0x0|R|



## **STATUS 0 REGISTER (CLEAR ON READ)** 

**Address: 0x11, Reset: 0x80, Name: STATUS0** 

**==> picture [314 x 101] intentionally omitted <==**

_**Table 49. Bit Descriptions for STATUS0**_ 

|**_Table 49. Bit Descriptions for STATUS0_**|**_Table 49. Bit Descriptions for STATUS0_**|**_Table 49. Bit Descriptions for STATUS0_**|**_Table 49. Bit Descriptions for STATUS0_**|**_Table 49. Bit Descriptions for STATUS0_**|**_Table 49. Bit Descriptions for STATUS0_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|7|NVM_BUSY_STATUS||NVM EFUSE Busy Status (Read Only). When power-on-reset (POR) or a<br>soft reset occurs, EFUSE is refreshed, which takes about 2.2 ms. When<br>this refresh occurs, EFUSE is busy during refresh right after power is<br>stable. The NVM_BUSY_STATUS bit is high (default) right out of POR or<br>soft reset. It remains high until EFUSE refresh is complete. Once EFUSE<br>refresh is completed, this bit is clear. The NVM_EFUSE_BUSY bit can be<br>monitored at the INT0 pin out of reset. NVM_BUSY_STATUS is set again<br>(default) during POR and soft reset.|0x1|R|
|6|NVM_DONE||NVM EFUSE Done Status (Sticky). When POR or a soft reset occurs,<br>EFUSE is refreshed which takes about 2.2 ms. When this is completed,<br>it clears NVM_BUSY_STATUS to 0 and sets NVM_DONE to 1. Default<br>value at POR is 1'b0. This NVM_DONE register bit is clear on read.|0x0|R|



**Rev. 0 | 57 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

_**Table 49. Bit Descriptions for STATUS0 (Continued)**_ 

|**_Table 49. Bit Descriptions for STATUS0(Continued)_**|**_Table 49. Bit Descriptions for STATUS0(Continued)_**|**_Table 49. Bit Descriptions for STATUS0(Continued)_**|**_Table 49. Bit Descriptions for STATUS0(Continued)_**|**_Table 49. Bit Descriptions for STATUS0(Continued)_**|**_Table 49. Bit Descriptions for STATUS0(Continued)_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|5|EFUSE_BUSY_REGERR_STICKY|EFUSE BU<br>during EFU|SY Register Error Sticky Status. When register write occurs<br>SE_BUSY = 1, an alarm triggers and reports sticky status.|0x0|R|
|4|FIFO_READY|FIFO Read<br>available in|y (Data Available). 1 indicates that there is at least one sample<br>the FIFO output buffer.|0x0|R|
|3|FIFO_WATERMARK|FIFO Water<br>desired num<br>FIFO_WAT<br>is written to<br>event which<br>SPI for the<br>clear the FI<br>pin).|mark. 1 indicates that the FIFO contains at least the<br>ber of samples, as set in the FIFO_SAMPLES register.<br>ERMARK is asserted when the next sample (above the value)<br>the FIFO. FIFO_WATERMARK behaves like an interrupt<br>contributes to an interrupt output. It clears on read. If using<br>FIFO data read, the<br>CS line must be deasserted as well to<br>FO_WATERMARK bit and interrupt (if mapped to an interrupt|0x0|R|
|2|FIFO_OVERRUN|FIFO Overr<br>of FIFO_OV<br>updated mo<br>to first axis<br>FIFO_OVE<br>sample set.|un Status. In FIFO stream and trigger mode, the assertion<br>ERRUN indicates FIFO contents are overwritten with most<br>tion or thermal sensor data. FIFO read pointer is advanced<br>of oldest sample set in the FIFO. The first time read after<br>RRUN assertion always returns the first axis data of the<br>FIFO_OVERRUN is not specified in FIFO normal mode.|0x0|R|
|1|FIFO_FULL|FIFO Full. F<br>samples if e|IFO_FULL is set when the FIFO collects 320 samples (or 318<br>xactly three channels are enabled).|0x0|R|
|0|PARITY_ERR_STICKY|Parity Error<br>Event 0 →<br>INT01_EVE<br>trigger.) A s|Sticky Status Bit. This bit can be trigger high by a Parity Error<br>1 or a parity error to its live status (PARITY_ERR) trigger. (The<br>NT register bit can be used, and the default is to a live status<br>ingle register read clears the parity error sticky bit.|0x0|R|



## **STATUS 1 REGISTER (CLEAR ON READ)** 

**Address: 0x12, Reset: 0x00, Name: STATUS1** 

**==> picture [261 x 101] intentionally omitted <==**

_**Table 50. Bit Descriptions for STATUS1**_ 

|**_Table 50. Bit Descriptions for STATUS1_**|**_Table 50. Bit Descriptions for STATUS1_**|**_Table 50. Bit Descriptions for STATUS1_**|**_Table 50. Bit Descriptions for STATUS1_**|**_Table 50. Bit Descriptions for STATUS1_**|**_Table 50. Bit Descriptions for STATUS1_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|7|NVM_IRQ||NVM/EFUSE IRQ Status (Sticky). When uncorrectable error is detected from either<br>EFUSE controller checker or external check enable, this bit is set. The NVM_IRQ<br>register is an accumulation interrupt status of the EFUSE controller error or with<br>User NVM_ECC_DET and User NVM_CRC_ERR interrupts. (A user can invoke an<br>EFUSE refresh, an ECC check, and/or a CRC check using the NVM_CTL register.)<br>A result of any errors can trigger an interrupt alarm in the STATUS0 and STATUS2<br>registers.|0x0|R|
|6|INACT||Inactivity. 1 indicates that the inactivity detection function has detected inactivity.|0x0|R|
|5|ACT||Activity. 1 indicates that the activity detection function has detected an over threshold<br>condition.|0x0|R|
|4|OVER_RANGE_STICKY||Overrange Sticky Status Bit. Indicates that the acceleration input has exceeded the<br>overrange threshold. The bit is sticky. (The INT01_EVENT register bit can be used,|0x0|R|



**Rev. 0 | 58 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

_**Table 50. Bit Descriptions for STATUS1 (Continued)**_ 

|**_Table 50. Bit Descriptions for STATUS1(Continued)_**|**_Table 50. Bit Descriptions for STATUS1(Continued)_**|**_Table 50. Bit Descriptions for STATUS1(Continued)_**|**_Table 50. Bit Descriptions for STATUS1(Continued)_**|**_Table 50. Bit Descriptions for STATUS1(Continued)_**|**_Table 50. Bit Descriptions for STATUS1(Continued)_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
||||and the default is a live status trigger.) A single register read clears the overrange<br>sticky bit.|||
|3|OVER_RANGE||Overrange. Indicates that the current acceleration input exceeds the<br>overrange threshold. Overrange detection can be disable by enabling the<br>DIS_OR_DETECTION register bit.|0x0|R|
|2|TRIPLE_TAP||Triple TAP Status. The TRIPLE_TAP bit is set when TRIPLE_TAP_EN is set and<br>three acceleration events that are greater than the value in the TAP_THRESH<br>register occur for less time than is specified in the TAP_DUR register. The third tap<br>starts after the time specified by the TAP_LATENT register plus the 2.5 ms settling<br>time but within the time specified in the TAP_WINDOW register after the double tap is<br>valid.|0x0|R|
|1|DOUBLE_TAP||Double TAP Status. The DOUBLE_TAP is set when TAP_WINDOW and<br>TAP_LATENT is greater than 0 and two acceleration events that are greater<br>than the value in the TAP_THRESH register occur for less time than is specified<br>in the TAP_DUR register. The second tap starts after the time specified by the<br>TAP_LATENT register plus TAP settling time of 2.5 ms but within the time specified in<br>the TAP_WINDOW register|0x0|R|
|0|SINGLE_TAP||Single TAP Status. The SINGLE_TAP bit is set when a single acceleration event that<br>is greater than the value in the TAP_THRESH register occurs for less time than is<br>specified in the TAP_DUR register.|0x0|R|



## **STATUS 2 REGISTER (CLEAR ON READ)** 

## **Address: 0x13, Reset: 0x04, Name: STATUS2** 

**==> picture [273 x 92] intentionally omitted <==**

_**Table 51. Bit Descriptions for STATUS2**_ 

|**_Table 51. Bit Descriptions for STATUS2_**|**_Table 51. Bit Descriptions for STATUS2_**|**_Table 51. Bit Descriptions for STATUS2_**|**_Table 51. Bit Descriptions for STATUS2_**|**_Table 51. Bit Descriptions for STATUS2_**|**_Table 51. Bit Descriptions for STATUS2_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|7|NVM_ECC_DONE||EFUSE ECC Done. When the NVM ECC done status bit is set high, it indicates<br>that the NVM controller has completed the ECC check request. Disabling the<br>NVM_CTL_ECC_CHECK bit in Register NVM_CTL, clears the NVM_ECC_DONE bit.|0x0|R|
|6|RESERVED||Reserved.|0x0|R|
|5|NVM_ECC_DET||EFUSE ECC Corrected. When the NVM ECC detect status bit is set high, it indicates<br>that the NVM controller has detected two single event upset (SEU) events, which is<br>uncorrectable. In the event that the ECC error is detected with two SEU events, refresh<br>the shadow registers by using the SOFT_RESET bit (Register REG_RESET). After a<br>SOFT_RESET event, the NVM_ECC_DET is clear.|0x0|R|
|4|NVM_CRC_DONE||EFUSE CRC Done. When the NVM CRC done status bit is set high, it indicates<br>that the NVM controller has completed the CRC check request. A clear of the<br>NVM_CTL_CRC_CHECK bit (Register NVM_CTL), clears the NVM_CRC_DONE bit.|0x0|R|
|3|NVM_CRC_ERR||EFUSE CRC Error. When the NVM CRC error status bit is set high, it indicates that the<br>NVM controller completed the CRC check with a CRC error event (an error syndrome was<br>found).|0x0|R|
|2|RESERVED||Reserved.|0x1|R|



**Rev. 0 | 59 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

_**Table 51. Bit Descriptions for STATUS2 (Continued)**_ 

|**_Table 51. Bit Descriptions for STATUS2(Continued)_**|**_Table 51. Bit Descriptions for STATUS2(Continued)_**|**_Table 51. Bit Descriptions for STATUS2(Continued)_**|**_Table 51. Bit Descriptions for STATUS2(Continued)_**|**_Table 51. Bit Descriptions for STATUS2(Continued)_**|**_Table 51. Bit Descriptions for STATUS2(Continued)_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|1|UV_FLAG_STICKY||UV Flag Sticky Status Bit. The flag high indicating that a prebrownout event (the V1P8<br>pin voltage falls to less than 1.5 V but still above the POR trigger point) has happened.<br>(The INT01_EVENT register bit can be used, and the default is a live status trigger.) A<br>single register read clears the undervoltage sticky bit. The UV flag detect can be disable<br>by enabling the DIS_UV_DET bit (Register OR_CFG). The V1P8 pin (voltage) is the power<br>supply voltage that is supplied to the core analog and digital circuitry (non-IO portion of<br>the chip), nominally 1.8 V and always observable at the V1P8pin. In regulator mode, it is<br>regulated down from the voltage supply. In overdrive mode, the 1.8 V core supply voltage is<br>directly supplied by the V1P8pin.|0x0|R|
|0|UV_FLAG||UV Flag from Analog. This bit is the UV flag status bit. When the undervoltage detector is<br>enabled, a live status flag is alarmed during a prebrownout event (the VIP8pin voltage falls<br>to less than 1.5 V; however, it is still more than the POR trigger point). The UV detector<br>feature can be disabled through the DIS_UV_DET bit.|0x0|R|



## **STATUS 3 REGISTER (CLEAR ON READ)** 

## **Address: 0x14, Reset: 0x00, Name: STATUS3** 

**==> picture [229 x 37] intentionally omitted <==**

_**Table 52. Bit Descriptions for STATUS3**_ 

|**_Table 52. Bit Descriptions for STATUS3_**|**_Table 52. Bit Descriptions for STATUS3_**|**_Table 52. Bit Descriptions for STATUS3_**|**_Table 52. Bit Descriptions for STATUS3_**|**_Table 52. Bit Descriptions for STATUS3_**|**_Table 52. Bit Descriptions for STATUS3_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:1]|RESERVED||Reserved.|0x0|R|
|0|DATA_READY||Data Ready. 1 indicates that a new valid sample is available to be read. This bit clears when<br>a data read is performed. DATA_READY is set again when new valid data is available; if<br>DATA_READY = 0 prior to a register read and new data becomes available after a complete<br>sample is read. During the old sample register read, DATA_READY is set to 1 to indicate a new<br>sample has arrived until the first byte of the new sample is read. If DATA_READY = 1 prior<br>to a register read, but a newer sample has arrived, the newest sample is provided, and it is<br>cleared at the start of the newest register read. The prior new data is discarded silently. When<br>the read is complete, DATA_READY is cleared to 0. DATA_READY is also available at am<br>external pin (SOUT) if the DRDY_SEL bit (Register SAR_I2C) is set to 1. DATA_READY is also<br>available to contribute to an external output (INT0 or INT1) if the DATA_RDY_INT0 bit (Register<br>INT0_MAP0) or the DATA_RDY_INT1 bit (Register INT1_MAP0) are set high.|0x0|R|



## **X AXIS DATA OUTPUT READ (HIGH BYTE, BITS[15:8]) REGISTER** 

**Address: 0x15, Reset: 0x00, Name: XDATA_H** 

**==> picture [164 x 37] intentionally omitted <==**

_**Table 53. Bit Descriptions for XDATA_H**_ 

|**_Table 53. Bit Descriptions for XDATA_H_**|**_Table 53. Bit Descriptions for XDATA_H_**|**_Table 53. Bit Descriptions for XDATA_H_**|**_Table 53. Bit Descriptions for XDATA_H_**|**_Table 53. Bit Descriptions for XDATA_H_**|**_Table 53. Bit Descriptions for XDATA_H_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|XDATA_H||X Axis Output Data High Byte. Resolution determined by dynamic range setting (see the Sensitivity<br>specification inTable 1). When using the VLP, ULP, or HS modes, the four LSBs in this register are<br>always zero because these modes use a 12-bit SAR.|0x0|R|



**Rev. 0 | 60 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

## **X AXIS DATA OUTPUT READ (LOW BYTE, BITS[7:0]) REGISTER** 

## **Address: 0x16, Reset: 0x00, Name: XDATA_L** 

**==> picture [162 x 37] intentionally omitted <==**

## _**Table 54. Bit Descriptions for XDATA_L**_ 

|**_Table 54. Bit Descriptions for XDATA_L_**|**_Table 54. Bit Descriptions for XDATA_L_**|**_Table 54. Bit Descriptions for XDATA_L_**|**_Table 54. Bit Descriptions for XDATA_L_**|**_Table 54. Bit Descriptions for XDATA_L_**|**_Table 54. Bit Descriptions for XDATA_L_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|XDATA_L||X Axis Output Data Low Byte. Resolution determined by dynamic range setting (see the Sensitivity<br>specification inTable 1). When using the VLP, ULP, or HS modes, the four LSBs in this register are<br>always zero because these modes use a 12-bit SAR.|0x0|R|



## **Y AXIS DATA OUTPUT READ (HIGH BYTE, BITS[15:8]) REGISTER** 

## **Address: 0x17, Reset: 0x00, Name: YDATA_H** 

**==> picture [163 x 37] intentionally omitted <==**

_**Table 55. Bit Descriptions for YDATA_H**_ 

|**_Table 55. Bit Descriptions for YDATA_H_**|**_Table 55. Bit Descriptions for YDATA_H_**|**_Table 55. Bit Descriptions for YDATA_H_**|**_Table 55. Bit Descriptions for YDATA_H_**|**_Table 55. Bit Descriptions for YDATA_H_**|**_Table 55. Bit Descriptions for YDATA_H_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|YDATA_H||Y Axis Output Data High Byte. Resolution determined by dynamic range setting (see the Sensitivity<br>specification inTable 1). When using the VLP, ULP, or HS modes, the four LSBs in this register are<br>always zero because these modes use a 12-bit SAR.|0x0|R|



## **Y AXIS DATA OUTPUT READ (LOW BYTE, BITS[7:0]) REGISTER** 

## **Address: 0x18, Reset: 0x00, Name: YDATA_L** 

**==> picture [162 x 38] intentionally omitted <==**

_**Table 56. Bit Descriptions for YDATA_L**_ 

|**_Table 56. Bit Descriptions for YDATA_L_**|**_Table 56. Bit Descriptions for YDATA_L_**|**_Table 56. Bit Descriptions for YDATA_L_**|**_Table 56. Bit Descriptions for YDATA_L_**|**_Table 56. Bit Descriptions for YDATA_L_**|**_Table 56. Bit Descriptions for YDATA_L_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|YDATA_L||Y Axis Output Data Low Byte. Resolution determined by dynamic range setting (see the Sensitivity<br>specification inTable 1). When using the VLP, ULP, or HS modes, the four LSBs in this register are<br>always zero because these modes use a 12-bit SAR.|0x0|R|



## **Z AXIS DATA OUTPUT READ (HIGH BYTE, BITS[15:8]) REGISTER** 

**Address: 0x19, Reset: 0x00, Name: ZDATA_H** 

**==> picture [162 x 38] intentionally omitted <==**

**Rev. 0 | 61 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

_**Table 57. Bit Descriptions for ZDATA_H**_ 

|**_Table 57. Bit Descriptions for ZDATA_H_**|**_Table 57. Bit Descriptions for ZDATA_H_**|**_Table 57. Bit Descriptions for ZDATA_H_**|**_Table 57. Bit Descriptions for ZDATA_H_**|**_Table 57. Bit Descriptions for ZDATA_H_**|**_Table 57. Bit Descriptions for ZDATA_H_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|ZDATA_H||Z Axis Output Data High Byte. Resolution determined by dynamic range setting (see the Sensitivity<br>specification inTable 1). When using the VLP, ULP, or HS modes, the four LSBs in this register are<br>always zero because these modes use a 12-bit SAR.|0x0|R|



## **Z AXIS DATA OUTPUT READ (LOW BYTE, BITS[7:0]) REGISTER** 

## **Address: 0x1A, Reset: 0x00, Name: ZDATA_L** 

**==> picture [162 x 38] intentionally omitted <==**

_**Table 58. Bit Descriptions for ZDATA_L**_ 

|**_Table 58. Bit Descriptions for ZDATA_L_**|**_Table 58. Bit Descriptions for ZDATA_L_**|**_Table 58. Bit Descriptions for ZDATA_L_**|**_Table 58. Bit Descriptions for ZDATA_L_**|**_Table 58. Bit Descriptions for ZDATA_L_**|**_Table 58. Bit Descriptions for ZDATA_L_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|ZDATA_L||Z Axis Output Data Low Byte. Resolution determined by dynamic range setting (see the Sensitivity<br>specification inTable 1). When using the VLP, ULP, or HS modes, the four LSBs in this register are<br>always zero because these modes use a 12-bit SAR.|0x0|R|



## **TEMPERATURE DATA OUTPUT READ (HIGH BYTE) REGISTER** 

## **Address: 0x1B, Reset: 0x00, Name: TDATA_H** 

**==> picture [162 x 37] intentionally omitted <==**

## _**Table 59. Bit Descriptions for TDATA_H**_ 

|**_Table 59. Bit Descriptions for TDATA_H_**|**_Table 59. Bit Descriptions for TDATA_H_**|**_Table 59. Bit Descriptions for TDATA_H_**|**_Table 59. Bit Descriptions for TDATA_H_**|**_Table 59. Bit Descriptions for TDATA_H_**|**_Table 59. Bit Descriptions for TDATA_H_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|TDATA_H||Temperature Output Data High Byte. Temperature sensor sensitivity for HIGH_GAIN_TEMP (Register<br>USER_TEMP_SENS_1) = 0 is 10.2 LSB/°C and for HIGH_GAIN_TEMP = 1 is 16.5 LSB/°C.|0x0|R|



## **TEMPERATURE DATA OUTPUT READ (LOW BYTE) AND SENSOR DSM REGISTER** 

## **Address: 0x1C, Reset: 0x00, Name: TDATA_L** 

**==> picture [252 x 38] intentionally omitted <==**

_**Table 60. Bit Descriptions for TDATA_L**_ 

|**_Table 60. Bit Descriptions for TDATA_L_**|**_Table 60. Bit Descriptions for TDATA_L_**|**_Table 60. Bit Descriptions for TDATA_L_**|**_Table 60. Bit Descriptions for TDATA_L_**|**_Table 60. Bit Descriptions for TDATA_L_**|**_Table 60. Bit Descriptions for TDATA_L_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:4]|TDATA_L||Temperature Output Data Low Byte. Temperature sensor sensitivity for HIGH_GAIN_TEMP<br>(Register USER_TEMP_SENS_1) = 0 is 10.2 LSB/°C and for HIGH_GAIN_TEMP = 1) is 16.5<br>LSB/°C.|0x0|R|
|[3:0]|XSENS_DSM||Sensitivity Xsens (DSM Path). Read-only X-axis digital sensitivity (fine) trim for low noise signal<br>path (HP, LP, or RBW mode). Data is in unsigned format. This sensitivity trim value is digitally<br>multiplied with the signal path output, and the result is truncated by removing seven LSBs (/128)<br>and then adding them back to the signal path. In PDM mode, this digital fine trim is not applied;<br>therefore, the user must read back this value and apply the same digital multiplication and<br>truncation to the PDM output.|0x0|R|



**Rev. 0 | 62 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

## **FIFO READ DATA (FROM FIFO BLOCK) REGISTER** 

## **Address: 0x1D, Reset: 0x00, Name: FIFO_DATA** 

**==> picture [170 x 36] intentionally omitted <==**

## _**Table 61. Bit Descriptions for FIFO_DATA**_ 

|**_Table 61. Bit Descriptions for FIFO_DATA_**|**_Table 61. Bit Descriptions for FIFO_DATA_**|**_Table 61. Bit Descriptions for FIFO_DATA_**|**_Table 61. Bit Descriptions for FIFO_DATA_**|**_Table 61. Bit Descriptions for FIFO_DATA_**|**_Table 61. Bit Descriptions for FIFO_DATA_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|FIFO_DATA||FIFO Data Value (from FIFO Block). When enabled, data can be stored in the FIFO. When reading<br>the FIFO_DATA register, the data of each axes is provided in 16-bit signed numbers.|0x0|R|



## **FIFO STATUS REGISTERS** 

## **Address: 0x1E, Reset: 0x00, Name: FIFO_STATUS0** 

**==> picture [199 x 36] intentionally omitted <==**

_**Table 62. Bit Descriptions for FIFO_STATUS0**_ 

|**_Table 62. Bit Descriptions for FIFO_STATUS0_**|**_Table 62. Bit Descriptions for FIFO_STATUS0_**|**_Table 62. Bit Descriptions for FIFO_STATUS0_**|**_Table 62. Bit Descriptions for FIFO_STATUS0_**|**_Table 62. Bit Descriptions for FIFO_STATUS0_**|**_Table 62. Bit Descriptions for FIFO_STATUS0_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|FIFO_ENTRIES[7:0]|F<br>F<br>m|IFO Current Entries (Write Pointer). FIFO_ENTRIES track the number of entries that the<br>IFO controller wrote into the FIFO memory. Users read FIFO_ENTRIES to know how<br>any FIFO entries they must read to not overrun the FIFO write pointer.|0x0|R|



## **Address: 0x1F, Reset: 0x00, Name: FIFO_STATUS1** 

**==> picture [270 x 36] intentionally omitted <==**

_**Table 63. Bit Descriptions for FIFO_STATUS1**_ 

|**_Table 63. Bit Descriptions for FIFO_STATUS1_**|**_Table 63. Bit Descriptions for FIFO_STATUS1_**|**_Table 63. Bit Descriptions for FIFO_STATUS1_**|**_Table 63. Bit Descriptions for FIFO_STATUS1_**|**_Table 63. Bit Descriptions for FIFO_STATUS1_**|**_Table 63. Bit Descriptions for FIFO_STATUS1_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:1]|RESERVED|Res|erved.|0x0|R|
|0|FIFO_ENTRIES[8]|FIF<br>FIF<br>FIF|O Current Entries (Write Pointer). FIFO_ENTRIES track the number of entries that the<br>O controller wrote into the FIFO memory. Users read FIFO_ENTRIES to know how many<br>O entries they must read to not overrun the FIFO write pointer.|0x0|R|



## **MISCELLANEOUS 0 (READ ONLY) REGISTER** 

**Address: 0x20, Reset: 0x00, Name: MISC0** 

**==> picture [311 x 82] intentionally omitted <==**

**Rev. 0 | 63 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

_**Table 64. Bit Descriptions for MISC0**_ 

|**_Table 64. Bit Descriptions for MISC0_**|**_Table 64. Bit Descriptions for MISC0_**|**_Table 64. Bit Descriptions for MISC0_**|**_Table 64. Bit Descriptions for MISC0_**|**_Table 64. Bit Descriptions for MISC0_**|**_Table 64. Bit Descriptions for MISC0_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|7|XL382|0<br>1|ADXL380 or ADXL382 Device (Different Sensors). When set, the device indicates the<br>ADXL382 revision.<br>ADXL380 variant.<br>ADXL382 variant.|0x0|R|
|6|PARITY_REG||Parity Error Register. When the calculated parity value is not matched against the stored<br>calculated parity value, a register of the parity error is set and remains set until the device<br>is reset or until a register write occurs. The chip generates a start signal periodically if the<br>parity check is enabled by the user.|0x0|R|
|5|PARITY_ERR||Parity Error Register. When the calculated parity value is not matched against the stored<br>calculated parity value, this register of the parity error is set and remains set until the<br>device is reset or until a register write occurs.|0x0|R|
|[4:0]|GAIN_SCALER_XY||Gain Scaler X and Y Axes. These bits are the Trim Gain Scaler X and Trim Gain Scaler<br>Y axes values. The gain value is calculated by the register value/4. For example, setting<br>these bits to a value of four represents a gain of 1.|0x0|R|



## **MISCELLANEOUS 1 (READ ONLY) REGISTER** 

## **Address: 0x21, Reset: 0x00, Name: MISC1** 

**==> picture [247 x 36] intentionally omitted <==**

_**Table 65. Bit Descriptions for MISC1**_ 

|**_Table 65. Bit Descriptions for MISC1_**|**_Table 65. Bit Descriptions for MISC1_**|**_Table 65. Bit Descriptions for MISC1_**|**_Table 65. Bit Descriptions for MISC1_**|**_Table 65. Bit Descriptions for MISC1_**|**_Table 65. Bit Descriptions for MISC1_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:5]|RESERVED||Reserved.|0x0|R|
|[4:0]|GAIN_SCALER_Z||Gain Scaler Z Axis. These bits are the Trim Gain Scaler Z axis value. The gain value<br>is calculated by the register value/4. For example, setting these bits to a value of four<br>represents a gain of 1.|0x0|R|



## **SENSOR DSM REGISTER** 

## **Address: 0x24, Reset: 0x00, Name: SENS_DSM** 

**==> picture [266 x 38] intentionally omitted <==**

_**Table 66. Bit Descriptions for SENS_DSM**_ 

|**_Table 66. Bit Descriptions for SENS_DSM_**|**_Table 66. Bit Descriptions for SENS_DSM_**|**_Table 66. Bit Descriptions for SENS_DSM_**|**_Table 66. Bit Descriptions for SENS_DSM_**|**_Table 66. Bit Descriptions for SENS_DSM_**|**_Table 66. Bit Descriptions for SENS_DSM_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:4]|YSENS_DSM||Sensitivity Ysens (DSM Path). Read-only Y-axis digital sensitivity (fine) trim for low noise signal<br>path (HP, LP, or RBW mode). Data is in unsigned format. This sensitivity trim value is digitally<br>multiplied with the signal path output, and the result is truncated by removing seven LSBs (/128)<br>and then adding them back to the signal path. In PDM mode, this digital fine trim is not applied;<br>therefore, the user must read back this value and apply the same digital multiplication and<br>truncation to the PDM output.|0x0|R|
|[3:0]|ZSENS_DSM||Sensitivity Zsens (DSM Path). Read-only Z-axis digital sensitivity (fine) trim for low noise signal<br>path (HP, LP, or RBW mode). Data is in unsigned format. This sensitivity trim value is digitally<br>multiplied with the signal path output, and the result is truncated by removing seven LSBs (/128)<br>and then adding them back to the signal path. In PDM mode, this digital fine trim is not applied;<br>therefore, the user must read back this value and apply the same digital multiplication and<br>truncation to the PDM output.|0x0|R|



**Rev. 0 | 64 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

## **CLOCK CONTROL REGISTER** 

## **Address: 0x25, Reset: 0x00, Name: CLK_CTRL** 

**==> picture [290 x 104] intentionally omitted <==**

_**Table 67. Bit Descriptions for CLK_CTRL**_ 

|**_Table 67. Bit Descriptions for CLK_CTRL_**|**_Table 67. Bit Descriptions for CLK_CTRL_**|**_Table 67. Bit Descriptions for CLK_CTRL_**|**_Table 67. Bit Descriptions for CLK_CTRL_**|**_Table 67. Bit Descriptions for CLK_CTRL_**|**_Table 67. Bit Descriptions for CLK_CTRL_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:4]|EXT_CLK_RATE|Ext<br>0000<br>No<br>0001<br>Div<br>0010<br>Div<br>0011<br>Div<br>0100<br>Div<br>0101<br>Div<br>0110<br>Div<br>0111<br>Div<br>1000<br>Div|ernal Clock Rate.<br>Division (Direct Drive).<br>ide External Clock by 2.<br>ide External Clock by 3.<br>ide External Clock by 4.<br>ide External Clock by 6.<br>ide External Clock by 8.<br>ide External Clock by 12.<br>ide External Clock by 16.<br>ide External Clock by 24.|0x0|R/W|
|[3:2]|RESERVED|Re|served.|0x0|R|
|[1:0]|CLK_SRC|Clo<br>00<br>Use<br>01<br>Use<br>10<br>Use|ck Source.<br>Internal Oscillator.<br>External MCLK Pin.<br>External BCLK Pin.|0x0|R/W|



## **OP_MODE REGISTER** 

**Address: 0x26, Reset: 0x00, Name: OP_MODE** 

**==> picture [320 x 128] intentionally omitted <==**

_**Table 68. Bit Descriptions for OP_MODE**_ 

|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|
|---|---|---|---|---|---|
|[7:6]|RANGE|Full<br>00<br>4_g._|Scale Range Settings. Available modes of operation are 4_g_, 8_g_, or 16_g_.|0x0|R/W|



**Rev. 0 | 65 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

## _**Table 68. Bit Descriptions for OP_MODE (Continued)**_ 

|**Bits**<br>~~**S**~~|**Bit Name**<br>~~**S**S~~|**Settings**|**Description**|**Reset**<br>~~SSS~~|**Access**<br>~~SSS~~|
|---|---|---|---|---|---|
|||01<br>10<br>11|8_g._<br>16_g._<br>Not applicable.|||
|5|PDM_MODE|0<br>1|PDM Mode. PDM mode on/off (active high).<br>PDM mode is disabled.<br>PDM mode is enabled.|0x0|R/W|
|4|AUDIO_MODE|0<br>1|Audio Mode for I2S/TDM. Audio mode on/off (I2S/TDM) active high.<br>Audio mode is disabled.<br>Audio mode is enabled.|0x0|R/W|
|[3:0]|OP_MODE|0000<br>0001<br>0010<br>0011<br>0100<br>0101<br>0110<br>0111<br>1000<br>1001<br>1010<br>1011<br>1100<br>1101<br>1110<br>1111|Mode of Operation.<br>Standby Mode.<br>Heart Sound Mode.<br>Ultra Low Power Mode.<br>Very Low Power Mode.<br>Low Power Mode.<br>Nonvalid.<br>LP and ULP Mode. LP is on serial port.<br>LP and VLP Mode. LP is on serial port.<br>RBW Mode.<br>Nonvalid.<br>RBW and ULP Mode. RBW is on serial port.<br>RBW and VLP Mode. RBW is on serial port.<br>High Performance Mode.<br>Nonvalid.<br>HP and ULP Mode. HP is on serial port.<br>HP and VLP Mode. HP is on serial port.|0x0|R/W|



## **DIGITAL ENABLE REGISTER** 

**Address: 0x27, Reset: 0x00, Name: DIG_EN** 

|[7:4]|MODE_CHANNEL_EN||Mode Channel Enable.<br>Bit 4 or mode channel enable, Bit 0: X-axis enable.<br>Bit 5 or mode channel enable, Bit 1: Y-axis enable.<br>Bit 6 or mode channel enable, Bit 2: Z-axis enable.<br>Bit 7 or mode channel enable, Bit 3: Temperature channel enable.<br>These register bits apply to all blocks (including the FIFO block) if settings are valid.|0x0|R/W|
|---|---|---|---|---|---|
|3|FIFO_EN||FIFO Enable.|0x0|R/W|



**Rev. 0 | 66 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

_**Table 69. Bit Descriptions for DIG_EN (Continued)**_ 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|||0<br>1|FIFO Disable (Default). When this bit is disabled, the FIFO is not in an operable<br>mode, and all FIFO and memory clocks are off.<br>FIFO Enable. When this bit is set, the FIFO can operate in normal mode. The FIFO<br>clock is active and incurs power consumption.|||
|2|DOUBLE_SPEED|0<br>1|Double Speed. Clocking Mode. Set to 0 for 512 kHz system clock or 1 for 768 kHz<br>system clock (external clock source only).<br>512 kHz System Clock.<br>768 kHz System Clock.|0x0|R/W|
|1|INT01_EVENT|0<br>1|INT0 and INT1 Event Contribution. When the INT01_EVENT bit is set, all interrupt<br>sticky bits are set when its associated live bit triggers an event status from 0 → 1.<br>Otherwise, the interrupt stick bit is always set whenever the live bit is high. (This bit<br>affects UV_FLAG_STICKY bit, OVER_RANGE_STICKY, and PARITY_ERR_STICKY<br>bit in STATUS0, STATUS1, and STATUS2 registers.)<br>Live status is used to contribute to the interrupt status.<br>Event status is used to contribute to the interrupt status.|0x0|R/W|
|0|PARITY_EN|0<br>1|Parity Enable. When the parity enable register bit is set high, the SEU detection<br>feature is enabled on all controllable and writable register bits (by iterating through all<br>register addresses to calculate the 1-bit sum of all of the register bit positions). If there<br>is a mismatch between the old (stored and valid) parity bit and the current (calculated<br>and valid) parity bit, an SEU parity error generates. (Either the sticky event bit or<br>live event bit is selected via the INT01_EVENT bit. Default is live event.) An interrupt<br>trigger sets a read only (STATUS0) register bit and/or external pins (INT0 or INT1,<br>if an interrupt contribution is enabled). A read only live (PARITY_ERR bit) register<br>bit and a read only parity value (PARITY register bit) are available for observation.<br>A internal 100 Hz clock is used to generate a periodic SEU detection event. Each<br>of these events triggers a parity calculation if PARITY_EN is set high (that is, it<br>stores both the current and old parity bit and their valid bit for comparison. If there<br>is any mismatch between the valid current parity and the valid old parity, a parity<br>error generates.) When a new register write command occurs, any ongoing parity<br>calculation is aborted, and both the old (stored for comparison) parity and the current<br>parity are invalidated. Their parity bits are set to 0x0. Once the 100 Hz SEU detection<br>event occurs, the current parity value and valid bit are stored in the old parity. Then,<br>the current parity value is set to 0x0 before the iterative calculation through all of<br>the register addresses to generate the new current parity value occurs and sets the<br>current valid at its completion. The SEU detection is conclusive only if both the current<br>parity valid and the old parity valid bits are set high.<br>Disable Parity Check (Default).<br>Enable Parity Check.|0x0|R/W|



## **DATA READY AND I[2] C COMMUNICATION PORT CONFIGURATION REGISTER** 

**Address: 0x28, Reset: 0x00, Name: SAR_I2C** 

**Rev. 0 | 67 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

_**Table 70. Bit Descriptions for SAR_I2C**_ 

|**_Table 70. Bit Descriptions for SAR_I2C_**|**_Table 70. Bit Descriptions for SAR_I2C_**|**_Table 70. Bit Descriptions for SAR_I2C_**|**_Table 70. Bit Descriptions for SAR_I2C_**|**_Table 70. Bit Descriptions for SAR_I2C_**|**_Table 70. Bit Descriptions for SAR_I2C_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|7|I2C_BYPASS|0<br>1|I2C Bypass. I2C glitch filter bypass. Set this bit to 1 to disable the I2C glitch filter. The glitch<br>filter is automatically disabled in the SPI variant.<br>Normal Mode (No Bypass).<br>When set to 1, I2C is in bypass mode.|0x0|R/W|
|6|I2C_HSM_EN|0<br>1|I2C HSM Register. I2C high speed mode enable. Setting this bit to 1 changes the glitch filter<br>configuration (standard/FM/FM+ = 50 ns, HSM = 10 ns) and supports up to 3.4 MHz I2C<br>operation.<br>I2C Normal Speed Mode.<br>I2C High Speed Mode.|0x0|R/W|
|5|I2C_SDA_SLOW|0<br>1|Adjustment of SDA Fall Slope. Slow down the slope driver, and it is recommended to enable<br>this bit in low VDDIOoperation. Adjustment of SDA fall slope by slowing down the output<br>driver. Suggest to enable this bit in high VDDIOoperation (>3.3V)<br>I2C SDA Normal Mode.<br>I2C SDA slow down the slope driver.|0x0|R/W|
|[4:1]|RESERVED||Reserved.|0x0|R|
|0|DRDY_SEL|0<br>1|Data Ready Signal Select. Send DRDY signal to SOUT0.<br>No action will occur when this bit is set to 0 (default).<br>Send data ready signal to SOUT0.|0x0|R/W|



## **NVM (EFUSE) USER CONTROL REGISTER** 

## **Address: 0x29, Reset: 0x00, Name: NVM_CTL** 

**==> picture [306 x 105] intentionally omitted <==**

_**Table 71. Bit Descriptions for NVM_CTL**_ 

|**_Table 71. Bit Descriptions for NVM_CTL_**|**_Table 71. Bit Descriptions for NVM_CTL_**|**_Table 71. Bit Descriptions for NVM_CTL_**|**_Table 71. Bit Descriptions for NVM_CTL_**|**_Table 71. Bit Descriptions for NVM_CTL_**|**_Table 71. Bit Descriptions for NVM_CTL_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|7|NVM_CTL_ECC_CHECK|0<br>1|NVM ECC Check Control Bit. When this bit is set, an NVM/EFUSE ECC checker<br>starts and reports if there is any errors a few clock cycles after at STATUS2<br>register.<br>The NVM controller waits in the background state.<br>Starts the ECC checker.|0x0|R/W|
|6|NVM_CTL_CRC_CHECK|0<br>1|NVM CRC Check Control Bit. When this bit set, an NVM/EFUSE CRC checker will<br>start and report if there is any errors a few clock cycles after at STATUS2 register<br>The NVM controller waits in the background state.<br>Start CRC checker.|0x0|R/W|
|[5:0]|RESERVED||Reserved.|0x0|R/W|



**Rev. 0 | 68 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

## **REGISTER RESET** 

## **Address: 0x2A, Reset: 0x00, Name: REG_RESET** 

**==> picture [242 x 81] intentionally omitted <==**

_**Table 72. Bit Descriptions for REG_RESET**_ 

|**_Table 72. Bit Descriptions for REG_RESET_**|**_Table 72. Bit Descriptions for REG_RESET_**|**_Table 72. Bit Descriptions for REG_RESET_**|**_Table 72. Bit Descriptions for REG_RESET_**|**_Table 72. Bit Descriptions for REG_RESET_**|**_Table 72. Bit Descriptions for REG_RESET_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:2]|RESERVED||Reserved.|0x0|R|
|1|SOFT_RESET|0<br>1|Software Reset. Write Code 0x52 (representing the letter R in ASCII or unicode) to this bit to<br>immediately reset the ADXL380. All register settings are cleared, EFUSE is initialized, and the<br>sensors are placed in standby mode. Interrupt pins are configured to a high output impedance<br>mode. A latency of approximately 0.5 ms is required after soft reset for the initialization. During<br>this time, only the write only bit is available and read data returns 0x0.<br>The device operates in normal mode.<br>When SOFT_RESET is set from 0 to 1, a software reset triggers, and the device is reset without<br>powering down the device.|0x0|R/W|
|0|RESERVED||Reserved.|0x0|R|



## **INTERRUPT PIN 0 ENABLES MAP0 REGISTER** 

## **Address: 0x2B, Reset: 0x80, Name: INT0_MAP0** 

**==> picture [326 x 163] intentionally omitted <==**

_**Table 73. Bit Descriptions for INT0_MAP0**_ 

|**_Table 73. Bit Descriptions for INT0_MAP0_**|**_Table 73. Bit Descriptions for INT0_MAP0_**|**_Table 73. Bit Descriptions for INT0_MAP0_**|**_Table 73. Bit Descriptions for INT0_MAP0_**|**_Table 73. Bit Descriptions for INT0_MAP0_**|**_Table 73. Bit Descriptions for INT0_MAP0_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|7|NVM_BUSY_INT0|NVM EFUSE<br>pin.<br>1<br>Enabled inte<br>0<br>Disabled inte|Busy Status Interrupt 0. Maps the NVM_BUSY status to the INT0<br>rrupt.<br>rrupt.|0x1|R/W|
|6|INACT_INT0|Inactivity Inte<br>1<br>Enabled inte<br>0<br>Disabled inte|rrupt 0. Maps the inactivity status to the INT0 pin.<br>rrupt.<br>rrupt.|0x0|R/W|



**Rev. 0 | 69 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

_**Table 73. Bit Descriptions for INT0_MAP0 (Continued)**_ 

|**_Table 73. Bit Descriptions for INT0_MAP0(Continued)_**|**_Table 73. Bit Descriptions for INT0_MAP0(Continued)_**|**_Table 73. Bit Descriptions for INT0_MAP0(Continued)_**|**_Table 73. Bit Descriptions for INT0_MAP0(Continued)_**|**_Table 73. Bit Descriptions for INT0_MAP0(Continued)_**|**_Table 73. Bit Descriptions for INT0_MAP0(Continued)_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|5|ACT_INT0<br>1<br>0||Activity Interrupt 0. Enables the activity detected interrupt to the INT0 pin.<br>Enabled interrupt.<br>Disabled interrupt.|0x0|R/W|
|4|RESERVED||Reserved.|0x0|R/W|
|3|FIFO_WATERMARK_INT0<br>1<br>0||FIFO Watermark Interrupt 0. 1 = maps the FIFO watermark status to the INT0<br>pin.<br>Enabled interrupt.<br>Disabled interrupt.|0x0|R/W|
|2|FIFO_OVERRUN_INT0<br>1<br>0||FIFO Overrun Interrupt 0. 1 = maps the FIFO overrun status to the INT0 pin.<br>Enabled interrupt.<br>Disabled interrupt.|0x0|R/W|
|1|FIFO_FULL_INT0<br>0<br>1||FIFO Full Interrupt 0.<br>Enabled interrupt.<br>Disabled interrupt.|0x0|R/W|
|0|DATA_RDY_INT0<br>1<br>0||DATA_READY Interrupt 0. Set to 1 to map DATA_READY to the INT0 pin.<br>Enabled interrupt.<br>Disabled interrupt.|0x0|R/W|



## **INTERRUPT PIN 0 ENABLES MAP1 REGISTER** 

## **Address: 0x2C, Reset: 0x00, Name: INT0_MAP1** 

**==> picture [301 x 163] intentionally omitted <==**

_**Table 74. Bit Descriptions for INT0_MAP1**_ 

|**_Table 74. Bit Descriptions for INT0_MAP1_**|**_Table 74. Bit Descriptions for INT0_MAP1_**|**_Table 74. Bit Descriptions for INT0_MAP1_**|**_Table 74. Bit Descriptions for INT0_MAP1_**|**_Table 74. Bit Descriptions for INT0_MAP1_**|
|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|||||
|7|NVM_DONE_INT0<br>1<br>0|NVM Done Interrupt 0. Maps the EFUSE done (NVM_DONE) status to the INT0 pin.<br>Enabled interrupt.<br>Disabled interrupt.|0x0|R/W|
|6|NVM_IRQ_INT0<br>1<br>0|NVM IRQ Interrupt 0. Maps the NVM/EFUSE IRQ status to the INT0 pin.<br>Enabled interrupt.<br>Disabled interrupt.|0x0|R/W|
|5|UV_FLAG_INT0<br>1<br>0|UV Flag Interrupt 0. UV flag interrupt map to INT0. 1 = maps the UV_FLAG_STICKY<br>status to the INT0 pin.<br>Enabled interrupt.<br>Disabled interrupt.|0x0|R/W|
|4|OVER_RANGE_INT0|Overrange Interrupt 0. 1 = maps the OVER_RANGE_STICKY status to the INT0 pin.|0x0|R/W|



**Rev. 0 | 70 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

_**Table 74. Bit Descriptions for INT0_MAP1 (Continued)**_ 

|**_Table 74. Bit Descriptions for INT0_MAP1(Continued)_**|**_Table 74. Bit Descriptions for INT0_MAP1(Continued)_**|**_Table 74. Bit Descriptions for INT0_MAP1(Continued)_**|**_Table 74. Bit Descriptions for INT0_MAP1(Continued)_**|**_Table 74. Bit Descriptions for INT0_MAP1(Continued)_**|
|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|||||
||1<br>0|Enabled interrupt.<br>Disabled interrupt.|||
|3|PARITY_ERR_INT0<br>1<br>0|Parity Error Interrupt 0. Parity Error Interrupt map to INT0. 1 = maps the PARITY_ERR<br>status to INT0 pin.<br>Enabled interrupt.<br>Disabled interrupt.|0x0|R/W|
|2|TRIPLE_TAP_INT0<br>1<br>0|Triple Tap Interrupt 0. Map the triple tap interrupt to the INT0 pin.<br>Enabled interrupt.<br>Disabled interrupt.|0x0|R/W|
|1|DOUBLE_TAP_INT0<br>1<br>0|Double Tap Interrupt 0. Map the double tap interrupt to the INT0 pin.<br>Enabled interrupt.<br>Disabled interrupt.|0x0|R/W|
|0|SINGLE_TAP_INT0<br>1<br>0|Single Tap Interrupt 0. Map the single tap interrupt to the INT0 pin.<br>Enabled interrupt.<br>Disabled interrupt.|0x0|R/W|



## **INTERRUPT PIN 1 ENABLES MAP0 REGISTER** 

## **Address: 0x2D, Reset: 0x00, Name: INT1_MAP0** 

**==> picture [321 x 163] intentionally omitted <==**

_**Table 75. Bit Descriptions for INT1_MAP0**_ 

|**_Table 75. Bit Descriptions for INT1_MAP0_**|**_Table 75. Bit Descriptions for INT1_MAP0_**|**_Table 75. Bit Descriptions for INT1_MAP0_**|**_Table 75. Bit Descriptions for INT1_MAP0_**|**_Table 75. Bit Descriptions for INT1_MAP0_**|**_Table 75. Bit Descriptions for INT1_MAP0_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|7|NVM_BUSY_INT1|1<br>0|NVM Busy Interrupt 1. Maps the EFUSE busy status to the INT1 pin.<br>Enabled interrupt.<br>Disabled interrupt.|0x0|R/W|
|6|INACT_INT1|1<br>0|Inactivity Interrupt 1. Maps the inactivity status to the INT1 pin.<br>Enabled interrupt.<br>Disabled interrupt.|0x0|R/W|
|5|ACT_INT1|1<br>0|Activity Interrupt 1. Enables the activity detected interrupt to the INT1 pin.<br>Enabled interrupt.<br>Disabled interrupt.|0x0|R/W|
|4|RESERVED||Reserved.|0x0|R/W|
|3|FIFO_WATERMARK_INT1|1|FIFO Watermark Interrupt 1. Set to 1 to map the FIFO_WATERMARK to the INT1<br>pin.<br>Enabled interrupt.|0x0|R/W|



**Rev. 0 | 71 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

_**Table 75. Bit Descriptions for INT1_MAP0 (Continued)**_ 

|**_Table 75. Bit Descriptions for INT1_MAP0(Continued)_**|**_Table 75. Bit Descriptions for INT1_MAP0(Continued)_**|**_Table 75. Bit Descriptions for INT1_MAP0(Continued)_**|**_Table 75. Bit Descriptions for INT1_MAP0(Continued)_**|**_Table 75. Bit Descriptions for INT1_MAP0(Continued)_**|
|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|||||
||0|Disabled interrupt.|||
|2|FIFO_OVERRUN_INT1<br>1<br>0|FIFO Overrun Interrupt 1. 1 = maps the FIFO overrun status to the INT1 pin.<br>Enabled interrupt.<br>Disabled interrupt.|0x0|R/W|
|1|FIFO_FULL_INT1<br>0<br>1|FIFO Full Interrupt 1.<br>Enabled interrupt.<br>Disabled interrupt.|0x0|R/W|
|0|DATA_RDY_INT1<br>1<br>0|DATA_READY Interrupt 1. Set to 1 to map DATA_READY to the INT1 pin.<br>Enabled interrupt.<br>Disabled interrupt.|0x0|R/W|



## **INTERRUPT PIN 1 ENABLES MAP1 REGISTER** 

## **Address: 0x2E, Reset: 0x80, Name: INT1_MAP1** 

**==> picture [301 x 163] intentionally omitted <==**

|**_Table 76. Bit Descriptions for INT1_MAP1_**|**_Table 76. Bit Descriptions for INT1_MAP1_**|**_Table 76. Bit Descriptions for INT1_MAP1_**|**_Table 76. Bit Descriptions for INT1_MAP1_**|**_Table 76. Bit Descriptions for INT1_MAP1_**|
|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|||||
|7|NVM_DONE_INT1<br>1<br>0|NVM Done Interrupt 1. Maps the EFUSE done (NVM_DONE) status to the INT1 pin.<br>Enabled interrupt.<br>Disabled interrupt.|0x1|R/W|
|6|NVM_IRQ_INT1<br>1<br>0|NVM IRQ Interrupt 1. Maps the NVM/EFUSE IRQ status to the INT1 pin.<br>Enabled interrupt.<br>Disabled interrupt.|0x0|R/W|
|5|UV_FLAG_INT1<br>1<br>0|UV Flag Interrupt 1. UV flag interrupt map to INT1. 1 = maps the UV_FLAG_STICKY<br>status to the INT1 pin.<br>Enabled interrupt.<br>Disabled interrupt.|0x0|R/W|
|4|OVER_RANGE_INT1<br>1<br>0|Overrange Interrupt 1. 1 = maps the OVER_RANGE_STICKY status to the INT1 pin.<br>Enabled interrupt.<br>Disabled interrupt.|0x0|R/W|
|3|PARITY_ERR_INT1<br>1<br>0|Parity Error Interrupt 1. 1 = maps the PARITY_ERR status to the INT1 pin.<br>Enabled interrupt.<br>Disabled interrupt.|0x0|R/W|
|2|TRIPLE_TAP_INT1<br>1|Triple Tap Interrupt 1. Maps the triple tap interrupt to the INT1 pin.<br>Enabled interrupt.|0x0|R/W|



**Rev. 0 | 72 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

_**Table 76. Bit Descriptions for INT1_MAP1 (Continued)**_ 

|**_Table 76. Bit Descriptions for INT1_MAP1(Continued)_**|**_Table 76. Bit Descriptions for INT1_MAP1(Continued)_**|**_Table 76. Bit Descriptions for INT1_MAP1(Continued)_**|**_Table 76. Bit Descriptions for INT1_MAP1(Continued)_**|**_Table 76. Bit Descriptions for INT1_MAP1(Continued)_**|**_Table 76. Bit Descriptions for INT1_MAP1(Continued)_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|||0|Disabled interrupt.|||
|1|DOUBLE_TAP_INT1|1<br>0|Double Tap Interrupt 1. Maps the double tap interrupt to the INT1 pin.<br>Enabled interrupt.<br>Disabled interrupt.|0x0|R/W|
|0|SINGLE_TAP_INT1|1<br>0|Single Tap Interrupt 1. Maps the single tap interrupt to the INT1 pin.<br>Enabled interrupt.<br>Disabled interrupt.|0x0|R/W|



## **FIFO CONFIGURATION 0 REGISTER** 

**Address: 0x30, Reset: 0x00, Name: FIFO_CFG0** 

**==> picture [342 x 141] intentionally omitted <==**

_**Table 77. Bit Descriptions for FIFO_CFG0**_ 

|**_Table 77. Bit Descriptions for FIFO_CFG0_**|**_Table 77. Bit Descriptions for FIFO_CFG0_**|**_Table 77. Bit Descriptions for FIFO_CFG0_**|**_Table 77. Bit Descriptions for FIFO_CFG0_**|**_Table 77. Bit Descriptions for FIFO_CFG0_**|**_Table 77. Bit Descriptions for FIFO_CFG0_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|7|FIFO_READ_RESET|0<br>1|FIFO Read Reset. This is a debug register bit. When set, read point, write point, and read<br>state machine are reset to default value 0x0.<br>FIFO operates as normal.<br>FIFO resets read pointer and write pointer.|0x0|R/W|
|6|FIFO_CH_ID|1<br>0|FIFO Channel ID Enable.<br>Enables prepending channel ID. When this bit is enabled, FIFO data is prepending 2-bit<br>channel ID on the first prior its 16-bit data.<br>FIFO prepending channel ID disables. FIFO_DATA only provides 16-bit signed data for<br>each channel without prepending its channel ID.|0x0|R/W|
|[5:4]|FIFO_MODE|00<br>01<br>10<br>11|FIFO Mode. Configures digital output during overrange event (not valid in PDM mode).<br>FIFO Disable Mode.<br>FIFO Normal Mode.<br>FIFO Stream Mode.<br>FIFO Trigger Mode.|0x0|R/W|
|3|FIFO_EXT_TRIG|1<br>0|FIFO External Trigger. The FIFO external trigger is used to monitor the external activity<br>trigger. When enabled, the FIFO trigger uses the FSYNC input as its activity trigger.<br>When disabled (default), the FIFO trigger monitors the internal activity trigger. This bit is<br>only valid in FIFO trigger mode (FIFO_MODE = 3).<br>Enabled Interrupt. The FIFO monitor external trigger (FSYNC input pin) for an activity<br>trigger in FIFO stream mode.<br>Disabled Interrupt. The FIFO internal trigger from the activity interrupt.|0x0|R/W|
|[2:1]|RESERVED||Reserved.|0x0|R|
|0|FIFO_SAMPLES[8]||FIFO Samples. The FIFO samples are the number of FIFO entries that the<br>FIFO_WATERMARK sets when the FIFO depth is larger or equal to the FIFO_SAMPLES.|0x0|R/W|



**Rev. 0 | 73 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

_**Table 77. Bit Descriptions for FIFO_CFG0 (Continued)**_ 

||||Note that FIFO_WATERMARK is a clear on read. Once it is set, because the FIFO depth<br>is at or larger than FIFO_SAMPLE, it must be read to clear.|||
|---|---|---|---|---|---|



## **FIFO CONFIGURATION 1 REGISTER** 

**Address: 0x31, Reset: 0x00, Name: FIFO_CFG1** 

## _**Table 78. Bit Descriptions for FIFO_CFG1**_ 

|[7:0]|FIFO_SAMPLES[7:0]||FIFO Samples. The FIFO samples are the number of FIFO entries that<br>FIFO_WATERMARK sets when the FIFO depth is larger or equal to the<br>FIFO_SAMPLES. Note that FIFO_WATERMARK is a clear on read. Once it is set,<br>because the FIFO depth is at or larger than FIFO_SAMPLE, it must be read to clear.|0x0|R/W|
|---|---|---|---|---|---|



## **SERIAL PORT CONFIGURATION 0 REGISTER** 

**Address: 0x32, Reset: 0x00, Name: SPT_CFG0** 

_**Table 79. Bit Descriptions for SPT_CFG0**_ 

|[7:6]|SPT_SLOT_WIDTH|00<br>01<br>10|Serial Port Slot Width.<br>32 BCLKs per Slot.<br>16 BCLKs per Slot.<br>24 BCLKs per Slot.|0x0|R/W|
|---|---|---|---|---|---|
|5|SPT_BCLK_POL|0<br>1|Serial Port Transmit BCLK Polarity.<br>BCLK Normal Polarity.<br>BCLK Inverted Polarity.|0x0|R/W|
|4|SPT_FSYNC_POL|0<br>1|Serial Port FSYNC Polarity.<br>FSYNC Normal Polarity.<br>FSYNC Inverted Polarity.|0x0|R/W|
|3|SPT_FSYNC_MODE|0<br>1|Serial Port FSYNC Mode<br>Stereo. 50% duty-cycle frame clock (I2S, left justified, or right justified).<br>TDM. Frame clock is single bit clock wide pulse.|0x0|R/W|
|[2:0]|SPT_DATA_FORMAT|000|Serial Port Data Format.<br>Typical I2S Mode, Delay by 1.|0x0|R/W|



**Rev. 0 | 74 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

_**Table 79. Bit Descriptions for SPT_CFG0 (Continued)**_ 

|**_Table 79. Bit Descriptions for SPT_CFG0(Continued)_**|**_Table 79. Bit Descriptions for SPT_CFG0(Continued)_**|**_Table 79. Bit Descriptions for SPT_CFG0(Continued)_**|**_Table 79. Bit Descriptions for SPT_CFG0(Continued)_**|**_Table 79. Bit Descriptions for SPT_CFG0(Continued)_**|
|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|||||
||001<br>010<br>011<br>100|Left Justified, Delay by 0.<br>Delay by 8.<br>Delay by 12.<br>Delay by 16.|||



## **SERIAL PORT CONFIGURATION 1 REGISTER** 

## **Address: 0x33, Reset: 0x08, Name: SPT_CFG1** 

**==> picture [367 x 128] intentionally omitted <==**

_**Table 80. Bit Descriptions for SPT_CFG1**_ 

|**_Table 80. Bit Descriptions for SPT_CFG1_**|**_Table 80. Bit Descriptions for SPT_CFG1_**|**_Table 80. Bit Descriptions for SPT_CFG1_**|**_Table 80. Bit Descriptions for SPT_CFG1_**|**_Table 80. Bit Descriptions for SPT_CFG1_**|
|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|||||
|7|SPT_XTRA_SAMP<br>0<br>1|Serial Port Selection for How to Fill Extra Samples.<br>Serial port outputs fresh data for one FSYNC frame and then sends zeros until the next<br>data is ready.<br>Serial port outputs fresh data for one FSYNC frame and then repeats the same sample<br>until the next data is ready.|0x0|R/W|
|6|SPT_TRI_STATE<br>0<br>1|Serial Port Output, Tristate Enabled.<br>Tristate Disabled.<br>Tristate Enabled.|0x0|R/W|
|[5:3]|SPT_Y_SLOT|Serial Port Time Slot Selection for Y-Axis Data. In I2S mode, set to 0/1 for the L/R channel<br>on SOUT0or 2/3 for the L/R channel on SOUT1, respectively. In TDM mode, set to 0 to 7 to<br>select the corresponding TDM slot.|0x1|R/W|
|[2:0]|SPT_X_SLOT|Serial Port Time Slot Selection for X-Axis Data. In I2S mode, set to 0/1 for L/R channel on<br>SOUT0, or 2/3 for L/R channel on SOUT1, respectively. In TDM mode, set to 0 to 7 to select<br>the corresponding TDM slot.|0x0|R/W|



## **SERIAL PORT CONFIGURATION 2 REGISTER** 

**Address: 0x34, Reset: 0x1A, Name: SPT_CFG2** 

**==> picture [366 x 89] intentionally omitted <==**

**Rev. 0 | 75 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

_**Table 81. Bit Descriptions for SPT_CFG2**_ 

|**_Table 81. Bit Descriptions for SPT_CFG2_**|**_Table 81. Bit Descriptions for SPT_CFG2_**|**_Table 81. Bit Descriptions for SPT_CFG2_**|**_Table 81. Bit Descriptions for SPT_CFG2_**|**_Table 81. Bit Descriptions for SPT_CFG2_**|**_Table 81. Bit Descriptions for SPT_CFG2_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|7|SPT_SOUT_SEL|S<br>st<br>0<br>S<br>1<br>S|OUTPin Selection for I2S/TDM. The SOUT0or SOUT1pin selection for I2S/TDM output<br>ream. Set to 0 for SOUT0or 1 for SOUT1.<br>erial Output on the SOUT0Pin.<br>erial Output on the SOUT1Pin.|0x0|R/W|
|6|SPT_DUAL_MODE|D<br>an<br>0<br>St<br>1<br>D<br>pi|ual SOUTxMode. Dual SOUTxmode for I2S/TDM output stream. When enabled, Slot 0<br>d Slot 1 output on SOUT0, and Slot 2 and Slot 3 output on SOUT1.<br>andard Operation. Serial audio channels are output on the SOUT0pin.<br>ual Stereo Operation. In stereo mode, Channel 0 to Channel 1 are output on the SOUT0<br>n and Channel 2 to Channel 3 are output on the MCLK pin.|0x0|R/W|
|[5:3]|SPT_TEMP_SLOT|S<br>ch<br>0|erial Port Time Slot Selection for Temperature Data. In I2S mode, set to 0/1 for the L/R<br>annel on SOUT0or 2/3 for the L/R channel on SOUT1, respectively. In TDM mode, set to<br>to 7 to select the corresponding TDM slot.|0x3|R/W|
|[2:0]|SPT_Z_SLOT|S<br>on<br>se|erial Port Time Slot Selection for Z-Axis Data. In I2S mode, set to 0/1 for the L/R channel<br>SOUT0or 2/3 for the L/R channel on SOUT1, respectively. In TDM mode, set to 0 to 7 to<br>lect the corresponding TDM slot.|0x2|R/W|



## **SYNC AND SERIAL PORT CONFIGURATION REGISTER** 

## **Address: 0x35, Reset: 0x00, Name: SYNC_CFG** 

**==> picture [309 x 150] intentionally omitted <==**

_**Table 82. Bit Descriptions for SYNC_CFG**_ 

|**_Table 82. Bit Descriptions for SYNC_CFG_**|**_Table 82. Bit Descriptions for SYNC_CFG_**|**_Table 82. Bit Descriptions for SYNC_CFG_**|**_Table 82. Bit Descriptions for SYNC_CFG_**|**_Table 82. Bit Descriptions for SYNC_CFG_**|**_Table 82. Bit Descriptions for SYNC_CFG_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|7|RESERVED|Reserve|d.|0x0|R|
|6|SYNC_SRC|SYNC S<br>0<br>Use FSY<br>1<br>Use INT1|ource. Sync source signal.<br>NC pin as sync signal.<br>pin as sync signal.|0x0|R/W|
|[5:4]|SYNC_MODE|SYNC M<br>00<br>No Exter<br>01<br>Synchron<br>10<br>Interpola<br>synchron|ode.<br>nal Synchronization of DSM Path.<br>izes DSM path operation and ODR to the external synchronization signal.<br>tion mode provides interpolated output of the DSM path based on the external<br>ization signal.|0x0|R/W|
|[3:2]|BCLK_SRC|BCLK So<br>00<br>External<br>01<br>Internal 5<br>10<br>Internal 2|urce.<br>(Default).<br>12 kHz.<br>56 kHz.|0x0|R/W|
|[1:0]|FSYNC_SRC|FSYNC<br>00<br>External|Source.<br>(Default).|0x0|R/W|



**Rev. 0 | 76 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

_**Table 82. Bit Descriptions for SYNC_CFG (Continued)**_ 

|**_Table 82. Bit Descriptions for SYNC_CFG(Continued)_**|**_Table 82. Bit Descriptions for SYNC_CFG(Continued)_**|**_Table 82. Bit Descriptions for SYNC_CFG(Continued)_**|**_Table 82. Bit Descriptions for SYNC_CFG(Continued)_**|**_Table 82. Bit Descriptions for SYNC_CFG(Continued)_**|
|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|||||
||01<br>10|Internal 8 kHz.<br>Internal 16 kHz.|||



## **PDM CONFIGURATION REGISTER** 

**Address: 0x36, Reset: 0x00, Name: PDM_CFG** 

**==> picture [331 x 57] intentionally omitted <==**

_**Table 83. Bit Descriptions for PDM_CFG**_ 

|**_Table 83. Bit Descriptions for PDM_CFG_**|**_Table 83. Bit Descriptions for PDM_CFG_**|**_Table 83. Bit Descriptions for PDM_CFG_**|**_Table 83. Bit Descriptions for PDM_CFG_**|**_Table 83. Bit Descriptions for PDM_CFG_**|**_Table 83. Bit Descriptions for PDM_CFG_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:6]|PDM_FSYNC_SLOTB||PDM Channel Select. 2'b00: empty (zero). 2'b01: Channel X. 2'b10:<br>Channel Y. 2'b11: Channel Z.|0x0|R/W|
|[5:4]|PDM_FSYNC_SLOTA||PDM Channel Select. 2'b00: empty (zero). 2'b01: Channel X. 2'b10:<br>Channel Y. 2'b11: Channel Z|0x0|R/W|
|[3:2]|PDM_SOUT0_SLOTB||PDM Channel Select. 2'b00: empty (zero). 2'b01: Channel X. 2'b10:<br>Channel Y. 2'b11: Channel Z.|0x0|R/W|
|[1:0]|PDM_SOUT0_SLOTA||PDM Channel Select. 2'b00: empty (zero). 2'b01: Channel X. 2'b10:<br>Channel Y. 2'b11: Channel Z.|0x0|R/W|



## **ACTIVITY, INACTIVITY, AND PDM CONTROL REGISTER** 

**Address: 0x37, Reset: 0x00, Name: ACT_INACT_CTL** 

**==> picture [329 x 149] intentionally omitted <==**

_**Table 84. Bit Descriptions for ACT_INACT_CTL**_ 

|**_Table 84. Bit Descriptions for ACT_INACT_CTL_**|**_Table 84. Bit Descriptions for ACT_INACT_CTL_**|**_Table 84. Bit Descriptions for ACT_INACT_CTL_**|**_Table 84. Bit Descriptions for ACT_INACT_CTL_**|**_Table 84. Bit Descriptions for ACT_INACT_CTL_**|**_Table 84. Bit Descriptions for ACT_INACT_CTL_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|7|PDM_POL<br>0<br>1|P<br>n<br>P<br>P|DM Polarity. When set to 0, 0 corresponds to positive full scale and 1 corresponds to<br>egative full scale. Set to 1 to invert.<br>DM Normal Polarity.<br>DM Inverted Polarity.|0x0|R/W|
|6|ACT_INACT_HPF<br>0<br>1|A<br>D<br>E<br>e|ctivity and Inactivity High-Pass Filter Enable.<br>isable. Unfiltered SAR data enters the activity and inactivity detectors.<br>nable. SAR data passes through the high-pass filter per the FILTER register prior to<br>ntering the activity and inactivity detectors.|0x0|R/W|



**Rev. 0 | 77 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

_**Table 84. Bit Descriptions for ACT_INACT_CTL (Continued)**_ 

|**_Table 84. Bit Descriptions for ACT_INACT_CTL(Continued)_**|**_Table 84. Bit Descriptions for ACT_INACT_CTL(Continued)_**|**_Table 84. Bit Descriptions for ACT_INACT_CTL(Continued)_**|**_Table 84. Bit Descriptions for ACT_INACT_CTL(Continued)_**|**_Table 84. Bit Descriptions for ACT_INACT_CTL(Continued)_**|**_Table 84. Bit Descriptions for ACT_INACT_CTL(Continued)_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[5:4]|LINKLOOP|00<br>01<br>10<br>11|Link Loop. Enable and configuration settings for linking or looping detection modes as well<br>as host microcontroller interrupt handling.<br>Default. Activity and inactivity detectors operate independently. Each detector requires its<br>interrupt to be cleared before a new detection may occur.<br>Linked. Activity and inactivity detectors are linked sequentially. Each detector requires the<br>other detector’s interrupt to be cleared before a new detection may occur. Both detectors<br>must be enabled via ACT_EN and INACT_EN to use this mode.<br>Default 2. Activity and inactivity detectors operate independently. Each requires its interrupt<br>to be cleared before a new detection may occur.<br>Looped. Activity and inactivity detectors are linked sequentially. Interrupts are generated<br>but do not need to be cleared before a new detection may occur. Both detectors must be<br>enabled via ACT_EN and INACT_EN to use this mode.|0x0|R/W|
|[3:2]|INACT_EN|00<br>01<br>10<br>11|Inactivity Enable. Referenced or absolute (default) inactivity mode enable.<br>No inactivity detection enabled.<br>Inactivity enabled.<br>No inactivity detection enabled (same as 00).<br>Referenced inactivity enabled.|0x0|R/W|
|[1:0]|ACT_EN|00<br>01<br>10<br>11|Activity Enable. This register bit enables the activity block feature. When disable, the activity<br>block is disable, and there is no clock provided to the block.<br>No activity detection.<br>Activity enabled.<br>No activity detection (same as 00).<br>Referenced activity enabled.|0x0|R/W|



## **ACTIVITY AND INACTIVITY AND SELF-TEST CONTROL REGISTER** 

**Address: 0x38, Reset: 0x00, Name: SNSR_AXIS_EN** 

**==> picture [306 x 126] intentionally omitted <==**

_**Table 85. Bit Descriptions for SNSR_AXIS_EN**_ 

|**_Table 85. Bit Descriptions for SNSR_AXIS_EN_**|**_Table 85. Bit Descriptions for SNSR_AXIS_EN_**|**_Table 85. Bit Descriptions for SNSR_AXIS_EN_**|**_Table 85. Bit Descriptions for SNSR_AXIS_EN_**|**_Table 85. Bit Descriptions for SNSR_AXIS_EN_**|**_Table 85. Bit Descriptions for SNSR_AXIS_EN_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|7|ST_MODE|Self<br>0<br>Disa<br>1<br>Ena|Test Mode. This bit configures the part in self test mode.<br>bles ST_MODE feature.<br>bles ST_MODE feature.|0x0|R/W|
|6|ST_FORCE|Self<br>sen<br>0<br>Disa<br>1<br>Ena|Test Force Control Bit. Enables an electrostatic force applied to the mechanical<br>sor; therefore, it induces a change in the output.<br>bles ST_FORCE feature.<br>bles ST_FORCE feature.|0x0|R/W|
|5|ST_DIR|Self<br>mec|Test Directional Bit. Flip the direction of the self test force being applied to the<br>hanical sensor.|0x0|R/W|



**Rev. 0 | 78 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

_**Table 85. Bit Descriptions for SNSR_AXIS_EN (Continued)**_ 

|**_Table 85. Bit Descriptions for SNSR_AXIS_EN(Continued)_**|**_Table 85. Bit Descriptions for SNSR_AXIS_EN(Continued)_**|**_Table 85. Bit Descriptions for SNSR_AXIS_EN(Continued)_**|**_Table 85. Bit Descriptions for SNSR_AXIS_EN(Continued)_**|**_Table 85. Bit Descriptions for SNSR_AXIS_EN(Continued)_**|**_Table 85. Bit Descriptions for SNSR_AXIS_EN(Continued)_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|||0<br>1|Disables ST_DIR feature.<br>Enables ST_DIR feature.|||
|[4:3]|RESERVED||Reserved.|0x0|R|
|[2:0]|ACT_INACT_AXIS_EN|000<br>001<br>010<br>100<br>011<br>101<br>110<br>111|Activity and Inactivity Axis Enabled.<br>No axes enabled.<br>X axis enabled.<br>Y axis enabled.<br>Z axis enabled.<br>X and Y axes enabled.<br>X and Z axes enabled.<br>Y and Z axes enabled.<br>X, Y, and Z axes enabled.|0x0|R/W|



## **ACTIVITY THRESHOLD (HIGH BYTE) REGISTER** 

## **Address: 0x39, Reset: 0x00, Name: THRESH_ACT_H** 

**==> picture [267 x 36] intentionally omitted <==**

_**Table 86. Bit Descriptions for THRESH_ACT_H**_ 

|**_Table 86. Bit Descriptions for THRESH_ACT_H_**|**_Table 86. Bit Descriptions for THRESH_ACT_H_**|**_Table 86. Bit Descriptions for THRESH_ACT_H_**|**_Table 86. Bit Descriptions for THRESH_ACT_H_**|**_Table 86. Bit Descriptions for THRESH_ACT_H_**|**_Table 86. Bit Descriptions for THRESH_ACT_H_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:3]|RESERVED||Reserved.|0x0|R|
|[2:0]|THRESH_ACT[10:8]||Threshold Act Value. Activity threshold value. To detect activity, the ADXL380 compares<br>the absolute value of the 12-bit (signed) SAR acceleration data with the 11-bit (unsigned)<br>THRESH_ACT value. THRESH_ACT is set in SAR codes; the value in_g_depends on the<br>measurement range setting that is selected. The 12-bit (signed) SAR is multiplied by 16<br>to compare (shift left toward MSB).|0x0|R/W|



## **ACTIVITY THRESHOLD (LOW BYTE) REGISTER** 

## **Address: 0x3A, Reset: 0x00, Name: THRESH_ACT_L** 

**==> picture [206 x 36] intentionally omitted <==**

_**Table 87. Bit Descriptions for THRESH_ACT_L**_ 

|**_Table 87. Bit Descriptions for THRESH_ACT_L_**|**_Table 87. Bit Descriptions for THRESH_ACT_L_**|**_Table 87. Bit Descriptions for THRESH_ACT_L_**|**_Table 87. Bit Descriptions for THRESH_ACT_L_**|**_Table 87. Bit Descriptions for THRESH_ACT_L_**|**_Table 87. Bit Descriptions for THRESH_ACT_L_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|THRESH_ACT[7:0]||Threshold Act Value. Activity threshold value. To detect activity, the ADXL380 compares<br>the absolute value of the 12-bit (signed) SAR acceleration data with the 11-bit (unsigned)<br>THRESH_ACT value. THRESH_ACT is set in SAR codes; the value in_g_depends on the<br>measurement range setting that is selected. The 12-bit (signed) SAR is multiplied by 16 to<br>compare (shift left toward MSB).|0x0|R/W|



**Rev. 0 | 79 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

## **TIMED ACTIVITY (HIGH BYTE, BITS[23:16]) REGISTER** 

## **Address: 0x3B, Reset: 0x00, Name: TIME_ACT_H** 

**==> picture [202 x 36] intentionally omitted <==**

_**Table 88. Bit Descriptions for TIME_ACT_H**_ 

|**_Table 88. Bit Descriptions for TIME_ACT_H_**|**_Table 88. Bit Descriptions for TIME_ACT_H_**|**_Table 88. Bit Descriptions for TIME_ACT_H_**|**_Table 88. Bit Descriptions for TIME_ACT_H_**|**_Table 88. Bit Descriptions for TIME_ACT_H_**|**_Table 88. Bit Descriptions for TIME_ACT_H_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|TIME_ACT[23:16]|T<br>d<br>><br>a<br>T|IME_ACT Bit. Required activity time. The 24-bit activity timer implements a robust activity<br>etection that minimizes false positive motion triggers. When the timer is used (TIME_ACT<br>0), only sustained motion can trigger activity detection. The value in this register sets the<br>mount of time that at least one axis must be greater than the activity threshold (set by<br>HRESH_ACT) for an activity event to be detected. 1 LSB = 500 µs.|0x0|R/W|



## **TIMED ACTIVITY (MID BYTE, BITS[15:7]) REGISTER** 

## **Address: 0x3C, Reset: 0x00, Name: TIME_ACT_M** 

**==> picture [198 x 35] intentionally omitted <==**

_**Table 89. Bit Descriptions for TIME_ACT_M**_ 

|**_Table 89. Bit Descriptions for TIME_ACT_M_**|**_Table 89. Bit Descriptions for TIME_ACT_M_**|**_Table 89. Bit Descriptions for TIME_ACT_M_**|**_Table 89. Bit Descriptions for TIME_ACT_M_**|**_Table 89. Bit Descriptions for TIME_ACT_M_**|**_Table 89. Bit Descriptions for TIME_ACT_M_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|TIME_ACT[15:8]||TIME_ACT Bit. Required activity time. The 24-bit activity timer implements a robust activity<br>detection that minimizes false positive motion triggers. When the timer is used (TIME_ACT<br>> 0), only sustained motion can trigger activity detection. The value in this register sets the<br>amount of time that at least one axis must be greater than the activity threshold (set by<br>THRESH_ACT) for an activity event to be detected. 1 LSB = 500 µs.|0x0|R/W|



## **TIMED ACTIVITY (LOW BYTE, BITS[7:0]) REGISTER** 

**Address: 0x3D, Reset: 0x00, Name: TIME_ACT_L** 

**==> picture [194 x 36] intentionally omitted <==**

_**Table 90. Bit Descriptions for TIME_ACT_L**_ 

|**_Table 90. Bit Descriptions for TIME_ACT_L_**|**_Table 90. Bit Descriptions for TIME_ACT_L_**|**_Table 90. Bit Descriptions for TIME_ACT_L_**|**_Table 90. Bit Descriptions for TIME_ACT_L_**|**_Table 90. Bit Descriptions for TIME_ACT_L_**|**_Table 90. Bit Descriptions for TIME_ACT_L_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|TIME_ACT[7:0]||TIME_ACT Bit. Required activity time. The 24-bit activity timer implements a robust activity<br>detection that minimizes false positive motion triggers. When the timer is used (TIME_ACT<br>> 0), only sustained motion can trigger activity detection. The value in this register sets the<br>amount of time that at least one axis must be greater than the activity threshold (set by<br>THRESH_ACT) for an activity event to be detected. 1 LSB = 500 µs.|0x0|R/W|



**Rev. 0 | 80 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

## **INACTIVITY THRESHOLD (HIGH BYTE) REGISTER** 

## **Address: 0x3E, Reset: 0x00, Name: THRESH_INACT_H** 

**==> picture [276 x 37] intentionally omitted <==**

_**Table 91. Bit Descriptions for THRESH_INACT_H**_ 

|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|
|---|---|---|---|---|---|
|[7:3]|RESERVED||Reserved.|0x0|R|
|[2:0]|THRESH_INACT[10:8]||Threshold Inactivity Value. Inactivity threshold value. To detect inactivity, the ADXL380<br>compares the absolute value of the 12-bit (signed) SAR acceleration data with the<br>11-bit (unsigned) THRESH_INACT value. THRESH_INACT is set in SAR codes; the<br>value in_g_depends on the measurement range setting that is selected. The 12-bit<br>(signed) SAR is multiplied by 16 to compare (shift left toward MSB).|0x0|R/W|



## **INACTIVITY THRESHOLD (LOW BYTE) REGISTER** 

## **Address: 0x3F, Reset: 0x00, Name: THRESH_INACT_L** 

**==> picture [214 x 37] intentionally omitted <==**

_**Table 92. Bit Descriptions for THRESH_INACT_L**_ 

|**_Table 92. Bit Descriptions for THRESH_INACT_L_**|**_Table 92. Bit Descriptions for THRESH_INACT_L_**|**_Table 92. Bit Descriptions for THRESH_INACT_L_**|**_Table 92. Bit Descriptions for THRESH_INACT_L_**|**_Table 92. Bit Descriptions for THRESH_INACT_L_**|**_Table 92. Bit Descriptions for THRESH_INACT_L_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|THRESH_INACT[7:0]||Threshold Inactivity Value. Inactivity threshold value. To detect inactivity, the ADXL380<br>compares the absolute value of the 12-bit (signed) SAR acceleration data with the 11-bit<br>(unsigned) THRESH_INACT value. THRESH_INACT is set in SAR codes; the value in<br>_g_depends on the measurement range setting that is selected. The 12-bit (signed) SAR<br>is multiplied by 16 to compare (shift left toward MSB).|0x0|R/W|



## **TIMED INACTIVITY (HIGH BYTE, BITS[23:16]) REGISTER** 

**Address: 0x40, Reset: 0x00, Name: TIME_INACT_H** 

**==> picture [210 x 36] intentionally omitted <==**

_**Table 93. Bit Descriptions for TIME_INACT_H**_ 

|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|
|---|---|---|---|---|---|
|[7:0]|TIME_INACT[23:16]|<br> <br> <br> <br> <br>|TIME_INACT Bit. Required inactivity time. The 24-bit activity timer implements a robust<br>activity detection that minimizes false positive motion triggers. When the timer is used<br>(TIME_INACT > 0), only sustained motion can trigger inactivity detection. The value<br>in this register sets the amount of time that all axes must be lower than the inactivity<br>threshold (set by THRESH_INACT) for an inactivity event to be detected. 1 LSB = 500<br>µs.|0x0|R/W|



**Rev. 0 | 81 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

## **TIMED INACTIVITY (MID BYTE, BITS[15:8]) REGISTER** 

## **Address: 0x41, Reset: 0x00, Name: TIME_INACT_M** 

**==> picture [206 x 36] intentionally omitted <==**

_**Table 94. Bit Descriptions for TIME_INACT_M**_ 

|**_Table 94. Bit Descriptions for TIME_INACT_M_**|**_Table 94. Bit Descriptions for TIME_INACT_M_**|**_Table 94. Bit Descriptions for TIME_INACT_M_**|**_Table 94. Bit Descriptions for TIME_INACT_M_**|**_Table 94. Bit Descriptions for TIME_INACT_M_**|**_Table 94. Bit Descriptions for TIME_INACT_M_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|TIME_INACT[15:8]|<br>a<br>(<br>r<br>(|TIME_INACT Bit. Required inactivity time. The 24-bit activity timer implements a robust<br>ctivity detection that minimizes false positive motion triggers. When the timer is used<br>TIME_INACT > 0), only sustained motion can trigger inactivity detection. The value in this<br>egister sets the amount of time that all axes must be lower than the inactivity threshold<br>set by THRESH_INACT) for an inactivity event to be detected. 1 LSB = 500 µs.|0x0|R/W|



## **TIMED INACTIVITY (LOW BYTE, BITS[7:0]) REGISTER** 

## **Address: 0x42, Reset: 0x00, Name: TIME_INACT_L** 

**==> picture [202 x 36] intentionally omitted <==**

_**Table 95. Bit Descriptions for TIME_INACT_L**_ 

|**_Table 95. Bit Descriptions for TIME_INACT_L_**|**_Table 95. Bit Descriptions for TIME_INACT_L_**|**_Table 95. Bit Descriptions for TIME_INACT_L_**|**_Table 95. Bit Descriptions for TIME_INACT_L_**|**_Table 95. Bit Descriptions for TIME_INACT_L_**|**_Table 95. Bit Descriptions for TIME_INACT_L_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|TIME_INACT[7:0]|TI<br>ac<br>(T<br>re<br>by|ME_INACT Bit. Required inactivity time. The 24-bit activity timer implements a robust<br>tivity detection that minimizes false positive motion triggers. When the timer is used<br>IME_INACT > 0), only sustained motion can trigger inactivity detection. The value in this<br>gister sets the amount of time that all axes must be lower than the inactivity threshold (set<br>THRESH_INACT) for an inactivity event to be detected. 1 LSB = 500 µs.|0x0|R/W|



## **TAP THRESHOLD REGISTER** 

## **Address: 0x43, Reset: 0x00, Name: TAP_THRESH** 

**==> picture [230 x 35] intentionally omitted <==**

_**Table 96. Bit Descriptions for TAP_THRESH**_ 

|**_Table 96. Bit Descriptions for TAP_THRESH_**|**_Table 96. Bit Descriptions for TAP_THRESH_**|**_Table 96. Bit Descriptions for TAP_THRESH_**|**_Table 96. Bit Descriptions for TAP_THRESH_**|**_Table 96. Bit Descriptions for TAP_THRESH_**|**_Table 96. Bit Descriptions for TAP_THRESH_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|TAP_THRESH_PRESCALE||TAP Threshold Prescale Register. This register is eight bits and holds the<br>threshold value for tap interrupts. The data format is unsigned; therefore, the<br>magnitude of the tap event is compared with the value in TAP_THRESH for<br>normal tap detection. The scale factor is 500 m_g_/LSB with a maximum value of<br>2 times the range value in gravity. A value of 0 disables both tap and double tap<br>detection.|0x0|R/W|



**Rev. 0 | 82 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

## **TAP DURATION REGISTER** 

## **Address: 0x44, Reset: 0x00, Name: TAP_DUR** 

**==> picture [174 x 36] intentionally omitted <==**

_**Table 97. Bit Descriptions for TAP_DUR**_ 

|**_Table 97. Bit Descriptions for TAP_DUR_**|**_Table 97. Bit Descriptions for TAP_DUR_**|**_Table 97. Bit Descriptions for TAP_DUR_**|**_Table 97. Bit Descriptions for TAP_DUR_**|**_Table 97. Bit Descriptions for TAP_DUR_**|**_Table 97. Bit Descriptions for TAP_DUR_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|TAP_DUR||TAP_DUR Value. The TAP_DUR register is eight bits and contains an unsigned time value<br>representing the maximum time that an event must be above the TAP_THRESH threshold to qualify<br>as a tap event. The scale factor is 625 µs/LSB.|0x0|R/W|



## **TAP LATENCY WAIT TIME REGISTER** 

## **Address: 0x45, Reset: 0x00, Name: TAP_LATENT** 

**==> picture [186 x 36] intentionally omitted <==**

_**Table 98. Bit Descriptions for TAP_LATENT**_ 

|**_Table 98. Bit Descriptions for TAP_LATENT_**|**_Table 98. Bit Descriptions for TAP_LATENT_**|**_Table 98. Bit Descriptions for TAP_LATENT_**|**_Table 98. Bit Descriptions for TAP_LATENT_**|**_Table 98. Bit Descriptions for TAP_LATENT_**|**_Table 98. Bit Descriptions for TAP_LATENT_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|TAP_LATENT||TAP Latent Bit. The TAP_LATENT register is eight bits and contains an unsigned time value<br>representing the wait time from the detection of a tap event to the start of the time window<br>(defined by the window register) during which a possible second tap event can be detected. The<br>scale factor is 1.25 ms/LSB. A value of 0 disables the double tap function.|0x0|R/W|



## **TAP WINDOW REGISTER** 

## **Address: 0x46, Reset: 0x00, Name: TAP_WINDOW** 

**==> picture [192 x 36] intentionally omitted <==**

_**Table 99. Bit Descriptions for TAP_WINDOW**_ 

|**_Table 99. Bit Descriptions for TAP_WINDOW_**|**_Table 99. Bit Descriptions for TAP_WINDOW_**|**_Table 99. Bit Descriptions for TAP_WINDOW_**|**_Table 99. Bit Descriptions for TAP_WINDOW_**|**_Table 99. Bit Descriptions for TAP_WINDOW_**|**_Table 99. Bit Descriptions for TAP_WINDOW_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|TAP_WINDOW||TAP Window. The TAP_WINDOW register is eight bits and contains an unsigned time value<br>representing the amount of time after the expiration of the latency time (determined by the<br>latent register) during which a second valid second tap (double tap) must be occur to be<br>considered a valid double tap. The scale factor is 1.25 ms/LSB.|0x0|R/W|



**Rev. 0 | 83 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

## **TAP CONFIGURATION REGISTER** 

## **Address: 0x47, Reset: 0x00, Name: TAP_CFG** 

**==> picture [235 x 65] intentionally omitted <==**

_**Table 100. Bit Descriptions for TAP_CFG**_ 

|**_Table 100. Bit Descriptions for TAP_CFG_**|**_Table 100. Bit Descriptions for TAP_CFG_**|**_Table 100. Bit Descriptions for TAP_CFG_**|**_Table 100. Bit Descriptions for TAP_CFG_**|**_Table 100. Bit Descriptions for TAP_CFG_**|**_Table 100. Bit Descriptions for TAP_CFG_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:3]|RESERVED||Reserved.|0x0|R|
|2|TRIPLE_TAP_EN|0<br>1|Triple TAP Enable Bit.<br>Disable Tap Enable.<br>Enable Triple Tap Feature.|0x0|R/W|
|[1:0]|TAP_AXIS|00<br>01<br>10|TAP Axis Configuration. Selects which axis to look at for tap detection.<br>X Axis.<br>Y Axis.<br>Z Axis.|0x0|R/W|



**Rev. 0 | 84 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

## **UNDERVOLTAGE AND OVERRANGE CONFIGURATION REGISTER** 

## **Address: 0x48, Reset: 0x00, Name: OR_CFG** 

**==> picture [372 x 112] intentionally omitted <==**

_**Table 101. Bit Descriptions for OR_CFG**_ 

|**_Table 101. Bit Descriptions for OR_CFG_**|**_Table 101. Bit Descriptions for OR_CFG_**|**_Table 101. Bit Descriptions for OR_CFG_**|**_Table 101. Bit Descriptions for OR_CFG_**|**_Table 101. Bit Descriptions for OR_CFG_**|**_Table 101. Bit Descriptions for OR_CFG_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:5]|RESERVED|R|eserved.|0x0|R|
|4|DIS_UV_DET|T<br>d<br>0<br>U<br>1<br>U|urns off undervoltage detector circuit that flags during prebrownout events. The<br>efault value is 0 (UV detector enabled).<br>V Detect Normal Mode.<br>V Detect Disabled.|0x0|R/W|
|3|DIS_OR_DETECTION|C<br>0<br>N<br>1<br>T|ompletely turns off overrange circuitry. Overrange condition cannot be detected.<br>ormal Overrange Circuitry Operation.<br>urn Off Overrange Circuitry.|0x0|R/W|
|2|DIS_OR_PROTECTION|D<br>b<br>0<br>N<br>1<br>D|isable overrange protection scheme. Overrange condition can still be detected,<br>ut excitations are not turned off during an OR event.<br>ormal.<br>isable.|0x0|R/W|
|[1:0]|DIG_OUT_DURING_OR|D<br>o<br>00<br>F<br>01<br>H<br>10<br>D|igital Output During an Overrange Event. Configures digital output during<br>verrange event (not valid in PDM mode).<br>ull-Scale Code with Correct Sign.<br>olds the previous data before overrange event.<br>oes nothing to the data.|0x0|R/W|



**Rev. 0 | 85 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

## **SAR TRIGGER AND DIGITAL FILTER CONFIGURATION REGISTER** 

## **Address: 0x49, Reset: 0x00, Name: TRIG_CFG** 

**==> picture [404 x 165] intentionally omitted <==**

_**Table 102. Bit Descriptions for TRIG_CFG**_ 

|**_Table 102. Bit Descriptions for TRIG_CFG_**|**_Table 102. Bit Descriptions for TRIG_CFG_**|**_Table 102. Bit Descriptions for TRIG_CFG_**|**_Table 102. Bit Descriptions for TRIG_CFG_**|**_Table 102. Bit Descriptions for TRIG_CFG_**|**_Table 102. Bit Descriptions for TRIG_CFG_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|7|DEC_2X_BYPASS<br>1<br>0||Dec 2× Bypass. The DEC_2X_BYPASS bit controls the second stage<br>(increases ODR by a factor of 2).<br>Disables the second stage 2× decimation filter.<br>Enables the second stage 2× decimation filter (default).|2× decimation filter<br>0x0|R/W|
|6|SINC_RATE<br>0<br>1||SINC Rate. SINC Rate controls the decimation rate of the first stage d<br>disabling of the second stage 2× decimation filter (increases ODR by<br>32× Decimation Rate. 32× decimation rate for the first stage decimatio<br>stage 2× decimation filter is controlled by DEC_2X_BYPASS (default)<br>16× Decimation Rate. 16× decimation rate for the first stage decimatio<br>second stage decimation filter|ecimation filter, and the<br>a factor of 4).<br>0x0<br>n filter, and second<br>.<br>n filter, disable the|R/W|
|5|IIR1_EN<br>0<br>1||IIR1 Filter Enable. Enable the optional IIR1 filter. Used when low grou<br>enabled. Repurpose the EQ filter module as an IIR1 filter. Assuming E<br>under HP mode, or in RBW or LP mode, and LPF_MODE is not set.<br>Disables the IIR1 filter (default).<br>Enables the IIR1 filter.|p delay mode is<br>Q_BYPASS is set<br>0x0|R/W|
|[4:3]|RESERVED||Reserved.|0x0|R|
|2|ROUND_MODE<br>0<br>1||Rounding Output Mode. Rounding mode selection for high-pass filter<br>Default is truncation mode.<br>Floor round the high-pass filter output when it gets truncated to 16 bit<br>offset introduced, which involves incrementing the data value by 1 if th<br>leaving it alone if it is positive.|output.<br>0x0<br>to minimize the DC<br>e signal is negative or|R/W|
|1|TRIG_SRC<br>0<br>1||TRIG Source.<br>FSYNC. Use FSYNC pin as SAR trigger.<br>INT1. Use INT1 pin as SAR trigger.|0x0|R/W|
|0|TRIG_MODE<br>0<br>1||Trigger Mode for SAR External Pin.<br>Internal. No external trigger. SAR convert start signal generated intern<br>External Trigger Mode. SAR convert start signal comes from pin speci<br>register.|0x0<br>ally (default).<br>fied by the TRIG_SRC|R/W|



**Rev. 0 | 86 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

## **X-AXIS SAR USER OFFSET REGISTER** 

## **Address: 0x4A, Reset: 0x00, Name: X_SAR_OFFSET** 

**==> picture [194 x 36] intentionally omitted <==**

## _**Table 103. Bit Descriptions for X_SAR_OFFSET**_ 

|**_Table 103. Bit Descriptions for X_SAR_OFFSET_**|**_Table 103. Bit Descriptions for X_SAR_OFFSET_**|**_Table 103. Bit Descriptions for X_SAR_OFFSET_**|**_Table 103. Bit Descriptions for X_SAR_OFFSET_**|**_Table 103. Bit Descriptions for X_SAR_OFFSET_**|**_Table 103. Bit Descriptions for X_SAR_OFFSET_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|X_SAR_OFFSET||User X-Axis Offset Calibration. User X-axis offset calibration for low power signal path (ULP,<br>VLP, or HS mode). Data is in twos complement format. Resolution (in m_g_/LSB) is equal to the<br>resolution in the Data Register 0x15 to Data Register 0x1A divided by 8.|0x0|R/W|



## **Y-AXIS SAR USER OFFSET REGISTER** 

## **Address: 0x4B, Reset: 0x00, Name: Y_SAR_OFFSET** 

**==> picture [194 x 36] intentionally omitted <==**

_**Table 104. Bit Descriptions for Y_SAR_OFFSET**_ 

|**_Table 104. Bit Descriptions for Y_SAR_OFFSET_**|**_Table 104. Bit Descriptions for Y_SAR_OFFSET_**|**_Table 104. Bit Descriptions for Y_SAR_OFFSET_**|**_Table 104. Bit Descriptions for Y_SAR_OFFSET_**|**_Table 104. Bit Descriptions for Y_SAR_OFFSET_**|**_Table 104. Bit Descriptions for Y_SAR_OFFSET_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|Y_SAR_OFFSET||User Y-Axis Offset Calibration. User Y-axis offset calibration for low power signal path (ULP,<br>VLP, or HS mode). Data is in twos complement format. Resolution (in m_g_/LSB) is equal to the<br>resolution in the Data Register 0x15 to Data Register 0x1A divided by 8.|0x0|R/W|



## **Z-AXIS SAR USER OFFSET REGISTER** 

## **Address: 0x4C, Reset: 0x00, Name: Z_SAR_OFFSET** 

**==> picture [194 x 36] intentionally omitted <==**

_**Table 105. Bit Descriptions for Z_SAR_OFFSET**_ 

|**_Table 105. Bit Descriptions for Z_SAR_OFFSET_**|**_Table 105. Bit Descriptions for Z_SAR_OFFSET_**|**_Table 105. Bit Descriptions for Z_SAR_OFFSET_**|**_Table 105. Bit Descriptions for Z_SAR_OFFSET_**|**_Table 105. Bit Descriptions for Z_SAR_OFFSET_**|**_Table 105. Bit Descriptions for Z_SAR_OFFSET_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|Z_SAR_OFFSET||User Z-Axis Offset Calibration. User Z-axis offset calibration for low power signal path (ULP,<br>VLP, or HS mode). Data is in twos complement format. Resolution (in m_g_/LSB) is equal to the<br>resolution in the Data Register 0x15 to Data Register 0x1A divided by 8.|0x0|R/W|



## **X-AXIS DSM USER OFFSET REGISTER** 

**Address: 0x4D, Reset: 0x00, Name: X_DSM_OFFSET** 

**==> picture [196 x 35] intentionally omitted <==**

**Rev. 0 | 87 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

_**Table 106. Bit Descriptions for X_DSM_OFFSET**_ 

|**_Table 106. Bit Descriptions for X_DSM_OFFSET_**|**_Table 106. Bit Descriptions for X_DSM_OFFSET_**|**_Table 106. Bit Descriptions for X_DSM_OFFSET_**|**_Table 106. Bit Descriptions for X_DSM_OFFSET_**|**_Table 106. Bit Descriptions for X_DSM_OFFSET_**|**_Table 106. Bit Descriptions for X_DSM_OFFSET_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|X_DSM_OFFSET|<br> <br>t|User X-Axis Offset Calibration. User X-axis offset calibration for low noise signal path (HP,<br>LP, or RBW mode). Data is in twos complement format. Resolution (in m_g_/LSB) is equal to<br>he resolution in the Data Register 0x15 to Data Register 0x1A) divided by 8.|0x0|R/W|



## **Y-AXIS DSM USER OFFSET REGISTER** 

## **Address: 0x4E, Reset: 0x00, Name: Y_DSM_OFFSET** 

**==> picture [196 x 36] intentionally omitted <==**

_**Table 107. Bit Descriptions for Y_DSM_OFFSET**_ 

|**_Table 107. Bit Descriptions for Y_DSM_OFFSET_**|**_Table 107. Bit Descriptions for Y_DSM_OFFSET_**|**_Table 107. Bit Descriptions for Y_DSM_OFFSET_**|**_Table 107. Bit Descriptions for Y_DSM_OFFSET_**|**_Table 107. Bit Descriptions for Y_DSM_OFFSET_**|**_Table 107. Bit Descriptions for Y_DSM_OFFSET_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|Y_DSM_OFFSET|<br> <br>r|User Y-Axis Offset Calibration. User Y-axis offset calibration for low noise signal path (HP, LP,<br>or RBW mode). Data is in twos complement format. Resolution (in m_g_/LSB) is equal to the<br>esolution in the Data Register 0x15 to Data Register 0x1A divided by 8.|0x0|R/W|



## **Z-AXIS DSM USER OFFSET REGISTER** 

**Address: 0x4F, Reset: 0x00, Name: Z_DSM_OFFSET** 

**==> picture [196 x 36] intentionally omitted <==**

_**Table 108. Bit Descriptions for Z_DSM_OFFSET**_ 

|**_Table 108. Bit Descriptions for Z_DSM_OFFSET_**|**_Table 108. Bit Descriptions for Z_DSM_OFFSET_**|**_Table 108. Bit Descriptions for Z_DSM_OFFSET_**|**_Table 108. Bit Descriptions for Z_DSM_OFFSET_**|**_Table 108. Bit Descriptions for Z_DSM_OFFSET_**|**_Table 108. Bit Descriptions for Z_DSM_OFFSET_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|Z_DSM_OFFSET|<br> <br>t|User Z-Axis Offset Calibration. User Z-axis offset calibration for low noise signal path (HP,<br>LP, or RBW mode). Data is in twos complement format. Resolution (in m_g_/LSB) is equal to<br>he resolution in the Data Register 0x15 to Data Register 0x1A divided by 8.|0x0|R/W|



## **DIGITAL FILTER CONFIGURATION REGISTER** 

**Address: 0x50, Reset: 0x00, Name: FILTER** 

**==> picture [344 x 142] intentionally omitted <==**

**Rev. 0 | 88 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

_**Table 109. Bit Descriptions for FILTER**_ 

|**_Table 109. Bit Descriptions for FILTER_**|**_Table 109. Bit Descriptions for FILTER_**|**_Table 109. Bit Descriptions for FILTER_**|**_Table 109. Bit Descriptions for FILTER_**|**_Table 109. Bit Descriptions for FILTER_**|**_Table 109. Bit Descriptions for FILTER_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|7|DCF_BYPASS|0<br>1|Droop Compensation Filter Bypass. This filter corrects the drooping effect of the first stage 32×<br>decimation filter.<br>Droop compensation filter is enabled.<br>Bypass Droop Compensation Filter.|0x0|R/W|
|6|EQ_BYPASS|0<br>1|EQ Filter Bypass. Applicable to HP modes for OP_MODE. EQ filter is disabled in RBW or LP<br>mode.<br>Normal EQ filter is in operation.<br>Bypass EQ Filter.|0x0|R/W|
|[5:4]|LPF_MODE|00<br>01<br>10<br>11|Low-Pass Filter Mode. Second-order, low-pass filter mode. Repurpose the EQ filter module as a<br>low-pass filter. DSM path only. EQ bypass must be set to 1 to use the LPF.<br>No Low-Pass Filtering.<br>1/4 × ODR.<br>1/8 × ODR.<br>1/16 × ODR.|0x0|R/W|
|3|HPF_PATH|0<br>1|High-Pass Filter (HPF) Path Selection. First-order, HPF. Set to 0 to use HPF on SAR path, or 1<br>to use HPF on DSM path.<br>HPF inserted in SAR Path.<br>HPF inserted in DSM Path.|0x0|R/W|
|[2:0]|HPF_CORNER|000<br>001<br>010<br>011<br>100<br>101<br>110|High-Pass Filter Corner. First-order, HPF corner.<br>No HPF.<br>24.7E-4 × ODR<br>6.2084E-4 × ODR<br>1.5545E-4 × ODR<br>0.3862E-4 × ODR<br>0.0954E-4 × ODR<br>0.0238E-4 × ODR|0x0|R/W|



**Rev. 0 | 89 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

## **USER TEMPERATURE SENSOR CONTROL REGISTERS** 

## **Address: 0x55, Reset: 0x00, Name: USER_TEMP_SENS_0** 

**==> picture [273 x 36] intentionally omitted <==**

## _**Table 110. Bit Descriptions for USER_TEMP_SENS_0**_ 

|**_Table 110. Bit Descriptions for USER_TEMP_SENS_0_**|**_Table 110. Bit Descriptions for USER_TEMP_SENS_0_**|**_Table 110. Bit Descriptions for USER_TEMP_SENS_0_**|**_Table 110. Bit Descriptions for USER_TEMP_SENS_0_**|**_Table 110. Bit Descriptions for USER_TEMP_SENS_0_**|**_Table 110. Bit Descriptions for USER_TEMP_SENS_0_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:6]|RESERVED|R|eserved.|0x0|R|
|[5:0]|USER_TEMP_OFFSET|Us<br>U<br>co<br>si|er Temperature Offset Trim. When USER_TEMP_TRIM_EN is set high, the<br>SER_TEMP_OFFSET overrides the default NVM trim settings. Data is in twos<br>mplement format. The significance of USER_TEMP_OFFSET, Bit 0, matches the<br>gnificance of TDATA_x, Bit 2, so the offset trim step size is 4 LSB/step.|0x0|R/W|



## **Address: 0x56, Reset: 0x00, Name: USER_TEMP_SENS_1** 

**==> picture [360 x 112] intentionally omitted <==**

## _**Table 111. Bit Descriptions for USER_TEMP_SENS_1**_ 

|**_Table 111. Bit Descriptions for USER_TEMP_SENS_1_**|**_Table 111. Bit Descriptions for USER_TEMP_SENS_1_**|**_Table 111. Bit Descriptions for USER_TEMP_SENS_1_**|**_Table 111. Bit Descriptions for USER_TEMP_SENS_1_**|**_Table 111. Bit Descriptions for USER_TEMP_SENS_1_**|**_Table 111. Bit Descriptions for USER_TEMP_SENS_1_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|7|USER_TEMP_TRIM_EN<br>0<br>1|<br> <br><br> <br>|User Temperature Offset Trim. When USER_TEMP_TRIM_EN is set high, the<br>USER_TEMP_OFFSET and USER_TEMP_SENS override the default NVM trim<br>settings.<br>Normal Operation (Temperature Sensitivity and Offset Trim Default Value).<br>User Temperature Sensitivity and Offset Trim Enable.|0x0|R/W|
|6|HIGH_GAIN_TEMP<br>0<br>1|<br> <br> <br> <br>|High Gain Temp Enable. Set to 1 to configure the temperature sensor to higher<br>sensitivity (LSB/°C) mode.<br>Normal Operation Mode. Temperature sensor sensitivity is 10.2 LSB/°C.<br>Temp Sensor Higher Sensitivity (LSB/°C) Mode. Temperature sensor sensitivity is<br>16.5 LSB/°C.|0x0|R/W|
|5|RESERVED||Reserved.|0x0|R|
|[4:0]|USER_TEMP_SENS|<br> <br> <br>|User Temperature Sensitivity Trim. When USER_TEMP_TRIM_EN is set high, the<br>USER_TEMP_SENS overrides the default NVM trim settings. Data is in twos<br>complement format. The temperature sensitivity trim step size is 1/128 = 0.78125%<br>per step.|0x0|R/W|



**Rev. 0 | 90 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

## **MISO AND GAIN SCALER CONFIGURATION REGISTER** 

## **Address: 0x58, Reset: 0x00, Name: MISO** 

**==> picture [348 x 89] intentionally omitted <==**

## _**Table 112. Bit Descriptions for MISO**_ 

|**_Table 112. Bit Descriptions for MISO_**|**_Table 112. Bit Descriptions for MISO_**|**_Table 112. Bit Descriptions for MISO_**|**_Table 112. Bit Descriptions for MISO_**|**_Table 112. Bit Descriptions for MISO_**|**_Table 112. Bit Descriptions for MISO_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|7|RESERVED||Reserved.|0x0|R|
|6|GAIN_SCALER_BYPASS|0<br>1|Bypass Gain Scaler in DSM Path.<br>Normal Operation.<br>Enable Bypass Gain Scaler in DSM Path.|0x0|R/W|
|[5:2]|RESERVED||Reserved.|0x0|R|
|1|MISO_ASEL0_PD|0<br>1|MISO Pad Pull-Down. Enables a weak pull-down path (MΩ) on MISO to avoid pin<br>floating.<br>Normal Mode.<br>Enable Pad Pull-Down.|0x0|R/W|
|0|MISO_ASEL0_DRV|0<br>1|MISO Pad Drive. Enables stronger output driver on MISO line. Recommended for<br>high speed SPI operation.<br>Normal Mode.<br>Enable Strong Pad Drive Strength.|0x0|R/W|



## **SOUT0 PAD CONTROL REGISTER** 

**Address: 0x59, Reset: 0x00, Name: SOUT0** 

**==> picture [274 x 65] intentionally omitted <==**

_**Table 113. Bit Descriptions for SOUT0**_ 

|**_Table 113. Bit Descriptions for SOUT0_**|**_Table 113. Bit Descriptions for SOUT0_**|**_Table 113. Bit Descriptions for SOUT0_**|**_Table 113. Bit Descriptions for SOUT0_**|**_Table 113. Bit Descriptions for SOUT0_**|**_Table 113. Bit Descriptions for SOUT0_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:2]|RESERVED||Reserved.|0x0|R|
|1|SOUT0_PD|0<br>1|SOUT Pad Pull-Down. Enables a weak pull-down path (MΩ) on SOUT0to avoid pin floating.<br>Normal Operation.<br>Enable Pad Pull-Down.|0x0|R/W|
|0|SOUT0_DRV|0<br>1|SOUT Pad Drive. Enables stronger output driver on SOUT0line. Recommended for high speed<br>I2S/TDM/PDM operation.<br>Normal Operation.<br>Enable Strong Pad Drive Strength.|0x0|R/W|



**Rev. 0 | 91 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

## **MCLK PAD REGISTER** 

## **Address: 0x5A, Reset: 0x00, Name: MCLK** 

**==> picture [233 x 65] intentionally omitted <==**

_**Table 114. Bit Descriptions for MCLK**_ 

|**_Table 114. Bit Descriptions for MCLK_**|**_Table 114. Bit Descriptions for MCLK_**|**_Table 114. Bit Descriptions for MCLK_**|**_Table 114. Bit Descriptions for MCLK_**|**_Table 114. Bit Descriptions for MCLK_**|**_Table 114. Bit Descriptions for MCLK_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:2]|RESERVED||Reserved.|0x0|R|
|1|MCLK_PD|0<br>1|MCLK Pad Pull-Down. Enables a weak pull-down path (MΩ) on MCLK to avoid pin floating.<br>Normal Operation.<br>Enable Pad Pull-Down.|0x0|R/W|
|0|MCLK_DRV|0<br>1|MCLK Pad Drive. Enables stronger output driver on MCLK line. Recommended for high speed<br>I2S/TDM/PDM operation.<br>Normal Operation.<br>Enable Pad Drive.|0x0|R/W|



## **BCLK PAD REGISTER** 

## **Address: 0x5B, Reset: 0x00, Name: BCLK** 

**==> picture [233 x 65] intentionally omitted <==**

_**Table 115. Bit Descriptions for BCLK**_ 

|**_Table 115. Bit Descriptions for BCLK_**|**_Table 115. Bit Descriptions for BCLK_**|**_Table 115. Bit Descriptions for BCLK_**|**_Table 115. Bit Descriptions for BCLK_**|**_Table 115. Bit Descriptions for BCLK_**|**_Table 115. Bit Descriptions for BCLK_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:2]|RESERVED||Reserved.|0x0|R|
|1|BCLK _PD|0<br>1|BCLK Pad Pull-Down. Enables a weak pull-down path (MΩ) on BCLK to avoid pin floating.<br>Normal Operation.<br>Enable Pad Pull-Down.|0x0|R/W|
|0|BCLK_DRV|0<br>1|BCLK Pad Drive. Enables stronger output driver on BCLK line. Recommended for high speed<br>I2S/TDM/PDM operation.<br>Normal Operation.<br>Enable Pad Drive.|0x0|R/W|



**Rev. 0 | 92 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

## **FSYNC PAD AND RESYNC CONFIGURATION REGISTER** 

## **Address: 0x5C, Reset: 0x00, Name: FSYNC** 

**==> picture [306 x 88] intentionally omitted <==**

_**Table 116. Bit Descriptions for FSYNC**_ 

|**_Table 116. Bit Descriptions for FSYNC_**|**_Table 116. Bit Descriptions for FSYNC_**|**_Table 116. Bit Descriptions for FSYNC_**|**_Table 116. Bit Descriptions for FSYNC_**|**_Table 116. Bit Descriptions for FSYNC_**|**_Table 116. Bit Descriptions for FSYNC_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|7|SYNC_RESYNC|F<br>o<br>w<br>r|orce resync when user must maintain the same phase relationship. Force a resynchronization<br>f the internal datapath logic to ensure consistent phase behavior of data output. Valid<br>hen using EXT_SYNC or AUDIO_MODE only. Toggle this bit to 1 then back to 0 to force<br>esynchronization.|0x0|R/W|
|[6:2]|RESERVED|R|eserved.|0x0|R|
|1|FSYNC_PD|F<br>0<br>N<br>1<br>E|SYNC Pad Pull-Down. Enables a weak pull-down path (MΩ) on FSYNC to avoid pin floating.<br>ormal Operation.<br>nable Pad Pull-Down.|0x0|R/W|
|0|FSYNC_DRV|F<br>s<br>0<br>N<br>1<br>E|SYNC Pad Drive. Enables stronger output driver on FSYNC line. Recommended for high<br>peed I2S/TDM/PDM operation.<br>ormal Operation.<br>nable Strong Pad Drive Strength.|0x0|R/W|



**Rev. 0 | 93 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

## **INT0 PAD CONTROL REGISTER** 

## **Address: 0x5D, Reset: 0x00, Name: INT0** 

**==> picture [300 x 88] intentionally omitted <==**

## _**Table 117. Bit Descriptions for INT0**_ 

|**_Table 117. Bit Descriptions for INT0_**|**_Table 117. Bit Descriptions for INT0_**|**_Table 117. Bit Descriptions for INT0_**|**_Table 117. Bit Descriptions for INT0_**|**_Table 117. Bit Descriptions for INT0_**|**_Table 117. Bit Descriptions for INT0_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|7|INT0_POL|0<br>1|INT0 Polarity. Configures whether the INT0 pin operates in active high (B7 low) or active low (B7<br>high) mode.<br>INT0 Active High Mode (Default)<br>INT0 Active Low Mode.|0x0|R/W|
|[6:2]|RESERVED||Reserved.|0x0|R|
|1|INT0 _PD|0<br>1|INT0 Pad Pull-Down. Enables a weak pull-down path (MΩ) on INT0 to avoid pin floating.<br>Normal Operation.<br>Enable Pad Pull-Down.|0x0|R/W|
|0|INT0_DRV|0<br>1|INT0 Pad Drive. Enables stronger output driver on INT0 line. Recommended if the interrupt pin has<br>heavy loading.<br>Normal Operation.<br>Enable Strong Pad Drive Strength.|0x0|R/W|



**Rev. 0 | 94 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **REGISTER MAP** 

## **INT1 PAD CONTROL REGISTER** 

## **Address: 0x5E, Reset: 0x00, Name: INT1** 

**==> picture [300 x 88] intentionally omitted <==**

## _**Table 118. Bit Descriptions for INT1**_ 

|**_Table 118. Bit Descriptions for INT1_**|**_Table 118. Bit Descriptions for INT1_**|**_Table 118. Bit Descriptions for INT1_**|**_Table 118. Bit Descriptions for INT1_**|**_Table 118. Bit Descriptions for INT1_**|**_Table 118. Bit Descriptions for INT1_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|7|INT1_POL|0<br>1|INT1 Polarity. Configures whether the INT1 pin operates in active high (B7 low) or active low (B7<br>high) mode.<br>INT1 Active High Mode.<br>INT1 Active Low Mode.|0x0|R/W|
|[6:2]|RESERVED||Reserved.|0x0|R|
|1|INT1_PD|0<br>1|INT1 Pad Pull-Down. Enables a weak pull-down path (MΩ) on INT1 to avoid pin floating.<br>Normal Operation.<br>Enable Pad Pull-Down.|0x0|R/W|
|0|INT1_DRV|0<br>1|INT1 Pad Drive. Enables stronger output driver on INT1 line. Recommended if the interrupt pin has<br>heavy loading.<br>Normal Operation.<br>Enable Strong Pad Drive Strength.|0x0|R/W|



**Rev. 0 | 95 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **APPLICATIONS INFORMATION** 

## **APPLICATION EXAMPLES** 

This section includes several application examples and initialization sequences for the ADXL380. Use these sequences as a starting point and modify these sequences to suit individual application requirements. 

## **DEVICE CONFIGURATION** 

All configuration register writes must be completed with the ADXL380 in standby mode. The only exception to this is the activity and inactivity threshold registers (Register 0x39, Register 0x3A, Register 0x3E, and Register 0x3F). These registers must be set after entering the desired operation mode (see the OP_MODE register, Register 0x26). See the following sections for example initialization sequences. 

Settings for each of the registers vary based on application requirements. For more information, see the Analog Devices Device ID Register section through the INT1 Pad Control Register section. 

## **Start-Up Routine** 

The following start-up routine shows the most basic initialization sequence to start receiving data from the device (via SPI or I[2] C). Before sending this sequence, verify that SPI or I[2] C communication is working correctly by reading Register 0x00 to confirm that the correct response (0xAD) is received. 

**1.** Write 0xF0 to Register 0x27 (DIG_EN). 

   - Enables x, y, z, and temperature channels. 

**2.** Write 0x0C to Register 0x26 (OP_MODE). 

   - Enables HP mode. 

- Enables HP mode. Data now starts accumulating in the FIFO. 

After entering HP mode, use the watermark interrupt to trigger reading data from the FIFO. Use a multibyte read of Register 0x1D (FIFO_DATA) to read the entire contents of the FIFO. Do not read more samples than are currently stored in the FIFO. Read FIFO_ENTRIES (Register 0x1E, Bits[7:0] and Register 0x1F, Bit 0) to determine the number of samples that are currently in the FIFO before each FIFO read. 

To ensure that no samples are lost, it is important to finish reading from the FIFO and de-assert the chip select line before a new sample becomes available. Reading from the FIFO while a new sample becomes available results in that sample being lost. To avoid the sample being lost, ensure that the digital communication is fast enough (use a fast SPI clock or high speed I[2] C) to complete the multibyte read before a new sample becomes available. 

## **Example: I[2] S Mode** 

I[2] S protocol for audio data is suitable for obtaining high speed, synchronous accelerometer data. Because latency is often important in audio applications, it is most common to set the system clock to 768 kHz as described in the Low Latency Mode section. This setting of the system clock requires setting up the clock divider (EXT_CLK_RATE, Register 0x25, Bits[7:4]) such that the BCLK divides down to 768 kHz. 

See the example sequence that follows for a 3.072 MHz BCLK and 48 kHz FSYNC: 

**1.** Write 0x00 to Register 0x32 (SPT_CFG0). 

   - Sets the word width to 32 bits. 

## **Example: FIFO Mode** 

The built-in FIFO can be enabled with the following example sequence: 

**1.** Write 0x78 to Register 0x27 (DIG_EN). 

   - Enables x, y, and z channels and enables FIFO mode. Data will not start accumulating in the FIFO until standby mode is exited. 

**2.** Write 0x60 to Register 0x30 (FIFO_CFG0). 

   - Enables FIFO channel ID and FIFO stream mode. 

**3.** Write 0x0C to Register 0x31 (FIFO_CFG1). 

   - Sets FIFO_SAMPLES (Register 0x30, Bit 0 and Register 0x31, Bits[7:0]) to 12. The FIFO_WATERMARK bit (Register 0x11, Bit 3) asserts when four full samples (X, Y, and Z) are stored in the FIFO. 

   - This value can be changed to fit the application needs. 

**4.** Write 0x08 to Register 0x2B (INT0_MAP0). 

   - Maps the FIFO_WATERMAK bit (Register 0x11, Bit 3) to the INT0 pin. 

**5.** Write 0x0C to Register 0x26 (OP_MODE). 

   - Configures the device to expect stereo FSYNC (50% duty cycle). 

**2.** Write 0x88 to Register 0x33 (SPT_CFG1). 

   - Sets time slots for x-axis and y-axis data-words. 

   - Sets the output to repeat samples if ODR < FSYNC rate. 

**3.** Write 0x5A to Register 0x34 (SPT_CFG2). 

   - Sets time slots for z-axis data-word. 

**4.** Write 0x80 to Register 0x35 (SYNC_CFG). 

   - Sets BCLK and FSYNC source (external). 

**5.** Optional: write 0x01 to Register 0x59 (SOUT0) and 0x01 to Register 0x5A (MCLK). 

   - Increases drive strength of the data output pins. 

**6.** Write 0xC0 to Register 0x49 (TRIG_CFG). 

   - Sets the internal decimation and filter bypasses to select the output data rate of 48 kHz. 

**7.** Write 0x32 to Register 0x25 (CLK_CTRL). 

   - Sets the external clock and sets the clock divider (EXT_CLK_RATE is divide by 4), which divides the 3.072 MHz BCLK down to the expected system clock (768 kHz). 

**8.** Write 0x40 to Register 0x50 (FILTER). 

**Rev. 0 | 96 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **APPLICATIONS INFORMATION** 

   - Sets LPF and HPF settings and disables the EQ filter. 

**9.** Write 0x74 to Register 0x27 (DIG_EN). 

   - Enables x, y, and z channels and sets the DOUBLE_SPEED bit in the DIG_EN register (Register 0x27, Bit 2), which is required for low latency mode. 

**10.** Write 0x1C to Register 0x26 (OP_MODE). 

   - Enables HP mode and audio mode. 

## **Example: PDM Mode** 

The PDM bypasses the digital filters and offers the best performance in terms of latency. Additional filtering and decimation may be required at the system level. See the example initialization sequence that follows: 

**1.** Write 0x39 to Register 0x36 (PDM_CFG). 

   - Configures x-data in Slot A, and y-data in Slot B (SOUT0 pin). 

## **Example: TDM Mode** 

Similar to the I[2] S protocol, the ADXL380 supports TDM protocol communication. Because latency is often important in audio applications, it is most common to set the ADXL380 system clock to 768 kHz as described in the Low Latency Mode section, which requires setting up the clock divider (EXT_CLK_RATE, Register 0x25, Bits[7:4]) such that the BCLK divides down to 768 kHz. 

See the example sequence that follows for a 6.144 MHz BCLK and 48 kHz FSYNC: 

**1.** Write 0x08 to Register 0x32 (SPT_CFG0). 

   - Sets the word width to 32 bits. 

   - Configures the device to expect a sync pulse that is a single bit clock wide. 

**2.** Write 0x88 to Register 0x33 (SPT_CFG1). 

   - Sets time slots for x-axis and y-axis data-words. 

   - Sets the output to repeat samples if ODR < FSYNC rate. 

**3.** Write 0x1A to Register 0x34 (SPT_CFG2). 

   - Sets time slots for z-axis data-word. 

**4.** Write 0x80 to Register 0x35 (SYNC_CFG). 

   - Sets BCLK and FSYNC source (external). 

**5.** Optional: write 0x01 to Register 0x59 (SOUT0) and 0x01 to Register 0x5A (MCLK). 

   - Increases drive strength of the data output pins. 

**6.** Write 0xC0 to Register 0x49 (TRIG_CFG). 

   - Sets the internal decimation and filter bypasses to select the output data rate of 48 kHz. 

**7.** Write 0x52 to Register 0x25 (CLK_CTRL). 

   - Sets the external clock and sets the clock divider (EXT_CLK_RATE is divide by 8), which divides the 6.144 MHz BCLK down to the expected system clock (768 kHz). 

**8.** Write 0x40 to Register 0x50 (FILTER). 

   - Sets LPF and HPF settings and disables the EQ filter. 

**9.** Write 0x74 to Register 0x27 (DIG_EN). 

   - Enables x, y, and z channels and sets the DOUBLE_SPEED bit in the DIG_EN register (Register 0x27, Bit 2), which is required for low latency mode. 

   - Configures z-data in Slot A (FSYNC pin). 

**2.** Optional: write 0x01 to Register 0x59 (SOUT0) and 0x01 to Register 0x5C (FSYNC). 

   - Increases drive strength of the data output pins. 

**3.** Write 0x02 to Register 0x25 (CLK_CTRL). 

   - Sets BCLK pin as the external clock source. 

   - Provide an external clock of 768 kHz on the BCLK pin. If a higher clock rate is required, choose an external clock divider such that the system clock remains at 768 kHz. For example, with a 6.144 MHz external clock, set EXT_CLK_RATE (Register 0x25, Bits[7:4]) to divide by 8. 

**4.** Write 0x74 to Register 0x27 (DIG_EN). 

   - Enables x, y, and z channels and sets the DOUBLE_SPEED bit in the DIG_EN register (Register 0x27, Bit 2), which is required for low latency mode. 

**5.** Write 0x2C to Register 0x26 (OP_MODE). 

   - Enables HP mode and enables PDM mode. 

## **Example: External Sync Mode** 

External synchronization allows the user to synchronize acceleration sampling to an external synchronization signal. This feature is only supported for the high performance signal chain (HP, RBW, or LP operational modes). In order to enable the external sync with the internal clock mode follow these steps: 

      **1.** Optional: write 0x00 to Register 0x25 (CLK_CTRL). 

         - This setting configures the ADXL380 to use the internal clock. If an external clock is desired, write 0b10 to the CLK_SRC bits (Register 0x25, Bits[1:0]). See the External Synchronization section for more details. 

      **2.** Write 0x10 to register 0x35 (SYNC_CFG). 

         - SYNC_MODE = 1. This setting synchronizes the output data rate of the ADXL380 with the external sync signal. 

      **3.** Write 0x70 to Register 0x27 (DIG_EN). 

         - Enables x, y, and z channels. 

      **4.** Write 0x0C to Register 0x26 (OP_MODE). 

         - Enables HP mode. 

**10.** Write 0x1C to Register 0x26 (OP_MODE). 

   - Enables HP mode and audio mode. 

**Rev. 0 | 97 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **APPLICATIONS INFORMATION** 

## **Example: Heart Sounds Mode** 

The ADXL380 has a heart sounds mode that optimizes performance and power consumption. Heart sounds mode is a single channel mode (z-axis only) that has low noise density while maintaining low power consumption (see Table 1). Heart sounds mode can be activated with the following example sequence: 

**1.** Write 0x10 to Register 0x27 (DIG_EN). 

   - Enables z channel only. 

**2.** Perform any configuration writes to the HPF settings if desired. 

**3.** Write 0x01 to Register 0x26 (OP_MODE). 

   - Enables HS mode. 

## **Example: Activity and Inactivity Detection Mode** 

The ADXL380 features built-in logic that detects activity (presence of acceleration more than a threshold) and inactivity (lack of acceleration more than a threshold). Activity and inactivity events can be used as triggers to manage the accelerometer mode of operation, trigger an interrupt to a host processor, and/or autonomously drive a motion switch. 

See the example sequence that follows to configure activity and inactivity detection: 

**1.** Write 0xA0 to Register 0x2B (INT0_MAP0) and 0x00 to Register 0x2C (INT0_MAP1) to map the activity interrupt to the INT0 pin. 

**2.** Write 0x40 to Register 0x2D (INT1_MAP0) and 0x00 to Register 0x2E (INT1_MAP1), to map the inactivity interrupt to the INT1 pin. 

**3.** Write 0x05 to Register 0x37 (ACT_INACT_CTL) to enable activity and inactivity detection. 

**4.** Write 0x03 to Register 0x38 (SNSR_AXIS_EN) to enable x-axis and y-axis for activity and inactivity detection. 

**5.** Write 0x00 to Register 0x3B (TIME_ACT_H), 0x00 to Register 0x3C (TIME_ACT_M), and 0xC8 to Register 0x3D (TIME_ACT_L) to set the activity time to 100 ms. 

## **Example: Tap Detection Mode** 

The ADXL380 have a built-in single, double, and triple tap detection. The tap threshold, duration, window, and latency can all be configured to fit the application needs (see Figure 73). 

See the example sequence that follows to configure tap detection: 

   **1.** Write 0x01 to Register 0x2C (INT0_MAP1). 

      - Maps the single tap detect interrupt to the INT0 pin. 

   **2.** Write 0x03 to Register 0x2E (INT1_MAP1). 

      - Maps the double and triple tap detect interrupts to the INT1 pin. When multiple interrupt functions are mapped to the same interrupt pin, the logical OR of the two functions determines when the interrupt is asserted. A read of Register 0x12 (STATUS1) can determine which tap event (double or triple) has occurred. 

   **3.** Write 0x80 to Register 0x43 (TAP_THRESH) to set the tap detect threshold to 4 _g_ . 

   **4.** Write 0x40 to Register 0x44 (TAP_DUR) to set the tap duration to 40 ms. 

   **5.** Write 0x20 to Register 0x45 (TAP_LATENT) to set the latency time to 40 ms. 

      - A value of 0x00 in this register disables double and triple tap detection. 

   **6.** Write 0x7D to Register 0x46 (TAP_WINDOW) to set the tap window duration to 320 ms, which sets the duration time where additional taps can be detected (second or third). 

   **7.** Write 0x06 to Register 0x48 (TAP_CFG). 

      - This enables triple tap detection and sets the z-axis as the active tap detection axis. 

   **8.** Write 0x70 to Register 0x27 (DIG_EN). 

      - Enables x, y, and z channels. 

   **9.** Write 0x03 to Register 0x26 (OP_MODE). 

      - Enables VLP mode. 

**6.** Write 0x00 to Register 0x40 (TIME_INACT_H), 0x00 to Register 0x41 (TIME_INACT_M), and 0xC8 to Register 0x42 (TIME_INACT_L) to set the activity time to 100 ms. 

**7.** Write 0x02 to Register 0x26 (OP_MODE) to enable ULP mode. 

**8.** Write 0x01 to Register 0x39 (THRESH_ACT_H) and 0x00 to Register 0x3A (THRESH_ACT_L) to set the activity threshold to 500 m _g_ . 

**9.** Write 0x00 to Register 0x3E (THRESH_INACT_H) and 0x80 to Register 0x3F (THRESH_INACT_L) to set the inactivity threshold to 250 m _g_ . 

**Rev. 0 | 98 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **APPLICATIONS INFORMATION** 

## **Example: Implementing Free Fall Detection** 

The ADXL380 has built-in, free fall detection using an inactivity interrupt. 

When an object is in true free fall, acceleration on all axes is 0 _g_ . Therefore, free fall detection is achieved by looking for acceleration on all axes to fall to less than a certain threshold (close to 0 _g_ ) for a certain amount of time. The inactivity detection functionality, when used in absolute mode, does exactly this. 

To use inactivity to implement free fall detection, set the value in the THRESH_INACT_x register (Register 0x3E and Register 0x3F) to the desired free fall threshold. Values between 300 m _g_ and 600 m _g_ are recommended; the register setting for these values varies based on the _g_ range setting of the ADXL380, as follows: 

## _THRESH_INACT_x_ = 

## _Threshold Value_ ( _g_ ) × _Scale Factor_ (LSB per _g_ ) 

Set the value in the TIME_INACT_x register (Register 0x40 through Register 0x42) to implement the minimum amount of time that the acceleration on all axes must be less than the free fall threshold to generate a free fall condition. Values between 100 ms and 350 ms are recommended; the register setting for this varies based on the output data rate. 

## _TIME_INACT_x_ = _Time_ (sec) × _Data Rate_ (Hz) 

When a free fall condition is detected, the inactivity status is set to 1, and, if the function is mapped to an interrupt pin (INT0 or INT1), an inactivity interrupt triggers on that pin. 

**Rev. 0 | 99 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **APPLICATIONS INFORMATION** 

## **POWER SUPPLY REQUIREMENTS** 

## **Hold Time** 

The ADXL380 operates using supply voltage rails ranging from 2.25 V to 3.6 V. The operating voltage range (VS) specified in Table 1 ranges from 2.25 V to 3.6 V to account for inaccuracies and transients of up to ±10% on the supply voltage. When power cycling the ADXL380, it is highly recommended to fully discharge the device to ground level (VS = 0 V) on each power cycle. If this is not possible, care must be taken regarding the following specifications: 

- Supply reset threshold (VRESET) 

To ensure a successful power-on reset (POR), VS must be held to less than VRESET for at least 1 ms before reapplying the supply to the ADXL380 (see Figure 79). 

## **Rise Time** 

The supply voltage rise time is defined as the time from 0 V to 90% of VS, which is true regardless of what supply voltage is used (see Figure 79). 

- Hold time 

- Rise time 

## **Supply Reset Threshold** 

During start-up or power cycling of the ADXL380, VS must always be started up from less than VRESET. When the ADXL380 is operating, any time power is removed from the ADXL380 or falls to less than 2.25 V, VS must be discharged lower than VRESET. 

_**Figure 79. POR and Start-Up Requirements**_ 

To enable supply discharge, it is recommended to power the ADXL380 from a microcontroller general-purpose input and output (GPIO), connect a shutdown discharge switch to the supply, or use a voltage regulator with a shutdown discharge feature. 

Following POR, the output requires 2 ms to settle after entering measurement mode. 

**Rev. 0 | 100 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **APPLICATIONS INFORMATION** 

## **INTERRUPTS** 

Several of the built-in functions of the ADXL380 can trigger interrupts to alert the host processor of certain status conditions. See the Interrupt Pins section for further details. 

## **Interrupt Pins** 

Interrupts can be mapped to either (or both) of two designated output pins, INT0 and INT1. All functions can be used simultaneously. If multiple interrupts are mapped to one pin, the OR combination of the interrupts determines the status of the pin. 

If no functions are mapped to an interrupt pin, that pin is automatically configured to a high impedance (high-Z) state. The pins are also placed in the high-Z state upon a reset. 

high by default so that when it is activated, the pin goes high. However, this configuration can be switched to active low by setting the INTx_POL bit in Register 0x5D, Bit 7 and Register 0x5E, Bit 7. 

The INT pins can be connected to the interrupt input of a host processor where interrupts are responded to with an interrupt routine. 

Both interrupt pins are push-pull low impedance pins with an output impedance of 50 Ω (typical) when being driven and digital output specifications, as shown in Table 119. Both pins have bus keepers when the pins are not internally driven. 

To prevent interrupts from being falsely triggered during configuration, disable interrupts while their settings, such as thresholds, timings, or other values, are configured. 

When a certain status condition is detected, the pin that condition is mapped to is activated. The configuration of the pin is active 

_**Table 119. Interrupt Pin Digital Output**_ 

|**_Table 119. Interrupt Pin Digital Output_**|**_Table 119. Interrupt Pin Digital Output_**||||
|---|---|---|---|---|
|**Parameter**<br>**Test Conditions**||**Limit1**<br>**Unit**<br>**Min**<br>**Max**|||
|Digital Output<br>Low Level Output Voltage (VOL)<br>High Level Output Voltage (VOH)<br>Low Level Output Current (IOL)<br>High Level Output Current (IOH)|IOL= 500 µA<br>IOH= −300 µA<br>VOL= VOL, max<br>VOH= VOH, min|0.9 × VDDIO<br>500|0.1 × VDDIO<br>−300|V<br>V<br>µA<br>µA|



> 1 Limits based on design, not production tested. 

**Rev. 0 | 101 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **APPLICATIONS INFORMATION** 

## **USING AN EXTERNAL CLOCK** 

An external clock can be used to improve clock frequency accuracy or to enable additional features (for example, interpolation sync). The register CLK_CTRL (Register 0x25) is used to set the external clock features. 

The external clock can be provided on either MCLK or BCLK. The CLK_SRC bits (Bits[1:0]) must be set to match the chosen clock source (internal, MCLK, or BCLK). 

The order of operation for external clock usage is as follows: 

**1.** Power on the ADXL380. 

**2.** Set the CLK_CTRL register (Register 0x25) to the desired value. 

**3.** Enable acceleration and temperature channels by writing to the MODE_CHANNEL_EN bits in the DIG_EN register (Register 0x27, Bits[7:4]). 

**4.** Set the ADXL380 to the desired operational mode (HP, RBW, LP, or so on) by writing to the OP_MODE bits in the OP_MODE register (Register 0x26, Bits[3:0]). 

The clock must be an integer multiple of the 512 kHz nominal clock frequency such that it can be divided down to fit the intended nominal clock frequency by setting the internal divider (EXT_CLK_RATE bits in the CLK_CTRL register (Register 0x25, Bits[7:4]). The EXT_CLK_RATE bits must be set to the appropriate divider according to Table 120. The external clock must be divided down to the expected system clock (512 kHz if using HP, RBW, or LP modes or 256 kHz if using VLP, ULP, HS modes). See Table 16 for more information. 

_**Table 120. External Clock Value Input and Corresponding Divider Settings (Register 0x25)**_ 

|**_Table 120. External Clock Value Input and Corresponding Divider Settings_**<br>**_(Register 0x25)_**|**_Table 120. External Clock Value Input and Corresponding Divider Settings_**<br>**_(Register 0x25)_**|**_Table 120. External Clock Value Input and Corresponding Divider Settings_**<br>**_(Register 0x25)_**|
|---|---|---|
|**External Clock Value**<br>**(MHz)**<br>**Divider Value**<br>**EXT_CLK_RATE**|||
|0.512<br>1.024<br>1.536<br>2.048<br>3.072<br>4.096<br>6.144<br>8.192<br>12.288|No Divider<br>Divide by 2<br>Divide by 3<br>Divide by 4<br>Divide by 6<br>Divide by 8<br>Divide by 12<br>Divide by 16<br>Divide by 24|4’b0000<br>4’b0001<br>4’b0010<br>4’b0011<br>4’b0100<br>4’b0101<br>4’b0110<br>4’b0111<br>4’b1000|



Note that when the DOUBLE_SPEED bit in the DIG_EN register (Register 0x27, Bit 2) is set to 1, the external clock input must be double the value in Table 120. 

## **MECHANICAL CONSIDERATIONS FOR MOUNTING** 

in large, apparent measurement errors due to undampened PCB vibration. Locating the accelerometer near a hard mounting point ensures that any PCB vibration at the accelerometer is more than the mechanical sensor resonant frequency of the accelerometer and, therefore, effectively invisible to the accelerometer. Multiple mounting points, close to the sensor, and/or a thicker PCB can also help to reduce the effect of system resonance on the performance of the sensor. 

**==> picture [82 x 75] intentionally omitted <==**

_**Figure 80. Incorrectly Placed Accelerometers**_ 

## **PCB FOOTPRINT** 

Figure 81 shows the recommended PCB footprint. The inner pads represent the ADXL380 pads (0.40 mm × 0.28 mm). The outer pads (0.50 mm × 0.38 mm) represent the footprint on the PCB (PCB pads). To minimize package level stress on the ADXL380, the following guidelines are outlined: 

- All PCB pad dimensions must match the dimensions shown in Figure 81. 

- PCB traces must be symmetric around the ADXL380, which means that the trace width must match the horizontally opposite traces and vertically opposite traces to minimize package stress when exposed to changing temperatures. 

- Do not place a ground pad under the ADXL380. 

**==> picture [149 x 162] intentionally omitted <==**

_**Figure 81. Recommended PCB Footprint, Inner Pads Represent Pads on the ADXL380 Package, Outer Pads Represent the Footprint on the PCB, and All Dimensions in Millimeters**_ 

Mount the ADXL380 on the PCB in a location that is close to a hard mounting point on the PCB to the case. Mounting the ADXL380 at an unsupported PCB location, as shown in Figure 80, can result 

**Rev. 0 | 102 of 103** 

**analog.com** 

Data Sheet 

**ADXL380** 

## **OUTLINE DIMENSIONS** 

**==> picture [98 x 78] intentionally omitted <==**

**==> picture [115 x 99] intentionally omitted <==**

**==> picture [111 x 34] intentionally omitted <==**

_**Figure 82. 14-Terminal Land Grid Array [LGA] (CC-14-3) Dimensions shown in millimeters**_ 

## **ORDERING GUIDE** 

|**Model1**<br>**Temperature Range**<br>**Package Description**<br>**Package Option**|**Model1**<br>**Temperature Range**<br>**Package Description**<br>**Package Option**|**Model1**<br>**Temperature Range**<br>**Package Description**<br>**Package Option**|**Model1**<br>**Temperature Range**<br>**Package Description**<br>**Package Option**|
|---|---|---|---|
|ADXL380-1BCCZ-RL<br>ADXL380-1BCCZ-RL7<br>ADXL380-2BCCZ-RL<br>ADXL380-2BCCZ-RL7|−40°C to +85°C<br>−40°C to +85°C<br>−40°C to +85°C<br>−40°C to +85°C|14-Terminal LGA<br>14-Terminal LGA<br>14-Terminal LGA<br>14-Terminal LGA|CC-14-3<br>CC-14-3<br>CC-14-3<br>CC-14-3|



> 1 Z = RoHS Compliant Part. 

## **MODELS, MEASUREMENT RANGE, AND COMMUNICATIONS INTERFACE** 

_**Table 121. Models, Measurement Range, and Communications Interface**_ 

|**_Table 121. Models, Measurement Range, and Communications Interface_**|**_Table 121. Models, Measurement Range, and Communications Interface_**|**_Table 121. Models, Measurement Range, and Communications Interface_**|
|---|---|---|
|**Model1**<br>**Measurement Range (****_g_)**<br>**Communications Interface**|||
|ADXL380-1BCCZ-RL7<br> <br>ADXL380-1BCCZ-RL<br> <br>ADXL380-2BCCZ-RL7<br> <br>ADXL380-2BCCZ-RL<br>|±4, ±8, ±16<br>±4, ±8, ±16<br>±4, ±8, ±16<br>±4, ±8, ±16|SPI<br>SPI<br>I2C<br>I2C|



> 1 Z = RoHS Compliant Part. 

## **EVALUATION BOARDS** 

_**Table 122. Evaluation Boards**_ 

|**_Table 122. Evaluation Boards_**|**_Table 122. Evaluation Boards_**|
|---|---|
|**Model1**<br>**Description**||
|EVAL-ADXL380-EB-1Z<br>EVAL-ADXL380-EB-2Z<br>EVAL-ADXL380-BB-1Z<br>EVAL-ADXL380-BB-2Z|Evaluation Board for the SPI Variant<br>Evaluation Board for the I2C Variant<br>Breakout Board for the SPI Variant<br>Breakout Board for the I2C Variant|



> 1 Z = RoHS-Compliant Part. 

**==> picture [111 x 32] intentionally omitted <==**

©2024 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. 

**Rev. 0 | 103 of 103**
Updated at April 28, 2026
Since its inception in 1965, Analog Devices has established itself as a global leader in the design and manufacturing of high-performance analog, mixed-signal, and digital signal processing (DSP) integrated circuits. The company is renowned for solving complex engineering challenges by providing critical technologies that seamlessly convert real-world phenomena into precise electrical signals for the industrial, automotive, communications, and consumer markets. Within its extensive portfolio, Analog Devices provides highly reliable clock, timing, and frequency management solutions, featuring a comprehensive array of precision timers, oscillators, and pulse generators. Complementing this core lineup is a robust offering of driver and interface ICs, particularly high-performance I/O expanders that enable seamless connectivity and streamline complex electronic system architectures. Beyond these foundational integrated circuits, Analog Devices leads the industry in sensor innovation, delivering advanced MEMS accelerometers and integrated MEMS modules designed for exceptional precision in motion sensing. To support complete hardware designs, the company's specialized offerings also encompass discrete bipolar transistors, sub-2.4GHz RF transceivers, temperature-compensated oscillators, and dedicated power management components such as DC/DC converters and LED driver ICs.
About Novapart

Novapart is a B2B electronic component broker specialising in stock shortages and cost reduction. We source hard-to-find parts and identify compliant alternatives across a catalogue of 410,000+ components from 500+ manufacturers.
Learn more →
Stock Shortage Specialist

When a component is unavailable, discontinued or has an unacceptable lead time, we tap into our network of vetted European and Asian distributors to source what you need — without compromising on quality or traceability.
Request a quote →
Compliant Alternatives

We identify pin-to-pin, electrically equivalent substitutes that meet the same certifications (RoHS, AEC-Q100, REACH) as your original specification — validated against datasheets, not just part numbers. Often at a lower cost.
BOM Analysis service →