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ADXL375BCCZ-RL
MEMS Accelerometer, ± 200g, X, Y, Z, LGA, 14 Pins, 20.5LSB/g
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- Manufacturer: ANALOG DEVICES
- Product type: MEMS Accelerometers
- SVHC: No SVHC (04-Feb-2026)
- No. of Pins: 14Pins
- Sensing Axis: X, Y, Z
- Product Range: -
- Qualification: -
- Sensitivity Max: 22.6LSB/g
- Sensitivity Min: 18.4LSB/g
- Sensitivity Typ: 20.5LSB/g
- Sensor Case Style: LGA
- MEMS Sensor Output: Digital
- Supply Voltage Max: 3.6V
- Supply Voltage Min: 2V
- Sensor Case / Package: LGA
- Sensing Range - Accelerometer: ± 200g
| Delivery and price | |
|---|---|
| Units per pack | 500 |
| Price | 7.18 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
**==> picture [159 x 45] intentionally omitted <==** ## **Data Sheet** ## **3-Axis, ±200** _**g**_ **Di ital MEMS Accelerometer g ADXL375** ## **FEATURES** **Low power: as low as 35 µA in measurement mode and 0.1 µA in standby mode at VS = 2.5 V Power consumption scales automatically with bandwidth Embedded, 32-level FIFO buffer minimizes processor load Bandwidth of up to 1 kHz** ## **Bandwidth selectable via serial command** **Shock event detection Activity/inactivity monitoring Supply voltage range: 2.0 V to 3.6 V I/O voltage range: 1.7 V to VS SPI (3- or 4-wire) and I[2] C digital interfaces Wide temperature range: −40°C to +85°C** **10,000** _**g**_ **shock survival** **Pb free/RoHS compliant Small and thin: 3 mm × 5 mm × 1 mm LGA package** ## **GENERAL DESCRIPTION** The ADXL375 is a small, thin, 3-axis accelerometer that provides low power consumption and high resolution measurement up to ±200 _g_ . The digital output data is formatted as 16-bit, twos complement data and is accessible through a SPI (3- or 4-wire) or I[2] C digital interface. An integrated memory management system with a 32-level first in, first out (FIFO) buffer can be used to store data to minimize host processor activity and lower overall system power consumption. Low power modes enable intelligent motion-based power management with threshold sensing and active acceleration measurement at extremely low power dissipation. The ADXL375 is supplied in a small, thin, 3 mm × 5 mm × 1 mm, 14-lead LGA. ## **APPLICATIONS** **Concussion and head trauma detection High force event detection** ## **FUNCTIONAL BLOCK DIAGRAM** **==> picture [304 x 190] intentionally omitted <==** **----- Start of picture text -----**<br> VS VDD I/O<br>ADXL375 POWER<br>MANAGEMENT<br>CONTROL INT1<br>SENSE ADC AND<br>ELECTRONICS DIGITAL INTERRUPT<br>3-AXIS FILTER LOGIC INT2<br>SENSOR<br>SDA/SDI/SDIO<br>32-LEVELFIFO SERIAL I/O SDO/ALT<br>ADDRESS<br>SCL/SCLK<br>GND CS<br>Figure 1.<br>11669-001<br>**----- End of picture text -----**<br> **Document Feedback** **Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.** **One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com** **ADXL375** **Data Sheet** ## **TABLE OF CONTENTS** Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Absolute Maximum Ratings ............................................................ 4 Thermal Resistance ...................................................................... 4 ESD Caution .................................................................................. 4 Soldering Profile ........................................................................... 5 Pin Configuration and Function Descriptions ............................. 6 Typical Performance Characteristics ............................................. 7 Theory of Operation ...................................................................... 10 Power Sequencing ...................................................................... 10 Current Consumption and Output Data Rate ........................ 10 Power Saving Modes .................................................................. 11 FIFO Buffer ................................................................................. 11 Self-Test ........................................................................................ 12 Interrupts ......................................................................................... 13 Enabling and Disabling Interrupts ........................................... 13 Clearing Interrupts ..................................................................... 13 Bits in the Interrupt Registers ................................................... 13 Serial Communications ................................................................. 15 SPI Mode ..................................................................................... 15 I[2] C Mode ...................................................................................... 18 Register Map ................................................................................... 20 Register Descriptions ................................................................. 21 Applications Information .............................................................. 26 Power Supply Decoupling ......................................................... 26 Mechanical Considerations for Mounting .............................. 26 Shock Detection ......................................................................... 26 Threshold Detection and Bandwidth ...................................... 27 Link Mode ................................................................................... 27 Sleep Mode vs. Low Power Mode............................................. 28 Offset Calibration ....................................................................... 28 Data Formatting at Output Data Rates of 3200 Hz and 1600 Hz ................................................................................ 28 Using Self-Test ............................................................................ 29 Axes of Acceleration Sensitivity ............................................... 30 Layout and Design Recommendations ................................... 31 Package Information .................................................................. 31 Outline Dimensions ....................................................................... 32 Ordering Guide .......................................................................... 32 ## **REVISION HISTORY** ## **4/14—Rev. A to Rev. B** Changes to Figure 24 ...................................................................... 15 Changes to Register 0x1E, Register 0x1F, Register 0x20—OFSX, OFSY, OFSZ (Read/Write) Section .............................................. 21 **9/13—Rev. 0 to Rev. A** Added MEMS to Product Title ....................................................... 1 **8/13—Revision 0: Initial Version** Rev. B | Page 2 of 32 **Data Sheet** **ADXL375** ## **SPECIFICATIONS** TA = 25°C, VS = 2.5 V, VDD I/O = 2.5 V, acceleration = 0 _g_ , CS = 10 µF tantalum, CI/O = 0.1 µF, output data rate (ODR) = 800 Hz, unless otherwise noted. **Table 1.** |**Table 1.**|||| |---|---|---|---| |**Parameter**|**Test Conditions/Comments**|**Min**<br>**Typ1**<br>**Max**|**Unit**| |SENSOR INPUT<br>Measurement Range2<br>Nonlinearity<br>Cross-Axis Sensitivity3|Each axis<br>Percentage of full scale|±180<br>±200<br>±0.25<br>±2.5|_g_<br>%<br>%| |SENSITIVITY<br>Sensitivity at XOUT, YOUT, ZOUT2, 4<br>Scale Factor at XOUT, YOUT, ZOUT2, 4<br>SensitivityChange Due to Temperature|Each axis<br>ODR ≤ 800 Hz<br>ODR ≤ 800 Hz|18.4<br>20.5<br>22.6<br>44<br>49<br>54<br>±0.02|LSB/_g_<br>m_g_/LSB<br>%/°C| |0_g_OFFSET<br>0_g_Output for XOUT, YOUT, ZOUT<br>0_g_Offset vs. Temperature|Each axis|−6000<br>±400<br>+6000<br>±10|m_g_<br>m_g_/°C| |NOISE|X-,y-, and z-axes|5|m_g_/√Hz| |OUTPUT DATA RATE AND BANDWIDTH5<br>Output Data Rate (ODR)4, 6|User selectable|0.1<br>3200|Hz| |SELF-TEST7<br>Output Change in Z-Axis||6.4|_g_| |POWER SUPPLY<br>Operating Voltage Range (VS)<br>Interface Voltage Range (VDD I/O)<br>Supply Current<br>Measurement Mode<br>Standby Mode<br>Turn-On and Wake-UpTime8|ODR ≥ 100 Hz<br>ODR ≤ 3 Hz<br>ODR = 3200 Hz|2.0<br>2.5<br>3.6<br>1.7<br>1.8<br>VS<br>145<br>35<br>0.1<br>1.4|V<br>V<br>µA<br>µA<br>µA<br>ms| |TEMPERATURE<br>OperatingTemperature Range||−40<br>+85|°C| |WEIGHT<br>Device Weight||30|mg| 1 Typical specifications are for at least 68% of the population of parts and are based on the worst case of mean ± 1 σ distribution, except for sensitivity, which represents the target value. > 2 Minimum and maximum specifications represent the worst case of mean ± 3 σ distribution and are not guaranteed in production. 3 Cross-axis sensitivity is defined as coupling between any two axes. 4 The output format for the 1600 Hz and 3200 Hz output data rates is different from the output format for the other output data rates. For more information, see the Data Formatting at Output Data Rates of 3200 Hz and 1600 Hz section. 5 Bandwidth is the −3 dB frequency and is half the output data rate: bandwidth = ODR/2. 6 Output data rates < 6.25 Hz exhibit additional offset shift with increased temperature. > 7 Self-test change is defined as the output ( _g_ ) when the SELF_TEST bit = 1 (DATA_FORMAT register, Address 0x31) minus the output ( _g_ ) when the SELF_TEST bit = 0. Due to device filtering, the output reaches its final value after 4 × τ when enabling or disabling self-test, where τ = 1/(data rate). For the self-test to operate correctly, the part must be in normal power operation (LOW_POWER bit = 0 in the BW_RATE register, Address 0x2C). 8 Turn-on and wake-up times are determined by the user-defined bandwidth. At a 100 Hz data rate, the turn-on and wake-up times are each approximately 11.1 ms. For other data rates, the turn-on and wake-up times are each approximately τ + 1.1 ms, where τ = 1/(data rate). Rev. B | Page 3 of 32 **ADXL375** **Data Sheet** ## **ABSOLUTE MAXIMUM RATINGS** ## **Table 2.** |**Table 2.**|| |---|---| |**Parameter**|**Rating**| |Acceleration, Any Axis<br>Unpowered<br>Powered<br>VS<br>VDD I/O<br>Digital Pins<br>Output Short-Circuit Duration<br>(Any Pin to Ground)<br>Temperature Range<br>Powered<br>Storage|10,000_g_<br>10,000_g_<br>−0.3 V to +3.9 V<br>−0.3 V to +3.9 V<br>−0.3 V to VDD I/O+ 0.3 V or 3.9 V,<br>whichever is less<br>Indefinite<br>−40°C to +105°C<br>−40°C to +105°C| ## **THERMAL RESISTANCE** θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. **Table 3. Package Characteristics** |**Package Type **|**θJA**|**θJC**<br>|**Unit**| |---|---|---|---| |14-Terminal LGA|150|85<br>|°C/W| ## **ESD CAUTION** **==> picture [242 x 62] intentionally omitted <==** Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Rev. B | Page 4 of 32 **Data Sheet** **ADXL375** ## **SOLDERING PROFILE** Figure 2 and Table 4 provide information about the recommended soldering profile. **==> picture [245 x 131] intentionally omitted <==** **----- Start of picture text -----**<br> CRITICAL ZONE<br>TP tP TL TO TP<br>RAMP-UP<br>TL TSMAX tL<br>TSMIN<br>PREHEATtS RAMP-DOWN<br>t25°C TO PEAK<br>TIME<br>TEMPERATURE<br>11669-015<br>**----- End of picture text -----**<br> _Figure 2. Recommended Soldering Profile_ **Table 4. Recommended Soldering Profile Limits[1, 2 ]** |**Profile Feature**|**Sn63/Pb37**|**Pb-Free**| |---|---|---| |Average Ramp Rate (TLto TP)<br>Preheat<br>Minimum Temperature (TSMIN)<br>Maximum Temperature (TSMAX)<br>Time from TSMINto TSMAX(tS)<br>Ramp-Up Rate (TSMAXto TL)<br>Liquidous Temperature (TL)<br>Time Maintained Above TL(tL)<br>Peak Temperature (TP)<br>Time Within 5°C of Actual TP(tP)<br>Ramp-Down Rate<br>Time 25°C (t25°C) to Peak Temperature|3°C/sec maximum<br>100°C<br>150°C<br>60 sec to 120 sec<br>3°C/sec maximum<br>183°C<br>60 sec to 150 sec<br>240°C +0°C/−5°C<br>10 sec to 30 sec<br>6°C/sec maximum<br>6 minutes maximum|3°C/sec maximum<br>150°C<br>200°C<br>60 sec to 180 sec<br>3°C/sec maximum<br>217°C<br>60 sec to 150 sec<br>260°C +0°C/−5°C<br>20 sec to 40 sec<br>6°C/sec maximum<br>8 minutes maximum| 1 Based on JEDEC Standard J-STD-020D.1. 2 For best results, the soldering profile should be in accordance with the recommendations of the manufacturer of the solder paste used. Rev. B | Page 5 of 32 **ADXL375** **Data Sheet** ## **PIN CONFIGURATION AND FUNCTION DESCRIPTIONS** **==> picture [40 x 21] intentionally omitted <==** **----- Start of picture text -----**<br> ADXL375<br>TOP VIEW<br>(Not to Scale)<br>**----- End of picture text -----**<br> **==> picture [162 x 128] intentionally omitted <==** **----- Start of picture text -----**<br> SCL/SCLK<br>VDD I/O 1 14 13 SDA/SDI/SDIO<br>GND 2 12 SDO/ALT ADDRESS<br>RESERVED 3 11 RESERVED<br>+X<br>GND 4 +Y 10 NC<br>+Z<br>GND 5 9 INT2<br>VS 6 7 8 INT1<br>CS<br>**----- End of picture text -----**<br> ## **NOTES** **1. NC = NOT INTERNALLY CONNECTED.** _Figure 3. Pin Configuration_ **Table 5. Pin Function Descriptions** |**Pin No.**|**Mnemonic**|**Description**| |---|---|---| |1<br>2<br>3<br>4<br>5<br>6<br>7<br>8<br>9<br>10<br>11<br>12<br>13<br>14|VDD I/O<br>GND<br>RESERVED<br>GND<br>GND<br>VS<br>CS<br>INT1<br>INT2<br>NC<br>RESERVED<br>SDO/ALT ADDRESS<br>SDA/SDI/SDIO<br>SCL/SCLK|Digital Interface Supply Voltage.<br>Ground. This pin must be connected to ground.<br>Reserved. This pin must be connected to VSor left open.<br>Ground. This pin must be connected to ground.<br>Ground. This pin must be connected to ground.<br>Supply Voltage.<br>Chip Select.<br>Interrupt 1 Output.<br>Interrupt 2 Output.<br>Not Internally Connected.<br>Reserved. This pin must be connected to ground or left open.<br>SPI 4-Wire Serial Data Output (SDO)/I2C Alternate Address Select (ALT ADDRESS).<br>I2C Serial Data (SDA)/SPI 4-Wire Serial Data Input (SDI)/SPI 3-Wire Serial Data Input and Output (SDIO).<br>I2C Serial Communications Clock (SCL)/SPI Serial Communications Clock (SCLK).| Rev. B | Page 6 of 32 **Data Sheet** **ADXL375** ## **TYPICAL PERFORMANCE CHARACTERISTICS** **==> picture [210 x 600] intentionally omitted <==** **----- Start of picture text -----**<br> 25<br>20<br>15<br>10<br>5<br>0<br>OFFSET ( g )<br>Figure 4. X-Axis Zero g Offset at 25°C, VS = 2.5 V<br>25<br>20<br>15<br>10<br>5<br>0<br>OFFSET ( g )<br>Figure 5. Y-Axis Zero g Offset at 25°C, VS = 2.5 V<br>16<br>14<br>12<br>10<br>8<br>6<br>4<br>2<br>0<br>OFFSET ( g )<br>PERCENT OF POPULATION (%)<br>11669-200<br>–3.0 –2.6 –2.2 –1.8 –1.4 –1.0 –0.6 –0.2 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0<br>PERCENT OF POPULATION (%)<br>11669-201<br>–3.0 –2.6 –2.2 –1.8 –1.4 –1.0 –0.6 –0.2 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0<br>PERCENT OF POPULATION (%)<br>11669-202<br>–3.0 –2.6 –2.2 –1.8 –1.4 –1.0 –0.6 –0.2 0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0<br>**----- End of picture text -----**<br> _Figure 6. Z-Axis Zero_ g _Offset at 25°C, VS = 2.5 V_ **==> picture [212 x 593] intentionally omitted <==** **----- Start of picture text -----**<br> 1.0<br>0.8<br>0.6<br>0.4<br>0.2<br>0<br>–0.2<br>–0.4<br>–0.6<br>–0.8<br>–1.0<br>–50 –35 –20 –5 10 25 40 55 70 85 100<br>TEMPERATURE (°C)<br>Figure 7. X-Axis Offset Drift, 15 Parts Soldered to PCB, VS = 2.5 V<br>1.0<br>0.8<br>0.6<br>0.4<br>0.2<br>0<br>–0.2<br>–0.4<br>–0.6<br>–0.8<br>–1.0<br>–50 –35 –20 –5 10 25 40 55 70 85 100<br>TEMPERATURE (°C)<br>Figure 8. Y-Axis Offset Drift, 15 Parts Soldered to PCB, VS = 2.5 V<br>1.0<br>0.8<br>0.6<br>0.4<br>0.2<br>0<br>–0.2<br>–0.4<br>–0.6<br>–0.8<br>–1.0<br>–50 –35 –20 –5 10 25 40 55 70 85 100<br>TEMPERATURE (°C)<br>) g<br>OFFSET DRIFT (<br>11669-203<br>) g<br>OFFSET DRIFT (<br>11669-204<br>) g<br>OFFSET DRIFT (<br>11669-205<br>**----- End of picture text -----**<br> _Figure 9. Z-Axis Offset Drift, 15 Parts Soldered to PCB, VS = 2.5 V_ Rev. B | Page 7 of 32 **ADXL375** **Data Sheet** **==> picture [209 x 178] intentionally omitted <==** **----- Start of picture text -----**<br> 25<br>20<br>15<br>10<br>5<br>0<br>SENSITIVITY (LSB/ g )<br>PERCENT OF POPULATION (%)<br>11669-206<br>18.0 18.2 18.4 18.6 18.8 19.0 19.2 19.4 19.6 19.8 20.0 20.2 20.4 20.6 20.8 21.0 21.2 21.4 21.6 21.8 22.0 22.2 22.4 22.6 22.8 23.0<br>**----- End of picture text -----**<br> _Figure 10. X-Axis Sensitivity at 25°C, VS = 2.5 V_ **==> picture [209 x 397] intentionally omitted <==** **----- Start of picture text -----**<br> 25<br>20<br>15<br>10<br>5<br>0<br>SENSITIVITY (LSB/ g )<br>Figure 11. Y-Axis Sensitivity at 25°C, VS = 2.5 V<br>16<br>14<br>12<br>10<br>8<br>6<br>4<br>2<br>0<br>SENSITIVITY (LSB/ g )<br>PERCENT OF POPULATION (%)<br>11669-207<br>18.0 18.2 18.4 18.6 18.8 19.0 19.2 19.4 19.6 19.8 20.0 20.2 20.4 20.6 20.8 21.0 21.2 21.4 21.6 21.8 22.0 22.2 22.4 22.6 22.8 23.0<br>PERCENT OF POPULATION (%)<br>11669-208<br>18.0 18.2 18.4 18.6 18.8 19.0 19.2 19.4 19.6 19.8 20.0 20.2 20.4 20.6 20.8 21.0 21.2 21.4 21.6 21.8 22.0 22.2 22.4 22.6 22.8 23.0<br>**----- End of picture text -----**<br> _Figure 12. Z-Axis Sensitivity at 25°C, VS = 2.5 V_ **==> picture [214 x 603] intentionally omitted <==** **----- Start of picture text -----**<br> 23.0<br>22.5<br>22.0<br>21.5<br>21.0<br>20.5<br>20.0<br>19.5<br>19.0<br>18.5<br>18.0<br>–50 –35 –20 –5 10 25 40 55 70 85 100<br>TEMPERATURE (°C)<br>Figure 13. X-Axis Sensitivity vs. Temperature, 16 Parts Soldered to PCB,<br>VS = 2.5 V S = 2.5 V = 2.5 V<br>23.0<br>22.5<br>22.0<br>21.5<br>21.0<br>20.5<br>20.0<br>19.5<br>19.0<br>18.5<br>18.0<br>–50 –35 –20 –5 10 25 40 55 70 85 100<br>TEMPERATURE (°C)<br>Figure 14. Y-Axis Sensitivity vs. Temperature, 16 Parts Soldered to PCB,<br>VS = 2.5 V S = 2.5 V = 2.5 V<br>23.0<br>22.5<br>22.0<br>21.5<br>21.0<br>20.5<br>20.0<br>19.5<br>19.0<br>18.5<br>18.0<br>–50 –35 –20 –5 10 25 40 55 70 85 100<br>TEMPERATURE (°C)<br>) g<br>SENSITIVITY (LSB/<br>11669-209<br>) g<br>SENSITIVITY (LSB/<br>11669-210<br>) g<br>SENSITIVITY (LSB/<br>11669-211<br>**----- End of picture text -----**<br> _Figure 13. X-Axis Sensitivity vs. Temperature, 16 Parts Soldered to PCB, VS = 2.5 V S = 2.5 V = 2.5 V_ _Figure 14. Y-Axis Sensitivity vs. Temperature, 16 Parts Soldered to PCB, VS = 2.5 V S = 2.5 V = 2.5 V_ _Figure 15. Z-Axis Sensitivity vs. Temperature, 16 Parts Soldered to PCB, VS = 2.5 V_ Rev. B | Page 8 of 32 **Data Sheet** **ADXL375** **==> picture [208 x 162] intentionally omitted <==** **----- Start of picture text -----**<br> 25<br>20<br>15<br>10<br>5<br>0<br>PERCENT OF POPULATION (%)<br>11669-212<br>80 85 90 95 100 105 110 115 120 125 130 135 140 145 150 155 160 165 170 175 180<br>**----- End of picture text -----**<br> **==> picture [217 x 169] intentionally omitted <==** **----- Start of picture text -----**<br> 200<br>150<br>100<br>50<br>0<br>2.0 2.4 2.8 3.2 3.6<br>SUPPLY VOLTAGE (V)<br>SUPPLY CURRENT (µA)<br>11669-215<br>**----- End of picture text -----**<br> **==> picture [86 x 7] intentionally omitted <==** **----- Start of picture text -----**<br> SELF-TEST RESPONSE (LSB)<br>**----- End of picture text -----**<br> _Figure 16. Z-Axis Self-Test Response at 25°C, VS = 2.5 V_ _Figure 19. Supply Current vs. Supply Voltage (VS) at 25°C_ **==> picture [491 x 375] intentionally omitted <==** **----- Start of picture text -----**<br> 25 200<br>X-AXIS, DUT1<br>20 X-AXIS, DUT2<br>150 Y-AXIS, DUT1<br>Y-AXIS, DUT2<br>Z-AXIS, DUT1<br>15 Z-AXIS, DUT2<br>100<br>10<br>50<br>5<br>0<br>0<br>100 110 120 130 140 150 160 170 180 190 200 0 50 100 150 200<br>CURRENT CONSUMPTION (µA) REFERENCE ACCELERATION ( g )<br>Figure 17. Current Consumption at 25°C, 100 Hz Output Data Rate, VS = 2.5 V S = 2.5 V = 2.5 V Figure 20. Output Linearity over the Dynamic Range<br>160 1.2<br>140<br>1.0<br>X-AXIS<br>120 Y-AXIS<br>Z-AXIS<br>0.8<br>100<br>80 0.6<br>60<br>0.4<br>40<br>20 0.2<br>0<br>0<br>1.60 3.12 6.25 12.50 25 50 100 200 400 800 1600 3200 10 100 1000<br>OUTPUT DATA RATE (Hz) FREQUENCY (Hz)<br>) g<br>OUTPUT (<br> PERCENT OF POPULATION (%)<br>11669-213 11669-216<br>NORMALIZED SENSITIVITY<br>CURRENT CONSUMPTION (µA)<br>11669-214 11669-217<br>**----- End of picture text -----**<br> _Figure 17. Current Consumption at 25°C, 100 Hz Output Data Rate, VS = 2.5 V S = 2.5 V = 2.5 V_ _Figure 21. Frequency Response_ _Figure 18. Current Consumption vs. Output Data Rate at 25°C, 10 Parts Soldered to PCB, VS = 2.5 V_ Rev. B | Page 9 of 32 **Data Sheet** ## **ADXL375** ## **THEORY OF OPERATION** The ADXL375 is a complete 3-axis acceleration measurement system with a measurement range of ±200 _g_ . It measures both dynamic acceleration resulting from motion or shock and static acceleration, such as gravity. The sensor is a polysilicon surface-micromachined structure built on top of a silicon wafer. Polysilicon springs suspend the structure over the surface of the wafer and provide resistance against forces due to applied acceleration. Deflection of the structure is measured using differential capacitors that consist of independent fixed plates and plates attached to the moving mass. Acceleration deflects the proof mass and unbalances the differential capacitor, resulting in a sensor output whose amplitude is proportional to acceleration. Phase sensitive demodulation is used to determine the magnitude and polarity of the acceleration. ## **POWER SEQUENCING** Power can be applied to VS or VDD I/O in any sequence without damaging the ADXL375. Table 7 provides a description of all the power modes. The interface voltage level is set using the interface supply voltage, VDD I/O, which must be present to ensure that the ADXL375 does not create a conflict on the communication bus. For single-supply operation, VDD I/O can be the same as the main supply, VS. In a dual-supply application, however, VDD I/O can differ from VS to accommodate the desired interface voltage, as long as VS is greater than or equal to VDD I/O. After VS is applied, the device enters standby mode. In standby mode, power consumption is minimized; the device waits for VDD I/O to be applied and for the command to enter measurement mode. This command can be initiated by setting the measure bit (Bit D3) in the POWER_CTL register (Address 0x2D). When the device is in standby mode, any register can be written to or read from. It is recommended that the device be configured in standby mode before enabling measurement mode. Clearing the measure bit returns the device to standby mode. ## **CURRENT CONSUMPTION AND OUTPUT DATA RATE** The ADXL375 automatically modulates its current consumption in proportion to its output data rate (see Table 6). The device bandwidth and output data rate are specified using the rate bits (Bits[D3:D0]) in the BW_RATE register (Address 0x2C). **Table 6. Typical Current Consumption vs. Data Rate (TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)** |**(TA = 25C, V**|**S = 2.5 V, VDD I/O**|**= 1.8 V)**|| |---|---|---|---| |**Rate Bits**|**Output Data**<br>**Rate (Hz)**|**Bandwidth**<br>**(Hz)**|**IDD (µA)**| |1111<br>1110<br>1101<br>1100<br>1011<br>1010<br>1001<br>1000<br>0111<br>0110<br>0101<br>0100<br>0011<br>0010<br>0001<br>0000|3200<br>1600<br>800<br>400<br>200<br>100<br>50<br>25<br>12.5<br>6.25<br>3.13<br>1.56<br>0.78<br>0.39<br>0.20<br>0.10|1600<br>800<br>400<br>200<br>100<br>50<br>25<br>12.5<br>6.25<br>3.13<br>1.56<br>0.78<br>0.39<br>0.20<br>0.10<br>0.05|145<br>90<br>140<br>140<br>140<br>140<br>90<br>60<br>50<br>40<br>35<br>35<br>35<br>35<br>35<br>35| **Table 7. Power Modes** |**Table 7. Power Modes**|||| |---|---|---|---| |**Power Mode**|**VS**|**VDD I/O**|**Description**| |Power Off<br>Bus Disabled<br>Bus Enabled<br>Standby or Measurement|Off<br>On<br>Off<br>On|Off<br>Off<br>On<br>On|The device is completely off, but it is still possible for the device to create a conflict on the<br>communication bus.<br>The device is on in standby mode, but communication is unavailable and the device can create<br>a conflict on the communication bus. Minimize the duration of the bus disabled state during<br>power-up to prevent a conflict on the communication bus.<br>No functions are available, but the device does not create a conflict on the communication bus.<br>At power-up, the device is in standby mode, awaiting a command to enter measurement<br>mode, and all sensor functions are off. After the device is instructed to enter measurement<br>mode, all sensor functions are available.| Rev. B | Page 10 of 32 **Data Sheet** **ADXL375** ## **POWER SAVING MODES** ## _**Low Power Mode**_ A low power mode is available for additional power savings. In low power mode, the internal sampling rate is reduced, allowing for power savings in the 12.5 Hz to 400 Hz data rate range at the expense of slightly greater noise. To enter low power mode, set the LOW_POWER bit (Bit D4) in the BW_RATE register (Address 0x2C). Table 8 shows the current consumption in low power mode for output data rates where there is an advantage to using low power mode. **Table 8. Typical Current Consumption vs. Data Rate, Low Power Mode (TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)** |**Rate Bits**|**Output Data**<br>**Rate (Hz)**|**Bandwidth**<br>**(Hz)**|**IDD (µA)**| |---|---|---|---| |1100<br>1011<br>1010<br>1001<br>1000<br>0111|400<br>200<br>100<br>50<br>25<br>12.5|200<br>100<br>50<br>25<br>12.5<br>6.25|90<br>60<br>50<br>45<br>40<br>35| For data rates not shown in Table 8, the use of low power mode does not provide any advantage over normal power mode. Therefore, it is recommended that low power mode be used only for the data rates shown in Table 8. ## _**Autosleep Mode**_ Additional power can be saved if the ADXL375 automatically switches to sleep mode during periods of inactivity. To enable the autosleep mode feature, 1. Set the THRESH_INACT register (Address 0x25) and the TIME_INACT register (Address 0x26) to values that signify inactivity. The appropriate values depend on the application. 2. Set the AUTO_SLEEP bit (Bit D4) and the link bit (Bit D5) in the POWER_CTL register (Address 0x2D). Current consumption at the sub-12.5 Hz data rates that are used in autosleep mode is typically 35 µA for VS = 2.5 V. For information about the advantages of using low power mode vs. autosleep mode, see the Sleep Mode vs. Low Power Mode section. ## _**Standby Mode**_ For even lower power operation, standby mode can be used. In standby mode, current consumption is reduced to 0.1 µA (typical). In this mode, no measurements are made, but the contents of the FIFO buffer are preserved. To enter standby mode, clear the measure bit (Bit D3) in the POWER_CTL register (Address 0x2D). ## **FIFO BUFFER** The ADXL375 contains patented technology for an embedded memory management system with a 32-level FIFO buffer that can be used to minimize host processor burden. This buffer has four modes: bypass, FIFO, stream, and trigger. Each mode can be selected by setting the FIFO_MODE bits (Bits[D7:D6]) in the FIFO_CTL register (Address 0x38; see Table 9). **Table 9. FIFO Modes (FIFO_CTL Register, Address 0x38)** |**Setting**|**Setting**|**FIFO**<br>**Mode**|**Description**| |---|---|---|---| |**D7**|**D6**||| |0<br>0<br>1<br>1|0<br>1<br>0<br>1|Bypass<br>FIFO<br>Stream<br>Trigger|FIFO buffer is bypassed.<br>FIFO buffer collects up to 32 samples and<br>then stops collecting data, collecting new<br>data only when the buffer is not full.<br>FIFO buffer holds the last 32 samples.<br>When the buffer is full, the oldest data<br>is overwritten with newer data.<br>FIFO buffer holds the last samples before<br>the trigger event and continues to collect<br>data until full. New data is collected only<br>when the buffer is not full.| For an in-depth description of the FIFO buffer and FIFO modes, see the AN-1025 Application Note, _Utilization of the First In, First Out (FIFO) Buffer in Analog Devices, Inc., Digital Accelerometers_ . ## _**Bypass Mode**_ In bypass mode, the FIFO buffer is not operational and, therefore, remains empty. ## _**FIFO Mode**_ In FIFO mode, data from measurements of the x-, y-, and z-axes is stored in the FIFO buffer. When the number of samples in the FIFO buffer equals the level specified by the samples bits of the FIFO_CTL register (Address 0x38), the watermark interrupt is set (see the Watermark Bit section). The FIFO buffer continues to accumulate samples until it is full (32 samples from measurements of the x-, y-, and z-axes) and then stops collecting data. After the FIFO buffer stops collecting data, the device continues to operate; therefore, features such as shock detection can be used after the FIFO buffer is full. The watermark interrupt bit remains set until the number of samples in the FIFO buffer is less than the value stored in the samples bits of the FIFO_CTL register. ## _**Stream Mode**_ In stream mode, data from measurements of the x-, y-, and z-axes is stored in the FIFO buffer. When the number of samples in the FIFO buffer equals the level specified by the samples bits of the FIFO_CTL register (Address 0x38), the watermark interrupt is set (see the Watermark Bit section). The FIFO buffer continues to accumulate samples; the buffer stores the latest 32 samples from measurements of the x-, y-, and z-axes, discarding older data as new data arrives. The watermark interrupt bit remains set until the number of samples in the FIFO buffer is less than the value stored in the samples bits of the FIFO_CTL register. Rev. B | Page 11 of 32 ## **ADXL375** ## _**Trigger Mode**_ In trigger mode, the FIFO buffer accumulates samples, storing the latest 32 samples from measurements of the x-, y-, and z-axes. After a trigger event occurs, an interrupt is sent to the INT1 or INT2 pin (determined by the trigger bit in the FIFO_CTL register), and the FIFO_TRIG bit (Bit D7) is set in the FIFO_STATUS register (Address 0x39). The FIFO buffer keeps the last n samples (n is the value specified by the samples bits in the FIFO_CTL register) and then operates in FIFO mode, collecting new samples only when the FIFO buffer is not full. A delay of at least 5 µs must elapse between the occurrence of the trigger event and the start of data readback from the FIFO buffer to allow the buffer to discard and retain the necessary samples. Additional trigger events cannot be recognized until the part is reset to trigger mode. To reset the part to trigger mode, 1. If desired, read data from the FIFO buffer (see the Retrieving Data from the FIFO Buffer section). Before resetting the part to trigger mode, read back the FIFO data; placing the device into bypass mode clears the FIFO buffer. 2. Configure the device for bypass mode by setting Bits[D7:D6] at Address 0x38 to 00. 3. Configure the device for trigger mode by setting Bits[D7:D6] at Address 0x38 to 11. ## _**Retrieving Data from the FIFO Buffer**_ When the FIFO buffer operates in FIFO, stream, or trigger mode, FIFO data can be read from the data registers (Address 0x32 to Address 0x37). Each time data is read from the FIFO buffer, the oldest x-, y-, and z-axis data is moved into the DATAX, DATAY, and DATAZ registers. If a single-byte read operation is performed, the remaining bytes of data for the current FIFO sample are lost. Therefore, data for all axes of interest must be read in a burst (multiple-byte) read operation. To ensure that the FIFO buffer is empty (that is, all new data has moved into the data registers), an interval of at least 5 µs must elapse between the end of the readback from the data registers and the start of a new read of the data registers or the FIFO_STATUS register (Address 0x39). The end of a read operation from the data registers is signified by the transition from Register 0x37 to Register 0x38 or by the CS pin going high. ## **Data Sheet** When SPI operation is enabled at a frequency of 1.6 MHz or lower, the register addressing portion of the transmission provides a sufficient delay to ensure that the FIFO buffer has completely emptied. When SPI operation is enabled at a frequency higher than 1.6 MHz, the CS pin must be deasserted to ensure a total delay of 5 µs; otherwise, the delay is not sufficient. When SPI operation is enabled at 5 MHz, the total delay necessary is at most 3.4 µs. When I[2] C mode is enabled on the part, the communication rate is low enough to ensure a sufficient delay between FIFO reads. ## **SELF-TEST** The ADXL375 incorporates a self-test feature that effectively tests its mechanical and electronic systems simultaneously. When the self-test function is enabled (via the SELF_TEST bit in the DATA_FORMAT register, Address 0x31), an electrostatic force is exerted on the mechanical sensor. This electrostatic force moves the mechanical sensing element in the same manner as acceleration, and it is additive to the external acceleration experienced by the device. This added electrostatic force results in an output change in the x-, y-, and z-axes. Because the electrostatic force is proportional to VS[2] , the output change varies with VS. The self-test response in the x- and y-axes exhibits bimodal behavior and, therefore, is not always a reliable indicator of sensor health or potential shift in device sensitivity. For this reason, perform the self-test check in the z-axis. Use of the self-test feature at data rates of less than 100 Hz or at 1600 Hz may yield values outside the limits shown in Figure 16. For the self-test function to operate correctly, the part must be in normal power operation (LOW_POWER bit = 0 in the BW_RATE register, Address 0x2C) and be configured for a data rate from 100 Hz to 800 Hz, or for a data rate of 3200 Hz (see Table 6). For more information about the self-test feature, see the Using Self-Test section. Rev. B | Page 12 of 32 **Data Sheet** **ADXL375** ## **INTERRUPTS** The ADXL375 provides two output pins for driving interrupts: INT1 and INT2. Both interrupt pins are push-pull, low impedance pins (see Table 10 for output specifications). The default configuration of the interrupt pins is active high. The polarity can be changed to active low by setting the INT_INVERT bit (Bit D5) in the DATA_FORMAT register (Address 0x31). All interrupt functions can be enabled simultaneously, but some functions may need to share the same interrupt pin. ## **BITS IN THE INTERRUPT REGISTERS** This section describes the interrupts that can be set in the INT_ENABLE register (Address 0x2E) and monitored in the INT_SOURCE register (Address 0x30). For an in-depth description of the FIFO buffer and the interrupt bits, see the AN-1025 Application Note, _Utilization of the First In, First Out (FIFO) Buffer in Analog Devices, Inc., Digital Accelerometers_ . ## **ENABLING AND DISABLING INTERRUPTS** ## _**DATA_READY Bit**_ Interrupts are enabled by setting the appropriate bits in the INT_ENABLE register (Address 0x2E); the interrupt is mapped to the INT1 pin or the INT2 pin based on the contents of the INT_MAP register (Address 0x2F). When the user configures the interrupt pins for the first time, it is recommended that the functions and interrupt mapping be configured before the interrupts are enabled. When changing the configuration of an interrupt, follow this procedure. 1. Disable the interrupt by clearing the bit corresponding to the function in the INT_ENABLE register. 2. Reconfigure the interrupt function. 3. Reenable the interrupt in the INT_ENABLE register. Configuration of the functions while the interrupts are disabled helps to prevent the accidental generation of an interrupt. ## **CLEARING INTERRUPTS** The interrupt functions are latched and can be cleared as follows: 1. Read the data registers (Address 0x32 to Address 0x37) to clear the data-related interrupts. 2. Read the INT_SOURCE register (Address 0x30) to clear the remaining interrupts. The DATA_READY bit is set when new data is available and is cleared when no new data is available. ## _**SINGLE_SHOCK Bit**_ The SINGLE_SHOCK bit is set when a single acceleration event that is greater than the value in the THRESH_SHOCK register (Address 0x1D) occurs for less time than is specified by the DUR register (Address 0x21). For more information, see the Shock Detection section. ## _**DOUBLE_SHOCK Bit**_ The DOUBLE_SHOCK bit is set when two acceleration events that are greater than the value in the THRESH_SHOCK register (Address 0x1D) occur for less time than is specified by the DUR register (Address 0x21). The second shock event starts after the time specified by the latent register (Address 0x22) but within the time specified by the window register (Address 0x23). For more information, see the Shock Detection section. ## _**Activity Bit**_ The activity bit is set when acceleration greater than the value stored in the THRESH_ACT register (Address 0x24) is experienced on any participating axis. Participating axes are specified by the ACT_INACT_CTL register (Address 0x27). **Table 10. Interrupt Pin Digital Output Specifications** |**Parameter**|**Test Conditions/Comments**|**Limit1**|**Unit**| |---|---|---|---| |||**Min**<br>**Max**|| |DIGITAL OUTPUT<br>Low Level Output Voltage (VOL)<br>High Level Output Voltage (VOH)<br>Low Level Output Current (IOL)<br>High Level Output Current (IOH)|IOL= 300 µA<br>IOH= −150 µA<br>VOL= VOL, MAX<br>VOH= VOH, MIN|0.2 × VDD I/O<br>0.8 × VDD I/O<br>300<br>−150|V<br>V<br>µA<br>µA| |PIN CAPACITANCE|fIN= 1 MHz, VS= 2.5 V|8|pF| |RISE/FALL TIME<br>Rise Time (tR)2<br>Fall Time (tF)3|CLOAD= 150 pF|210<br>150|ns<br>ns| - 1 Limits based on characterization results; not production tested. - 2 Rise time is measured as the transition time from VOL, MAX to VOH, MIN of the interrupt pin. - 3 Fall time is measured as the transition time from VOH, MIN to VOL, MAX of the interrupt pin. Rev. B | Page 13 of 32 **Data Sheet** ## **ADXL375** ## _**Inactivity Bit**_ The inactivity bit is set when acceleration less than the value stored in the THRESH_INACT register (Address 0x25) is experienced for more time than is specified by the TIME_INACT register (Address 0x26) on all participating axes. Participating axes are specified by the ACT_INACT_CTL register (Address 0x27). The maximum value for TIME_INACT is 255 sec. ## _**Watermark Bit**_ The watermark bit is set when the number of samples in the FIFO buffer equals the value stored in the samples bits (Bits[D4:D0]) of the FIFO_CTL register (Address 0x38). The watermark bit is cleared automatically when the FIFO buffer is read and the FIFO contents return to a value below the value specified by the samples bits. ## _**Overrun Bit**_ The overrun bit is set when new data replaces unread data. The precise operation of the overrun function depends on the FIFO mode (see the FIFO Buffer section). - In bypass mode, the overrun bit is set when new data replaces unread data in the data registers (Address 0x32 to Address 0x37). - In FIFO mode, stream mode, and trigger mode, the overrun bit is set when the FIFO buffer is full. The overrun bit is automatically cleared when the FIFO buffer contents are read. Rev. B | Page 14 of 32 **Data Sheet** **ADXL375** ## **SERIAL COMMUNICATIONS** The ADXL375 supports I[2] C and SPI digital communications. In both cases, the ADXL375 operates as a slave device. When the CS pin is tied high to VDD I/O, I[2] C mode is enabled. The CS pin must be tied high to VDD I/O or be driven by an external controller. If the CS pin is left unconnected, the user may not be able to communicate with the part. In SPI mode, the CS pin is controlled by the bus master. In both SPI and I[2] C modes of operation, ignore data transmitted from the ADXL375 to the master device during writes to the ADXL375. ## **SPI MODE** The ADXL375 can be configured for 3-wire SPI mode or 4-wire SPI mode, as shown in Figure 22 and Figure 23. Clearing the SPI bit (Bit D6) in the DATA_FORMAT register (Address 0x31) selects 4-wire mode; setting the SPI bit selects 3-wire mode. The maximum SPI clock speed is 5 MHz with 100 pF maximum loading. The timing scheme requires clock polarity (CPOL) = 1 and clock phase (CPHA) = 1. If power is applied to the ADXL375 before the clock polarity and phase of the host processor are configured, take the CS pin high before changing the clock polarity and phase. When using 3-wire SPI mode, it is recommended that the SDO pin be either pulled up to VDD I/O or pulled down to GND via a 10 kΩ resistor. **==> picture [139 x 161] intentionally omitted <==** **----- Start of picture text -----**<br> ADXL375 PROCESSOR<br>CS D OUT<br>SDIO D IN/OUT<br>SDO<br>SCLK D OUT<br>Figure 22. 3-Wire SPI Connection Diagram<br>ADXL375 PROCESSOR<br>CS D OUT<br>SDI D OUT<br>SDO D IN<br>SCLK D OUT<br>11669-004<br>11669-003<br>**----- End of picture text -----**<br> _Figure 23. 4-Wire SPI Connection Diagram_ CS is the serial port enable line and is controlled by the SPI master. This line must go low at the start of a transmission and high at the end of a transmission, as shown in Figure 25 to Figure 27. SCLK is the serial port clock and is supplied by the SPI master. SCLK should idle high during a period of no transmission. In 4-wire SPI mode, SDI and SDO are the serial data input and output, respectively. In 3-wire SPI mode, SDIO functions as both the serial data input and output. Data is updated on the falling edge of SCLK and should be sampled on the rising edge of SCLK. To read or write multiple bytes in a single transmission, the multiple-byte bit (MB in Figure 25 to Figure 27), located after the R/W bit in the first byte transfer, must be set. After the register address byte and the first byte of data, each subsequent set of eight clock pulses causes the ADXL375 to point to the next register for a read or write. This shifting continues until the clock pulses cease and CS is deasserted. To perform reads or writes on different, nonsequential registers, CS must be deasserted between transmissions and the new register must be addressed separately. Figure 25 and Figure 26 show the timing diagrams for 4-wire SPI writes and reads, respectively. Figure 27 shows the timing diagram for 3-wire SPI reads or writes. For correct operation of the part, the logic thresholds and timing parameters in Table 11 and Table 12 must be met at all times. Use of the 3200 Hz and 1600 Hz output data rates is recommended only with SPI communication speeds greater than or equal to 2 MHz. The 800 Hz output data rate is recommended only with communication speeds greater than or equal to 400 kHz, and the remaining data rates scale proportionally. For example, the minimum recommended communication speed for a 200 Hz output data rate is 100 kHz. Operation at an output data rate above the recommended maximum value may result in undesirable effects on the acceleration data, including missing samples or additional noise. ## _**Preventing Bus Traffic Errors**_ The ADXL375 CS pin is used both for initiating SPI transactions and for enabling I[2] C mode. When the ADXL375 is used on a SPI bus with multiple devices, its CS pin is held high while the master communicates with the other devices. There may be conditions where a SPI command transmitted to another device looks like a valid I[2] C command. In this case, the ADXL375 interprets this command as an attempt to communicate in I[2] C mode and may interfere with other bus traffic. Unless bus traffic can be adequately controlled to ensure that such a condition never occurs, it is recommended that a logic gate be added in front of Pin 13 (SDA/SDI/SDIO), as shown in Figure 24. This OR gate holds the SDA line high when CS is high to prevent SPI bus traffic at the ADXL375 from appearing as an I[2] C start command. **==> picture [145 x 66] intentionally omitted <==** **----- Start of picture text -----**<br> ADXL375 PROCESSOR<br>CS D OUT<br>SDA/SDI/SDIO D IN/OUT<br>SDO D IN<br>SCLK D OUT<br>11669-104<br>**----- End of picture text -----**<br> _Figure 24. Recommended SPI Connection Diagram When Using Multiple SPI Devices on a Single Bus_ Rev. B | Page 15 of 32 **Data Sheet** ## **ADXL375** **==> picture [499 x 480] intentionally omitted <==** **----- Start of picture text -----**<br> CS<br>tDELAY tSCLK tM tS tQUIET tCS, DIS<br>SCLK<br>tHOLD<br>tSETUP<br>SDI W MB A5 A0 D7 D0<br>tSDO ADDRESS BITS DATA BITS tDIS<br>SDO X X X X X X<br>Figure 25. SPI 4-Wire Write Timing Diagram<br>CS<br>tDELAY tSCLK tM tS tQUIET tCS, DIS<br>SCLK<br>tHOLD<br>tSETUP<br>SDI R MB A5 A0 X X<br>tSDO ADDRESS BITS tDIS<br>SDO X X X X D7 D0<br>DATA BITS<br>Figure 26. SPI 4-Wire Read Timing Diagram<br>CS<br>tDELAY tSCLK tM tS tQUIET tCS, DIS<br>SCLK<br>tHOLD<br>tSETUP tSDO<br>SDIO R/W MB A5 A0 D7 D0<br>ADDRESS BITS DATA BITS<br>NOTES<br>1. tSDO IS ONLY PRESENT DURING READS.<br>11669-017<br>11669-018<br>11669-019<br>**----- End of picture text -----**<br> _Figure 27. SPI 3-Wire Read/Write Timing Diagram_ Rev. B | Page 16 of 32 **Data Sheet** **ADXL375** **Table 11. SPI Digital Input/Output Specifications** |**Parameter**|**Test Conditions/Comments**|**Limit1**|**Unit**| |---|---|---|---| |||**Min**<br>**Max**|| |DIGITAL INPUT<br>Low Level Input Voltage (VIL)<br>High Level Input Voltage (VIH)<br>Low Level Input Current (IIL)<br>High Level Input Current (IIH)|VS= VDD I/O<br>VS= 0 V|0.3 × VDD I/O<br>0.7 × VDD I/O<br>0.1<br>−0.1|V<br>V<br>µA<br>µA| |DIGITAL OUTPUT<br>Low Level Output Voltage (VOL)<br>High Level Output Voltage (VOH)<br>Low Level Output Current (IOL)<br>High Level Output Current (IOH)|IOL= 10 mA<br>IOH= −4 mA<br>VOL= VOL, MAX<br>VOH= VOH, MIN|0.2 × VDD I/O<br>0.8 × VDD I/O<br>10<br>−4|V<br>V<br>mA<br>mA| |PIN CAPACITANCE|fIN= 1 MHz, VS= 2.5 V|8|pF| 1 Limits based on characterization results; not production tested. **Table 12. SPI Timing (TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)[1]** |**Table 12. SPI**|**iming (TA = 25C, VS = 2.5**|**V, VDD I/O =**|**.8 V)**| |---|---|---|---| |**Parameter**|**Limit2, 3**|**Unit**|**Description**| ||**Min**<br>**Max**||| |fSCLK<br>tSCLK<br>tDELAY<br>tQUIET<br>tDIS<br>tCS, DIS<br>tS<br>tM<br>tSETUP<br>tHOLD<br>tSDO<br>tR4<br>tF4|5<br>200<br>5<br>5<br>10<br>150<br>0.3 × tSCLK<br>0.3 × tSCLK<br>5<br>5<br>40<br>20<br>20|MHz<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns|SPI clock frequency<br>Mark-space ratio (1/(SPI clock frequency)) for the SCLK input is 40/60 to 60/40<br>CS<br>falling edge to SCLK falling edge<br>SCLK rising edge to CS<br>rising edge<br>CS<br>rising edge to SDO/SDIO disabled<br>CS<br>deassertion between SPI communications<br>SCLK low pulse width (space)<br>SCLK high pulse width (mark)<br>SDI/SDIO valid before SCLK rising edge<br>SDI/SDIO valid after SCLK rising edge<br>SCLK falling edge to SDO/SDIO output transition<br>SDO/SDIO output high to output low transition<br>SDO/SDIO output low to output high transition| 1 The CS, SCLK, SDI, and SDO pins are not internally pulled up or down; they must be driven for proper operation. - 2 Limits based on characterization results, with fSCLK = 5 MHz and bus load capacitance of 100 pF; not production tested. 3 The timing values are referred to the input thresholds (VIL and VIH) given in Table 11. - 4 Output rise and fall times measured with capacitive load of 150 pF. tR and tF are not shown in Figure 25 to Figure 27. Rev. B | Page 17 of 32 **ADXL375** **Data Sheet** ## **I[2] C MODE** When the CS pin is tied high to VDD I/O, the ADXL375 is configured for I[2] C mode. I[2] C mode requires a simple 2-wire connection, as shown in Figure 28. The ADXL375 conforms to the _UM10204 I[2] C-Bus Specification and User Manual_ , Rev. 03— 19 June 2007, available from NXP Semiconductors. The ADXL375 supports standard (100 kHz) and fast (400 kHz) data transfer modes if the bus parameters given in Table 13 and Table 14 are met. Single- or multiple-byte reads and writes are supported, as shown in Figure 29. When the ALT ADDRESS pin (Pin 12) is tied high to VDD I/O, the 7-bit I[2] C address for the device is 0x1D, followed by the R/W bit. In this configuration, the write address is 0x3A, and the read address is 0x3B. An alternate I[2] C address of 0x53 can be selected by grounding the ALT ADDRESS pin (see Figure 28). In this configuration, the write address is 0xA6, and the read address is 0xA7. Unused pins have no internal pull-up or pull-down resistors; therefore, the CS and ALT ADDRESS pins have no known state or default state if the pins are left floating or unconnected. When using I[2] C mode, it is required that the CS pin be connected to VDD I/O and that the ALT ADDRESS pin be connected to either VDD I/O or GND. **==> picture [161 x 99] intentionally omitted <==** **----- Start of picture text -----**<br> VDD I/O<br>ADXL375 RP RP PROCESSOR<br>CS<br>SDA D IN/OUT<br>ALT ADDRESS<br>SCL D OUT 11669-008<br>**----- End of picture text -----**<br> _Figure 28. I[2] C Connection Diagram (Address 0x53)_ Due to communication speed limitations, the maximum output data rate when using 400 kHz I[2] C mode is 800 Hz, which scales linearly with a change in the I[2] C communication speed. For example, using I[2] C mode at 100 kHz limits the maximum ODR to 200 Hz. Operation at an output data rate above the recommended maximum value may result in undesirable effects on the acceleration data, including missing samples or additional noise. If other devices are connected to the same I[2] C bus, the nominal operating voltage level of the other devices cannot exceed VDD I/O by more than 0.3 V. External pull-up resistors, RP, are necessary for proper I[2] C operation (see Figure 28). To ensure proper operation, refer to the _UM10204 I[2] C-Bus Specification and User Manual_ , Rev. 03—19 June 2007, when selecting pull-up resistor values. **==> picture [484 x 141] intentionally omitted <==** **----- Start of picture text -----**<br> SINGLE-BYTE WRITE<br>MASTER START SLAVE ADDRESS + WRITE REGISTER ADDRESS DATA STOP<br>SLAVE ACK ACK ACK<br>MULTIPLE-BYTE WRITE<br>MASTER START SLAVE ADDRESS + WRITE REGISTER ADDRESS DATA DATA STOP<br>SLAVE ACK ACK ACK ACK<br>SINGLE-BYTE READ<br>MASTER START SLAVE ADDRESS + WRITE REGISTER ADDRESS START [1] SLAVE ADDRESS + READ NACK STOP<br>SLAVE ACK ACK ACK DATA<br>MULTIPLE-BYTE READ<br>MASTER START SLAVE ADDRESS + WRITE REGISTER ADDRESS START [1] SLAVE ADDRESS + READ ACK NACK STOP<br>SLAVE ACK ACK ACK DATA DATA<br>1THIS START IS EITHER A REPEATED START OR A STOP FOLLOWED BY A START.<br>NOTES<br>1. THE SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING. 11669-033<br>**----- End of picture text -----**<br> _Figure 29. I[2] C Device Addressing_ **Table 13. I[2] C Digital Input/Output Specifications** |**Parameter**|**Test Conditions/Comments**|**Limit1**|**Unit**| |---|---|---|---| |||**Min**<br>**Max**|| |DIGITAL INPUT<br>Low Level Input Voltage (VIL)<br>High Level Input Voltage (VIH)<br>Low Level Input Current (IIL)<br>High Level Input Current (IIH)|VS= VDD I/O<br>VS= 0 V|0.3 × VDD I/O<br>0.7 × VDD I/O<br>0.1<br>−0.1|V<br>V<br>µA<br>µA| |DIGITAL OUTPUT<br>Low Level Output Voltage (VOL)<br>Low Level Output Current (IOL)|VDD I/O< 2 V, IOL= 3 mA<br>VDD I/O≥ 2 V, IOL= 3 mA<br>VOL= VOL, MAX|0.2 × VDD I/O<br>400<br>3|V<br>mV<br>mA| |PIN CAPACITANCE|fIN= 1 MHz, VS= 2.5 V|8|pF| 1 Limits based on characterization results; not production tested. Rev. B | Page 18 of 32 **Data Sheet** **ADXL375** **Table 14. I[2] C Timing (TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)** |**Table 14. IC **|**iming (TA = 25C, VS = 2.5**|**V, VDD I/O = 1.**|**V)**| |---|---|---|---| |**Parameter**|**Limit1, 2**|**Unit**|**Description**| ||**Min**<br>**Max**||| |fSCL<br>t1<br>t2<br>t3<br>t4<br>t5<br>t63, 4, 5<br>t7<br>t8<br>t9<br>t10<br>t11<br>Cb|400<br>2.5<br>0.6<br>1.3<br>0.6<br>100<br>0<br>0.9<br>0.6<br>0.6<br>1.3<br>300<br>0<br>300<br>250<br>400|kHz<br>μs<br>μs<br>μs<br>μs<br>ns<br>μs<br>μs<br>μs<br>μs<br>ns<br>ns<br>ns<br>ns<br>pF|SCL clock frequency<br>SCL cycle time<br>SCL high time<br>SCL low time<br>Hold time for start/repeated start condition<br>Data setup time<br>Data hold time<br>Setup time for repeated start condition<br>Setup time for stop condition<br>Bus-free time between a stop condition and a start condition<br>Rise time of SCL and SDA when receiving<br>Rise time of SCL and SDA when receiving or transmitting<br>Fall time of SCL and SDA when receiving<br>Fall time of SCL and SDA when transmitting<br>Capacitive load for each bus line| 1 Limits based on characterization results, with fSCL = 400 kHz and a 3 mA sink current; not production tested. 2 The timing values are referred to the input thresholds (VIL and VIH) given in Table 13. 3 t6 is the data hold time that is measured from the falling edge of SCL. It applies to data during the transmission and acknowledge phases. 4 To bridge the undefined region of the falling edge of SCL, a transmitting device must internally provide an output hold time of at least 300 ns for the SDA signal (with respect to VIH, MIN of the SCL signal). 5 The maximum value for t6 must be met only if the device does not stretch the low period (t3) of the SCL signal. The maximum value for t6 is a function of the clock low time (t3), the clock rise time (t10), and the minimum data setup time (t5(MIN)). This value is calculated as t6(MAX) = t3 − t10 − t5(MIN). **==> picture [506 x 108] intentionally omitted <==** **----- Start of picture text -----**<br> SDA<br>t9 t3 t10 t11 t4<br>SCL<br>t4 t6 t2 t5 t7 t1 t8<br>START REPEATED STOP<br>CONDITION START CONDITION<br>CONDITION 11669-034<br>**----- End of picture text -----**<br> _Figure 30. I[2] C Timing Diagram_ Rev. B | Page 19 of 32 **ADXL375** **Data Sheet** ## **REGISTER MAP** All registers in the ADXL375 are eight bits in length. **Table 15. Register Map** |**Table 15. Register Map**|**Table 15. Register Map**||||| |---|---|---|---|---|---| |**Address**||**Register Name**|**Access Type **|**Reset Value**|**Description**| |**Hex**|**Decimal**||||| |0x00<br>0x01 to 0x1C<br>0x1D<br>0x1E<br>0x1F<br>0x20<br>0x21<br>0x22<br>0x23<br>0x24<br>0x25<br>0x26<br>0x27<br>0x2A<br>0x2B<br>0x2C<br>0x2D<br>0x2E<br>0x2F<br>0x30<br>0x31<br>0x32<br>0x33<br>0x34<br>0x35<br>0x36<br>0x37<br>0x38<br>0x39|0<br>1 to 28<br>29<br>30<br>31<br>32<br>33<br>34<br>35<br>36<br>37<br>38<br>39<br>42<br>43<br>44<br>45<br>46<br>47<br>48<br>49<br>50<br>51<br>52<br>53<br>54<br>55<br>56<br>57|DEVID<br>Reserved<br>THRESH_SHOCK<br>OFSX<br>OFSY<br>OFSZ<br>DUR<br>Latent<br>Window<br>THRESH_ACT<br>THRESH_INACT<br>TIME_INACT<br>ACT_INACT_CTL<br>SHOCK_AXES<br>ACT_SHOCK_STATUS<br>BW_RATE<br>POWER_CTL<br>INT_ENABLE<br>INT_MAP<br>INT_SOURCE<br>DATA_FORMAT<br>DATAX0<br>DATAX1<br>DATAY0<br>DATAY1<br>DATAZ0<br>DATAZ1<br>FIFO_CTL<br>FIFO_STATUS|R<br>N/A<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R<br>R/W<br>R/W<br>R/W<br>R/W<br>R<br>R/W<br>R<br>R<br>R<br>R<br>R<br>R<br>R/W<br>R|11100101<br>N/A<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000<br>00001010<br>00000000<br>00000000<br>00000000<br>00000010<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000|Device ID<br>Reserved; do not access<br>Shock threshold<br>X-axis offset<br>Y-axis offset<br>Z-axis offset<br>Shock duration<br>Shock latency<br>Shock window<br>Activity threshold<br>Inactivity threshold<br>Inactivity time<br>Axis enable control for activity and inactivity detection<br>Axis control for single shock/double shock<br>Source of single shock/double shock<br>Data rate and power mode control<br>Power saving features control<br>Interrupt enable control<br>Interrupt mapping control<br>Interrupt source<br>Data format control<br>X-Axis Data 0<br>X-Axis Data 1<br>Y-Axis Data 0<br>Y-Axis Data 1<br>Z-Axis Data 0<br>Z-Axis Data 1<br>FIFO control<br>FIFO status| Rev. B | Page 20 of 32 **Data Sheet** **ADXL375** ## **REGISTER DESCRIPTIONS** All registers in the ADXL375 are eight bits in length. ## _**Register 0x00—DEVID (Read Only)**_ |**D7**|**D6**|**D5**|**D4**|**D3**|**D2**|**D1**|**D0**| |---|---|---|---|---|---|---|---| |1|1|1|0|0|1|0|1| The read-only DEVID register holds the fixed device ID code of 0xE5 (345 octal). ## _**Register 0x1D—THRESH_SHOCK (Read/Write)**_ The THRESH_SHOCK register contains the unsigned threshold value for shock interrupts. The magnitude of the shock event is compared with the value in the THRESH_SHOCK register for shock detection. The scale factor is 780 m _g_ /LSB. A value of 0 may result in undesirable behavior if single shock/double shock interrupts are enabled. ## _**Register 0x1E, Register 0x1F, Register 0x20—OFSX, OFSY, OFSZ (Read/Write)**_ The OFSX, OFSY, and OFSZ registers contain user-configured offset adjustments in twos complement format with a scale factor of 0.196 _g_ /LSB. The value stored in the offset registers is automat-ically added to the acceleration data, and the resulting value is stored in the output data registers (Address 0x32 to Address 0x37). For more information about offset calibration and the use of the offset registers, see the Offset Calibration section. ## _**Register 0x21—DUR (Read/Write)**_ The DUR register contains an unsigned time value representing the maximum time that an event must be above the THRESH_ SHOCK threshold to qualify as a shock event. The scale factor is 625 µs/LSB. A value of 0 disables the single shock and double shock functions. ## _**Register 0x22—Latent (Read/Write)**_ The latent register contains an unsigned time value representing the wait time from the detection of a shock event to the start of the time window (specified by the window register) during which a possible second shock event can be detected. The scale factor is 1.25 ms/LSB. A value of 0 disables the double shock function. ## _**Register 0x23—Window (Read/Write)**_ The window register contains an unsigned time value representing the amount of time after the expiration of the latency time (specified by the latent register) during which a second valid shock can begin. The scale factor is 1.25 ms/LSB. A value of 0 disables the double shock function. ## _**Register 0x24—THRESH_ACT (Read/Write)**_ The THRESH_ACT register contains the unsigned threshold value for detecting activity. The magnitude of the activity event is compared with the value in the THRESH_ACT register. The scale factor is 780 m _g_ /LSB. A value of 0 may result in undesirable behavior if the activity interrupt is enabled. ## _**Register 0x25—THRESH_INACT (Read/Write)**_ The THRESH_INACT register contains the unsigned threshold value for detecting inactivity. The magnitude of the inactivity event is compared with the value in the THRESH_INACT register. The scale factor is 780 m _g_ /LSB. A value of 0 may result in undesirable behavior if the inactivity interrupt is enabled. ## _**Register 0x26—TIME_INACT (Read/Write)**_ The TIME_INACT register contains an unsigned time value representing the amount of time that acceleration must be less than the value in the THRESH_INACT register for inactivity to be detected. The scale factor is 1 sec/LSB. Unlike the other interrupt functions, which use unfiltered output data (see the Threshold Detection and Bandwidth section), the inactivity function uses filtered output data. At least one output sample must be generated for the inactivity interrupt to be triggered. For this reason, the inactivity function may appear to be unresponsive if the TIME_INACT register is set to a value less than the time constant of the output data rate. A value of 0 results in an interrupt when the output data is less than the value in the THRESH_INACT register. The maximum value for TIME_INACT is 255 sec. _**Register 0x27—ACT_INACT_CTL (Read/Write)**_ |**D7**|**D6**|**D5**|**D4**| |---|---|---|---| |ACT AC/DC|ACT_X enable|ACT_Y enable|ACT_Z enable| |**D3**|**D2**|**D1**|**D0**| |INACT AC/DC|INACT_X enable|INACT_Y enable|INACT_Z enable| The ACT_INACT_CTL register selects dc-coupled or ac-coupled operation and selects the axes that participate in activity and inactivity detection. ## **ACT AC/DC and INACT AC/DC Bits** A setting of 0 for the ACT AC/DC and INACT AC/DC bits selects dc-coupled operation; a setting of 1 selects ac-coupled operation. In dc-coupled operation, the current acceleration magnitude is compared directly with the values in the THRESH_ ACT and THRESH_INACT registers to determine whether activity or inactivity is detected. In ac-coupled operation for activity detection, the acceleration value at the start of activity detection is taken as a reference value. New samples of acceleration data are then compared to this reference value and, if the magnitude of the difference exceeds the THRESH_ACT value, an activity interrupt is triggered. Similarly, in ac-coupled operation for inactivity detection, a reference value is used for comparison and is updated whenever the device exceeds the inactivity threshold. After the reference value is selected, the device compares the magnitude of the difference between the reference value and the current acceleration with the THRESH_INACT value. If the difference is less than the value in the THRESH_INACT register for the time specified in the TIME_INACT register, the device is considered inactive, and the inactivity interrupt is triggered. Rev. B | Page 21 of 32 **ADXL375** **Data Sheet** ## **ACT_x Enable and INACT_x Enable Bits** A setting of 1 for the ACT_x enable and INACT_x enable bits enables x-, y-, or z-axis participation in detecting activity or inactivity. A setting of 0 excludes the selected axis from participation. If all axes are excluded, the function is disabled. For activity detection, all participating axes are logically OR’ed, causing the activity function to be triggered when any participating axis exceeds the activity threshold. For inactivity detection, all participating axes are logically AND’ed, causing the inactivity function to be triggered only if all participating axes are below the inactivity threshold for the specified time. ## _**Register 0x2A—SHOCK_AXES (Read/Write)**_ |**D7**|**D6**|**D5**|**D4**| |---|---|---|---| |0|0|0|0| |**D3**|**D2**|**D1**|**D0**| |Suppress|SHOCK_X enable|SHOCK_Y enable|SHOCK_Z enable| The SHOCK_AXES register specifies the participation of each of the three axes in single shock/double shock detection. ## **Suppress Bit** Setting the suppress bit suppresses double shock detection if acceleration greater than the value in the THRESH_SHOCK register is present during the latency time between shocks. For more information, see the Shock Detection section. ## **SHOCK_x Enable Bits** A setting of 1 in the SHOCK_X enable, SHOCK_Y enable, or SHOCK_Z enable bit enables x-, y-, or z-axis participation in shock detection. A setting of 0 excludes the selected axis from participation in shock detection. ## _**Register 0x2B—ACT_SHOCK_STATUS (Read Only)**_ |**D7**|**D6**|**D5**|**D4**| |---|---|---|---| |0|ACT_X source|ACT_Y source|ACT_Z source| |**D3**|**D2**|**D1**|**D0**| |Asleep|SHOCK_X source|SHOCK_Y source|SHOCK_Z source| The read-only ACT_SHOCK_STATUS register indicates the first axis involved in an activity or shock event. ## **ACT_x Source and SHOCK_x Source Bits** The ACT_x source and SHOCK_x source bits indicate the first axis involved in an activity or shock event. A setting of 1 corresponds to involvement in the event; a setting of 0 corresponds to no involvement. When new data is available, these bits are not cleared but are overwritten by the new data. Read the ACT_SHOCK_STATUS register before clearing the interrupt. Disabling an axis from participation in activity or shock events clears the corresponding source bit in this register when the next activity or single shock/double shock event occurs. ## **Asleep Bit** A setting of 1 in the asleep bit indicates that the part is asleep; a setting of 0 indicates that the part is not asleep. This bit toggles only if the device is configured for autosleep. For more information about the autosleep mode, see the AUTO_SLEEP Bit section. ## _**Register 0x2C—BW_RATE (Read/Write)**_ |**D7**|**D6**|**D5**|**D4**|**D3**|**D2**|**D1**|**D0**| |---|---|---|---|---|---|---|---| |0|0|0|LOW_POWER|Rate|||| The BW_RATE register configures the device bandwidth and output data rate; this register also enables and disables low power mode. ## **LOW_POWER Bit** A setting of 0 in the LOW_POWER bit selects normal operation; a setting of 1 selects reduced power operation, which has somewhat higher noise. For more information, see the Low Power Mode section. ## **Rate Bits** The rate bits select the device bandwidth and output data rate (see Table 6 and Table 8). The default value for these bits is 0x0A, which translates to a 100 Hz output data rate. The selected output data rate must be appropriate for the communication protocol and frequency selected. Selecting an output data rate that is too high for the communication speed may result in samples being discarded (for more information, see the Serial Communications section). ## _**Register 0x2D—POWER_CTL (Read/Write)**_ |**D7**|**D6**|**D5**|**D4**|**D3**|**D2**|**D1**|**D0**| |---|---|---|---|---|---|---|---| |0|0|Link|AUTO_SLEEP|Measure|Sleep|Wakeup|| The POWER_CTL register can be used to configure the device for autosleep mode; this register is also used to set the device to measurement mode or standby mode. ## **Link Bit** The link bit serially links the activity and inactivity functions. If both the activity and inactivity functions are enabled, a setting of 1 in the link bit delays the start of the activity detection function until inactivity is detected. After activity is detected, inactivity detection begins, preventing the detection of activity. When this bit is set to 0, the inactivity and activity functions are concurrent. For more information about the link feature, see the Link Mode section. Before clearing the link bit, it is recommended that the part be placed in standby mode (set the measure bit, Bit D3, to 0). After clearing the link bit, reset the part to measurement mode (set the measure bit, Bit D3, to 1). This configuration sequence ensures that the device is properly biased if sleep mode is manually disabled; otherwise, the first few samples of data after the link bit is cleared may have additional noise, especially if the device is asleep when the bit is cleared. Rev. B | Page 22 of 32 **Data Sheet** **ADXL375** ## **AUTO_SLEEP Bit** If the link bit is set, a setting of 1 in the AUTO_SLEEP bit enables the autosleep function. In autosleep mode, the ADXL375 automatically switches to sleep mode if the inactivity function is enabled and inactivity is detected (that is, when acceleration is below the THRESH_INACT value for at least the time specified by the TIME_INACT value). If activity detection is also enabled, the ADXL375 automatically wakes up from sleep after detecting activity and returns to operation at the output data rate set in the BW_RATE register. A setting of 0 in the AUTO_SLEEP bit disables automatic switching to sleep mode. If the link bit is not set, the AUTO_SLEEP feature is disabled and setting the AUTO_SLEEP bit has no effect on device operation. For more information about the link feature, see the Link Bit section and the Link Mode section. For more information about autosleep mode, see the Autosleep Mode section. Before clearing the AUTO_SLEEP bit, it is recommended that the part be placed in standby mode (set the measure bit, Bit D3, to 0). After clearing the AUTO_SLEEP bit, reset the part to measurement mode (set the measure bit, Bit D3, to 1). This configuration sequence ensures that the device is properly biased if sleep mode is manually disabled; otherwise, the first few samples of data after the AUTO_SLEEP bit is cleared may have additional noise, especially if the device is asleep when the bit is cleared. ## **Measure Bit** A setting of 0 in the measure bit places the part into standby mode; a setting of 1 places the part into measurement mode. The ADXL375 powers up in standby mode with minimum power consumption (see the Power Sequencing section). ## **Sleep Bit** A setting of 0 in the sleep bit places the part into the normal mode of operation; a setting of 1 places the part into sleep mode. Sleep mode suppresses the DATA_READY interrupt, stops transmission of data to the FIFO buffer, and switches the sampling rate to the rate specified by the wakeup bits (Bits[D1:D0]). In sleep mode, only the activity function can be used. When the DATA_READY interrupt is suppressed, the output data registers (Register 0x32 to Register 0x37) are still updated at the sampling rate set by the wakeup bits. Before clearing the sleep bit, it is recommended that the part be placed in standby mode (set the measure bit, Bit D3, to 0). After clearing the sleep bit, reset the part to measurement mode (set the measure bit, Bit D3, to 1). ## **Wakeup Bits** The wakeup bits control the sampling rate during sleep mode (see Table 16). **Table 16. Sampling Rate in Sleep Mode** |**Setting**|**Setting**|**Frequency (Hz)**| |---|---|---| |**D1**|**D0**|| |0<br>0<br>1<br>1|0<br>1<br>0<br>1|8<br>4<br>2<br>1| ## _**Register 0x2E—INT_ENABLE (Read/Write)**_ |**D7**|**D6**|**D5**|**D4**| |---|---|---|---| |DATA_READY|SINGLE_SHOCK|DOUBLE_SHOCK|Activity| |**D3**|**D2**|**D1**|**D0**| |Inactivity|0|Watermark|Overrun| A setting of 1 for any bit in the INT_ENABLE register enables the specified function to generate interrupts; a setting of 0 for any bit in this register prevents the function from generating interrupts. The DATA_READY, watermark, and overrun bits enable only the interrupt output; the functions are always enabled. It is recommended that interrupts be configured in Register 0x2F before their outputs are enabled in this register. For more information about the interrupts, see the Bits in the Interrupt Registers section. _**Register 0x2F—INT_MAP (Read/Write)**_ |**D7**|**D6**|**D5**|**D4**| |---|---|---|---| |DATA_READY|SINGLE_SHOCK|DOUBLE_SHOCK|Activity| |**D3**|**D2**|**D1**|**D0**| |Inactivity|0|Watermark|Overrun| A setting of 0 for any bit in the INT_MAP register causes the specified interrupt to be sent to the INT1 pin; a setting of 1 for any bit in this register causes the specified interrupt to be sent to the INT2 pin. All selected interrupts for a given pin are OR’ed. _**Register 0x30—INT_SOURCE (Read Only)**_ |**D7**|**D6**|**D5**|**D4**| |---|---|---|---| |DATA_READY|SINGLE_SHOCK|DOUBLE_SHOCK|Activity| |**D3**|**D2**|**D1**|**D0**| |Inactivity|X1|Watermark|Overrun| 1 X = ignore this bit. A setting of 1 for any bit in the INT_SOURCE register indicates that the specified function has triggered an interrupt; a setting of 0 for any bit in this register indicates that the specified function has not triggered an interrupt. The DATA_READY, watermark, and overrun bits are always set if the corresponding interrupt occurs, regardless of the settings in the INT_ENABLE register; these bits are cleared by reading data from the data registers (Address 0x32 to Address 0x37). The DATA_READY and watermark bits may require multiple reads to be cleared. Other bits, and their corresponding interrupts, are cleared by reading the INT_SOURCE register. Rev. B | Page 23 of 32 **ADXL375** **Data Sheet** ## _**Register 0x31—DATA_FORMAT (Read/Write)**_ |**D7**|**D6**|**D5**|**D4**|**D3**|**D2**|**D1**|**D0**| |---|---|---|---|---|---|---|---| |SELF_TEST|SPI|INT_INVERT|0|1|Justify|1|1| The DATA_FORMAT register controls the presentation of data to Register 0x32 through Register 0x37. ## **SELF_TEST Bit** A setting of 1 in the SELF_TEST bit applies a self-test force to the sensor, causing a shift in the output data. A value of 0 disables the self-test force. For more information about the self-test function, see the Self-Test section and the Using Self-Test section. ## _**Register 0x38—FIFO_CTL (Read/Write)**_ |**D7**|**D6**|**D5**|**D4**|**D3**|**D2**|**D1**|**D0**| |---|---|---|---|---|---|---|---| |FIFO_MODE||Trigger|Samples||||| The FIFO_CTL register is used to configure the FIFO buffer for the device. For more information, see the FIFO Buffer section. For an in-depth description of the FIFO buffer, see the AN-1025 Application Note, _Utilization of the First In, First Out (FIFO) Buffer in Analog Devices, Inc., Digital Accelerometers_ . ## **FIFO_MODE Bits** These bits set the FIFO mode, as described in Table 17. ## **SPI Bit** **Table 17. FIFO Modes** A value of 1 in the SPI bit configures the device for 3-wire SPI mode; a value of 0 configures the device for 4-wire SPI mode. ## **INT_INVERT Bit** A value of 0 in the INT_INVERT bit sets the polarity of the interrupt pins to active high; a value of 1 sets the polarity of the interrupt pins to active low. ## **Justify Bit** A setting of 1 in the justify bit selects left justified (MSB) mode; a setting of 0 selects right justified (LSB) mode with sign extension. ## _**Register 0x32 to Register 0x37—DATAX0, DATAX1, DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only)**_ These six bytes (Register 0x32 to Register 0x37) are each eight bits in length and contain the output data for each axis. - Register 0x32 and Register 0x33 contain the output data for the x-axis. - Register 0x34 and Register 0x35 contain the output data for the y-axis. - Register 0x36 and Register 0x37 contain the output data for the z-axis. The output data is in twos complement format. DATAx0 is the least significant byte, and DATAx1 is the most significant byte (x represents X, Y, or Z). The DATA_FORMAT register (Address 0x31) controls the format of the data. It is recommended that a multiple-byte read of all six registers be performed to prevent a change in data between reads of sequential registers. When using the 3200 Hz or 1600 Hz output data rate, the LSB of the output data-word is always 0. When the data is right justified, the LSB corresponds to Bit D0 of the DATAx0 register; when the data is left justified, the LSB corresponds to Bit D3 of the DATAx0 register. |**Setting**|**Setting**|**FIFO**<br>**Mode**|**Description**| |---|---|---|---| |**D7**|**D6**||| |0<br>0<br>1<br>1|0<br>1<br>0<br>1|Bypass<br>FIFO<br>Stream<br>Trigger|FIFO buffer is bypassed.<br>FIFO buffer collects up to 32 samples and<br>then stops collecting data, collecting new<br>data only when the buffer is not full.<br>FIFO buffer holds the last 32 samples.<br>When the buffer is full, the oldest data<br>is overwritten with newer data.<br>FIFO buffer holds the last samples before<br>the trigger event and continues to collect<br>data until full. New data is collected only<br>when the buffer is not full.| ## **Trigger Bit** A value of 0 in the trigger bit links the trigger event of trigger mode to the INT1 pin, and a value of 1 links the trigger event to the INT2 pin. ## **Samples Bits** The function of the samples bits depends on the FIFO mode selected (see Table 18). Entering a value of 0 in the samples bits immediately sets the watermark bit in the INT_SOURCE register, regardless of the FIFO mode selected. Undesirable operation may occur if a value of 0 is used for the samples bits when trigger mode is used. ## **Table 18. Samples Bits Functions** |**FIFO Mode**|**Samples Bits Function**| |---|---| |Bypass<br>FIFO<br>Stream<br>Trigger|None.<br>Specifies how many FIFO entries are needed to<br>trigger a watermark interrupt.<br>Specifies how many FIFO entries are needed to<br>trigger a watermark interrupt.<br>Specifies how many FIFO samples are retained in<br>the FIFO buffer before a trigger event.| Rev. B | Page 24 of 32 **Data Sheet** **ADXL375** ## _**Register 0x39—FIFO_STATUS (Read Only)**_ |**D7**|**D6**|**D5**|**D4**|**D3**|**D2**|**D1**|**D0**| |---|---|---|---|---|---|---|---| |FIFO_TRIG|0|Entries|||||| The read-only FIFO_STATUS register indicates whether a trigger event has occurred and reports the number of data values stored in the FIFO buffer. ## **FIFO_TRIG Bit** When the FIFO_TRIG bit is set to 1, a trigger event has occurred; when the FIFO_TRIG bit is set to 0, no trigger event has occurred. ## **Entries Bits** The entries bits report how many data values are stored in the FIFO buffer. The data stored in the FIFO buffer is accessed by reading the data registers (Address 0x32 to Address 0x37). FIFO reads must be done in burst mode (multiple-byte mode) because each FIFO level is cleared after any read (single- or multiplebyte) of the FIFO buffer. The FIFO buffer stores a maximum of 32 entries, which equates to a maximum of 33 entries available at any given time because an additional entry is available at the output filter of the device. Rev. B | Page 25 of 32 **Data Sheet** ## **ADXL375** ## **APPLICATIONS INFORMATION POWER SUPPLY DECOUPLING** A 1 µF tantalum capacitor (CS) at VS and a 0.1 µF ceramic capacitor (CI/O) at VDD I/O placed close to the ADXL375 supply pins are recommended to adequately decouple the accelerometer from noise on the power supply. If additional decoupling is necessary, a resistor or ferrite bead (no larger than 100 Ω) in series with VS may be helpful. Additionally, increasing the bypass capacitance on VS to a 10 µF tantalum capacitor in parallel with a 0.1 µF ceramic capacitor may also improve noise performance. Make sure that the connection from the ADXL375 ground to the power supply ground has low impedance because noise transmitted through ground has an effect similar to noise transmitted through VS. It is recommended that VS and VDD I/O be separate supplies to minimize digital clocking noise on the VS supply. If it is not possible to use separate supplies, additional filtering of the supplies, as previously mentioned, may be necessary. **==> picture [227 x 109] intentionally omitted <==** **----- Start of picture text -----**<br> VS VDD I/O<br>CS CI/O<br>VS VDD I/O<br>ADXL375<br>SDA/SDI/SDIO<br>INTERRUPT INT1 SDO/ALT ADDRESS 3- OR 4-WIRESPI OR I [2] C<br>CONTROL INT2 SCL/SCLK INTERFACE<br>GND CS 11669-016<br>**----- End of picture text -----**<br> _Figure 31. Application Diagram_ ## **MECHANICAL CONSIDERATIONS FOR MOUNTING** Mount the ADXL375 on the PCB in a location close to a hard mounting point of the PCB to the case. Mounting the ADXL375 at an unsupported PCB location, as shown in Figure 32, may result in large, apparent measurement errors due to undampened PCB vibration. Locating the accelerometer near a hard mounting point ensures that any PCB vibration at the accelerometer is above the mechanical sensor resonant frequency of the accelerometer and is, therefore, effectively invisible to the accelerometer. Multiple mounting points, close to the sensor, and/or a thicker PCB also help to reduce the effects of system resonance on the performance of the sensor. **==> picture [178 x 63] intentionally omitted <==** **----- Start of picture text -----**<br> ACCELEROMETERS<br>PCB<br>MOUNTING POINTS 11669-036<br>**----- End of picture text -----**<br> ## **SHOCK DETECTION** The shock interrupt function can detect mechanical shock events based on amplitude and pulse width. Figure 33 illustrates the following parameters for a valid single shock event and a valid double shock event. - Shock detection threshold—defined by the THRESH_ SHOCK register (Address 0x1D). - Maximum shock duration time (time limit for shocks)— defined by the DUR register (Address 0x21). - Shock latency time—defined by the latent register (Address 0x22). The latency time is the waiting period from the end of the first shock until the start of the time window, when a second shock can be detected. - Time window for second shock—defined by the window register (Address 0x23). The time window is the interval after the latency time (set by the latent register). Although a second shock must begin after the latency time expires, it need not finish before the end of the time defined by the window register. **==> picture [228 x 148] intentionally omitted <==** **----- Start of picture text -----**<br> FIRST SHOCK SECOND SHOCK<br>THRESHOLD<br>(THRESH_SHOCK)<br>TIME LIMIT FOR<br>SHOCKS (DUR)<br>LATENCY TIME WINDOW FOR<br>TIME SECOND SHOCK<br>(LATENT) (WINDOW)<br>SINGLE SHOCK DOUBLE SHOCK<br>INTERRUPT INTERRUPT<br>ACCELERATION<br>INTERRUPTS 11669-037<br>**----- End of picture text -----**<br> _Figure 33. Shock Interrupt Function with Valid Single and Double Shocks_ If only the single shock function is in use, the single shock interrupt is triggered when the acceleration goes below the threshold, as long as the duration time is not exceeded. If both the single and double shock functions are in use, the single shock interrupt is triggered when the double shock event is either validated or invalidated. _Figure 32. Incorrectly Placed Accelerometers_ Rev. B | Page 26 of 32 **Data Sheet** **ADXL375** Several events invalidate the second shock of a double shock event. - If the suppress bit in the SHOCK_AXES register (Bit D3, Address 0x2A) is set, any acceleration spike above the threshold during the latency time (set by the latent register) invalidates the double shock detection (see Figure 34). **==> picture [242 x 109] intentionally omitted <==** **----- Start of picture text -----**<br> INVALIDATES DOUBLE SHOCK IF<br>SUPPRESS BIT SET<br>TIME LIMIT<br>FOR SHOCKS LATENCY TIME WINDOW FOR SECOND<br>(DUR) TIME (LATENT) SHOCK (WINDOW)<br>ACCELERATION<br>11669-038<br>**----- End of picture text -----**<br> **==> picture [188 x 18] intentionally omitted <==** **----- Start of picture text -----**<br> Figure 34. Double Shock Event Invalid Due to High g Event<br>When the Suppress Bit Is Set<br>**----- End of picture text -----**<br> - A double shock event can be invalidated if acceleration above the threshold is detected at the start of the time window for the second shock (set by the window register), resulting in an invalid double shock at the start of this window (see Figure 35). - A double shock event can be invalidated if acceleration exceeds the time limit for shocks (set by the DUR register), resulting in an invalid double shock at the end of the DUR time limit for the second shock event (see Figure 35). **==> picture [242 x 255] intentionally omitted <==** **----- Start of picture text -----**<br> INVALIDATES DOUBLE SHOCK<br>AT START OF WINDOW<br>TIME LIMIT<br>FOR SHOCKS<br>(DUR)<br>TIME LIMIT<br>FOR SHOCKS LATENCY TIME WINDOW FOR<br>(DUR) TIME SECOND SHOCK (WINDOW)<br>(LATENT)<br>TIME LIMIT<br>FOR SHOCKS<br>(DUR)<br>INVALIDATES<br>DOUBLE SHOCK AT<br>END OF DUR<br>ACCELERATION<br>ACCELERATION<br>11669-039<br>**----- End of picture text -----**<br> Single shocks, double shocks, or both can be detected by setting the appropriate bits in the INT_ENABLE register (Address 0x2E). Participation of each of the three axes in single shock/double shock detection is controlled by setting the appropriate bits in the SHOCK_AXES register (Address 0x2A). For the double shock function to operate, both the latent and window registers must be set to a nonzero value. Every mechanical system has somewhat different shock responses based on the mechanical characteristics of the system. Therefore, some experimentation with values for the DUR, latent, window, and THRESH_SHOCK registers is required. Setting a very low value in the latent, window, or THRESH_ SHOCK register can result in unpredictable responses due to the accelerometer picking up echoes of the shock inputs. After a shock interrupt is received, the first axis to exceed the THRESH_SHOCK level is reported in the ACT_SHOCK_ STATUS register (Address 0x2B). This register is never cleared but is overwritten with new data. ## **THRESHOLD DETECTION AND BANDWIDTH** Lower output data rates are achieved by decimating a common sampling frequency inside the device. The activity and single shock/double shock detection functions are performed using undecimated data. Because the bandwidth of the output data varies with the data rate and is lower than the bandwidth of the undecimated data, the high frequency and high _g_ data that is used to determine activity and single shock/double shock events may not be present if the output of the accelerometer is examined. This may result in the triggering of these functions when acceleration data does not appear to meet the conditions set by the user for the corresponding function. ## **LINK MODE** The link bit (Bit D5) in the POWER_CTL register (Address 0x2D) can be used to reduce the number of activity interrupts that the processor must service. The link bit configures the device to look for activity only after inactivity. For proper operation of this feature, the processor must still respond to the activity and inactivity interrupts by reading the INT_SOURCE register (Address 0x30) and, therefore, clearing the interrupts. If an activity interrupt is not cleared, the part cannot enter autosleep mode. The asleep bit (Bit D3) in the ACT_SHOCK_STATUS register (Address 0x2B) indicates whether the part is asleep. _Figure 35. Shock Interrupt Function with Invalid Double Shocks_ Rev. B | Page 27 of 32 **Data Sheet** ## **ADXL375** ## **SLEEP MODE vs. LOW POWER MODE** In applications where a low data rate and low power consumption are desired (at the expense of noise performance), it is recommended that low power mode be used. Low power mode preserves the functionality of the DATA_READY interrupt and the FIFO buffer for postprocessing of the acceleration data. To enable low power mode, set the LOW_POWER bit (Bit D4) in the BW_RATE register (Address 0x2C). Sleep mode also provides a low data rate and low power consumption, but it is not intended for data acquisition. However, when sleep mode is used in conjunction with the autosleep and link modes, the part can automatically switch to a low power, low sampling rate mode when inactivity is detected. To prevent the generation of redundant inactivity interrupts, the inactivity interrupt is automatically disabled and the activity interrupt is enabled. To enable autosleep mode, set the AUTO_SLEEP bit (Bit D4) and the link bit (Bit D5) in the POWER_CTL register (Address 0x2D). When the ADXL375 is in sleep mode, the host processor can also be placed into sleep mode or low power mode to save significant system power. When activity is detected, the accelerometer automatically switches back to the original data rate of the application and provides an activity interrupt that can be used to wake up the host processor. Similar to when inactivity occurs, detection of activity events is disabled and detection of inactivity is enabled. ## **OFFSET CALIBRATION** Accelerometers are mechanical structures containing elements that are free to move. These moving parts can be very sensitive to mechanical stresses, much more so than solid-state electronics. The 0 _g_ bias, or offset, is an important accelerometer metric because it defines the baseline for measuring acceleration. Additional stresses can be applied during assembly of a system containing an accelerometer. These stresses can come from, but are not limited to, component soldering, board stress during mounting, and application of any compounds on or over the component. If calibration is deemed necessary, it is recommended that it be performed after system assembly to compensate for these effects. A simple method of calibration is to measure the offset while assuming that the sensitivity of the ADXL375 is as specified in Table 1. The offset can then be automatically accounted for by using the built-in offset registers. The result of this calibration is that the data acquired from the data registers already compensates for any offset. The number of samples averaged is selected by the system designer, but a recommended starting point is 0.1 sec worth of data for data rates of 100 Hz or greater—that is, 10 samples at the 100 Hz data rate. For data rates less than 100 Hz, it is recommended that at least 10 samples be averaged. These values are stored as X0 _g_ , Y0 _g_ , and Z+1 _g_ for the 0 _g_ measurements on the x- and y-axes and the 1 _g_ measurement on the z-axis, respectively. The values measured for X0 _g_ and Y0 _g_ correspond to the x- and y-axis offsets, and compensation is performed by subtracting these values from the output of the accelerometer to obtain the actual acceleration, as follows: **==> picture [80 x 25] intentionally omitted <==** Because the z-axis measurement is performed in a +1 _g_ field, a no-turn or single-point calibration scheme assumes an ideal sensitivity, SZ, for the z-axis. This value is subtracted from Z+1 _g_ to obtain the z-axis offset, which is then subtracted from future measured values to obtain the actual value, as follows: **==> picture [53 x 10] intentionally omitted <==** **==> picture [77 x 10] intentionally omitted <==** The ADXL375 can automatically compensate the output for offset by using the offset registers (Register 0x1E, Register 0x1F, and Register 0x20). These registers contain an 8-bit, twos complement value that is automatically added to all measured acceleration values; the result is then placed into the data registers. Because the value placed in an offset register is additive, a negative value in the register eliminates a positive offset, and a positive value in the register eliminates a negative offset. The register has a scale factor of 1.56 _g_ /LSB. As with all registers in the ADXL375, the offset registers do not retain the values written into them when power is removed from the part. Power cycling the ADXL375 returns the offset registers to their default value of 0x00. Because the no-turn or single-point calibration method assumes an ideal sensitivity in the z-axis, any error in the sensitivity results in offset error. ## **DATA FORMATTING AT OUTPUT DATA RATES OF 3200 HZ AND 1600 HZ** When using the 3200 Hz or 1600 Hz output data rate, the LSB of the output data-word is always 0. When the data is right justified, the LSB corresponds to Bit D0 of the DATAx0 register; when the data is left justified, the LSB corresponds to Bit D3 of the DATAx0 register. In a no-turn or single-point calibration scheme, the part is oriented such that one axis, typically the z-axis, is in the 1 _g_ field of gravity, and the remaining axes, typically the x- and y-axes, are in a 0 _g_ field. The output is then measured by taking the average of a series of samples. Rev. B | Page 28 of 32 **Data Sheet** **ADXL375** ## **USING SELF-TEST** The self-test change is defined as the difference between the acceleration output of an axis with self-test enabled and the acceleration output of the same axis with self-test disabled. Due to device filtering, the output reaches its final value after 4 × τ when enabling or disabling self-test, where τ = 1/(data rate). This definition assumes that the sensor does not move between these two measurements; if the sensor moves, a non-self-test related shift corrupts the test. Proper configuration of the ADXL375 is necessary for an accurate self-test measurement. To configure the part for selftest, follow this procedure. 1. Set the data rate from 100 Hz to 800 Hz, or set the data rate to 3200 Hz by writing to the rate bits (Bits[D3:D0]) in the BW_RATE register (Address 0x2C). Write a value from 0x0A to 0x0D, or write 0x0F to the BW_RATE register. 2. For accurate self-test measurements, configure the part for normal power operation by clearing the LOW_POWER bit (Bit D4) in the BW_RATE register (Address 0x2C). 3. After the part is configured for accurate self-test measurement, retrieve samples of x-, y-, and z-axis acceleration data from the sensor and average them together. The number of samples averaged is selected by the system designer, but a recommended starting point is 0.1 sec worth of data for data rates of 100 Hz or greater—that is, 10 samples at the 100 Hz data rate. 4. Store the averaged values and label them appropriately as the values with self-test disabled, that is, XST_OFF, YST_OFF, and ZST_OFF. 5. Enable self-test by setting the SELF_TEST bit (Bit D7) in the DATA_FORMAT register (Address 0x31). The output requires some time (approximately four samples) to settle after self-test is enabled. 7. Store the averaged values and label them appropriately as the values with self-test enabled, that is, XST_ON, YST_ON, and ZST_ON. 8. Disable self-test by clearing the SELF_TEST bit (Bit D7) in the DATA_FORMAT register (Address 0x31). With the stored values for self-test enabled and disabled, the self-test change is as follows: **==> picture [81 x 8] intentionally omitted <==** **==> picture [78 x 8] intentionally omitted <==** **==> picture [79 x 9] intentionally omitted <==** Because the measured output for each axis is expressed in LSBs, XST, YST, and ZST are also expressed in LSBs. These values can be converted to acceleration ( _g_ ) by multiplying each value by the 49 m _g_ /LSB scale factor. If the self-test change is within the valid range, the test is considered successful. Generally, a part is considered to pass if the minimum magnitude of change is achieved. However, a part that changes by more than the maximum magnitude is not necessarily a failure. The self-test response in the x- and y-axes exhibits bimodal behavior and, therefore, is not always a reliable indicator of sensor health or potential shift in device sensitivity. For this reason, perform the self-test check in the z-axis. Another effective method for using the self-test to verify accelerometer functionality is to toggle the self-test at a certain rate and then perform an FFT on the output. The FFT should have a corresponding tone at the frequency where the self-test was toggled. Using an FFT in this way removes the dependency of the test on supply voltage and self-test magnitude, which can vary within a rather wide range. 6. After allowing the output to settle, retrieve samples of x-, y-, and z-axis acceleration data and average them together. It is recommended that the same number of samples be taken for the self-test average as was done for the non-self-test average. Rev. B | Page 29 of 32 **ADXL375** **Data Sheet** ## **AXES OF ACCELERATION SENSITIVITY** **==> picture [190 x 153] intentionally omitted <==** **----- Start of picture text -----**<br> AZ<br>AY<br>AX 11669-021<br>**----- End of picture text -----**<br> _Figure 36. Axes of Acceleration Sensitivity (Corresponding Output Voltage Increases When Accelerated Along the Sensitive Axis)_ **==> picture [386 x 191] intentionally omitted <==** **----- Start of picture text -----**<br> XOUT = 1 g<br>YOUT = 0 g<br>ZOUT = 0 g<br>TOP<br>GRAVITY<br>XOUT = 0 g XOUT = 0 g<br>YOUT = –1 g YOUT = 1 g<br>ZOUT = 0 g ZOUT = 0 g<br>XOUT = –1 g<br>YOUT = 0 g<br>ZOUT = 0 g XOUT = 0 g XOUT = 0 g<br>YOUT = 0 g YOUT = 0 g<br>ZOUT = 1 g ZOUT = –1 g<br>TOP TOP<br>11669-022<br>TOP<br>**----- End of picture text -----**<br> _Figure 37. Output Response vs. Orientation to Gravity_ Rev. B | Page 30 of 32 **Data Sheet** **ADXL375** ## **LAYOUT AND DESIGN RECOMMENDATIONS** Figure 38 shows the recommended printed wiring board land pattern. **==> picture [177 x 199] intentionally omitted <==** **----- Start of picture text -----**<br> 3.3400<br>1.0500<br>0.5500<br>0.2500<br>3.0500<br>5.3400<br>0.2500<br>1.1450 11669-014<br>**----- End of picture text -----**<br> _Figure 38. Recommended Printed Wiring Board Land Pattern (Dimensions shown in millimeters)_ ## **PACKAGE INFORMATION** Figure 39 and Table 19 provide information about the package branding for the ADXL375. **==> picture [100 x 143] intentionally omitted <==** **----- Start of picture text -----**<br> 3 7 5 B<br># y w w<br>v v v v<br>C N T Y<br>11669-102<br>**----- End of picture text -----**<br> _Figure 39. Product Information on Package (Top View)_ **Table 19. Package Branding Information** |**Branding Key**|**Field Description**| |---|---| |375B<br>#<br>yww<br>vvvv<br>CNTY|Part identifier for theADXL375<br>RoHS-compliant designation<br>Date code<br>Factory lot code<br>Countryof origin| Rev. B | Page 31 of 32 **ADXL375** **Data Sheet** ## **OUTLINE DIMENSIONS** **==> picture [253 x 152] intentionally omitted <==** **----- Start of picture text -----**<br> 3.00<br>CORNERPAD A1 BSC 0.49 BOTTOM VIEW 0.813 × 0.50<br>13 14 1<br>5.00 0.80<br>BSC BSC<br>0.50<br>8 6<br>7<br>TOP VIEW 1.01<br>0.49<br>0.79<br>1.00<br>0.95 END VIEW 0.74 1.50<br>0.85 0.69<br>SEATING<br>PLANE<br>03-16-2010-A<br>**----- End of picture text -----**<br> _Figure 40. 14-Terminal Land Grid Array [LGA] (CC-14-1) Dimensions shown in millimeters_ ## **ORDERING GUIDE** |**ORDERING GUIDE**|||||| |---|---|---|---|---|---| |**Model1**|**Temperature**<br>**Range **|**Measurement**<br>**Range (****_g_) **|**Specified**<br>**Voltage (V)**|**Package Description**|**Package**<br>**Option**| |ADXL375BCCZ<br>ADXL375BCCZ-RL<br>ADXL375BCCZ-RL7<br>EVAL-ADXL375Z<br>EVAL-ADXL375Z-M<br>EVAL-ADXL375Z-S|−40°C to +85°C<br>−40°C to +85°C<br>−40°C to +85°C<br>−40°C to +85°C|±200<br>±200<br>±200|2.5<br>2.5<br>2.5|14-Terminal Land Grid Array [LGA]<br>14-Terminal Land Grid Array [LGA]<br>14-Terminal Land Grid Array [LGA]<br>Evaluation Board<br>Inertial Sensor Evaluation System, Includes<br>ADXL375Satellite<br>ADXL375Satellite, Standalone (can be used<br>with other inertial sensor evaluation systems)|CC-14-1<br>CC-14-1<br>CC-14-1| 1 Z = RoHS Compliant Part. I[2] C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). **©2013–2014 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.** **D11669-0-4/14(B)** Rev. B | Page 32 of 32
Updated at April 28, 2026
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