ADXL372BCCZ-RL7

MEMS Accelerometer, ± 200g, X, Y, Z, I2C, SPI, LGA, 16 Pins, 100mg/LSB

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Manufacturer: ANALOG DEVICES
Product type: MEMS Accelerometers
MSL: MSL 3 - 168 hours
SVHC: No SVHC (04-Feb-2026)
No. of Pins: 16Pins
Sensing Axis: X, Y, Z
Product Range: -
Qualification: -
Sensitivity Typ: 100mg/LSB
Output Interface: I2C, SPI
Sensor Case Style: LGA
MEMS Sensor Output: Digital
Supply Voltage Max: 3.5V
Supply Voltage Min: 1.6V
Sensor Case / Package: LGA
Operating Temperature Max: 105°C
Operating Temperature Min: -40°C
Sensing Range - Accelerometer: ± 200g
Delivery and price
Units per pack	1500
Price	10.07 €
Current stock	1000+
Lead time	30 days
Datasheet
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## **Micropower, 3-Axis, ±200** _**g**_ **Digital Output, MEMS** 

## **Data Sheet** 

## **ADXL372** 

## **FEATURES** 

## **±200** _**g**_ **measurement range** 

## **200 Hz to 3200 Hz user selectable bandwidth with 4-pole antialiasing filter** 

## **Selectable oversampling ratio** 

## **Adjustable high-pass filter Ultralow power** 

## **Power can be derived from a coin cell battery** 

## **22 µA at 3200 Hz ODR, 2.5 V supply** 

**Low power, wake-up mode for low** _**g**_ **activity detection** 

## **1.4 µA instant on mode with adjustable threshold** 

**<0.1 µA standby mode** 

## **GENERAL DESCRIPTION** 

The ADXL372 is an ultralow power, 3-axis, ±200 _g_ MEMS accelerometer that consumes 22 µA at a 3200 Hz output data rate (ODR). The ADXL372 does not power cycle its front end to achieve its low power operation and therefore does not run the risk of aliasing the output of the sensor. 

In addition to its ultralow power consumption, the ADXL372 has many features to enable impact detection while providing system level power reduction. The device includes a deep multimode output first in, first out (FIFO), several activity detection modes, and a method for capturing only the peak acceleration of over threshold events. 

## **Built in features for system level power savings** 

## **Autonomous interrupt processing without processor intervention** 

**Deep embedded FIFO to minimize host processor load** 

## **Ultralow power event monitoring detects impacts and wakes up fast enough to capture the transient events Ability to capture and store peak acceleration values of events** 

**Adjustable, low** _**g**_ **threshold activity and inactivity detection Wide supply range: 1.6 V to 3.5 V** 

**Acceleration sample synchronization via external trigger SPI digital interface and limited I[2] C interface format support 12-bit output at 100 m** _**g**_ **/LSB scale factor** 

**Wide temperature range: −40°C to +105°C Small, thin, 3 mm × 3.25 mm × 1.06 mm package** 

## **APPLICATIONS** 

**Impact and shock detection Asset health assessment Portable Internet of Things (IoT) edge nodes Concussion and head trauma detection** 

Two additional lower power modes with interrupt driven, wake-up features are available for monitoring motion during periods of inactivity. In wake-up mode, acceleration data can be averaged to obtain a low enough output noise to trigger on low _g_ thresholds. In instant on mode, the ADXL372 consumes 1.4 µA while continuously monitoring the environment for impacts. When an impact event that exceeds the internally set threshold is detected, the device switches to normal operating mode fast enough to record the event. 

High _g_ applications tend to experience acceleration content over a wide range of frequencies. The ADXL372 includes a 4-pole lowpass antialiasing filter to attenuate out of band signals that are common in high _g_ applications. The ADXL372 also incorporates a high-pass filter to eliminate initial and slow changing errors, such as ambient temperature drift. 

The ADXL372 provides 12-bit output data at 100 m _g_ /LSB scale factor. The user can access configuration and data registers via the serial peripheral interface (SPI) or limited I[2] C protocol. The ADXL372 operates over a wide supply voltage range and is available in a 3 mm × 3.25 mm × 1.06 mm package. 

Multifunction pin names may be referenced by their relevant function only. 

## **FUNCTIONAL BLOCK DIAGRAM** 

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VS VDDI/O<br>INT1<br>3-AXIS INT2<br>SENSORMEMS 12-BITADC DIGITALLOGIC, MOSI<br>FIFO, MISO<br>AND<br>SPI CS<br>SCLK<br>AXIS 4-POLE<br>DEMODULATORS ANTIALIASING ADXL372<br>FILTERS<br>GND<br>Figure 1.<br>Document Feedback<br>15430-001<br>**----- End of picture text -----**<br>


**Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.** 

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.<br>Tel: 781.329.4700  ©2017–2018 Analog Devices, Inc. All rights reserved.<br>Technical Support www.analog.com<br>**----- End of picture text -----**<br>


**ADXL372** 

**Data Sheet** 

## **TABLE OF CONTENTS** 

Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 Absolute Maximum Ratings ............................................................ 6 Thermal Resistance ...................................................................... 6 Recommended Soldering Profile ............................................... 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 13 Mechanical Device Operation .................................................. 13 Operating Modes ........................................................................ 13 Bandwidth ................................................................................... 13 Power/Noise Trade-Off .............................................................. 14 Power Savings ............................................................................. 15 Autonomous Event Detection ....................................................... 16 Activity and Inactivity................................................................ 16 Motion Warning ......................................................................... 18 Impact Detection Features ............................................................ 19 Wide Bandwidth ......................................................................... 19 Instant On Impact Detection .................................................... 19 Capturing Impact Events ........................................................... 19 FIFO ................................................................................................. 20 Benefits of the FIFO ................................................................... 20 Using the FIFO ........................................................................... 20 Retrieving Data from FIFO ....................................................... 21 Interrupts ......................................................................................... 22 Interrupt Pins .............................................................................. 22 Types of Interrupts ..................................................................... 22 Additional Features ........................................................................ 24 Using an External Clock ............................................................ 24 Synchronized Data Sampling .................................................... 24 Self Test ........................................................................................ 24 User Register Protection ............................................................ 25 User Offset Trims ....................................................................... 25 Serial Communications ................................................................. 26 Serial Interface ............................................................................ 26 

Multibyte Transfers .................................................................... 26 Invalid Addresses and Address Folding .................................. 27 Register Map ................................................................................... 30 Register Details ............................................................................... 32 Analog Devices ID Register ...................................................... 32 Analog Devices MEMS ID Register ......................................... 32 Device ID Register ..................................................................... 32 Product Revision ID Register ................................................... 32 Status Register ............................................................................. 33 Activity Status Register .............................................................. 33 FIFO Entries Register, MSB ...................................................... 34 FIFO Entries Register, LSB ........................................................ 34 X-Axis Data Register, MSB ....................................................... 34 X-Axis Data Register, LSB ......................................................... 34 Y-Axis Data Register, MSB ........................................................ 35 Y-Axis Data Register, LSB ......................................................... 35 Z-Axis Data Register, MSB ....................................................... 35 Z-Axis Data Register, LSB ......................................................... 35 Highest Peak Data Registers ..................................................... 36 X-Axis Highest Peak Data Register, MSB ............................... 36 X-Axis Highest Peak Data Register, LSB ................................. 36 Y-Axis Highest Peak Data Register, MSB ................................ 36 Y-Axis Highest Peak Data Register, LSB ................................. 37 Z-Axis Highest Peak Data Register, MSB ............................... 37 Z-Axis Highest Peak Data Register, LSB ................................. 37 Offset Trim Registers ................................................................. 38 X-Axis Offset Trim Register, LSB ............................................. 38 Y-Axis Offset Trim Register, LSB ............................................. 38 Z-Axis Offset Trim Register, LSB ............................................. 38 X-Axis Activity Threshold Register, MSB ............................... 39 X-Axis of Activity Threshold Register, LSB ............................ 39 Y-Axis Activity Threshold Register, MSB ............................... 39 Y-Axis of Activity Threshold Register, LSB ............................ 40 Z-Axis Activity Threshold Register, MSB ............................... 40 Z-Axis of Activity Threshold Register, LSB ............................ 40 Activity Time Register ............................................................... 41 X-Axis Inactivity Threshold Register, MSB ............................ 41 X-Axis of Inactivity Threshold Register, LSB ......................... 42 Y-Axis Inactivity Threshold Register, MSB ............................ 42 Y-Axis of Inactivity Threshold Register, LSB ......................... 43 

Rev. B | Page 2 of 56 

**Data Sheet** 

**ADXL372** 

Z-Axis Inactivity Threshold Register, MSB ............................. 43 Z-Axis of Inactivity Threshold Register, LSB .......................... 43 Inactivity Time Registers............................................................ 44 Inactivity Timer Register, MSB ................................................. 44 Inactivity Timer Register, LSB ................................................... 44 X-Axis Motion Warning Threshold Register, MSB ................ 45 X-Axis of Motion Warning Notification Register, LSB .......... 45 Y-Axis Motion Warning Notification Threshold Register, MSB ............................................................................................... 46 Y-Axis of Motion Warning Notification Register, LSB .......... 46 Z-Axis Motion Warning Notification Threshold Register, MSB ............................................................................................... 46 Z-Axis Motion Warning Notification Register, LSB............... 47 High-Pass Filter Settings Register ............................................. 47 FIFO Samples Register ............................................................... 48 FIFO Control Register ................................................................ 48 Interrupt Pin Function Map Registers ..................................... 49 

INT2 Function Map Register .................................................... 50 External Timing Control Register ............................................ 50 Measurement Control Register ................................................. 51 Power Control Register .............................................................. 52 Self Test Register ......................................................................... 53 RESET (Clears) Register, Part in Standby Mode .................... 53 FIFO Access Register .................................................................. 53 Applications Information ............................................................... 54 Application Examples ................................................................. 54 Operation at Voltages Other Than 2.5 V ................................. 54 Operation at Temperatures Other Than Ambient.................. 54 Mechanical Considerations for Mounting .............................. 54 Axes of Acceleration Sensitivity ................................................ 55 Layout and Design Recommendations .................................... 55 Outline Dimensions ........................................................................ 56 Ordering Guide ........................................................................... 56 

## **REVISION HISTORY** 

## **8/2018—Rev. A to Rev. B** 

Changes to Figure 34 ...................................................................... 19 Changes to I[2] C Protocol Section ................................................... 26 Added Note 1, Table 14; Renumbered Sequentially ................... 31 

## **12/2017—Rev. 0 to Rev. A** 

Changes to Turn-On Time, Measurement Mode Instruction to Valid Data Parameter; Table 1 ......................................................... 5 Changes to Instant On Impact Detection Section ...................... 19 Changes to Address: 0x3A, Reset: 0x00, Name: FIFO_CTL Section .............................................................................................. 48 

**3/2017—Revision 0: Initial Version** 

Rev. B | Page 3 of 56 

**ADXL372** 

**Data Sheet** 

## **SPECIFICATIONS** 

TA = 25°C, VS = 2.5 V, VDDI/O = 2.5 V, 3200 Hz ODR, 1600 Hz bandwidth, acceleration = 0 _g_ , default register settings, unless otherwise noted. All minimum and maximum specifications are guaranteed. Typical specifications may not be guaranteed. 

## **Table 1.** 

|**Table 1.**||||
|---|---|---|---|
|**Parameter**|**Test Conditions/Comments**|**Min**<br>**Typ**<br>**Max**|**Unit**|
|SENSOR INPUT<br>Measurement Range<br>Nonlinearity<br>Sensor Resonant Frequency<br>Cross Axis Sensitivity1|Each axis<br>Percentage of full scale|±200<br>±0.5<br>16<br>±2.5|_g_<br>%<br>kHz<br>%|
|OUTPUT RESOLUTION<br>All OperatingModes|Each axis|12|Bits|
|SCALE FACTOR<br>Scale Factor Calibration Error <br>Scale Factor at XOUT, YOUT, ZOUT<br>Scale Factor Change Due to Temperature2|Each axis<br>Expressed in m_g_/LSB<br>Expressed in LSB/_g_|±10<br>100<br>10<br>0.1|%<br>m_g_/LSB<br>LSB/_g_<br>%/°C|
|0_g_OFFSET<br>0_g_Output<br>0_g_Offset vs. Temperature2<br>Normal Operation<br>Low Noise Mode|Each axis<br>XOUT, YOUT, ZOUT<br>At VS= 2.5 V<br>1.6 V ≤ VS≤ 3.5 V<br>XOUT, YOUT, ZOUT<br>XOUT, YOUT, ZOUT|−3<br>±1<br>+3<br>−7<br>±1<br>+7<br>±50<br>±35|_g_<br>_g_<br>m_g_/°C<br>m_g_/°C|
|NOISE PERFORMANCE<br>RMS Noise<br>Normal Operation<br>Low Noise Mode|Each axis|3.5<br>3|LSB<br>LSB|
|BANDWIDTH<br>ODR<br>High-Pass Filter, −3 dB Corner3<br>Low-Pass (Antialiasing) Filter, −3 dB Corner4|User selectable<br>4-pole low-pass filter|400<br>6400<br>0.24<br>30.48<br>200<br>ODR/2|Hz<br>Hz<br>Hz|
|POWER SUPPLY<br>Operating Voltage Range (VS) <br>Input/Output Voltage Range (VDDI/O) <br>Supply Current<br>Measurement Mode<br>Normal Operation<br>Low Noise Mode<br>Instant On Mode<br>Wake-Up Mode<br>Standby<br>Power Supply Rejection Ratio (PSRR)<br>Input Frequency<br>100 Hz to 1 kHz<br>1 kHz to 250 kHz|3200 Hz ODR<br>Varies with wake-up rate<br>At slowest wake-up rate<br>CS= 1.1 µF, CIO= 1.1 µF, input is<br>100 mV sine wave on VS|1.6<br>2.5<br>3.5<br>1.6<br>2.5<br>VS<br>22<br>33<br>1.4<br>0.77<br><0.1<br>−20<br>−17|V<br>V<br>µA<br>µA<br>µA<br>µA<br>µA<br>dB<br>dB|



Rev. B | Page 4 of 56 

**Data Sheet ADXL372** 

|**Parameter**|**Test Conditions/Comments**|**Min**<br>**Typ**<br>**Max**|**Unit**|
|---|---|---|---|
|Turn-On Time<br>Power-Up to Standby<br>Measurement Mode Instruction to Valid Data<br>Instant On ULP Monitoringto Full Bandwidth Data|3200 Hz ODR<br>CS= 1.1 µF, CIO= 1.1 µF<br>Filter settle bit = 1<br>Filter settle bit = 0|5<br>16<br>370<br>1|ms<br>ms<br>ms<br>ms|
|ENVIRONMENTAL TEMPERATURE<br>OperatingTemperature Range||−40<br>+105|°C|



1 Cross axis sensitivity is defined as coupling between any two axes. 

2 −40°C to +25°C or +25°C to +105°C. 

3 This parameter has an available corner frequency scale with the ODR setting. 

4 Bandwidth and ODR are set independent of each other. 

Rev. B | Page 5 of 56 

**Data Sheet** 

## **ADXL372** 

## **ABSOLUTE MAXIMUM RATINGS** 

## **Table 2.** 

|**Table 2.**||
|---|---|
|**Parameter**|**Rating**|
|Acceleration<br>Any Axis, Unpowered<br>Any Axis, Powered<br>VS<br>VDDI/O<br>All Other Pins<br>Output Short-Circuit Duration (Any Pin to<br>Ground)<br>ESD, Human Body Model (HBM)<br>Temperature Range (Storage)|10000_g_<br>10000_g_<br>−0.3 V to +3.6 V<br>−0.3 V to +3.6 V<br>−0.3 V to VS<br>Indefinite<br>2000 V<br>−50°C to<br>+150°C|



Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. 

## **THERMAL RESISTANCE** 

Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. 

## **Table 3.** 

|**Table 3.**|||||
|---|---|---|---|---|
|**Package Type1**|**θJA**|**θJC**|**Unit**|**Device Weight**|
|CC-16-4|150|85|°C/W|18 m_g_|



1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal test board with four thermal vias. See JEDEC JESD51. 

## **RECOMMENDED SOLDERING PROFILE** 

Figure 2 and Table 4 provide details about the recommended soldering profile. 

|**tP**<br>**tL**<br>**t25°C TO PEAK**<br>**tS**<br>**PREHEAT**<br>**CRITICAL ZONE**<br>**TL TO TP**<br>**TEMPERATURE**<br>**TIME**<br>**RAMP-DOWN**<br>**RAMP-UP**<br>**TSMIN**<br>**TSMAX**<br>**TP**<br>**TL**<br>15430-002<br>_Figure 2. Recommended Soldering Profile_<br>**Table 4. Recommended Soldering Profile**|**tP**<br>**tL**<br>**t25°C TO PEAK**<br>**tS**<br>**PREHEAT**<br>**CRITICAL ZONE**<br>**TL TO TP**<br>**TEMPERATURE**<br>**TIME**<br>**RAMP-DOWN**<br>**RAMP-UP**<br>**TSMIN**<br>**TSMAX**<br>**TP**<br>**TL**<br>15430-002<br>_Figure 2. Recommended Soldering Profile_<br>**Table 4. Recommended Soldering Profile**|**tP**<br>**tL**<br>**t25°C TO PEAK**<br>**tS**<br>**PREHEAT**<br>**CRITICAL ZONE**<br>**TL TO TP**<br>**TEMPERATURE**<br>**TIME**<br>**RAMP-DOWN**<br>**RAMP-UP**<br>**TSMIN**<br>**TSMAX**<br>**TP**<br>**TL**<br>15430-002<br>_Figure 2. Recommended Soldering Profile_<br>**Table 4. Recommended Soldering Profile**|
|---|---|---|
|**Profile Feature**|**Condition**||
||**Sn63/Pb37**|**Pb-Free**|
|Average Ramp Rate (TLto TP)<br>Preheat<br>Minimum Temperature (TSMIN)<br>Maximum Temperature (TSMAX)<br>Time (TSMINto TSMAX) (tS)<br>TSMAXto TL<br>Ramp-Up Rate<br>Time Maintained Above<br>Liquidous (TL)<br>Liquidous Temperature (TL)<br>Time (tL)<br>Peak Temperature (TP)<br>Time Within 5°C of Actual Peak<br>Temperature (tP)<br>Ramp-Down Rate<br>Time 25°C to Peak Temperature|3°C/sec max<br>100°C<br>150°C<br>60 sec to<br>120 sec<br>3°C/sec max<br>183°C<br>60 sec to<br>150 sec<br>240 + 0/−5°C<br>10 sec to 30 sec<br>6°C/sec max<br>6 minutes max|3°C/sec max<br>150°C<br>200°C<br>60 sec to<br>180 sec<br>3°C/sec max<br>217°C<br>60 sec to<br>150 sec<br>260 + 0/−5°C<br>20 sec to 40 sec<br>6°C/sec max<br>8 minutes max|



## **ESD CAUTION** 

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Rev. B | Page 6 of 56 

**Data Sheet** 

**ADXL372** 

## **PIN CONFIGURATION AND FUNCTION DESCRIPTIONS** 

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16 15 14<br>VDDI/O 1 13 GND<br>NIC 2 12 GND<br>ADXL372<br>RESERVED 3 TOP VIEW 11 INT1<br>(Not to Scale)<br>SCLK 4 10 RESERVED<br>RESERVED 5 9 INT2<br>6 7 8<br>NOTES<br>1. NIC = NO CONNECT. THIS PIN IS NOT<br>    INTERNALLY CONNECTED.<br>Figure 3. Pin Configuration (Top View)<br>15430-003<br>S<br>GND NIC V<br>MOSI/SDA MISO CS/SCL<br>**----- End of picture text -----**<br>


**Table 5. Pin Function Descriptions** 

|**Pin No.**|**Mnemonic**|**Description**|
|---|---|---|
|1<br>2<br>3<br>4<br>5<br>6<br>7<br>8<br>9<br>10<br>11<br>12<br>13<br>14<br>15<br>16|VDDI/O<br>NIC<br>RESERVED<br>SCLK<br>RESERVED<br>MOSI/SDA<br>MISO<br>CS<br>/SCL<br>INT2<br>RESERVED<br>INT1<br>GND<br>GND<br>VS<br>NIC<br>GND|Supply Voltage for Digital Input/Output.<br>No Connect. This pin is not internally connected.<br>Reserved. This pin may be left unconnected or connected to GND.<br>SPI Serial Communications Clock.<br>Reserved. This pin may be left unconnected or connected to GND.<br>SPI Master Output, Slave Input (MOSI). I2C Serial Data (SDA).<br>SPI Master Input, Slave Output.<br>SPI Chip Select (CS<br>). I2C Serial Communications Clock (SCL).<br>Interrupt 2 Output. This pin also serves as an input for synchronized sampling.<br>Reserved. This pin may be left unconnected or connected to GND.<br>Interrupt 1 Output. This pin also serves as an input for external clocking.<br>Ground. This pin must be connected to ground.<br>Ground. This pin must be connected to ground.<br>Supply Voltage.<br>No Connect. This pin is not internally connected.<br>Ground. Thispin must be connected toground.|



Rev. B | Page 7 of 56 

**ADXL372** 

**Data Sheet** 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

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60<br>DISTRIBUTIONS SHOWN ARE OBTAINED FROM<br>6404 PARTS FROM THREE DIFFERENT PRODUCTION LOTS.<br>50<br>40<br>30<br>20<br>10<br>0<br>–30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30<br>ZERO g  OFFSET (LSB)<br>PERCENT OF POPULATION (%)<br>15430-004<br>**----- End of picture text -----**<br>


_Figure 4. X-Axis Zero_ g _Offset at 25°C, VS = 2.5 V_ 

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70<br>DISTRIBUTIONS SHOWN ARE OBTAINED FROM<br>6404 PARTS FROM THREE DIFFERENT PRODUCTION LOTS.<br>60<br>50<br>40<br>30<br>20<br>10<br>0<br>–30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30<br>ZERO g  OFFSET (LSB)<br>PERCENT OF POPULATION (%)<br>15430-005<br>**----- End of picture text -----**<br>


_Figure 5. Y-Axis Zero_ g _Offset at 25°C, VS = 2.5 V_ 

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60<br>DISTRIBUTIONS SHOWN ARE OBTAINED FROM<br>6404 PARTS FROM THREE DIFFERENT PRODUCTION LOTS.<br>50<br>40<br>30<br>20<br>10<br>0<br>–30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30<br>ZERO g  OFFSET (LSB)<br>PERCENT OF POPULATION (%)<br>15430-006<br>**----- End of picture text -----**<br>


_Figure 6. Z-Axis Zero_ g _Offset at 25°C, VS = 2.5 V_ 

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35<br>DISTRIBUTIONS SHOWN ARE OBTAINED FROM 144 PARTS FROM<br>THREE DIFFERENT PRODUCTION LOTS, FLIPPED IN ±1 g  FIELD.<br>30<br>25<br>20<br>15<br>10<br>5<br>0<br>8.0 8.4 8.8 9.2 9.6 10.0 10.4 10.8 11.2 11.6 12.0<br>SENSITIVITY (LSB/ g )<br>PERCENT OF POPULATION (%)<br>15430-007<br>**----- End of picture text -----**<br>


_Figure 7. X-Axis Sensitivity at 25°C, VS = 2.5 V_ 

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50<br>DISTRIBUTIONS SHOWN ARE OBTAINED FROM 144 PARTS FROM<br>THREE DIFFERENT PRODUCTION LOTS, FLIPPED IN ±1 g  FIELD.<br>40<br>30<br>20<br>10<br>0<br>8.0 8.4 8.8 9.2 9.6 10.0 10.4 10.8 11.2 11.6 12.0<br>SENSITIVITY (LSB/ g )<br>PERCENT OF POPULATION (%)<br>15430-008<br>**----- End of picture text -----**<br>


_Figure 8. Y-Axis Sensitivity at 25°C, VS = 2.5 V_ 

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45<br>DISTRIBUTIONS SHOWN ARE OBTAINED FROM 144 PARTS FROM<br>THREE DIFFERENT PRODUCTION LOTS, FLIPPED IN ±1 g  FIELD.<br>40<br>35<br>30<br>25<br>20<br>15<br>10<br>5<br>0<br>8.0 8.4 8.8 9.2 9.6 10.0 10.4 10.8 11.2 11.6 12.0<br>SENSITIVITY (LSB/ g )<br>PERCENT OF POPULATION (%)<br>15430-009<br>**----- End of picture text -----**<br>


_Figure 9. Z-Axis Sensitivity at 25°C, VS = 2.5 V_ 

Rev. B | Page 8 of 56 

**Data Sheet** 

**ADXL372** 

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20 DISTRIBUTIONS SHOWN ARE OBTAINED FROM 143 PARTS  FROM THREE 5<br>DIFFERENT PRODUCTION LOTS. TEMPERATURE COEFFICIENTS ARE<br>18 MEASURED BETWEEN –40°C TO 25°C AND BETWEEN 25°C TO 105°C. THE DISPLAYED TEMPERATURE COEFFICIENT IS THE LARGER OF THE TWO. 4<br>1614 LLLFCCP CCPLeeTH 32 TLLLLLLLL!SEESee<br>12 1<br>COCO Co Cee TTT eee<br>10 CCCP CE Cece 0 te<br>8 CCCP –1 =<br>6 POC aceccre –2 2<br>4 (Coe ee –3 ee TTerrily.<br>2 –4<br>0 af a y L __CC LL |<aaa8RCEee –5 Oe a<br>–40 –30 –20 –10 0 10 20 30 40 –60 –40 –20 0 20 40 60 80 100 120<br>ZERO g  OFFSET TEMPERATURE COEFFICIENT (m g /°C) TEMPERATURE (°C)<br>Figure 10. X-Axis Zero  g  Offset Temperature Coefficient, VS = 2.5 V   Figure 13. X-Axis Zero  g  Normalized Offset vs. Temperature,<br>36 Parts Soldered to PCB, ODR = 3200 Hz<br>20 DISTRIBUTIONS SHOWN ARE OBTAINED FROM 143 PARTS  FROM THREE DIFFERENT 5<br>PRODUCTION LOTS. TEMPERATURE COEFFICIENTS ARE MEASURED BETWEEN<br>18 –40°C TO 25°C AND BETWEEN 25°C TO 105°C. THE DISPLAYED TEMPERATURE COEFFICIENT IS THE LARGER OF THE TWO. 4<br>1614 SeePECEEEC LLLL 32 TLLLLLLLILSEE EEE<br>12 PECEECa) | EEE 1 ne<br>10 PCCEL oy |) Gece 0 aaa<br>8 PCE PCC –1 ee a<br>6 PCCP PELE=s0000 –2 ==eT 2<br>4 PCE “S500 –3 TELLoo ote)<br>2 –4<br>0 PC EC jamusSELL –5 ee ee<br>–40 –30 –20 –10 0 10 20 30 40 –60 –40 –20 0 20 40 60 80 100 120<br>ZERO g  OFFSET TEMPERATURE COEFFICIENT (m g /°C) TEMPERATURE (°C)<br>Figure 11. Y-Axis Zero  g  Offset Temperature Coefficient, VS = 2.5 V  Figure 14. Y-Axis Zero  g  Normalized Offset vs. Temperature,<br>36 Parts Soldered to PCB, ODR = 3200 Hz<br>25 5<br>DISTRIBUTIONS SHOWN ARE OBTAINED FROM 143 PARTS  FROM THREE DIFFERENT<br>PRODUCTION LOTS. TEMPERATURE COEFFICIENTS ARE MEASURED BETWEEN<br>–40°C TO 25°C AND BETWEEN 25°C TO 105°C. THE DISPLAYED TEMPERATURECOEFFICIENT IS THE LARGER OF THE TWO. 4<br>20 HEE EEL 3 TELFE L E LLLLLL,EES<br>2<br>15 1<br>= S SS ee<br>CCITT) =  a 0 e —4<br>10 –1<br>–2<br>50 TTT CMMI) = Ty_ –4–3–5 fs2EEREee<br>–40 –30 –20 –10 0 10 20 30 40 –60 –40 –20 0 20 40 60 80 100 120<br>ZERO  g  OFFSET TEMPERATURE COEFFICIENT (m g /°C) TEMPERATURE (°C)<br>Figure 12. Z-Axis Zero  g  Offset Temperature Coefficient, VS = 2.5 V  Figure 15. Z-Axis Zero  g  Normalized Offset vs. Temperature,<br>36 Parts Soldered to PCB, ODR = 3200 Hz<br>) g<br> NORMALIZED OFFSET (<br> g<br>PERCENT OF POPULATION (%)<br>X-AXIS ZERO<br>15430-010 15430-013<br>) g<br> NORMALIZED OFFSET (<br> g<br>PERCENT OF POPULATION (%)<br>Y-AXIS ZERO<br>15430-011 15430-014<br>) g<br> NORMALIZED OFFSET (<br> g<br>PERCENT OF POPULATION (%)<br>Z-AXIS ZERO<br>15430-012 15430-015<br>**----- End of picture text -----**<br>


Rev. B | Page 9 of 56 

**Data Sheet** 

## **ADXL372** 

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**----- Start of picture text -----**<br>
1.05 70<br>DISTRIBUTIONS SHOWN ARE OBTAINED FROM<br>1.04 pot | | TT 6404 PARTS FROM THREE DIFFERENT PRODUCTION LOTS.<br>60<br>1.03<br>| ao AAT | | | fT ht<br>1.02 | A, | | ot Tt 50<br>1.01<br>0700<br>40<br>1.00<br>0.99 | | |ASA| 30<br>0.980.97 | 20<br>0.96 | | | | | | FV YA<br>10<br>0.95 | | | | | | | MT<br>0.94 | | tT | | | tT tl 0<br>–60 –40 –20 0 20 40 60 80 100 120 16 18 20 22 24 26 28 30<br>TEMPERATURE (°C) CURRENT CONSUMPTION (µA)<br>Figure 16. X-Axis Normalized Sensitivity Deviation from 25°C vs.  Figure 19. Current Consumption at 25°C, Normal Mode, 3200 Hz Output Data<br>Temperature, 18 Parts Soldered to PCB, ODR = 3200 Hz  Rate, VS = 2.5 V<br>1.04 70<br>DISTRIBUTIONS SHOWN ARE OBTAINED FROM<br>6404 PARTS FROM THREE DIFFERENT PRODUCTION LOTS.<br>1.03<br>60<br>Lpeeh et tot ot tt Pa<br>1.02 a //\\ 4 |<br>| CRNAtndi Lf | tt tt 50 TTT|) mole<br>1.01<br>esEe Mal | 40 oan S000<br>1.00<br>30<br>0.99 aide:CeMaCe Soee Seen<br>0.98 TTT 20 ptt<br>0.97 Semmes 10 ey |<br>0.96 PEPE EE2 0 OSPPE =.<br>–60 –40 –20 0 20 40 60 80 100 120 24 26 28 30 32 34 36 38 40<br>TEMPERATURE (°C) CURRENT CONSUMPTION (µA)<br>Figure 17. Y-Axis Normalized Sensitivity Deviation from 25°C vs.  Figure 20. Current Consumption at 25°C, Low Noise Mode, 3200 Hz Output Data<br>Temperature, 17 Parts Soldered to PCB, ODR = 3200 Hz  Rate, VS = 2.5 V<br>1.04 70<br>DISTRIBUTIONS SHOWN ARE OBTAINED FROM<br>6404 PARTS FROM THREE DIFFERENT PRODUCTION LOTS.<br>1.03<br>60<br>Eft ttt ttt eeeererean<br>1.02<br>50<br>1.01 PelSSRTT TTT Ee<br>ima TT 40 ioe e008<br>1.00<br>30<br>0.99<br>eiaoeTae an “S500<br>0.98 20<br>0.97 FEEEEEAwt 10 EE CEE<br>0.96–60 ae –40 –20 0 20 40 60 80 100 120 0 fe) 0.6 0.8 Y 1.0 | 1.2 1.4 San— 1.6 1.8 2.0 2.2<br>TEMPERATURE (°C)<br>CURRENT CONSUMPTION (µA)<br>DEVIATION FROM 25°C<br>PERCENT OF POPULATION (%)<br>X-AXIS NORMALIZED SENSITIVITY<br>15430-016 15430-019<br>DEVIATION FROM 25°C<br>PERCENT OF POPULATION (%)<br>Y-AXIS NORMALIZED SENSITIVITY<br>15430-017<br>15430-020<br>DEVIATION FROM 25°C<br>Z-AXIS NORMALIZED SENSITIVITY PERCENT OF POPULATION (%)<br>15430-018 15430-021<br>**----- End of picture text -----**<br>


_Figure 18. Z-Axis Normalized Sensitivity Deviation from 25°C vs. Temperature, 18 Parts Soldered to PCB, ODR = 3200 Hz_ 

_Figure 21. Current Consumption at 25°C, Instant On Mode, VS = 2.5 V_ 

Rev. B | Page 10 of 56 

**Data Sheet** 

**ADXL372** 

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60<br>DISTRIBUTIONS SHOWN ARE<br>OBTAINED FROM 6404 PARTS<br>FROM THREE DIFFERENT<br>PRODUCTION LOTS.<br>50<br>40<br>30<br>20<br>10<br>0<br>0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2<br>CURRENT CONSUMPTION (µA)<br>Figure 22. Current Consumption at 25°C, Wake-Up Mode, VS = 2.5 V<br>60 DISTRIBUTIONS SHOWN ARE OBTAINED FROM 6404 PARTS FROM THREE DIFFERENT PRODUCTION LOTS.<br>50<br>40<br>30<br>20<br>10<br>0<br>–20 –15 –10 –5 0 5 10 15 20 25 30<br>CLOCK FREQUENCY DEVIATION FROM IDEAL (%)<br>PERCENT OF POPULATION (%)<br>15430-022<br>PERCENT OF POPULATION (%)<br>15430-023<br>**----- End of picture text -----**<br>


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70<br>DISTRIBUTIONS SHOWN ARE OBTAINED FROM<br>6404 PARTS FROM THREE DIFFERENT PRODUCTION LOTS.<br>60<br>50<br>40<br>30<br>20<br>10<br>0<br>0 5 10 15 20 25 30 35 40<br>CURRENT CONSUMPTION (nA)<br>PERCENT OF POPULATION (%)<br>15430-025<br>**----- End of picture text -----**<br>


_Figure 25. Current Consumption at 25°C, Standby Mode, VS = 2.5 V_ 

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60 DISTRIBUTIONS SHOWN ARE OBTAINED FROM 6404 PARTS FROM THREE DIFFERENT PRODUCTION LOTS. 4.5 VVDDDD = 1.6V = 2.5V<br>4.0 V DD  = 3.5V<br>50<br>3.5<br>40 3.0<br>2.5<br>30<br>2.0<br>20 1.5<br>1.0<br>10<br>0.5<br>0 –20 –15 –10 –5 0 5 10 15 20 25 30 0–50 –30 –10 10 30 50 70 90 110<br>CLOCK FREQUENCY DEVIATION FROM IDEAL (%) TEMPERATURE (°C)<br>Figure 23. Clock Frequency Deviation from Ideal at 25°C, ODR = 3200 Hz, VS = S =  =  Figure 26. Standby Current vs. Temperature<br>2.5 V<br>40<br>60 DISTRIBUTIONS SHOWN ARE OBTAINED FROM6404 PARTS FROM THREE DIFFERENT PRODUCTION LOTS. VV V DDDDDD = 1.6V = 2.5V  = 3.5V<br>35<br>50<br>30<br>40<br>25<br>30<br>20<br>20<br>15<br>10<br>10<br>–50 –30 –10 10 30 50 70 90 110<br>0<br>–20 –15 –10 –5 0 5 10 15 20 25 30 TEMPERATURE (°C)<br>CLOCK FREQUENCY DEVIATION FROM IDEAL (%)<br>STANDBY CURRENT (µA)<br>PERCENT OF POPULATION (%)<br>15430-023 15430-026<br>PERCENT OF POPULATION (%) MEASUREMENT MODE CURRENT (µA)<br>15430-027<br>15430-024<br>**----- End of picture text -----**<br>


_Figure 23. Clock Frequency Deviation from Ideal at 25°C, ODR = 3200 Hz, VS = S =  = 2.5 V_ 

_Figure 24. Clock Frequency Deviation from Ideal at 25°C, ODR = 6400Hz, VS = 2.5 V_ 

_Figure 27. Measurement Mode Current vs. Temperature_ 

Rev. B | Page 11 of 56 

**ADXL372** 

**Data Sheet** 

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6<br>VDD = 1.6V<br>VDD = 2.5V<br>VDD = 3.5V<br>5<br>4<br>3<br>2<br>1<br>0<br>–50 –30 –10 10 30 50 70 90 110<br>TEMPERATURE (°C)<br>INSTANT ON CURRENT (µA)<br>15430-028<br>**----- End of picture text -----**<br>


_Figure 28. Instant On Current vs. Temperature_ 

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6<br>VDD = 1.6V<br>VDD = 2.5V<br>VDD = 3.5V<br>5<br>4<br>3<br>2<br>1<br>0<br>–50 –30 –10 10 30 50 70 90 110<br>TEMPERATURE (°C)<br>Figure 29. Wake-Up Current vs. Temperature<br>WAKE-UP CURRENT (µA)<br>15430-029<br>**----- End of picture text -----**<br>


Rev. B | Page 12 of 56 

**Data Sheet** 

**ADXL372** 

## **THEORY OF OPERATION** 

The ADXL372 is a complete 3-axis acceleration measurement system that operates at extremely low power levels. Acceleration is reported digitally, and the device communicates via the SPI and I[2] C protocols. Built in digital logic enables autonomous operation and implements functions that enhance system level power savings. 

## **MECHANICAL DEVICE OPERATION** 

The moving component of the sensor is a polysilicon surface micromachined structure built on top of a silicon wafer. Polysilicon springs suspend the structure over the surface of the wafer and provide a resistance against acceleration forces. 

Deflection of the structure is measured using differential capacitors that consist of independent fixed plates and plates attached to the moving mass. Acceleration deflects the structure and unbalances the differential capacitor, resulting in a sensor output whose amplitude is proportional to acceleration. Phase sensitive demodulation determines the magnitude and polarity of the acceleration. 

## **OPERATING MODES** 

The ADXL372 has three operating modes: measurement mode for continuous, wide bandwidth sensing; an instant on mode for low power impact detection; and wake-up mode for limited bandwidth low _g_ activity detection. Measurement can be suspended by placing the device in standby mode. 

## _**Measurement Mode**_ 

Measurement mode is the default operating mode of the ADXL372. In this mode, acceleration data is read continuously, and the accelerometer consumes 22 µA (typical) at an ODR of 3200 Hz using a 2.5 V supply. Actual current consumption is dependent on the ODR chosen. All features described in this data sheet are available when operating the ADXL372 in this mode. 

## _**Instant On Mode**_ 

Instant on mode enables extremely low power impact detection. In this mode, the accelerometer constantly monitors the environment while consuming a very low current of 1.4 µA (typical). When an event that exceeds an internal threshold is detected, the device switches into measurement mode to record the event. The target default threshold is 10 _g_ to 15 _g_ , but it can vary. A register option allows the threshold to be increased to a target of 30 _g_ to 40 _g_ if the default threshold is too low. 

To save power, no new digital acceleration data is made available until the accelerometer switches into normal operation. However, all registers have normal read/write functionality. 

## _**Wake-Up Mode**_ 

Wake-up mode is ideal for simple detection of the presence or absence of motion at an extremely low power consumption. Wakeup mode is particularly useful for the implementation of a low _g_ motion activated on/off switch, allowing the rest of the system to be powered down until sustained activity is detected. 

In wake-up mode, the device is powered down for a duration of time equal to the wake-up timer, set by the WAKEUP_RATE bits in the TIMING register, and then turns on for a duration equal to the filter settling time (see the Filter Settling Time section). The current drawn in this mode is determined by both these parameters. 

**Table 6. Wake-Up Current in µA at Different Wake-Up Timer and Filter Settings** 

|**Wake-Up Timer (ms)**|**Filter Settling Time**|**Filter Settling Time**|
|---|---|---|
||**16 ms**|**370 ms**|
|52<br>104<br>208<br>512<br>2048<br>4096<br>8192<br>24576|5.8 µA<br>3.6 µA<br>2.3 µA<br>1.4 µA<br>0.91 µA<br>0.83 µA<br>0.79 µA<br>0.77µA|19.4 µA<br>17.3 µA<br>14.4 µA<br>9.7 µA<br>4 µA<br>2.5 µA<br>1.7 µA<br>1.1µA|



If motion is detected, the accelerometer can respond autonomously in several ways, depending on the device configuration, such as the following: 

- Switch into full bandwidth measurement mode. 

- Signal an interrupt to a microcontroller. 

- Wake up downstream circuitry. 

While in wake-up mode, all registers and the FIFO have normal read/write functionality, and real-time data can be read from the data registers at the reduced wake-up rate. However, no new data is stored in the FIFO during wake-up mode, and there are no interrupts available in wake-up mode. 

## _**Standby**_ 

Placing the ADXL372 in standby mode suspends measurement and reduces current consumption to less than 100 nA. All interrupts are cleared, and no new interrupts are generated. The ADXL372 powers up in standby mode with all sensor functions turned off. 

## **BANDWIDTH** 

## _**Low-Pass Antialiasing Filter**_ 

High _g_ events often include acceleration content over a wide range of frequencies. The analog-to-digital converter (ADC) of the ADXL372 samples the input acceleration at the user selected ODR. In the absence of antialiasing filters, input signals whose frequency is more than half the ODR alias or that fold into the measurement bandwidth can lead to inaccurate measurements. To mitigate this inaccuracy, a four-pole, low-pass filter is provided at the input of the ADC. The filter bandwidth is user selectable, and the default bandwidth is 200 Hz. The maximum bandwidth is constrained to at most half of the ODR, to ensure that the Nyquist criteria is not violated. 

Rev. B | Page 13 of 56 

**Data Sheet** 

## **ADXL372** 

## _**High-Pass Filter**_ 

The ADXL372 offers a one-pole, high-pass filter with a user selectable −3 dB frequency. Applications that do not require dc acceleration measurements can use the high-pass filter to minimize constant or slow varying offset errors including initial bias, bias drift due to temperature, and bias drift due to supply voltage. 

The high-pass filter is a first-order infinite impulse response (IIR) filter. Table 7 lists the available −3 dB frequencies, which are user selectable and dependent on the output data rate. The high-pass and low-pass filters can be used simultaneously to set up a band-pass option. 

**Table 7. High-Pass Filter −3 dB Corner Frequencies** 

|**Setting**|||**ODR (Hz)**|||
|---|---|---|---|---|---|
||**6400**|**3200**|**1600**|**800**|**400**|
|00<br>01<br>10<br>11|30.48<br>15.58<br>7.88<br>3.96|15.24<br>7.79<br>3.94<br>1.98|7.61<br>3.89<br>1.97<br>0.99|3.81<br>1.94<br>0.98<br>0.49|1.9<br>0.97<br>0.49<br>0.24|



## _**Filter Settling Time**_ 

After entering measurement mode, the first output value does not appear until after the filter settling time has passed. This time is selectable using the FILTER_SETTLE bit in the POWER_CTL register. The recommended (and default) settling time to acquire valid data when using either the high-pass filter or the low-pass activity detect filter is 370 ms. The filter settling time of 16 ms is ideal for when both the high-pass filter and low-pass activity detect filter are disabled. 

## _**Selectable ODR**_ 

The ADXL372 can report acceleration data at 400 Hz, 800 Hz, 1600 Hz, 3200 Hz, or 6400 Hz. The ODR is user selectable and the default is 400 Hz. In the event that the user selects an antialiasing filter bandwidth greater than half the ODR, the device defaults the bandwidth to half the ODR. Increasing or decreasing the ODR increases or decreases the current consumption accordingly, as shown in Figure 30. 

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50<br>40<br>30<br>20<br>10<br>0<br>256 1024 4096<br>ODR (Hz)<br>CURRENT (µA)<br>15430-030<br>**----- End of picture text -----**<br>


_Figure 30. Measurement Mode Current vs. ODR for Five Parts_ 

## **POWER/NOISE TRADE-OFF** 

The noise performance of the ADXL372 in normal operation, typically 3.5 LSB rms at 3200 Hz ODR and 1600 Hz bandwidth, is adequate for most applications, depending on bandwidth and the desired resolution. For cases where lower noise is needed, the ADXL372 provides a lower noise operating mode that trades reduced noise for a somewhat higher current consumption. In all cases, operating at a higher bandwidth setting increases the rms noise and operating with a lower bandwidth decreases the noise. Table 8 lists the current consumption and noise densities obtained for normal operation and the lower noise mode at a typical 2.5 V supply. 

Operating the ADXL372 at a higher supply voltage also decreases noise. Table 9 lists the current consumption and noise densities obtained for normal operation and the lower noise mode at the highest recommended supply, 3.5 V. 

**Table 8. Noise and Current Consumption for VS = 2.5 V** 

|**Table 8. Noise and Current Consumption for VS**|**= 2.5 V**||
|---|---|---|
|**Mode**|**Typical RMS Noise (LSB)**|**Typical Current Consumption (µA)**|
|Normal Operation1<br>Low Noise1|3.5<br>3|22<br>33|



1 VS = 2.5 V, ODR = 3200 Hz, and bandwidth = 1600 Hz. 

**Table 9. Noise and Current Consumption for VS = 3.5 V** 

|**Table 9. Noise and Current Consumption for VS**|**= 3.5 V**||
|---|---|---|
|**Mode**|**Typical RMS Noise (LSB)**|**Typical Current Consumption (µA)**|
|Normal Operation1<br>Low Noise1|3<br>2.5|32<br>44|



1 VS = 3.5 V, ODR = 3200 Hz, and bandwidth = 1600 Hz. 

Rev. B | Page 14 of 56 

**Data Sheet** 

**ADXL372** 

## **POWER SAVINGS** 

The digital interface of the ADXL372 is implemented with system level power savings in mind. The following features enhance power savings: 

- Burst reads and writes reduce the number of SPI communication cycles required to configure the device and retrieve data. 

   - The FIFO is implemented such that consecutive samples can be read continuously via a multibyte read of unlimited length; thus, one FIFO read instruction can clear the entire contents of the FIFO. The ADXL372 FIFO construction also allows the use of direct memory access (DMA) to read the FIFO contents. 

- Concurrent operation of activity and inactivity detection enables set it and forget it operation. Loop modes further reduce communications power by enabling the clearing of interrupts without processor intervention. 

Rev. B | Page 15 of 56 

**Data Sheet** 

## **ADXL372** 

## **AUTONOMOUS EVENT DETECTION** 

## **ACTIVITY AND INACTIVITY** 

The ADXL372 features built in logic that detects activity (defined as acceleration above a user set threshold) and inactivity (defined as acceleration below a user set threshold). Activity and inactivity events can be used as triggers to manage the accelerometer operating mode, trigger an interrupt to a host processor, and/or autonomously drive a motion switch. 

Detection of an activity or inactivity event is indicated in the STATUS2 register and can be configured to generate an interrupt. In addition, the activity status of the device, that is, whether it is moving or stationary, is indicated by the AWAKE bit, described in the Using the AWAKE Bit section. 

Activity and inactivity detection can be used when the accelerometer is in either measurement mode or wake-up mode. However, the activity and inactivity interrupts are not available in wake-up mode because the device is inherently looking for activity in this mode, and any changes to activity or inactivity detection features must be made while the device is in standby mode. 

## _**Low-Pass Activity Detect Filter**_ 

The ADXL372 combines high _g_ impact detection and low _g_ movement detection in one device. For low _g_ detection, an internal low-pass filter with a −3 dB corner of approximately 10 Hz averages data to reduce the rms noise, allowing accurate detection of activity or inactivity thresholds as low as 500 m _g_ . For high _g_ impact detection, the low-pass activity detect filter can be turned off through a register setting. When using both the lowpass activity detect filter and the high-pass filter, the user must select a high-pass filter corner that does not exceed 10 Hz; otherwise, activity detection data is severely attenuated. 

## _**Activity Detection**_ 

An activity event is detected when acceleration in at least one enabled axis remains above a specified threshold for a specified time. Enabled axes, thresholds, and time are user selected. Each axis has its own activity threshold, but the activity timer is shared among all three axes. When multiple axes are selected, an overthreshold event on any one enabled axis triggers the activity detection. 

## **Referenced and Absolute Configurations** 

Activity detection can be configured as referenced or absolute mode for all axes through the ACT_REF bit in the THRESH_ ACT_X_L register. 

When using absolute activity detection, acceleration samples are compared directly to a user set threshold to determine whether motion is present. For example, if a threshold of 0.5 _g_ is set and the acceleration on the z-axis is 1 _g_ longer than the user defined activity time, the activity status asserts. 

In many applications, it is advantageous for activity detection to be based not on an absolute threshold, but on a deviation from a reference point or orientation. The referenced activity detection is particularly useful because it removes the effect on activity detection of the static 1 _g_ imposed by gravity as well as any static offset errors, which can be up to several _g_ . In absolute activity detection, when the threshold is set to less than 1 _g_ , activity is immediately detected in this case. 

In the referenced configuration, activity is detected when acceleration samples are above an internally defined reference by a user defined amount for the user defined amount of time, as described by 

## _Abs_ ( _Acceleration_ − _Reference_ ) > _Threshold_ 

## where _Abs_ is the absolute value. 

Consequently, activity is detected only when the acceleration has deviated sufficiently from the initial orientation. The default setting for the accelerometer is in absolute mode. After it is placed in referenced mode through the appropriate register setting, the reference for activity detection is calculated as soon as full bandwidth measurement mode is turned on. To reset the reference, it is necessary to put the device back into absolute mode and then back to referenced mode. The new reference is set as soon as the device enters full bandwidth measurement mode again. If using both activity and inactivity detection in referenced mode, both must be set back to absolute mode before the reference can be reset. 

## **Activity Timer** 

Ideally, the intent of activity detection is to wake up a system only when motion is intentional, ignoring noise or small, unintentional movements. In addition to being sensitive to low _g_ events, the ADXL372 activity detection algorithm is robust in filtering out undesired triggers. 

The ADXL372 activity detection functionality includes a timer to filter out unwanted motion and ensure that only sustained motion is recognized as activity. The timer period depends on the ODR selected. At 3200 Hz and below, it is ~6.6 ms; at 6400 Hz, it is ~3.3 ms. For activity detection to trigger, above threshold activity must be sustained for a time equal to the number of activity timer periods specified in the activity time register. For example, a setting of 10 in this register means that above threshold activity must be sustained for 66 ms at 3200 Hz ODR. A register value of zero results in single sample activity detection. The maximum allowable activity time is ~1.68 sec (or 841.5 ms at 6400 Hz ODR). Note that the activity timer is operational in measurement mode only. 

Rev. B | Page 16 of 56 

**Data Sheet** 

**ADXL372** 

## **Activity Detection in Wake-Up Mode** 

If activity detection is enabled while the device is in wake-up mode, the device uses single sample activity detection, no matter the activity time register setting. If activity is detected, the device automatically returns to full bandwidth measurement mode. However, the activity interrupt is not generated unless the activity time setting is zero. If it is not zero, after entering measurement mode, the interrupt is not generated until the device sees sustained activity for the amount of time given in the activity time register. The awake interrupt automatically goes high upon entering measurement mode if the device is in default mode or autosleep mode. If it is in linked or loop mode (but not autosleep), it is linked to the activity interrupt, which behaves as previously mentioned. 

After the device automatically enters measurement mode due to activity detection, if autosleep is not on, it must be placed manually back into wake-up mode. 

## _**Inactivity Detection**_ 

An inactivity event is detected when acceleration in all enabled axes remains below a specified threshold for a specified time. Enabled axes, threshold, and time are user selected. Each axis has its own inactivity threshold, but the inactivity timer is shared among all three axes. When multiple axes are selected, all enabled axes must stay under the threshold for the required amount of time to trigger inactivity detection. 

## **Referenced and Absolute Configurations** 

Inactivity detection is also configurable as referenced or absolute through the INACT_REF bit in the THRESH_INACT_X_L register. When using absolute inactivity detection, acceleration samples are compared directly to a user set threshold for the user set time to determine the absence of motion. Inactivity is detected when enough consecutive samples are all below the threshold. 

When using referenced inactivity detection, inactivity is detected when acceleration samples are within a user specified amount from an internally defined reference for a user defined amount of time. 

## _Abs_ ( _Acceleration_ − _Reference_ ) < _Threshold_ 

Referenced inactivity, like referenced activity, is particularly useful for eliminating the effects of the static acceleration due to gravity, as well as other static offsets. With absolute inactivity, if the inactivity threshold is set lower than 1 _g_ , a device resting motionless may never detect inactivity. With referenced inactivity, the same device under the same configuration detects inactivity. The default setting for the accelerometer is in absolute mode. After it is placed in referenced mode through the appropriate register setting, the reference for inactivity detection is calculated as soon as full bandwidth measurement mode is turned on. To reset the reference, it is necessary to put the device back into absolute mode and then back to referenced mode. The new reference is set as soon as the device enters full bandwidth measurement mode again. If using both inactivity and activity detection in referenced mode, both must be set back to absolute mode before the reference can be reset. 

## **Inactivity Timer** 

The ADXL372 inactivity detect functionality includes a timer to allow detection of sustained inactivity. The timer period depends on the ODR selected. At 3200 Hz and below, it is ~26 ms; at 6400 Hz, it is ~13 ms. For inactivity detection to trigger, below threshold inactivity must be sustained for a time equal to the number of inactivity timer periods specified in the inactivity time registers. For example, a setting of 10 in these registers means that below threshold inactivity must be sustained for 260 ms at 3200 Hz ODR. A value of zero in these registers results in single sample, inactivity detection. The maximum allowable inactivity time is ~28.4 minutes at 3200 Hz ODR (or ~14.2 minutes at 6400 Hz ODR). 

## _**Linking Activity and Inactivity Detection**_ 

When in measurement mode or wake-up mode, the activity and inactivity detection functions can be used concurrently and processed manually by a host processor, or they can be configured to interact in several other ways, such as those that follow. 

## **Default Mode** 

In default mode, activity and inactivity detection are both available simultaneously, and all interrupts must be serviced by a host processor; that is, a processor must read each interrupt before it is cleared and can be used again. Refer to the Interrupts section for information on clearing interrupts. 

The flowchart in Figure 31 illustrates default mode operation. 

**==> picture [213 x 174] intentionally omitted <==**

**----- Start of picture text -----**<br>
WAIT FOR WAIT FOR<br>ACTIVITY PROCESSOR TO<br>EVENT CLEAR INTERRUPT<br>AWAKE = 1<br>INACTIVITY<br>INTERRUPT<br>TRIGGERS<br>ACTIVITY<br>INTERRUPT<br>TRIGGERS<br>AWAKE = 1<br>WAIT FOR WAIT FOR<br>PROCESSOR TO INACTIVITY<br>CLEAR INTERRUPT EVENT<br>NOTES<br>1. THE AWAKE BIT DEFAULTS TO 1 WHEN ACTIVITY AND INACTIVITY<br>    ARE NOT LINKED. 15430-031<br>**----- End of picture text -----**<br>


_Figure 31. Flowchart Illustrating Activity and Inactivity Operation in Default Mode_ 

Rev. B | Page 17 of 56 

**ADXL372** 

**Data Sheet** 

## **Linked Mode** 

In linked mode, activity and inactivity detection are linked to each other such that only one of the functions is enabled at any given time. As soon as activity is detected, the device is assumed to be moving (or awake) and stops looking for activity; rather, inactivity is expected as the next event. Therefore, only inactivity detection operates. 

Similarly, when inactivity is detected, the device is assumed to be stationary (or asleep). Thus, activity is expected as the next event; therefore, only activity detection operates. 

In linked mode, each interrupt must be serviced by a host processor before the next interrupt is enabled. 

The flowchart in Figure 32 illustrates linked mode operation. 

**==> picture [237 x 90] intentionally omitted <==**

**----- Start of picture text -----**<br>
WAIT FOR WAIT FOR AWAKE = 0 INACTIVITY<br>ACTIVITY PROCESSOR TO<br>INTERRUPT<br>EVENT CLEAR INTERRUP<br>AWAKE = 1 WAIT FOR WAIT FOR<br>ACTIVITY PROCESSOR TO INACTIVITY<br>INTERRUPT CLEAR INTERRUPT EVENT<br>15430-032<br>**----- End of picture text -----**<br>


_Figure 32. Flowchart Illustrating Activity and Inactivity Operation in Linked Mode_ 

## **Loop Mode** 

In loop mode, motion detection operates as described in the Linked Mode section, but interrupts do not need to be serviced by a host processor. This configuration simplifies the implementation of commonly used motion detection and enhances power savings by reducing the amount of power used in bus communication. 

The flowchart in Figure 33 illustrates loop mode operation. 

**AWAKE = 1** 

**==> picture [183 x 68] intentionally omitted <==**

**----- Start of picture text -----**<br>
WAIT FOR WAIT FOR<br>ACTIVITY INACTIVITY<br>EVENT EVENT<br>AWAKE = 0 15430-033<br>**----- End of picture text -----**<br>


_Figure 33. Flowchart Illustrating Activity and Inactivity Operation in Loop Mode_ 

## **Autosleep** 

If autosleep is selected, after the device is placed in wake-up mode (see the Wake-Up Mode section), it automatically sets to loop mode and begins looking for activity. When activity is detected, the device automatically enters measurement mode and immediately begins looking for inactivity. When inactivity is detected, the device automatically re-enters wake-up mode. Note that the device must be manually placed in wake-up mode before autosleep can begin functioning. It does not automatically enter wake-up mode if the device is started up manually in measurement mode. 

## _**Using the AWAKE Bit**_ 

The AWAKE bit is a status bit that indicates whether the ADXL372 is awake or asleep. In default mode or autosleep mode, the AWAKE bit is high whenever the device is in measurement mode. In linked or loop mode, the AWAKE bit is high whenever the device experiences an activity condition, and it is low when the device experiences an inactivity condition. 

The awake signal can be mapped to the INT1 or the INT2 pin allowing the pin to serve as a status output to connect or disconnect power to downstream circuitry based on the awake status of the accelerometer. Used in conjunction with loop mode, this configuration implements a simple, autonomous motion activated switch. 

If the turn-on time of downstream circuitry can be tolerated, this motion switch configuration can save significant system level power by eliminating the standby current consumption of the remainder of the application circuit. This standby current can often exceed the full operating current of the ADXL372. 

## **MOTION WARNING** 

In addition to the activity threshold previously described, the ADXL372 offers a secondary threshold. This second threshold, the motion warning threshold, can be set independently of the activity threshold. It does not have any functionality related to autosleep, linked, or loop mode, or the device awake status. The purpose of the motion warning functionality is to issue a notification to the system, via the status bit and/or interrupt, that the observed acceleration has exceeded the second threshold. It is controlled by the THRESH_ACT2_x_x registers, and by the ACTIVITY2 interrupt, which is sent only to the INT2 pin. Each axis has its own motion warning threshold. However, the motion warning activity interrupt does not have an activity timer. It is only used for single sample, activity detection. The motion warning threshold also shares the same referenced vs. absolute configuration as the primary activity detection. 

Rev. B | Page 18 of 56 

**Data Sheet** 

**ADXL372** 

## **IMPACT DETECTION FEATURES** 

Impact detection applications often require high _g_ and high bandwidth acceleration measurements, and the ADXL372 is designed with these applications in mind. Several features are included that target impact detection and aim to simplify the system design. 

## **WIDE BANDWIDTH** 

An impact is a transient event that produces an acceleration pulse with frequency content over a wide range. A sufficiently wide bandwidth is needed to capture the impact event because lowering bandwidth has the effect of reducing the magnitude of the recorded signal, resulting in measurement inaccuracy. 

The ADXL372 can operate with bandwidths of up to 3200 Hz at extremely low power levels. A steep filter roll-off is also useful for effective suppression of out of band content, and the ADXL372 incorporates a four-pole, low-pass antialiasing filter for this purpose. 

## **INSTANT ON IMPACT DETECTION** 

The ADXL372 instant on mode is an ultralow power mode that continuously monitors the environment for impact events that exceed a built in threshold. When an impact is detected, the device switches into full measurement mode and captures the impact profile. 

User must enter instant on mode from full bandwidth measurement mode with 16 ms delay before the first valid data gets ready. No digital data is available in this mode of operation. The user can configure the device to detect an impact between a threshold level of either 10 _g_ to 15 _g_ or 30 _g_ to 40 _g_ by using the INSTANT_ON_ THRESH bit in the POWER_CTL register. When an impact beyond the selected threshold is detected, the ADXL372 switches to full bandwidth measurement mode and begins outputting digital data. 

**==> picture [242 x 95] intentionally omitted <==**

**----- Start of picture text -----**<br>
DATA IS RECORDED AS SOON AS<br>IT ENTERS MEASUREMENT MODE<br>20<br>ACCELERATION < THRESHOLD<br>INSTANT ON MODE (~2µA) MEASUREMENT MODE<br>) g<br>ACCELERATION (<br>15430-034<br>**----- End of picture text -----**<br>


_Figure 34. Instant On Mode Using Default Threshold_ 

After the accelerometer is in full bandwidth measurement mode, it must be set back into instant on mode manually. It cannot return to instant on mode automatically. 

## **CAPTURING IMPACT EVENTS** 

In certain applications, a single (3-axis) acceleration sample at the peak of an impact event contains sufficient information about the event, and the full acceleration history is not required. For these applications, the ADXL372 provides the capability to store only the peak acceleration of each over threshold event. The x, y, and z acceleration samples at the peak of the event can be stored in the FIFO. Applications that do not require the full event profile can greatly increase the time between FIFO reads by storing only peak acceleration information. A peak is defined as the x, y, and z acceleration sample that has the highest magnitude (root sum squared) of all other values within a particular over threshold event. In addition to recording the peak of each over threshold impact event in the FIFO, the ADXL372 can also keep track of the absolute highest peak recorded in separate registers. 

**==> picture [238 x 95] intentionally omitted <==**

**----- Start of picture text -----**<br>
TIME INACT<br>) g<br>ACCELERATION (<br>15430-035<br>**----- End of picture text -----**<br>


_Figure 35. Capturing Impact Events_ 

Enable peak detection by doing the following: 

- Put the FIFO in peak detect and stream mode (b0011101x to Register 0x3A). 

- Set the desired activity threshold and time settings (Register 0x23 to Register 0x29). 

- Set the desired inactivity threshold and time settings (Register 0x2A to Register 0x31). 

- Set the activity mode to linked or loop mode (Register 0x3E). 

As soon as the activity interrupt is triggered, the device records the x, y, and z values of the peak acceleration event that occurs between the activity interrupt trigger and the next inactivity interrupt trigger, as shown in Figure 35 in the FIFO. It continues to do this for each period of activity between the triggering of the activity interrupt and consequent triggering of the inactivity interrupt. The process does work in linked mode, but the user must be clear each interrupt before the device looks for the next activity or inactivity interrupt. For as long as peak detect mode is selected, the device also stores the highest overall peak recorded in the MAXPEAK_x_x registers. When these values are read out of the registers, the register data is cleared, and the device begins looking for the new highest peak. 

Rev. B | Page 19 of 56 

**ADXL372** 

**Data Sheet** 

## **FIFO** 

The ADXL372 includes a deep, 512 sample FIFO buffer. 

## **BENEFITS OF THE FIFO** 

The FIFO buffer is an important feature in ultralow power applications in two ways: system level power savings and data recording/event context. 

## _**System Level Power Savings**_ 

Appropriate use of the FIFO enables system level power savings by enabling the host processor to sleep for extended periods while the accelerometer autonomously collects data. Alternatively, using the FIFO to collect data can unburden the host while it tends to other tasks. 

## _**Data Recording/Event Context**_ 

The FIFO can be used in a triggered mode to record all data leading up to an activity detection event, thereby providing context for the event. In the case of a system that identifies impact events, for example, the accelerometer can keep the entire system off while it stores acceleration data in its FIFO and looks for an activity event. When the impact event occurs, data collected prior to the event is frozen in the FIFO. The accelerometer can now wake the rest of the system and transfer this data to the host processor, thereby providing context for the impact event. 

Generally, the more context available, the more intelligent decisions a system can achieve, making a deep FIFO especially useful. For example, the ADXL372 FIFO can store up to 512 1-axis samples at 400 Hz ODR, providing a 1.28 sec window, or 170 3-axis samples at 3200 Hz to provide a 50 ms window, which is a typical duration for impact events. 

## **USING THE FIFO** 

The FIFO is a 512 sample memory buffer that can save power, unburden the host processor, and autonomously record data. FIFO operation is configured via Register 0x39 and Register 0x3A. The 512 FIFO samples can be allotted in several ways, such as the following: 

- 170 sample sets of concurrent 3-axis data 

- 256 sample sets of concurrent 2-axis data (user selectable) 

- 512 sample sets of single-axis data 

- 170 sets of impact event peak (x, y, z) 

All FIFO modes must be configured while in standby mode. When reading data from multiple axes from the FIFO, to ensure that data is not overwritten and stored out of order, at least one sample set must be left in the FIFO after every read (therefore, a set of 3-axis data must have 169 samples at most). 

## _**FIFO Disabled**_ 

When the FIFO is disabled, no new data is stored in it, and any data already in it is cleared. 

The FIFO is disabled by setting the FIFO_MODE bits in the FIFO_CTL register (Register 0x3A) to 0b00. 

## _**Oldest Saved Mode (First N)**_ 

In oldest saved mode, the FIFO accumulates data until it is full and then stops. After reading the data, the FIFO must be disabled and re-enabled to save a new set of data. One possible use case for this mode is to enable it right after entering instant on mode. After a shock is detected, the data immediately stores in the FIFO to be read whenever convenient. 

The FIFO is placed into oldest saved mode by setting the FIFO_MODE bits in the FIFO_CTL register (Register 0x3A) to 0b11. 

## _**Stream Mode (Last N)**_ 

In stream mode, the FIFO always contains the most recent data. The oldest sample is discarded when space is needed to make room for a newer sample. 

Stream mode is useful for unburdening a host processor. The processor can tend to other tasks while data is being collected in the FIFO. When the FIFO fills to a certain number of samples (specified by the FIFO_SAMPLES register along with Bit 0 in the FIFO_CTL register), it triggers a watermark interrupt (if this interrupt is enabled). At this point, the host processor can read the contents of the entire FIFO and then return to its other tasks as the FIFO fills again. 

The FIFO is placed into stream mode by setting the FIFO_MODE bits in the FIFO_CTL register (Register 0x3A) to 0b01. 

## _**Triggered Mode**_ 

In triggered mode, the FIFO operates as in stream mode until an activity detection event, after which it saves the samples surrounding that event. The operation is similar to a one-time run trigger on an oscilloscope. The number of samples to be saved after the activity event is specified in FIFO_SAMPLES (Register 0x39[7:0], along with Bit 0 in the FIFO_CTL register, Register 0x3A). For example if the FIFO_SAMPLE is set to 12, there are 500 samples before the trigger and 12 after the trigger. The trigger can be reset by clearing the activity interrupt and reading all 512 locations of the FIFO. If this is not complete, future FIFO data reads may contain invalid data. Place the FIFO into triggered mode by setting the FIFO_MODE bits in the FIFO_CTL register (Register 0x3A) to 0b10. 

The FIFO operates in one of the following four modes: FIFO disabled, oldest saved mode (first N), stream mode (last N), and triggered mode. 

Rev. B | Page 20 of 56 

**Data Sheet** 

**ADXL372** 

## **RETRIEVING DATA FROM FIFO** 

Access FIFO data by reading the FIFO_DATA register. A multibyte read to this register does not auto-increment the address, and instead continues to pop data from the FIFO. Data is left justified and formatted as shown in Table 10. 

When reading data, the most significant byte (Bits[B15:B8]) is read first, followed by the least significant byte (Bits[B7:B0]). Bits[B15:B4] represent the 12-bit, twos complement acceleration data. Bit 0 serves as a series start indicator: only the first data byte of a series contains a 1 in this bit, and the remaining items contain a 0. 

**Table 10. FIFO Buffer Data Format** 

|**B15 (MSB)**|**B14**|**B13**|**B12**|**B11**|**B10**|**B9**|**B8**|
|---|---|---|---|---|---|---|---|
|||||Data||||
|**B7**|**B6**|**B5**|**B4**|**B3**|**B2**|**B1**|**B0**|
|Data||||Reserved|||Series start indicator|



Rev. B | Page 21 of 56 

**ADXL372** 

**Data Sheet** 

## **INTERRUPTS** 

Several of the built in functions of the ADXL372 can trigger interrupts to alert the host processor of certain status conditions. The functionality of these interrupts is described in this section. 

## **INTERRUPT PINS** 

Interrupts can be mapped to either (or both) of two designated output pins, INT1 and INT2, by setting the appropriate bits in the INT1_MAP register and INT2_MAP register, respectively. All functions can be used simultaneously. If multiple interrupts are mapped to one pin, the OR combination of the interrupts determines the status of the pin. 

If no functions are mapped to an interrupt pin, that pin is automatically configured to a high impedance (high-Z) state. The pins are also placed in the high-Z state upon a reset. 

When a certain status condition is detected, the pin that condition is mapped to is activated. The configuration of the pin is active high by default so when it is activated, the pin goes high. However, this configuration can be switched to active low by setting the INTx_LOW bit in the appropriate INTx_MAP register. 

The INTx pins can connect to the interrupt input of a host processor where interrupts are responded to with an interrupt routine. Because multiple functions can be mapped to the same pin, the STATUS register can determine which condition caused the interrupt to trigger. 

Interrupts are cleared in several of the following ways: 

- Reading the STATUS2 register clears ACTIVITY and INACT interrupts. However, if activity detection is operating in default mode, and the activity or inactivity timers are set to 0, the only way to clear the activity or inactivity bits, respectively, is to set the device into standby mode and restart full bandwidth measurement mode. 

- Setting the device into standby mode and back into full bandwidth measurement mode clears the ACTIVITY2 interrupt. 

- Reading from the data registers clears the DATA_RDY interrupt. 

- Reading enough data from the FIFO buffer so that interrupt conditions are no longer met, and then reading the STATUS register (Register 0x04) clears the FIFO_RDY, FIFO_FULL, and FIFO_OVR interrupts. 

Both interrupt pins are push-pull low impedance pins with an output impedance of about 500 Ω (typical) and digital output specifications as shown in Table 11. Both have bus keepers that hold them to a valid logic state when they are in a high impedance mode. 

To prevent interrupts from being falsely triggered during configuration, disable interrupts while their settings, such as thresholds, timings, or other values, are configured. 

## _**Alternate Functions**_ 

The INT1 and INT2 pins can be configured for use as input pins instead of for signaling interrupts. INT1 is used as an external clock input when the EXT_CLK bit in the TIMING register is set. INT2 is used as the trigger input for synchronized sampling when the EXT_SYNC bit in the TIMING register is set. One or both of these alternate functions can be used concurrently; however, if an interrupt pin is used for its alternate function, it cannot simultaneously be used to signal interrupts. 

## **TYPES OF INTERRUPTS** 

## _**Activity and Inactivity Interrupts**_ 

The ACTIVITY bit and INACT bit are set when activity and inactivity are detected, respectively. Detection procedures and criteria are described in the Autonomous Event Detection section. 

## _**Data Ready Interrupt**_ 

The DATA_RDY bit is set when new valid data is available, and it is cleared when no new data is available. 

The DATA_RDY bit does not set while any of the data registers are being read. If DATA_RDY = 0 prior to a register read and new data becomes available during the register read, DATA_RDY remains 0 until the read is complete and only then sets to 1. 

If DATA_RDY = 1 prior to a register read, it is cleared at the start of the register read. 

If DATA_RDY = 1 prior to a register read and new data becomes available during the register read, DATA_RDY is cleared to 0 at the start of the register read and remains 0 throughout the read. When the read is complete, DATA_RDY is set to 1. 

## _**FIFO Interrupts**_ 

## **FIFO Watermark** 

The FIFO_FULL bit is set when the number of samples stored in the FIFO is equal to or exceeds the number specified in FIFO_SAMPLES (Register 0x39 together with Bit 0 in the FIFO_CTL register). The FIFO_FULL bit is cleared automatically when enough samples are read from the FIFO, such that the number of samples remaining is lower than that specified. 

If the number of FIFO samples is set to 0, the watermark interrupt is set. To avoid unexpectedly triggering this interrupt, the default value of the FIFO_SAMPLES register is 0x80. 

## **FIFO Ready** 

The FIFO_RDY bit is set when there is at least one valid sample available in the FIFO output buffer. This bit is cleared when no valid data is available in the FIFO. In FIFO triggered mode, it is only set after the activity interrupt is detected, and the data surrounding the event is saved in the FIFO. 

Rev. B | Page 22 of 56 

**Data Sheet** 

**ADXL372** 

## **Overrun** 

The FIFO_OVR bit is set when the FIFO has overrun or overflowed, such that new data replaces unread data, which may indicate a full FIFO that has not yet been emptied or a clocking error caused by a slow SPI transaction. If the FIFO is configured to oldest saved mode, an overrun event indicates that there is insufficient space available for a new sample. 

The FIFO_OVR bit is cleared when both the contents of the FIFO and the STATUS register are read. It is also cleared when the FIFO is disabled. 

**Table 11. Interrupt Pin Digital Output** 

|**Table 11. Interrupt Pin Digital Output**||||
|---|---|---|---|
|**Parameter**|**Test Conditions**|**Limit1**|**Unit**|
|||**Min**<br>**Max**||
|Digital Output<br>Low Level Output Voltage (VOL)<br>High Level Output Voltage (VOH)<br>Low Level Output Current (IOL)<br>High Level Output Current (IOH)<br>Pin Capacitance<br>Rise/Fall Time<br>Rise Time (tR)2<br>Fall Time (tF)3|IOL= 500 µA<br>IOH= −300 µA<br>VOL= VOL, MAX<br>VOH= VOH, MIN<br>fIN= 1 MHz, VIN= 2.0 V<br>CLOAD= 150 pF<br>CLOAD= 150pF|0.2 × VDDI/O<br>0.8 × VDDI/O<br>500<br>−300<br>8<br>210<br>150|V<br>V<br>µA<br>µA<br>pF<br>ns<br>ns|



1 Limits based on characterization results, not production tested. 

2 Rise time is measured as the transition time from VOL, MAX to VOH, MIN of the interrupt pin. 

3 Fall time is measured as the transition time from VOH, MIN to VOL, MAX of the interrupt pin. 

Rev. B | Page 23 of 56 

**Data Sheet** 

## **ADXL372** 

## **ADDITIONAL FEATURES** 

## **USING AN EXTERNAL CLOCK** 

When operating at 3200 Hz ODR or lower, the ADXL372 has a built in 307.2 kHz (typical) clock that, by default, serves as the time base for internal operations. At 6400 Hz ODR, this clock speed increases to 614.4 kHz (typical). If desired, an external clock can be provided instead, for either improved clock frequency accuracy or for control of the output data rate. To use an external clock, set the EXT_CLK bit (Bit 1) in the TIMING register (Register 0x3D) and apply a clock to the INT1 pin. 

The external clock can operate at the nominal 307.2 kHz or slower (when using ODR ≤ 3200 Hz), or 614.4 kHz or slower (when using ODR = 6400 Hz) to allow the user to achieve any desired output data rate. Lower external clock rates must be used with caution because it may result in aliasing of high frequency signals that may be present in certain applications. 

ODR and bandwidth scale proportionally with the clock. The ADXL372 provides a discrete number of options for ODR. ODRs other than those provided are achieved by selecting an appropriate clock frequency. For example, to achieve a 2560 Hz ODR, use the 3200 Hz setting with a clock frequency that is 80% of nominal, or 245.76 kHz. Bandwidth also scales by the same ratio, so if a 400 Hz bandwidth is selected, the resulting bandwidth is 320 Hz. 

## **SYNCHRONIZED DATA SAMPLING** 

For applications that require a precisely timed acceleration measurement, the ADXL372 features an option to synchronize acceleration sampling to an external trigger. The EXT_SYNC bit in the TIMING register enables this feature. When the EXT_SYNC bit is set to 1, the INT2 pin automatically reconfigures for use as the sync trigger input. 

When external triggering is enabled, it is up to the system designer to ensure that the sampling frequency meets system requirements. Sampling too infrequently causes aliasing. Noise can be lowered by oversampling; however, sampling at too high a frequency may not allow enough time for the accelerometer to process the acceleration data and convert it to valid digital output data. 

These values are doubled when an ODR rate of 6400 Hz is selected. Additionally, the trigger signal applied to the INT2 pin must meet the following criteria: 

- The trigger signal must be active high. 

- The pulse width of the trigger signal must be at least 53 µs. 

- • The minimum sampling frequency is set only by system requirements. Samples need not be polled at any minimum rate; however, if samples are polled at a rate lower than the bandwidth set by the antialiasing filter, aliasing may occur. 

The EXT_SYNC is an active high signal. Due to the asynchronous nature of the internal clock and external sync, there may be a one ODR clock cycle difference between consecutive external sync pulses. The external sync sets the ODR of the system. For example, if sending an external sync at a 2 kHz rate, all 3 axes (if enabled) are sampled in that 2 kHz window. 

## **SELF TEST** 

The ADXL372 incorporates a pass or fail self test feature that effectively tests its mechanical and electronic systems simultaneously. When the self test function is invoked, an electrostatic force is applied to the mechanical sensor. This electrostatic force moves the mechanical sensing element in the same manner as acceleration, and the acceleration experienced by the device increases because of this force. 

## _**Self Test Procedure**_ 

The self test function is enabled via the ST bit in the SELF_TEST register, Register 0x40. The recommended procedure for using the self test functionality is as follows: 

1. Place the device into measurement mode. 

2. Make sure the low-pass activity filter is enabled. 

3. Assert self test by setting the ST bit in the SELF_TEST register (Register 0x40). 

Read the self test status bits, ST_DONE and USER_ST, after approximately 300 ms to check the pass or fail condition. 

When the Nyquist criterion is met, signal integrity is maintained. An internal antialiasing filter is available in the ADXL372 and can assist the system designer in maintaining signal integrity. To prevent aliasing, set the filter bandwidth to a frequency no greater than half the sampling rate. For example, when sampling at 1600 Hz, set the filter bandwidth to no higher than 800 Hz. 

Because of internal timing requirements, the maximum allowable external trigger frequencies are as follows: 

- 1-axis data = 3100 Hz 

- 2-axis data = 2700 Hz 

- 3-axis data = 2200 Hz 

Rev. B | Page 24 of 56 

**Data Sheet** 

**ADXL372** 

## **USER REGISTER PROTECTION** 

The ADXL372 includes user register protection for single event upsets (SEUs). An SEU is a change of state caused by ions or electromagnetic radiation striking a sensitive node in a microelectronic device. The state change is a result of the free charge created by ionization in or close to an important node of a logic element (for example, a memory bit). The SEU itself is not considered permanently damaging to transistor or circuit functionality, but can create erroneous register values. The registers protected from SEU are Register 0x20 to Register 0x3F. 

Protection is implemented via a 99-bit error correcting (Hamming type) code and detects both single bit and double bit errors. The check bits are recomputed any time a write to any of the protected registers occurs. At any time, if the stored version of the check bits is not in agreement with the current check bit calculation, the ERR_USER_REGS status bit is set. 

The ERR_USER_REGS bit in the STATUS register starts high when set on an unconfigured device and clears upon the first register write. 

## **USER OFFSET TRIMS** 

The ADXL372 has a 4-bit offset trim for each axis that allows users to add positive or negative offset to the default static acceleration values and correct any deviations from ideal that may result as a consequence of varying the operating parameters of the device. The offset trims have a full-scale range of about ±60 LSB with a trim profile as shown in Figure 36. 

**==> picture [213 x 180] intentionally omitted <==**

**----- Start of picture text -----**<br>
80<br>X-AXIS<br>Y-AXIS<br>60 Z-AXIS<br>40<br>20<br>0<br>–20<br>–40<br>–60<br>–80<br>0 2 4 6 8 10 12 14 16<br>REGISTER VALUE<br>Figure 36. User Offset Trim Profile<br>OFFSET CHANGE (LSB)<br>15430-036<br>**----- End of picture text -----**<br>


Rev. B | Page 25 of 56 

**ADXL372** 

**Data Sheet** 

## **SERIAL COMMUNICATIONS** 

## **SERIAL INTERFACE** 

The ADXL372 is designed to communicate in either the SPI or the I[2] C protocol. It autodetects the format being used, requiring no configuration control to select the format. 

## _**SPI Protocol**_ 

The timing scheme is as follows: CPHA = CPOL = 0. The ADXL372 supports a SCLK frequency up to 10 MHz. Wire the ADXL372 for SPI communication as shown in Figure 37. For successful communication, follow the logic thresholds and timing parameters in Table 12. The command structure for the read register and write register are shown in Figure 40 and Figure 41, respectively. The read and write register commands support multibyte (burst) read/write access. The waveform diagrams for multibyte read and write commands are shown in Figure 42 and Figure 43, respectively. 

Ignore data transmitted from the ADXL372 to the master device during writes to the ADXL372. 

**==> picture [149 x 80] intentionally omitted <==**

**----- Start of picture text -----**<br>
PROCESSOR<br>CS DOUT<br>MOSI DOUT<br>MISO DIN<br>SCLK DOUT<br>15430-037<br>**----- End of picture text -----**<br>


_Figure 37. 4-Wire SPI Connection Diagram_ 

## _**I[2] C Protocol**_ 

The ADXL372 supports point to point I[2] C communication. However, for devices with REVID = 0x02, when sharing an SDA bus, the ADXL372 may prevent communication with other devices on that bus. If at any point, even when the ADXL372 is not being addressed, the 0x3A or 0x3B bytes (when the ADXL372 Device ID is set to 0x1D), or the 0xA6 or 0xA7 bytes (when the ADXL372 Device ID is set to 0x53) are transmitted on the SDA bus, the ADXL372 responds with an acknowledge bit and pulls the SDA line down. For example, this can happen when reading or writing the data bytes to another sensor on the bus. When the ADXL372 pulls the SDA line down, communication with other devices on the bus may be interrupted. To work around this issue, the ADXL372 must be connected to a separate SDA bus, or the SCLK pin must be switched high when communication with the ADXL372 is not desired (it must be normally grounded). 

The ADXL372 supports standard (100 kHz), fast (up to 1 MHz), and high speed (up to 3.4 MHz) data transfer modes if the bus parameters given in Table 13 are met. There is no minimum SCL frequency, with the exception that when reading data, the clock must be fast enough to read an entire sample set before new data overwrites it. Single byte or multibyte reads/writes are supported. With the MISO pin low, the I[2] C address for the device is 0x1D, and an alternate I[2] C address of 0x53 can be chosen by pulling the MISO pin high. 

There are no internal pull-up or pull-down resistors for any unused pins; therefore, there is no known state or default state for the pins if left floating or unconnected. It is a requirement that SCLK be connected to ground when communicating to the ADXL372 using the I[2] C. 

Due to communication speed limitations, the maximum output data rate when using 400 kHz I[2] C is 800 Hz and scales linearly with a change in the I[2] C communication speed. For example, using I[2] C at 100 kHz limits the maximum ODR to 200 Hz. Operation at an output data rate above the recommended maximum can result in undesirable effect on the acceleration data, including missing samples or additional noise. 

**==> picture [160 x 99] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD I/O<br>ADXL372 RP RP PROCESSOR<br>MISO<br>SDA D IN/OUT<br>SCLK<br>SCL D OUT 15430-038<br>**----- End of picture text -----**<br>


_Figure 38. I[2] C Connection Diagram (ADXL372 Device ID = 0x53)_ 

If other devices are connected to the same I[2] C bus, the nominal operating voltage level of these other devices cannot exceed VDDI/O by more than 0.3 V. External pull-up resistors, RP, are necessary for proper I[2] C operation. Single byte or multibyte reads/writes are supported, as shown from Figure 45 to Figure 47. 

## **MULTIBYTE TRANSFERS** 

Both the SPI and I[2] C protocols support multibyte transfers, also known as burst transfers. A register read or write begins with the address specified in the command and auto-increments for each additional byte in the transfer. Always read acceleration data using multibyte transfers to ensure a concurrent and complete set of x-, y-, and z-acceleration data is read. 

The FIFO runs on the serial port clock during FIFO reads and can sustain bursting at the SPI clock rate as long as the SPI clock is 1 MHz or faster. 

The address auto-increment function is disabled when the FIFO address is used, which is so that data can be read continuously from the FIFO as a multibyte transaction. In cases where the starting address of a multibyte transaction is less than the FIFO address, the address auto-increments until the FIFO address is reached, and then it stops at the FIFO address. 

When writing data to the ADXL372 in I[2] C mode, the no acknowledge (NACK) is never generated. Instead, the acknowledge (ACK) bit is sent after every received byte because it is not known how many bytes are included in the transfer. The master decides how many bytes are sent and ends the transaction with the stop condition. 

Rev. B | Page 26 of 56 

**Data Sheet** 

**ADXL372** 

## **INVALID ADDRESSES AND ADDRESS FOLDING** 

The ADXL372 has a 6-bit address bus, mapping only 104 registers in the possible 256 register address space. The addresses do not fold to repeat the registers at addresses above 0x104. Attempted access to register addresses above 0x104 are mapped to the invalid register at 0x67 and have no functional effect. 

Register 0x00 to Register 0x42 are for customer access, as described in Table 14. Register 0x43 to Register 0x67 are reserved for factory use. 

TA = 25°C, VS = 2.5 V, VDDI/O = 2.5 V, unless otherwise noted. 

**Table 12. SPI Logic Levels and Timing** 

|**Parameter**|**Description**|**Min**<br>**Typ**<br>**Max**|**Unit**|
|---|---|---|---|
|INPUT DC LEVELS<br>VIL<br>VIH<br>IIL<br>IIH|Low level input voltage<br>High level input voltage<br>Low level input current, VIN= 0 V<br>High level input current, VIN= VDDI/O|0.3 × VDDI/O<br>0.7 × VDDI/O<br>−0.1<br>0.1|V<br>V<br>μA<br>μA|
|OUTPUT DC LEVELS<br>VOL<br>VOH<br>IOL<br>IOH|Low level output voltage, IOL= IOL, MIN<br>High level output voltage, IOL= IOH, MAX<br>Low level output current, VOL= VOL, MAX<br>High level output current, VOL= VOH, MIN|0.2 × VDDI/O<br>0.8 × VDDI/O<br>−10<br>4|V<br>V<br>mA<br>mA|
|INPUT AC<br>SCLK Frequency<br>tHIGH<br>tLOW<br>tCSS<br>tCSH<br>tCSD<br>tSCLKS<br>tSU<br>tHD|SCLK high time<br>SCLK low time<br>CS<br>setup time<br>CS<br>hold time<br>CS<br>disable time<br>Rising SCLK setup time<br>MOSI setup time<br>MOSI hold time|0.1<br>10<br>40<br>40<br>20<br>20<br>40<br>20<br>20<br>20|MHz<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns|
|OUTPUT AC<br>tP<br>tEN<br>tDIS|Propagation delay, CLOAD= 30 pF<br>Enable MISO time<br>Disable MISO time|30<br>30<br>20|ns<br>ns<br>ns|



## _**SPI Timing Diagrams**_ 

**==> picture [458 x 146] intentionally omitted <==**

**----- Start of picture text -----**<br>
tCSD<br>CS<br>tCSS tHIGH tLOW tCSH tSCLKS<br>SCLK<br>tSU tHD<br>MOSI<br>tEN tP tDIS<br>MISO 15430-046<br>**----- End of picture text -----**<br>


_Figure 39. SPI Timing Diagram_ 

Rev. B | Page 27 of 56 

**ADXL372** 

**Data Sheet** 

**==> picture [432 x 381] intentionally omitted <==**

**----- Start of picture text -----**<br>
ee CS  /<br>1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16<br>SCLK<br>UU<br>MOSI A6 A5 A4 A3 A2 A1 A0 RW<br>300000000<br>MISO D7 D6 D5 D4 D3 D2 D1 D0<br>Ac<br>||<br>Figure 40. SPI Timing Diagram, Single Byte Read<br>a CS<br>1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16<br>SCLK<br>UU<br>MOSI A6 A5 A4 A3 A2 A1 A0 RW D7 D6 D5 D4 D3 D2 D1 D0<br>MO0GGRGG0G000000000C<br>MISO<br>Figure 41. SPI Timing Diagram, Single Byte Write<br>S CS Y<br>1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17<br>SCLK<br>OO<br>MOSI A6 A5 A4 A3 A2 A1 A0 RW<br>00000000<br>BYTE 1 BYTE n<br>——— | ——a ———+|<br>MISO D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0<br>Figure 42. SPI Timing Diagram, Mulitbyte Read<br>CS a<br>1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17<br>SCLK<br>OTE.<br>BYTE 1 BYTE n<br>MOSI A6 A5 A4 A3 A2 A1 A0 RW a D7 D6 D5 D4 D3 D2 ———> D1 D0 D7 D0 --—— D7 D6 D5 D4 D3 D2 D1 D0<br>MISO<br>15430-039<br>15430-040<br>15430-041<br>15430-042<br>**----- End of picture text -----**<br>


_Figure 43. SPI Timing Diagram, Multibyte Write_ 

Rev. B | Page 28 of 56 

**Data Sheet** 

**ADXL372** 

TA = 25°C, VS = 2.5 V, VDDI/O = 1.8 V, unless otherwise noted. 

**Table 13. I[2] C Logic Level and Timing** 

|**Table 13. I[2]C Logic Level and Timinggic Level and Timingic Level and Timingg**|||
|---|---|---|
|**Parameter**<br>**Description**<br>**Min**|**I2C_HSM_EN = 0**<br>**I2C_HSM_EN = 1**<br>**Typ**<br>**Max**<br>**Min**<br>**Typ**<br>**Max**|**Unit**|
|INPUT AC<br>SCLK Frequency<br>0<br>tHIGH<br>SCLK high time<br>260<br>tLOW<br>SCLK low time<br>500<br>tSUSTA<br>Start setup time<br>260<br>tHDSTA<br>Start hold time<br>260<br>tSUDAT<br>Data setup time<br>50<br>tHDDAT<br>Data hold time<br>0<br>tSUSTO<br>Stop setup time<br>260<br>tBUF<br>Bus free time<br>500<br>tRCL<br>SCL input rise time<br>tFCL<br>SCL input fall time<br>20 × (V<br>tRDA<br>SDA input rise time<br>tFDA<br>SDA input fall time<br>20 × (V|1<br>0<br>3.4<br>120<br>320<br>160<br>160<br>10<br>0<br>150<br>160<br>120<br>20<br>80<br>20 × (VDD/5.5)<br>120<br>20<br>80<br>120<br>20<br>160<br>20 × (VDD/5.5)<br>120<br>20<br>160|MHz<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns|
|OUTPUT AC<br>CLOAD|550<br>400|pF|



## _**I[2] C Timing Diagrams**_ 

**tFDA tRDA tBUF SDA tSUSTA tHDSTA tSUDAT tHDDAT tLOW tHIGH tRCL tFCL tSUSTO tSUSTA SCL** _Figure 44. I[2] C Timing Diagram_ **1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 SCL** ~~T~~ UTT ~~O~~ **START DEVICE ADDRESS REGISTER ADDRESS STARTRPT. DEVICE ADDRESS DATA BYTE STOP SDA** ~~i~~ **A6 A5 A4 A3 A2 A1 A0** ~~=a~~ **RW AK 0 A6 A5 A4 A3 A2 A1** ~~<a~~ **A0 AK A6 A5 A4 A3 A2 A1 A0** ~~|~~ **RW AK D7** ~~~—~~ **D6 D5 D4 D3 D2** ~~—*~~ **D1 D0** | **AK** ~~70000000. 30008G00084 180800000 7W8G88E8804-|~~ **INDICATES SDA IS CONTROLLED BY ADXL372** 

_Figure 45. I[2] C Timing Diagram, Single Byte Read_ 

**1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 SCL** ~~T~~ U ~~T~~ **START** ~~i~~ **DEVICE ADDRESS** ~~i~~ **REGISTER ADDRESS** ~~a~~ **DATA BYTE** ~~—*~~ 1 **STOP SDA A6 A5 A4 A3 A2 A1 A0 RW AK 0 A6 A5 A4 A3 A2 A1 A0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK** ~~70000000. 3800880000400000000"0/|~~ **INDICATES SDA IS CONTROLLED BY ADXL372** 

_Figure 46. I[2] C Timing Diagram, Single Byte Write_ 

**1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 19 SCL** ~~T~~ OUT Se ~~o~~ **START DEVICE ADDRESS REGISTER ADDRESS DATA BYTE 1 DATA BYTE n SDA** ~~no~~ **A6 A5 A4 A3 A2 A1 A0** ~~a~~ **RW AK 0 A6 A5 A4 A3 A2 A1** ~~>|~~ **A0 AK** ~~+~~ **D7 D6 D5 D4 D3 D2** ~~—|~~ **D1 D0 AK D7 D0 AK** ~~—~~ **D7 D6 D5 D4 D3 D2** ~~—|~~ **D1 D0 AK INDICATES SDA IS CONTROLLED BY ADXL372** 

_Figure 47. I[2] C Timing Diagram, Multibyte Write_ 

Rev. B | Page 29 of 56 

**ADXL372** 

**Data Sheet** 

## **REGISTER MAP** 

## **Table 14. Register Map** 

|**Reg**|**Name**|**Bits**|**Bit 7**|**Bit 6**|**Bit 5**|**Bit 4**|**Bit 3**|**Bit 2**|**Bit 1**|**Bit 0**|**Reset**|**RW**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|0x00|DEVID_AD|[7:0]|DEVID_AD||||||||0xAD|R|
|0x01|DEVID_MST|[7:0]|DEVID_MST||||||||0x1D|R|
|0x02|PARTID|[7:0]|DEVID_PRODUCT||||||||0xFA|R|
|0x03|REVID|[7:0]|REVID||||||||0x031|R|
|0x04|STATUS|[7:0]|ERR_USER_<br>REGS|AWAKE|USER_NVM_BUSY|RESERVED|FIFO_OVR|FIFO_FULL|FIFO_RDY|DATA_RDY|0xA0|R|
|0x05|STATUS2|[7:0]|RESERVED|ACTIVITY2|ACTIVITY|INACT|RESERVED||||0x00|R|
|0x06|FIFO_ENTRIES2|[7:0]|RESERVED||||||FIFO_ENTRIES[9:8]||0x00|R|
|0x07|FIFO_ENTRIES|[7:0]||||FIFO_ENTRIES[7:0]|||||0x00|R|
|0x08|XDATA_H|[7:0]||||XDATA[11:4]|||||0x00|R|
|0x09|XDATA_L|[7:0]|XDATA[3:0]||||RESERVED||||0x00|R|
|0x0A|YDATA_H|[7:0]||||YDATA[11:4]|||||0x00|R|
|0x0B|YDATA_L|[7:0]|YDATA[3:0]||||RESERVED||||0x00|R|
|0x0C|ZDATA_H|[7:0]||||ZDATA[11:4]|||||0x00|R|
|0x0D|ZDATA_L|[7:0]|ZDATA[3:0]||||RESERVED||||0x00|R|
|0x15|MAXPEAK_X_H|[7:0]||||MAXPEAK_X[11:4]|||||0x00|R|
|0x16|MAXPEAK_X_L|[7:0]|MAXPEAK_X[3:0]||||RESERVED||||0x00|R|
|0x17|MAXPEAK_Y_H|[7:0]||||MAXPEAK_Y[11:4]|||||0x00|R|
|0x18|MAXPEAK_Y_L|[7:0]|MAXPEAK_Y[3:0]||||RESERVED||||0x00|R|
|0x19|MAXPEAK_Z_H|[7:0]||||MAXPEAK_Z[11:4]|||||0x00|R|
|0x1A|MAXPEAK_Z_L|[7:0]|MAXPEAK_Z[3:0]||||RESERVED||||0x00|R|
|0x20|OFFSET_X|[7:0]|RESERVED||||OFFSET_X||||0x00|R/W|
|0x21|OFFSET_Y|[7:0]|RESERVED||||OFFSET_Y||||0x00|R/W|
|0x22|OFFSET_Z|[7:0]|RESERVED||||OFFSET_Z||||0x00|R/W|
|0x23|THRESH_ACT_X_H|[7:0]||||THRESH_ACT_X[10:3]|||||0x00|R/W|
|0x24|THRESH_ACT_X_L|[7:0]|THRESH_ACT_X[2:0]|||RESERVED|||ACT_REF|ACT_X_EN|0x00|R/W|
|0x25|THRESH_ACT_Y_H|[7:0]||||THRESH_ACT_Y[10:3]|||||0x00|R/W|
|0x26|THRESH_ACT_Y_L|[7:0]|THRESH_ACT_Y[2:0]|||RESERVED||||ACT_Y_EN|0x00|R/W|
|0x27|THRESH_ACT_Z_H|[7:0]||||THRESH_ACT_Z[10:3]|||||0x00|R/W|
|0x28|THRESH_ACT_Z_L|[7:0]|THRESH_ACT_Z[2:0]|||RESERVED||||ACT_Z_EN|0x00|R/W|
|0x29|TIME_ACT|[7:0]||||ACT_COUNT|||||0x00|R/W|
|0x2A|THRESH_INACT_X_H|[7:0]||||THRESH_INACT_X[10:3]|||||0x00|R/W|
|0x2B|THRESH_INACT_X_L|[7:0]|THRESH_INACT_X[2:0]|||RESERVED|||INACT_REF|INACT_X_EN|0x00|R/W|
|0x2C|THRESH_INACT_Y_H|[7:0]||||THRESH_INACT_Y[10:3]|||||0x00|R/W|
|0x2D|THRESH_INACT_Y_L|[7:0]|THRESH_INACT_Y[2:0]|||RESERVED||||INACT_Y_EN|0x00|R/W|
|0x2E|THRESH_INACT_Z_H|[7:0]||||THRESH_INACT_Z[10:3]|||||0x00|R/W|
|0x2F|THRESH_INACT_Z_L|[7:0]|THRESH_INACT_Z[2:0]|||RESERVED||||INACT_Z_EN|0x00|R/W|
|0x30|TIME_INACT_H|[7:0]||||INACT_COUNT[15:8]|||||0x00|R/W|
|0x31|TIME_INACT_L|[7:0]||||INACT_COUNT[7:0]|||||0x00|R/W|
|0x32|THRESH_ACT2_X_H|[7:0]||||THRESH_ACT2_X[10:3]|||||0x00|R/W|
|0x33|THRESH_ACT2_X_L|[7:0]|THRESH_ACT2_X[2:0]|||RESERVED|||ACT2_REF|ACT2_X_EN|0x00|R/W|
|0x34|THRESH_ACT2_Y_H|[7:0]||||THRESH_ACT2_Y[10:3]|||||0x00|R/W|
|0x35|THRESH_ACT2_Y_L|[7:0]|THRESH_ACT2_Y[2:0]|||RESERVED||||ACT2_Y_EN|0x00|R/W|
|0x36|THRESH_ACT2_Z_H|[7:0]||||THRESH_ACT2_Z[10:3]|||||0x00|R/W|
|0x37|THRESH_ACT2_Z_L|[7:0]|THRESH_ACT2_Z[2:0]|||RESERVED||||ACT2_Z_EN|0x00|R/W|



Rev. B | Page 30 of 56 

**Data Sheet** 

**ADXL372** 

|**Reg**|**Name**|**Bits**|**Bit 7**|**Bit 6**|**Bit 5**|**Bit 4**|**Bit 3**|**Bit 2**|**Bit 1**|**Bit 0**|**Reset**|**RW**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|0x38|HPF|[7:0]|RESERVED||||||HPF_CORNER||0x00|R/W|
|0x39|FIFO_SAMPLES|[7:0]|FIFO_SAMPLES[7:0]||||||||0x80|R/W|
|0x3A|FIFO_CTL|[7:0]|RESERVED||FIFO_FORMAT|||FIFO_MODE||FIFO_<br>SAMPLES[8]|0x00|R/W|
|0x3B|INT1_MAP|[7:0]|INT1_LOW|AWAKE_<br>INT1|ACT_INT1|INACT_INT1|FIFO_OVR_<br>INT1|FIFO_FULL_<br>INT1|FIFO_RDY_<br>INT1|DATA_RDY_<br>INT1|0x00|R/W|
|0x3C|INT2_MAP|[7:0]|INT2_LOW|AWAKE_<br>INT2|ACT2_INT2|INACT_INT2|FIFO_OVR_<br>INT2|FIFO_FULL_<br>INT2|FIFO_RDY_<br>INT2|DATA_RDY_<br>INT2|0x00|R/W|
|0x3D|TIMING|[7:0]|ODR|||WAKEUP_RATE|||EXT_CLK|EXT_SYNC|0x00|R/W|
|0x3E|MEASURE|[7:0]|USER_OR_<br>DISABLE|AUTOSLEEP|LINKLOOP||LOW_NOISE|BANDWIDTH|||0x00|R/W|
|0x3F|POWER_CTL|[7:0]|I2C_HSM_<br>EN|RESERVED|INSTANT_ON_THRESH|FILTER_SETTLE|LPF_DISABLE|HPF_DISABLE|MODE||0x00|R/W|
|0x40|SELF_TEST|[7:0]|RESERVED|||||USER_ST|ST_DONE|ST|0x00|R/W|
|0x41|RESET|[7:0]|RESET||||||||0x00|W|
|0x42|FIFO_DATA|[7:0]|FIFO_DATA||||||||0x00|R|



1 The reset value of the REVID register is either 0x03 or 0x02 for the ADXL372. 

Rev. B | Page 31 of 56 

**ADXL372** 

**Data Sheet** 

**==> picture [535 x 177] intentionally omitted <==**

**----- Start of picture text -----**<br>
REGISTER DETAILS<br>ANALOG DEVICES ID REGISTER<br>Address: 0x00, Reset: 0xAD, Name: DEVID_AD<br>This register contains the Analog Devices, Inc., ID, 0xAD.<br>7 6 5 4 3 2 1 0<br>1 0 1 0 1 1 0 1<br>[7 :0 ] DEVID_AD (R)<br>Analog Devices ID, 0xAD.<br>Table 15. Bit Descriptions for DEVID_AD<br>Bits  Bit Name  Settings  Description  Reset  Access<br>[7:0]  DEVID_AD  Analog Devices ID, 0xAD.  0xAD  R<br>**----- End of picture text -----**<br>


**==> picture [535 x 482] intentionally omitted <==**

**----- Start of picture text -----**<br>
ANALOG DEVICES MEMS ID REGISTER<br>Address: 0x01, Reset: 0x1D, Name: DEVID_MST<br>This register contains the Analog Devices MEMS ID, 0x1D.<br>7 6 5 4 3 2 1 0<br>0 0 0 1 1 1 0 1<br>[7 :0 ] DEVID_M ST (R)<br>Analog Devices MEMS ID, 0x1D.<br>Table 16. Bit Descriptions for DEVID_MST<br>Bits  Bit Name  Settings  Description  Reset  Access<br>[7:0]  DEVID_MST  Analog Devices MEMS ID, 0x1D.  0x1D  R<br>DEVICE ID REGISTER<br>Address: 0x02, Reset: 0xFA, Name: PARTID<br>This register contains the device ID, 0xFA (372 octal).<br>7 6 5 4 3 2 1 0<br>1 1 1 1 1 0 1 0<br>[7 :0 ] DEVID_PRODUCT (R)<br>Device ID, 0xFA (372 Octal).<br>Table 17. Bit Descriptions for PARTID<br>Bits  Bit Name  Settings  Description  Reset  Access<br>[7:0]  DEVID_PRODUCT  Device ID, 0xFA (372 Octal).  0xFA  R<br>PRODUCT REVISION ID REGISTER<br>Address: 0x03, Reset: 0x02, Name: REVID<br>This register contains the mask revision ID, beginning with 0x00 and incrementing for each subsequent revision.<br>7 6 5 4 3 2 1 0<br>0 0 0 0 0 0 1 0<br>[7 :0 ] REVID (R)<br>Mask revision.<br>Table 18. Bit Descriptions for REVID<br>Bits  Bit Name  Settings  Description  Reset  Access<br>[7:0]  REVID  Mask revision.  0x2  R<br>**----- End of picture text -----**<br>


Rev. B | Page 32 of 56 

**Data Sheet** 

**ADXL372** 

## **STATUS REGISTER** 

**Address: 0x04, Reset: 0xA0, Name: STATUS** 

This register includes the following bits that describe various conditions of the ADXL372. 

||||||
|---|---|---|---|---|
|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|ERR_USER_REGS||SEU Event. An SEU event has been detected in a user register.|0x1|R|
|AWAKE||Awake Status. Activity has been detected and the device is moving.|0x0|R|
|USER_NVM_BUSY||1 = nonvolatile memory (NVM) is busy programming fuses.|0x1|R|
|RESERVED||Reserved.|0x0|R|
|FIFO_OVR||FIFO Overrun. FIFO has overflowed, and data has been lost.|0x0|R|
|FIFO_FULL||FIFO Watermark. The FIFO watermark level, specified in FIFO_SAMPLES, has<br>been reached.|0x0|R|
|FIFO_RDY||FIFO Ready. At least one valid sample is available in the FIFO.|0x0|R|
|DATA_RDY||Data ready status includes data written to user data registers or FIFO. Status is<br>high after the full data set has completed. A complete x, y, and z measurement<br>has been made and results can be read.|0x0|R|



## **ACTIVITY STATUS REGISTER** 

**Address: 0x05, Reset: 0x00, Name: STATUS2** 

**==> picture [187 x 92] intentionally omitted <==**

**----- Start of picture text -----**<br>
7 6 5 4 3 2 1 0<br>0 0 0 0 0 0 0 0<br>[ 7 ] RESERVED [ 3:0 ] RESERVED<br>[ 6 ] ACT IVIT Y2 ( R) [ 4 ] INACT  ( R)<br>Status of ACTIVITY2. Inactivity.<br>[ 5] ACT IVIT Y ( R)<br>Activity.<br>**----- End of picture text -----**<br>


**Table 20. Bit Descriptions for STATUS2** 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|7|RESERVED||Reserved.|0x0|R|
|6|ACTIVITY2||Status of ACTIVITY2.|0x0|R|
|5|ACTIVITY||Activity. Activity has been detected.|0x0|R|
|4|INACT||Inactivity. Inactivity has been detected.|0x0|R|
|[3:0]|RESERVED||Reserved.|0x0|R|



Rev. B | Page 33 of 56 

**ADXL372** 

**Data Sheet** 

## **FIFO ENTRIES REGISTER, MSB** 

## **Address: 0x06, Reset: 0x00, Name: FIFO_ENTRIES2** 

The FIFO_ENTRIES2 and FIFO_ENTRIES registers indicate the number of valid data samples present in the FIFO buffer. The number ranges from 0 to 512 or 0x00 to 0x200. FIFO_ENTRIES contains the least significant byte, and FIFO_ENTRIES2 contains the two most significant bits. 

**==> picture [255 x 44] intentionally omitted <==**

**----- Start of picture text -----**<br>
7 6 5 4 3 2 1 0<br>0 0 0 0 0 0 0 0<br>[7 :2 ] RESERVED [1 :0 ] FIFO_ENTRIES[9 :8 ] (R)<br>Num ber of data sam ples stored in the<br>FIFO.<br>**----- End of picture text -----**<br>


## **Table 21. Bit Descriptions for FIFO_ENTRIES2** 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:2]|RESERVED||Reserved.|0x0|R|
|[1:0]|FIFO_ENTRIES[9:8]||Number of data samples stored in the FIFO.|0x0|R|



## **FIFO ENTRIES REGISTER, LSB** 

**Address: 0x07, Reset: 0x00, Name: FIFO_ENTRIES** 

7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 

**[7 :0 ] FIFO_ENTRIES[7 :0 ] (R)** Num ber of data sam ples stored in the FIFO. 

**Table 22. Bit Descriptions for FIFO_ENTRIES** 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|FIFO_ENTRIES[7:0]||Number of data samples stored in the FIFO.|0x0|R|



## **X-AXIS DATA REGISTER, MSB** 

**Address: 0x08, Reset: 0x00, Name: XDATA_H** 

These two registers contain the x-axis acceleration data. Data is left justified and formatted as twos complement. XDATA_H contains the eight most significant bits (MSBs), and XDATA_L contains the four least significant bits (LSBs) of the 12-bit value. 

7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 **[7 :0 ] XDATA[1 1 :4 ] (R)** X-axis data. 

**Table 23. Bit Descriptions for XDATA_H** 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|XDATA[11:4]||X-axis data.|0x0|R|



## **X-AXIS DATA REGISTER, LSB** 

**Address: 0x09, Reset: 0x00, Name: XDATA_L** 

**==> picture [209 x 37] intentionally omitted <==**

**----- Start of picture text -----**<br>
7 6 5 4 3 2 1 0<br>0 0 0 0 0 0 0 0<br>[7 :4 ] XDATA[3 :0 ] (R) [3 :0 ] RESERVED<br>X-axis data.<br>**----- End of picture text -----**<br>


**Table 24. Bit descriptions for XDATA_L** 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:4]|XDATA[3:0]||X-axis data.|0x0|R|
|[3:0]|RESERVED||Reserved.|0x0|R|



Rev. B | Page 34 of 56 

**Data Sheet** 

**ADXL372** 

## **Y-AXIS DATA REGISTER, MSB** 

**Address: 0x0A, Reset: 0x00, Name: YDATA_H** 

The YDATA_H and YDATA_L registers contain the y-axis, LSB acceleration data. Data is left justified and formatted as twos complement. YDATA_H contains the eight most significant bits (MSBs), and YDATA_L contains the four least significant bits (LSBs) of the 12-bit value. 

YDATA_L latches on a read of YDATA_H to ensure data integrity. 

7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 

**[7 :0 ] YDATA[1 1 :4 ] (R)** Y-axis data. 

**Table 25. Bit Descriptions for YDATA_H** 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|YDATA[11:4]||Y-axis data.|0x0|R|



## **Y-AXIS DATA REGISTER, LSB** 

## **Address: 0x0B, Reset: 0x00, Name: YDATA_L** 

7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 **[7 :4 ] YDATA[3 :0 ] (R) [3 :0 ] RESERVED** Y-axis data. 

|**Table 26. Bit Descriptions for YDATA_L**|**Table 26. Bit Descriptions for YDATA_L**|||||
|---|---|---|---|---|---|
|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|[7:4]|YDATA[3:0]||Y-axis data.|0x0|R|
|[3:0]|RESERVED||Reserved.|0x0|R|



## **Z-AXIS DATA REGISTER, MSB** 

**Address: 0x0C, Reset: 0x00, Name: ZDATA_H** 

These two registers contain the z-axis acceleration data. Data is left justified and formatted as twos complement. ZDATA_H contains the eight most significant bits (MSBs), and ZDATA_L contains the four least significant bits (LSBs) of the 12-bit value. 

7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 

**[7 :0 ] ZDATA[1 1 :4 ] (R)** Z-axis data. 

**Table 27. Bit Descriptions for ZDATA_H** 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|ZDATA[11:4]||Z-axis data.|0x0|R|



## **Z-AXIS DATA REGISTER, LSB** 

**Address: 0x0D, Reset: 0x00, Name: ZDATA_L** 

7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 **[7 :4 ] ZDATA[3 :0 ] (R) [3 :0 ] RESERVED** Z-axis data. **Table 28. Bit Descriptions for ZDATA_L Bits Bit Name Settings Description Reset Access** [7:4] ZDATA[3:0] Z-axis data. 0x0 R [3:0] RESERVED Reserved. 0x0 R 

Rev. B | Page 35 of 56 

**ADXL372** 

**Data Sheet** 

## **HIGHEST PEAK DATA REGISTERS** 

The highest peak data registers contain the acceleration data corresponding to the highest magnitude sample recorded since the last read of this register. Data is left justified and formatted as twos complement. 

## **X-AXIS HIGHEST PEAK DATA REGISTER, MSB** 

**Address: 0x15, Reset: 0x00, Name: MAXPEAK_X_H** 

7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 

**[7 :0 ] M AXPEAK_X[1 1 :4 ] (R)** Stores the highest m agnitude observed since the last read of this register. 

## **Table 29. Bit Descriptions for MAXPEAK_X_H** 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|MAXPEAK_X[11:4]||Stores the highest magnitude observed since the last read of this register.<br>The 8 MSBs of the x-axis value.|0x0|R|



## **X-AXIS HIGHEST PEAK DATA REGISTER, LSB** 

**Address: 0x16, Reset: 0x00, Name: MAXPEAK_X_L** 

7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 

**[7 :4 ] M AXPEAK_X[3 :0 ] (R) [3 :0 ] RESERVED** Stores the highest m agnitude observed since the last read of this register. 

## **Table 30. Bit Descriptions for MAXPEAK_X_L** 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:4]|MAXPEAK_X[3:0]||Stores the highest magnitude observed since the last read of this register.<br>The 4 LSBs of the x-axis value.|0x0|R|
|[3:0]|RESERVED||Reserved.|0x0|R|



## **Y-AXIS HIGHEST PEAK DATA REGISTER, MSB** 

**Address: 0x17, Reset: 0x00, Name: MAXPEAK_Y_H** 

7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 

**[7 :0 ] M AXPEAK_Y[1 1 :4 ] (R)** Stores the highest m agnitude observed since the last read of this register. 

## **Table 31. Bit Descriptions for MAXPEAK_Y_H** 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|MAXPEAK_Y[11:4]||Stores the highest magnitude observed since the last read of this register.<br>The 8 MSBs of the y-axis value.|0x0|R|



Rev. B | Page 36 of 56 

**Data Sheet** 

**ADXL372** 

## **Y-AXIS HIGHEST PEAK DATA REGISTER, LSB** 

**Address: 0x18, Reset: 0x00, Name: MAXPEAK_Y_L** 

## 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 

**[7 :4 ] M AXPEAK_Y[3 :0 ] (R)** Stores the highest m agnitude observed since the last read of this register. 

## **[3 :0 ] RESERVED** 

## **Table 32. Bit Descriptions for MAXPEAK_Y_L** 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:4]|MAXPEAK_Y[3:0]||Stores the highest magnitude observed since the last read of this register.<br>The 4 LSBs of the y-axis value.|0x0|R|
|[3:0]|RESERVED||Reserved.|0x0|R|



## **Z-AXIS HIGHEST PEAK DATA REGISTER, MSB** 

**Address: 0x19, Reset: 0x00, Name: MAXPEAK_Z_H** 

7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 

**[7 :0 ] M AXPEAK_Z[1 1 :4 ] (R)** Stores the highest m agnitude observed since the last read of this register. 

## **Table 33. Bit Descriptions for MAXPEAK_Z_H** 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|MAXPEAK_Z[11:4]||Stores the highest magnitude observed since the last read of this register.<br>The 8 MSBs of the z-axis value.|0x0|R|



## **Z-AXIS HIGHEST PEAK DATA REGISTER, LSB** 

**Address: 0x1A, Reset: 0x00, Name: MAXPEAK_Z_L** 

## 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 

**[7 :4 ] M AXPEAK_Z[3 :0 ] (R) [3 :0 ] RESERVED** Stores the highest m agnitude observed since the last read of this register. 

## **Table 34. Bit Descriptions for MAXPEAK_Z_L** 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:4]|MAXPEAK_Z[3:0]||Stores the highest magnitude observed since the last read of this register.<br>The 4 LSBs of the z-axis value.|0x0|R|
|[3:0]|RESERVED||Reserved.|0x0|R|



Rev. B | Page 37 of 56 

**Data Sheet** 

## **ADXL372** 

## **OFFSET TRIM REGISTERS** 

Offset trim registers are each four bits and offer user set, offset adjustments in twos complement format. The scale factor of these registers is shown in Figure 36. 

**X-AXIS OFFSET TRIM REGISTER, LSB Address: 0x20, Reset: 0x00, Name: OFFSET_X** 

7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 **[7 :4 ] RESERVED [3 :0 ] OFFSET_X (R/W )** Offset added to X-axis data. **Table 35. Bit Descriptions for OFFSET_X Bits Bit Name Settings Description Reset Access** [7:4] RESERVED Reserved. 0x0 R [3:0] OFFSET_X Offset added to x-axis data. 0x0 R/W 

## **Y-AXIS OFFSET TRIM REGISTER, LSB** 

## **Address: 0x21, Reset: 0x00, Name: OFFSET_Y** 

|**Y-AXIS OFFSET TRIM REGISTER, LSB**<br>**Address: 0x21, Reset: 0x00, Name: OFFSET_Y**|**Y-AXIS OFFSET TRIM REGISTER, LSB**<br>**Address: 0x21, Reset: 0x00, Name: OFFSET_Y**|**Y-AXIS OFFSET TRIM REGISTER, LSB**<br>**Address: 0x21, Reset: 0x00, Name: OFFSET_Y**||||
|---|---|---|---|---|---|
|**[7 :4 ] RESERVED**<br>**Table 36. Bit Descriptions for OFFSET_Y**|||Offset added to Y-axis data.<br>0<br>0<br>1<br>0<br>2<br>0<br>3<br>0<br>4<br>0<br>5<br>0<br>6<br>0<br>7<br>0<br>**[3 :0 ] OFFSET_Y (R/W )**|||
|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|[7:4]|RESERVED||Reserved.|0x0|R|
|[3:0]|OFFSET_Y||Offset added to y-axis data.|0x0|R/W|



## **Z-AXIS OFFSET TRIM REGISTER, LSB** 

**Address: 0x22, Reset: 0x00, Name: OFFSET_Z** 

7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 **[7 :4 ] RESERVED [3 :0 ] OFFSET_Z (R/W )** Offset added to Z-axis data. **Table 37. Bit Descriptions for OFFSET_Z Bits Bit Name Settings Description Reset Access** [7:4] RESERVED Reserved. 0x0 R [3:0] OFFSET_Z Offset added to z-axis data. 0x0 R/W 

Rev. B | Page 38 of 56 

**Data Sheet** 

**ADXL372** 

## **X-AXIS ACTIVITY THRESHOLD REGISTER, MSB** 

## **Address: 0x23, Reset: 0x00, Name: THRESH_ACT_X_H** 

This 11-bit unsigned value sets the threshold for activity detection. This value is set in codes and the scale factor is 100 m _g_ /code. To detect activity, the absolute value of the 12-bit acceleration data is compared with the 11-bit (unsigned) activity threshold value. The THRESH_ACT_x_L register contains the least significant bits and the THRESH_ACT_x_H register contains the most significant byte of the activity threshold value. 

**==> picture [535 x 493] intentionally omitted <==**

**----- Start of picture text -----**<br>
7 6 5 4 3 2 1 0<br>0 0 0 0 0 0 0 0<br>[7 :0 ] THRESH_ACT_X[1 0 :3 ] (R/W )<br>Threshold for activity detection.<br>Table 38. Bit Descriptions for THRESH_ACT_X_H<br>Bits  Bit Name  Settings  Description  Reset  Access<br>[7:0]  THRESH_ACT_X[10:3]  Threshold for activity detection. The 8 MSBs of x-axis threshold.  0x0  R/W<br>X-AXIS OF ACTIVITY THRESHOLD REGISTER, LSB<br>Address: 0x24, Reset: 0x00, Name: THRESH_ACT_X_L<br>7 6 5 4 3 2 1 0<br>0 0 0 0 0 0 0 0<br>[7 :5 ] THRESH_ACT_X[2 :0 ] (R/W ) [0 ] ACT_X_EN (R/W )<br>Threshold for activity detection. Enable activity detection using X-axis<br>data.<br>[4 :2 ] RESERVED 0: X-axis ignored.<br>1: X-axis used.<br>[1 ] ACT_REF (R/W )<br>Selects referenced or absolute activity<br>processing.<br>1: Referenced activity processing.<br>0: Absolute activity processing.<br>Table 39. Bit Descriptions for THRESH_ACT_X_L<br>Bits  Bit Name  Settings  Description  Reset  Access<br>[7:5]  THRESH_ACT_X[2:0]  Threshold for activity detection. The 3 LSBs of x-axis threshold.  0x0  R/W<br>[4:2]  RESERVED  Reserved.  0x0  R<br>1  ACT_REF  Selects referenced or absolute activity processing.  0x0  R/W<br>1  Referenced activity processing.<br>0  Absolute activity processing.<br>0  ACT_X_EN  Enable activity detection using X-axis data.  0x0  R/W<br>0  X-axis ignored.<br>1  X-axis used.<br>Y-AXIS ACTIVITY THRESHOLD REGISTER, MSB<br>Address: 0x25, Reset: 0x00, Name: THRESH_ACT_Y_H<br>7 6 5 4 3 2 1 0<br>0 0 0 0 0 0 0 0<br>[7 :0 ] THRESH_ACT_Y[1 0 :3 ] (R/W )<br>Threshold for activity detection.<br>**----- End of picture text -----**<br>


## **Table 40. Bit Descriptions for THRESH_ACT_Y_H** 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|THRESH_ACT_Y[10:3]||Threshold for activity detection. The 8 MSBs of y-axis threshold.|0x0|R/W|



Rev. B | Page 39 of 56 

**ADXL372** 

**Data Sheet** 

## **Y-AXIS OF ACTIVITY THRESHOLD REGISTER, LSB** 

**Address: 0x26, Reset: 0x00, Name: THRESH_ACT_Y_L** 

7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 

**[7 :5 ] THRESH_ACT_Y[2 :0 ] (R/W ) [0 ] ACT_Y_EN (R/W )** Threshold for activity detection. Enable activity detection using Y-axis data. **[4 :1 ] RESERVED** 0: Y-axis ignored. 1: Y-axis used. 

**Table 41. Bit Descriptions for THRESH_ACT_Y_L** 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:5]|THRESH_ACT_Y[2:0]||Threshold for activity detection. The 3 LSBs of y-axis threshold.|0x0|R/W|
|[4:1]|RESERVED||Reserved.|0x0|R|
|0|ACT_Y_EN|0<br>1|Enable activity detection using y-axis data.<br>Y-axis ignored.<br>Y-axis used.|0x0|R/W|



## **Z-AXIS ACTIVITY THRESHOLD REGISTER, MSB** 

**Address: 0x27, Reset: 0x00, Name: THRESH_ACT_Z_H** 

7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 

**[7 :0 ] THRESH_ACT_Z[1 0 :3 ] (R/W )** Threshold for activity detection. 

|**Table**|**42. Bit Descriptions for THRESH_ACT_Z_H **|**42. Bit Descriptions for THRESH_ACT_Z_H **|**42. Bit Descriptions for THRESH_ACT_Z_H **|||
|---|---|---|---|---|---|
|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|[7:0]|THRESH_ACT_Z[10:3]||Threshold for activity detection. The 8 MSBs of z-axis threshold.|0x0|R/W|



## **Z-AXIS OF ACTIVITY THRESHOLD REGISTER, LSB** 

**Address: 0x28, Reset: 0x00, Name: THRESH_ACT_Z_L** 

7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 **[7 :5 ] THRESH_ACT_Z[2 :0 ] (R/W ) [0 ] ACT_Z_EN (R/W )** Threshold for activity detection. Enable activity detection using Z-axis data. 

**[4 :1 ] RESERVED** 

0: Z-axis ignored. 1: Z-axis used. 

**Table 43. Bit Descriptions for THRESH_ACT_Z_L** 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:5]|THRESH_ACT_Z[2:0]||Threshold for activity detection. The 3 LSBs of z-axis threshold.|0x0|R/W|
|[4:1]|RESERVED||Reserved.|0x0|R|
|0|ACT_Z_EN|0<br>1|Enable activity detection using Z-axis data.<br>Z-axis ignored.<br>Z-axis used.|0x0|R/W|



Rev. B | Page 40 of 56 

**Data Sheet** 

**ADXL372** 

## **ACTIVITY TIME REGISTER** 

## **Address: 0x29, Reset: 0x00, Name: TIME_ACT** 

The activity timer implements a robust activity detection that minimizes false positive motion triggers. When the timer is used, only sustained motion can trigger activity detection. The time (in milliseconds) is given by the following equation: 

_Time_ = _TIME_ACT_ × 3.3 ms per code 

where: 

_TIME_ACT_ is the value set in this register. 

3.3 ms per code is the scale factor of the TIME_ACT register for ODR = 6400 Hz. It is 6.6 ms per code for ODR = 3200 Hz and below. See the Activity Timer section for more information. 

7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 

**[ 7 :0 ] ACT _CO UNT  ( R/W )** Number of multiples of 3.3 ms activity timer for which above threshold required to detect activity. 

## **Table 44. Bit Descriptions for TIME_ACT** 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|ACT_COUNT||Number of multiples of 3.3 ms activity timer for which above threshold acceleration is<br>required to detect activity. It is 3.3 ms per code for 6400 Hz ODR, and it is 6.6 ms per code<br>for 3200 Hz ODR and below.|0x0|R/W|



## **X-AXIS INACTIVITY THRESHOLD REGISTER, MSB** 

## **Address: 0x2A, Reset: 0x00, Name: THRESH_INACT_X_H** 

This 11-bit unsigned value sets the threshold for inactivity detection. This value is set in codes and the scale factor is 100 m _g_ /code. To detect inactivity, the absolute value of the 12-bit acceleration data is compared with the 11-bit (unsigned) inactivity threshold value. The THRESH_INACT_x_L register contains the least significant bits and the THRESH_INACT_x_H register contains the most significant byte of the inactivity threshold value. 

7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 **[7 :0 ] THRESH_INACT_X[1 0 :3 ] (R/W )** Threshold for inactivity detection. **Table 45. Bit Descriptions for THRESH_INACT_X_H Bits Bit Name Settings Description Reset Access** [7:0] THRESH_INACT_X[10:3] Threshold for inactivity detection. The 8 MSBs of x-axis. 0x0 R/W 

Rev. B | Page 41 of 56 

**ADXL372** 

**Data Sheet** 

## **X-AXIS OF INACTIVITY THRESHOLD REGISTER, LSB** 

**Address: 0x2B, Reset: 0x00, Name: THRESH_INACT_X_L** 

7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 **[7 :5 ] THRESH_INACT_X[2 :0 ] (R/W ) [0 ] INACT_X_EN (R/W )** Threshold for inactivity detection. X axis m asked from  participating in inactivity detection. **[4 :2 ] RESERVED** 0: X-axis ignored. 1: X-axis used. **[1 ] INACT_REF (R/W )** Selects referenced or absolute activity processing. 1: Referenced activity processing. 0: Absolute activity processing. **Table 46. Bit Descriptions for THRESH_INACT_X_L Bits Bit Name Settings Description Reset Access** [7:5] THRESH_INACT_X[2:0] Threshold for inactivity detection. The 3 LSBs of the x-axis. 0x0 R/W [4:2] RESERVED Reserved. 0x0 R 1 INACT_REF Selects referenced or absolute inactivity processing. 0x0 R/W 1 Referenced inactivity processing. 0 Absolute inactivity processing. 0 INACT_X_EN X-axis masked from participating in inactivity detection. 0x0 R/W 0 X-axis ignored. 1 X-axis used. 

## **Y-AXIS INACTIVITY THRESHOLD REGISTER, MSB** 

**Address: 0x2C, Reset: 0x00, Name: THRESH_INACT_Y_H** 

7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 

**[7 :0 ] THRESH_INACT_Y[1 0 :3 ] (R/W )** Threshold for inactivity detection. 

|**Table 47. Bit Descriptions for THRESH_INACT_Y_H **|**Table 47. Bit Descriptions for THRESH_INACT_Y_H **|**Table 47. Bit Descriptions for THRESH_INACT_Y_H **|**Table 47. Bit Descriptions for THRESH_INACT_Y_H **|||
|---|---|---|---|---|---|
|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|[7:0]|THRESH_INACT_Y[10:3]||Threshold for inactivity detection. The 8 MSBs of the y-axis.|0x0|R/W|



Rev. B | Page 42 of 56 

**Data Sheet** 

**ADXL372** 

## **Y-AXIS OF INACTIVITY THRESHOLD REGISTER, LSB** 

**Address: 0x2D, Reset: 0x00, Name: THRESH_INACT_Y_L** 

|**Y-AXIS OF INACTIVITY THRESHOLD REGISTER, LSB**<br>**Address: 0x2D, Reset: 0x00, Name: THRESH_INACT_Y_L**|**Y-AXIS OF INACTIVITY THRESHOLD REGISTER, LSB**<br>**Address: 0x2D, Reset: 0x00, Name: THRESH_INACT_Y_L**|**Y-AXIS OF INACTIVITY THRESHOLD REGISTER, LSB**<br>**Address: 0x2D, Reset: 0x00, Name: THRESH_INACT_Y_L**|**Y-AXIS OF INACTIVITY THRESHOLD REGISTER, LSB**<br>**Address: 0x2D, Reset: 0x00, Name: THRESH_INACT_Y_L**|||
|---|---|---|---|---|---|
|Threshold for inactivity detection.<br>Y axis m asked from  participating in<br>inactivity detection.<br>1: Y-axis used.<br>0: Y-axis ignored.<br>0<br>0<br>1<br>0<br>2<br>0<br>3<br>0<br>4<br>0<br>5<br>0<br>6<br>0<br>7<br>0<br>**[7 :5 ] THRESH_INACT_Y[2 :0 ] (R/W )**<br>**[0 ] INACT_Y_EN (R/W )**<br>**[4 :1 ] RESERVED**<br>**Table 48. Bit Descriptions for THRESH_INACT_Y_L**||||||
|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|[7:5]|THRESH_INACT_Y[2:0]||Threshold for inactivity detection. The 3 LSBs of the y-axis.|0x0|R/W|
|[4:1]|RESERVED||Reserved.|0x0|R|
|0|INACT_Y_EN|0<br>1|Y-axis masked from participating in inactivity detection.<br>Y-axis ignored.<br>Y-axis used.|0x0|R/W|



## **Z-AXIS INACTIVITY THRESHOLD REGISTER, MSB** 

**Address: 0x2E, Reset: 0x00, Name: THRESH_INACT_Z_H** 

||||||
|---|---|---|---|---|
|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|THRESH_INACT_Z[10:3]||Threshold for inactivity detection. The 8 MSBs of the z-axis.|0x0|R/W|



## **Z-AXIS OF INACTIVITY THRESHOLD REGISTER, LSB** 

**Address: 0x2F, Reset: 0x00, Name: THRESH_INACT_Z_L** 

**==> picture [307 x 57] intentionally omitted <==**

**----- Start of picture text -----**<br>
7 6 5 4 3 2 1 0<br>0 0 0 0 0 0 0 0<br>[7 :5 ] THRESH_INACT_Z[2 :0 ] (R/W ) [0 ] INACT_Z_EN (R/W )<br>Threshold for inactivity detection. Z axis m asked from  participating in<br>inactivity detection.<br>[4 :1 ] RESERVED 0: Z-axis ignored.<br>1: Z-axis used.<br>**----- End of picture text -----**<br>


## **Table 50. Bit Descriptions for THRESH_INACT_Z_L** 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:5]|THRESH_INACT_Z[2:0]||Threshold for inactivity detection. The 3 LSBs of the z-axis.|0x0|R/W|
|[4:1]|RESERVED||Reserved.|0x0|R|
|0|INACT_Z_EN|0<br>1|Z-axis masked from participating in inactivity detection.<br>Z-axis ignored.<br>Z-axis used.|0x0|R/W|



Rev. B | Page 43 of 56 

**Data Sheet** 

## **ADXL372** 

## **INACTIVITY TIME REGISTERS** 

The 16-bit value in these registers sets the time that all enabled axes must be lower than the inactivity threshold for an inactivity event to be detected. The TIME_INACT_L register holds the eight LSBs, and the TIME_INACT_H register holds the eight MSBs of the 16-bit TIME_INACT value. 

Calculate the time as follows: 

_Time = TIME_INACT_ × 26 ms per code 

where: 

_TIME_INACT_ is the 16-bit value set by the TIME_INACT_L register (eight LSBs) and the TIME_INACT_H register (eight MSBs). 26 ms per code is the scale factor of the TIME_INACT_L and TIME_INACT_H registers for 3200 Hz and below. It is 13 ms per code of ODR = 6400 Hz. See the Inactivity Timer section for more information. 

## **INACTIVITY TIMER REGISTER, MSB** 

**Address: 0x30, Reset: 0x00, Name: TIME_INACT_H** 

7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 

**[ 7 :0 ] INACT _CO UNT [ 15:8 ] ( R/W )** Number of multiples of 26 ms inactivity timer for which below threshold required to detect inactivity. 

## **Table 51. Bit Descriptions for TIME_INACT_H** 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|INACT_COUNT[15:8]||Number of multiples of 26 ms inactivity timer for which below threshold<br>acceleration is required to detect inactivity. It is 26 ms per code for 3200 Hz<br>ODR and below, and it is 13 ms per code for 6400 Hz ODR.|0x0|R/W|



## **INACTIVITY TIMER REGISTER, LSB** 

**Address: 0x31, Reset: 0x00, Name: TIME_INACT_L** 

7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 

**[ 7 :0 ] INACT _CO UNT [ 7 :0 ] ( R/W )** Number of multiples of 26 ms inactivity timer for which below threshold required to detect inactivity. 

## **Table 52. Bit Descriptions for TIME_INACT_L** 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|INACT_COUNT[7:0]||Number of multiples of 26 ms inactivity timer for which below threshold<br>acceleration is required to detect inactivity.|0x0|R/W|



Rev. B | Page 44 of 56 

**Data Sheet** 

**ADXL372** 

## **X-AXIS MOTION WARNING THRESHOLD REGISTER, MSB** 

## **Address: 0x32, Reset: 0x00, Name: THRESH_ACT2_X_H** 

This 11-bit unsigned value sets the threshold for motion detection. This value is set in codes and the scale factor is 100 m _g_ /code. To detect motion, the absolute value of the 12-bit acceleration data is compared with the 11-bit (unsigned) ACTIVITY2 threshold value. The THRESH_ACT2_x_L register contains the least significant bits and the THRESH_ACT2_x_H register contains the most significant byte of the ACTIVITY2 threshold value. 

**==> picture [73 x 14] intentionally omitted <==**

**----- Start of picture text -----**<br>
7 6 5 4 3 2 1 0<br>0 0 0 0 0 0 0 0<br>**----- End of picture text -----**<br>


**[7 :0 ] THRESH_ACT2 _X[1 0 :3 ] (R/W )** OTN Threshold. 

**Table 53. Bit Descriptions for THRESH_ACT2_X_H** 

|**Bits**|**Bit Name**|**Settings**|**Description1**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|THRESH_ACT2_X[10:3]||OTN Threshold. The 8 MSBs of the x-axis threshold for motion warning<br>interrupt.|0x0|R/W|
|1OTN stands for other threshold notification.||||||



## **X-AXIS OF MOTION WARNING NOTIFICATION REGISTER, LSB** 

**Address: 0x33, Reset: 0x00, Name: THRESH_ACT2_X_L** 

**==> picture [534 x 260] intentionally omitted <==**

**----- Start of picture text -----**<br>
7 6 5 4 3 2 1 0<br>0 0 0 0 0 0 0 0<br>[7 :5 ] THRESH_ACT2 _X[2 :0 ] (R/W ) [0 ] ACT2 _X_EN (R/W )<br>OTN Threshold. X axis ACT2 enable.<br>0: X-axis ignored.<br>[4 :2 ] RESERVED 1: X-axis used.<br>[1 ] ACT2 _REF (R/W )<br>Selects referenced or absolute over-threshold<br>notification processing.<br>1: Referenced activity processing.<br>0: Absolute activity processing.<br>Table 54. Bit Descriptions for THRESH_ACT2_X_L<br>Bits  Bit Name  Settings  Description [1] Reset  Access<br>[7:5]  THRESH_ACT2_X[2:0]  OTN Threshold. The 3 LSBs of the x-axis threshold for motion warning interrupt.  0x0  R/W<br>[4:2]  RESERVED  Reserved.  0x0  R<br>1  ACT2_REF  Selects referenced or absolute motion warning notification processing.   0x0  R/W<br>1  Referenced activity processing.<br>0  Absolute activity processing.<br>0  ACT2_X_EN  X-axis ACT2 enable. When set to 1, the x-axis participates in motion warning  0x0  R/W<br>notification detection.<br>0  X-axis ignored.<br>1  X-axis used.<br>**----- End of picture text -----**<br>


1 OTN stands for other threshold notification, and ACT2 stands for ACTIVITY2. 

Rev. B | Page 45 of 56 

**ADXL372** 

**Data Sheet** 

## **Y-AXIS MOTION WARNING NOTIFICATION THRESHOLD REGISTER, MSB** 

**Address: 0x34, Reset: 0x00, Name: THRESH_ACT2_Y_H** 

7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 

**[7 :0 ] THRESH_ACT2 _Y[1 0 :3 ] (R/W )** OTN Threshold. 

## **Table 55. Bit Descriptions for THRESH_ACT2_Y_H** 

|**Bits**|**Bit Name**|**Settings**|**Description1**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|THRESH_ACT2_Y[10:3]||OTN Threshold. The 8 MSBs of the y-axis threshold for motion warning interrupt.|0x0|R/W|



1 OTN stands for other threshold notification. 

## **Y-AXIS OF MOTION WARNING NOTIFICATION REGISTER, LSB** 

**Address: 0x35, Reset: 0x00, Name: THRESH_ACT2_Y_L** 

7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 

**[7 :5 ] THRESH_ACT2 _Y[2 :0 ] (R/W ) [0 ] ACT2 _Y_EN (R/W )** OTN Threshold. Y axis ACT2 enable. 0: Y-axis ignored. **[4 :1 ] RESERVED** 1: Y-axis used. 

**Table 56. Bit Descriptions for THRESH_ACT2_Y_L** 

|**Bits**|**Bit Name**|**Settings**|**Description1**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:5]|THRESH_ACT2_Y[2:0]||OTN Threshold. The 3 LSBs of the y-axis threshold for motion warning interrupt.|0x0|R/W|
|[4:1]|RESERVED||Reserved.|0x0|R|
|0|ACT2_Y_EN|0<br>1|Y-axis ACT2 enable. When 1, the y-axis participates in motion warning<br>notification detection.<br>Y-axis ignored.<br>Y-axis used.|0x0|R/W|



1 OTN stands for other threshold notification, and ACT2 stands for ACTIVITY2. 

## **Z-AXIS MOTION WARNING NOTIFICATION THRESHOLD REGISTER, MSB** 

**Address: 0x36, Reset: 0x00, Name: THRESH_ACT2_Z_H** 

7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 **[7 :0 ] THRESH_ACT2 _Z[1 0 :3 ] (R/W )** OTN Threshold. **Table 57. Bit Descriptions for THRESH_ACT2_Z_H Bits Bit Name Settings Description[1] Reset Access** [7:0] THRESH_ACT2_Z[10:3] OTN Threshold. The 8 MSBs of the z-axis threshold for motion warning interrupt. 0x0 R/W 

1 OTN stands for other threshold notification. 

Rev. B | Page 46 of 56 

**Data Sheet** 

**ADXL372** 

## **Z-AXIS MOTION WARNING NOTIFICATION REGISTER, LSB** 

**Address: 0x37, Reset: 0x00, Name: THRESH_ACT2_Z_L** 

|**Z-AXIS MOTION WARNING NOTIFICATION REGISTER, LSB**<br>**Address: 0x37, Reset: 0x00, Name: THRESH_ACT2_Z_L**|**Z-AXIS MOTION WARNING NOTIFICATION REGISTER, LSB**<br>**Address: 0x37, Reset: 0x00, Name: THRESH_ACT2_Z_L**|**Z-AXIS MOTION WARNING NOTIFICATION REGISTER, LSB**<br>**Address: 0x37, Reset: 0x00, Name: THRESH_ACT2_Z_L**|**Z-AXIS MOTION WARNING NOTIFICATION REGISTER, LSB**<br>**Address: 0x37, Reset: 0x00, Name: THRESH_ACT2_Z_L**|||
|---|---|---|---|---|---|
|OTN Threshold.<br>Z axis ACT2 enable.<br>1:<br>Z-axis used.<br>0:<br>Z-axis ignored.<br>0<br>0<br>1<br>0<br>2<br>0<br>3<br>0<br>4<br>0<br>5<br>0<br>6<br>0<br>7<br>0<br>**[7 :5 ] THRESH_ACT2 _Z[2 :0 ] (R/W )**<br>**[0 ] ACT2 _Z_EN (R/W )**<br>**[4 :1 ] RESERVED**<br>**Table 58. Bit Descriptions for THRESH_ACT2_Z_L **||||||
|**Bits**|**Bit Name**|**Settings**|**Description1**|**Reset**|**Access**|
|[7:5]|THRESH_ACT2_Z[2:0]||OTN Threshold. The 3 LSBs of the z-axis threshold for motion warning interrupt.|0x0|R/W|
|[4:1]|RESERVED||Reserved.|0x0|R|
|0|ACT2_Z_EN|0<br>1|Z-axis ACT2 enable. When 1, the z-axis participates in motion warning<br>notification detection.<br>Z-axis ignored.<br>Z-axis used.|0x0|R/W|



1 OTN stands for other threshold notification, and ACT2 stands for ACTIVITY2. 

## **HIGH-PASS FILTER SETTINGS REGISTER** 

**Address: 0x38, Reset: 0x00, Name: HPF** 

Use this register to specify parameters for the internal high-pass filter. 

7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 **[7 :2 ] RESERVED [1 :0 ] HPF_CORNER (R/W )** High-Pass Filter Corner Frequency Selection. 00: High Pass Filter Corner 0. 01: High Pass Filter Corner 1. 10: High Pass Filter Corner 2. 11: High Pass Filter Corner 3. 

**Table 59. Bit Descriptions for HPF** 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:2]|RESERVED||Reserved.|0x0|R|
|[1:0]|HPF_CORNER|00<br>01<br>10<br>11|High-Pass Filter Corner Frequency Selection.<br>High Pass Filter Corner 0. At ODR 6400 Hz = 30.48 Hz, at ODR 3200 Hz = 15.24 Hz, at<br>ODR 1600 Hz = 7.61 Hz, at ODR 800 Hz = 3.81 Hz, and at ODR 400 Hz = 1.90 Hz.<br>High Pass Filter Corner 1. At ODR 6400 Hz = 15.58 Hz, at ODR 3200 Hz = 7.79 Hz, at ODR<br>1600 Hz = 3.89 Hz, at ODR 800 Hz = 1.94 Hz, and at ODR 400 Hz = 0.97 Hz.<br>High Pass Filter Corner 2. At ODR 6400 Hz = 7.88 Hz, at ODR 3200 Hz = 3.94 Hz, at ODR<br>1600 Hz = 1.97 Hz, at ODR 800 Hz = 0.98 Hz, and at ODR 400 Hz = 0.49 Hz.<br>High Pass Filter Corner 3. At ODR 6400 Hz = 3.96 Hz, at ODR 3200 Hz = 1.98 Hz, at ODR<br>1600 Hz = 0.99 Hz, at ODR 800 Hz = 0.49 Hz, and at ODR 400 Hz = 0.24 Hz.|0x0|R/W|



Rev. B | Page 47 of 56 

**ADXL372** 

**Data Sheet** 

## **FIFO SAMPLES REGISTER** 

**Address: 0x39, Reset: 0x80, Name: FIFO_SAMPLES** 

Use the FIFO_SAMPLES value to specify the number of samples to store in the FIFO. The 8 least significant bits (LSBs) of the FIFO_SAMPLES value are stored in this register. The most significant bit (MSB) of the FIFO_SAMPLES value is Bit 0 of the FIFO_CTL register. 

The default value of this register is 0x80 to avoid triggering the FIFO watermark interrupt (see the FIFO Watermark section for more information). In trigger FIFO mode, FIFO_SAMPLES program the number of samples to be saved after the trigger is detected. 

7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 

**[7 :0 ] FIFO_SAM PLES[7 :0 ] (R/W )** FIFO Sam ples. 

## **Table 60. Bit Descriptions for FIFO_SAMPLES** 

**==> picture [534 x 40] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||||
|---|---|---|---|---|---|
|Bits|Bit Name|Settings|Description|Reset|Access|
|[7:0]|FIFO_SAMPLES[7:0]|FIFO Samples. Watermark number of FIFO samples that triggers a FIFO_FULL|0x80|R/W|
|condition when reached. Values range from 0 to 512.|

**----- End of picture text -----**<br>


## **FIFO CONTROL REGISTER** 

**Address: 0x3A, Reset: 0x00, Name: FIFO_CTL** 

Use this register to specify the operating parameters for the FIFO. 

**==> picture [330 x 174] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||||||
|---|---|---|---|---|---|---|---|
|7|6|5|4|3|2|1|0|
|0|0|0|0|0|0|0|0|
|[ 7 :6 ] RESERVED|[ 0 ] FIFO _SAM PLES[ 8 ] ( R/W )|
|FIFO Samples.|
|[ 5:3] FIFO _FO RM AT  ( R/W )|
|FIFO Format.|[ 2:1] FIFO _M O DE ( R/W )|
|111:|FIFO stores peak acceleration (x, y,|FIFO Mode.|
|and z) of every over-threshold event.|0:|FIFO is bypassed.|
|001:|FIFO stores x-axis acceleration data|1:|FIFO operates in stream mode.|
|only.|10:|FIFO operates in trigger mode.|
|010:|FIFO stores y-axis acceleration data|11:|FIFO operates in oldest saved mode.|
|only.|
|011:|FIFO stores x- and y-axis acceleration|
|data.|
|100:|FIFO stores z-axis acceleration data|
|only.|
|101:|FIFO stores x- and z-axis acceleration|
|data.|
|110:|FIFO stores y- and z-axis acceleration|
|data.|
|000:|FIFO stores x-, y- and z-axis acceleration|
|data.|

**----- End of picture text -----**<br>


**Table 61. Bit Descriptions for FIFO_CTL** 

**==> picture [534 x 167] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||||
|---|---|---|---|---|---|
|Bits|Bit Name|Settings|Description|Reset|Access|
|[7:6]|RESERVED|Reserved.|0x0|R|
|[5:3]|FIFO_FORMAT|FIFO Format. Specifies which data is stored in the FIFO buffer.|0x0|R/W|
|111|FIFO stores peak acceleration (x, y, and z) of every over threshold event.|
|001|FIFO stores x-axis acceleration data only.|
|010|FIFO stores y-axis acceleration data only.|
|011|FIFO stores x- and y-axis acceleration data.|
|100|FIFO stores z-axis acceleration data only.|
|101|FIFO stores x- and z-axis acceleration data.|
|110|FIFO stores y- and z-axis acceleration data.|
|000|FIFO stores x-, y- and z-axis acceleration data.|

**----- End of picture text -----**<br>


Rev. B | Page 48 of 56 

**ADXL372** 

## **Data Sheet** 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[2:1]|FIFO_MODE|0<br>1<br>10<br>11|FIFO Mode. Specifies FIFO operating mode.<br>FIFO is bypassed.<br>FIFO operates in stream mode.<br>FIFO operates in trigger mode.<br>FIFO operates in oldest saved mode.|0x0|R/W|
|0|FIFO_SAMPLES[8]||FIFO Samples. Watermark number of FIFO samples that triggers a FIFO_FULL<br>condition when reached. Values range from 0 to 512.|0x0|R/W|



## **INTERRUPT PIN FUNCTION MAP REGISTERS** 

## **Address: 0x3B, Reset: 0x00, Name: INT1_MAP** 

The INT1_MAP and INT2_MAP registers configure the INT1 and INT2 interrupt pins, respectively. Bits[6:0] select which function(s) generate an interrupt on the pin. If its corresponding bit is set to 1, the function generates an interrupt on the INTx pin. Bit B7 configures whether the pin operates in active high (B7 low) or active low (B7 high) mode. Any number of functions can be selected simultaneously for each pin. If multiple functions are selected, their conditions are OR'ed together to determine the INTx pin state. The status of each function can be determined by reading the status register. If no interrupts are mapped to an INTx pin, the pin remains in a high impedance state. 

**==> picture [72 x 15] intentionally omitted <==**

**----- Start of picture text -----**<br>
7 6 5 4 3 2 1 0<br>0 0 0 0 0 0 0 0<br>**----- End of picture text -----**<br>


- **[ 7 ] INT 1_LO W  ( R/W ) [ 0 ] DAT A_RDY_INT 1 ( R/W )** Configures INT1 for active low operation. Map data ready interrupt onto INT1. **[ 6 ] AW AKE_INT 1 ( R/W ) [ 1] FIFO _RDY_INT 1 ( R/W )** Map awake interrupt onto INT1. Map FIFO_READY interrupt onto INT1. **[ 5] ACT _INT 1 ( R/W ) [ 2] FIFO _FULL_INT 1 ( R/W )** Map activity interrupt onto INT1. Map FIFO_FULL interrupt onto INT1. 

- **[ 4 ] INACT _INT 1 ( R/W ) [ 3] FIFO _O VR_INT 1 ( R/W )** Map inactivity interrupt onto INT1. Map FIFO_OVERRUN interrupt onto INT1. 

**Table 62. Bit Descriptions for INT1_MAP** 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|7|INT1_LOW||Configures INT1 for active low operation.|0x0|R/W|
|6|AWAKE_INT1||Map awake interrupt onto INT1.|0x0|R/W|
|5|ACT_INT1||Map activity interrupt onto INT1.|0x0|R/W|
|4|INACT_INT1||Map inactivity interrupt onto INT1.|0x0|R/W|
|3|FIFO_OVR_INT1||Map FIFO_OVERRUN interrupt onto INT1.|0x0|R/W|
|2|FIFO_FULL_INT1||Map FIFO_FULL interrupt onto INT1.|0x0|R/W|
|1|FIFO_RDY_INT1||Map FIFO_READY interrupt onto INT1.|0x0|R/W|
|0|DATA_RDY_INT1||Map data ready interrupt onto INT1.|0x0|R/W|



Rev. B | Page 49 of 56 

**ADXL372** 

**Data Sheet** 

## **INT2 FUNCTION MAP REGISTER** 

**Address: 0x3C, Reset: 0x00, Name: INT2_MAP** 

**==> picture [73 x 14] intentionally omitted <==**

**----- Start of picture text -----**<br>
7 6 5 4 3 2 1 0<br>0 0 0 0 0 0 0 0<br>**----- End of picture text -----**<br>


**[ 7 ] INT 2_LO W  ( R/W )** Configures INT2 for active low operation. **[ 6 ] AW AKE_INT 2 ( R/W )** Map awake interrupt onto INT2. **[ 5] ACT 2_INT 2 ( R/W )** Map activity 2 interrupt onto INT2. **[ 4 ] INACT _INT 2 ( R/W )** Map inactivity interrupt onto INT2. 

- **[ 0 ] DAT A_RDY_INT 2 ( R/W )** Map data ready interrupt onto INT2. 

- **[ 1] FIFO _RDY_INT 2 ( R/W )** Map FIFO_READY interrupt onto INT2. 

- **[ 2] FIFO _FULL_INT 2 ( R/W )** Map FIFO_FULL interrupt onto INT2. 

- **[ 3] FIFO _O VR_INT 2 ( R/W )** Map FIFO_OVERRUN interrupt onto INT2. 

**Table 63. Bit Descriptions for INT2_MAP** 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|7|INT2_LOW||Configures INT2 for active low operation.|0x0|R/W|
|6|AWAKE_INT2||Map awake interrupt onto INT2.|0x0|R/W|
|5|ACT2_INT2||Map Activity 2 (motion warning) interrupt onto INT2.|0x0|R/W|
|4|INACT_INT2||Map inactivity interrupt onto INT2.|0x0|R/W|
|3|FIFO_OVR_INT2||Map FIFO_OVERRUN interrupt onto INT2.|0x0|R/W|
|2|FIFO_FULL_INT2||Map FIFO_FULL interrupt onto INT2.|0x0|R/W|
|1|FIFO_RDY_INT2||Map FIFO_READY interrupt onto INT2.|0x0|R/W|
|0|DATA_RDY_INT2||Map data ready interrupt onto INT2.|0x0|R/W|



## **EXTERNAL TIMING CONTROL REGISTER** 

**Address: 0x3D, Reset: 0x00, Name: TIMING** 

Use this register to control the ADXL372 timing parameters: ODR and external timing triggers. 

7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 **[ 7 :5] O DR ( R/W ) [ 0 ] EXT _SYNC ( R/W )** Output data rate. Enable external trigger. 000: 400 Hz ODR. 001: 800 Hz ODR. **[ 1] EXT _CLK ( R/W )** 010: 1600 Hz ODR. Enable external clock. 011: 3200 Hz ODR. 100: 6400 Hz ODR. **[ 4 :2] W AKEUP_RAT E ( R/W )** Timer Rate for Wake-Up Mode. 0: 52ms. 1: 104ms. 10: 208ms. 11: 512ms. 100: 2048ms. 101: 4096ms. 110: 8192ms. 111: 24576ms. 

**Table 64. Bit Descriptions for TIMING** 

|**Bits**|**Bit Name**|**Settings**<br>**Descrip**|**tion**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:5]|ODR|Output<br>000<br>400 Hz<br>001<br>800 Hz<br>010<br>1600 H<br>011<br>3200 H<br>100<br>6400 H|data rate.<br>ODR.<br>ODR.<br>z ODR.<br>z ODR.<br>z ODR.|0x0|R/W|



Rev. B | Page 50 of 56 

**Data Sheet** 

**ADXL372** 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[4:2]|WAKEUP_RATE|0<br>1<br>10<br>11<br>100<br>101<br>110<br>111|Timer Rate for Wake-Up Mode.<br>52 ms.<br>104 ms.<br>208 ms.<br>512 ms.<br>2048 ms.<br>4096 ms.<br>8192 ms.<br>24576 ms.|0x0|R/W|
|1|EXT_CLK||Enable external clock.|0x0|R/W|
|0|EXT_SYNC||Enable external trigger.|0x0|R/W|



## **MEASUREMENT CONTROL REGISTER Address: 0x3E, Reset: 0x00, Name: MEASURE** 

Use this register to control several measurement settings. 

|User overange disable.<br>Bandwidth.<br>100: 3200 Hz Bandwidth.<br>011: 1600 Hz Bandwidth.<br>010: 800 Hz Bandwidth.<br>001: 400 Hz Bandwidth.<br>000: 200 Hz Bandwidth.<br>Autosleep.<br>Low Noise.<br>1: Low noise operation.<br>0: Norm al operation.<br>Link/Loop Activity Processing.<br>10: Looped Mode.<br>1: Linked Mode.<br>0: Default Mode.<br>0<br>0<br>1<br>0<br>2<br>0<br>3<br>0<br>4<br>0<br>5<br>0<br>6<br>0<br>7<br>0<br>**[7 ] USER_OR_DISABLE (R/W )**<br>**[2 :0 ] BANDW IDTH (R/W )**<br>**[6 ] AUTOSLEEP (R/W )**<br>**[3 ] LOW _NOISE (R/W )**<br>**[5 :4 ] LINKLOOP (R/W )**<br>**Table 65. Bit Descriptions for MEASURE**|User overange disable.<br>Bandwidth.<br>100: 3200 Hz Bandwidth.<br>011: 1600 Hz Bandwidth.<br>010: 800 Hz Bandwidth.<br>001: 400 Hz Bandwidth.<br>000: 200 Hz Bandwidth.<br>Autosleep.<br>Low Noise.<br>1: Low noise operation.<br>0: Norm al operation.<br>Link/Loop Activity Processing.<br>10: Looped Mode.<br>1: Linked Mode.<br>0: Default Mode.<br>0<br>0<br>1<br>0<br>2<br>0<br>3<br>0<br>4<br>0<br>5<br>0<br>6<br>0<br>7<br>0<br>**[7 ] USER_OR_DISABLE (R/W )**<br>**[2 :0 ] BANDW IDTH (R/W )**<br>**[6 ] AUTOSLEEP (R/W )**<br>**[3 ] LOW _NOISE (R/W )**<br>**[5 :4 ] LINKLOOP (R/W )**<br>**Table 65. Bit Descriptions for MEASURE**|User overange disable.<br>Bandwidth.<br>100: 3200 Hz Bandwidth.<br>011: 1600 Hz Bandwidth.<br>010: 800 Hz Bandwidth.<br>001: 400 Hz Bandwidth.<br>000: 200 Hz Bandwidth.<br>Autosleep.<br>Low Noise.<br>1: Low noise operation.<br>0: Norm al operation.<br>Link/Loop Activity Processing.<br>10: Looped Mode.<br>1: Linked Mode.<br>0: Default Mode.<br>0<br>0<br>1<br>0<br>2<br>0<br>3<br>0<br>4<br>0<br>5<br>0<br>6<br>0<br>7<br>0<br>**[7 ] USER_OR_DISABLE (R/W )**<br>**[2 :0 ] BANDW IDTH (R/W )**<br>**[6 ] AUTOSLEEP (R/W )**<br>**[3 ] LOW _NOISE (R/W )**<br>**[5 :4 ] LINKLOOP (R/W )**<br>**Table 65. Bit Descriptions for MEASURE**|User overange disable.<br>Bandwidth.<br>100: 3200 Hz Bandwidth.<br>011: 1600 Hz Bandwidth.<br>010: 800 Hz Bandwidth.<br>001: 400 Hz Bandwidth.<br>000: 200 Hz Bandwidth.<br>Autosleep.<br>Low Noise.<br>1: Low noise operation.<br>0: Norm al operation.<br>Link/Loop Activity Processing.<br>10: Looped Mode.<br>1: Linked Mode.<br>0: Default Mode.<br>0<br>0<br>1<br>0<br>2<br>0<br>3<br>0<br>4<br>0<br>5<br>0<br>6<br>0<br>7<br>0<br>**[7 ] USER_OR_DISABLE (R/W )**<br>**[2 :0 ] BANDW IDTH (R/W )**<br>**[6 ] AUTOSLEEP (R/W )**<br>**[3 ] LOW _NOISE (R/W )**<br>**[5 :4 ] LINKLOOP (R/W )**<br>**Table 65. Bit Descriptions for MEASURE**|User overange disable.<br>Bandwidth.<br>100: 3200 Hz Bandwidth.<br>011: 1600 Hz Bandwidth.<br>010: 800 Hz Bandwidth.<br>001: 400 Hz Bandwidth.<br>000: 200 Hz Bandwidth.<br>Autosleep.<br>Low Noise.<br>1: Low noise operation.<br>0: Norm al operation.<br>Link/Loop Activity Processing.<br>10: Looped Mode.<br>1: Linked Mode.<br>0: Default Mode.<br>0<br>0<br>1<br>0<br>2<br>0<br>3<br>0<br>4<br>0<br>5<br>0<br>6<br>0<br>7<br>0<br>**[7 ] USER_OR_DISABLE (R/W )**<br>**[2 :0 ] BANDW IDTH (R/W )**<br>**[6 ] AUTOSLEEP (R/W )**<br>**[3 ] LOW _NOISE (R/W )**<br>**[5 :4 ] LINKLOOP (R/W )**<br>**Table 65. Bit Descriptions for MEASURE**|User overange disable.<br>Bandwidth.<br>100: 3200 Hz Bandwidth.<br>011: 1600 Hz Bandwidth.<br>010: 800 Hz Bandwidth.<br>001: 400 Hz Bandwidth.<br>000: 200 Hz Bandwidth.<br>Autosleep.<br>Low Noise.<br>1: Low noise operation.<br>0: Norm al operation.<br>Link/Loop Activity Processing.<br>10: Looped Mode.<br>1: Linked Mode.<br>0: Default Mode.<br>0<br>0<br>1<br>0<br>2<br>0<br>3<br>0<br>4<br>0<br>5<br>0<br>6<br>0<br>7<br>0<br>**[7 ] USER_OR_DISABLE (R/W )**<br>**[2 :0 ] BANDW IDTH (R/W )**<br>**[6 ] AUTOSLEEP (R/W )**<br>**[3 ] LOW _NOISE (R/W )**<br>**[5 :4 ] LINKLOOP (R/W )**<br>**Table 65. Bit Descriptions for MEASURE**|
|---|---|---|---|---|---|
|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|7|USER_OR_DISABLE||User overange disable.|0x0|R/W|
|6|AUTOSLEEP||Autosleep. When set to 1, autosleep is enabled, and the device enters wake-up<br>mode automatically upon detection of inactivity. Activity and inactivity<br>detection must be in linked mode or loop mode (the LINKLOOP bits in the<br>MEASURE register) to enable autosleep; otherwise, the bit is ignored.|0x0|R/W|
|[5:4]|LINKLOOP|0<br>1<br>10|Link/Loop Activity Processing. These bits select how activity and inactivity<br>processing are linked.<br>Default Mode. Activity and inactivity detection, when enabled, operate<br>simultaneously and their interrupts (if mapped) must be acknowledged by<br>the host processor by reading the status register. Autosleep is disabled in this<br>mode.<br>Linked Mode. Activity and inactivity detection are linked sequentially such that<br>only one is enabled at a time. Their interrupts (if mapped) must be acknowledged<br>by the host processor by reading the status register.<br>Looped Mode. Activity and inactivity detection are linked sequentially such<br>that only one is enabled at a time, and their interrupts are internally acknowledged<br>(do not need to be serviced by the host processor). To use either linked or looped<br>mode, both ACT_x_EN and INACT_x_EN must be set to 1; otherwise, the default<br>mode is used. For additional information, refer to the Linking Activity and<br>Inactivity Detection section.|0x0|R/W|



Rev. B | Page 51 of 56 

**ADXL372** 

**Data Sheet** 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|3|LOW_NOISE|0<br>1|Low Noise. Selects low noise operation.<br>Normal operation. Device operates at the normal noise level and ultralow<br>current consumption<br>Low noise operation. Device operates at ~1/3 the normal noise level.|0x0|R/W|
|[2:0]|BANDWIDTH|000<br>001<br>010<br>011<br>100|Bandwidth. Select the desired output signal bandwidth. A 4-pole low-pass<br>filter at the selected frequency limits the signal bandwidth.<br>200 Hz Bandwidth.<br>400 Hz Bandwidth.<br>800 Hz Bandwidth.<br>1600 Hz Bandwidth.<br>3200 Hz Bandwidth.|0x0|R/W|



## **POWER CONTROL REGISTER** 

|**Address: 0x3F, Reset: 0x00, Name: POWER_CTL**<br>I2C speed select. 1=  High speed mode.<br>Mode of operation.<br>00: Standby.<br>01: Wakeup mode.<br>10: Instant on mode.<br>11: Full bandwidth measurement mode.<br>Disables the digital high-pass filter.<br>User selectable instant on threshold<br>select. 0 =  low threshold 1 =  high threshold.<br>1: Selects the high instant on threshold.<br>0: Selects the low instant on threshold.<br>Disables the digital low-pass filter.<br>User selectable filter settling period.<br>0 =  370 ms settle period, and 1 =  16<br>ms settle period.<br>0: Filter settling set to 370 ms.<br>1:<br>when HPF and LPF are disabled.<br>Filter settling set to 16 ms. Ideal for<br>0<br>0<br>1<br>0<br>2<br>0<br>3<br>0<br>4<br>0<br>5<br>0<br>6<br>0<br>7<br>0<br>**[ 7 ] I2C_HSM _EN ( R/W )**<br>**[ 1:0 ] M O DE ( R/W )**<br>**[ 6 ] RESERVED**<br>**[ 2] HPF_DISABLE ( R/W )**<br>**[ 5] INST ANT _O N_T HRESH ( R/W )**<br>**[ 3] LPF_DISABLE ( R/W )**<br>**[ 4 ] FILT ER_SET T LE ( R/W )**<br>**Table 66. Bit Descriptions for POWER_CTL**|**Address: 0x3F, Reset: 0x00, Name: POWER_CTL**<br>I2C speed select. 1=  High speed mode.<br>Mode of operation.<br>00: Standby.<br>01: Wakeup mode.<br>10: Instant on mode.<br>11: Full bandwidth measurement mode.<br>Disables the digital high-pass filter.<br>User selectable instant on threshold<br>select. 0 =  low threshold 1 =  high threshold.<br>1: Selects the high instant on threshold.<br>0: Selects the low instant on threshold.<br>Disables the digital low-pass filter.<br>User selectable filter settling period.<br>0 =  370 ms settle period, and 1 =  16<br>ms settle period.<br>0: Filter settling set to 370 ms.<br>1:<br>when HPF and LPF are disabled.<br>Filter settling set to 16 ms. Ideal for<br>0<br>0<br>1<br>0<br>2<br>0<br>3<br>0<br>4<br>0<br>5<br>0<br>6<br>0<br>7<br>0<br>**[ 7 ] I2C_HSM _EN ( R/W )**<br>**[ 1:0 ] M O DE ( R/W )**<br>**[ 6 ] RESERVED**<br>**[ 2] HPF_DISABLE ( R/W )**<br>**[ 5] INST ANT _O N_T HRESH ( R/W )**<br>**[ 3] LPF_DISABLE ( R/W )**<br>**[ 4 ] FILT ER_SET T LE ( R/W )**<br>**Table 66. Bit Descriptions for POWER_CTL**|**Address: 0x3F, Reset: 0x00, Name: POWER_CTL**<br>I2C speed select. 1=  High speed mode.<br>Mode of operation.<br>00: Standby.<br>01: Wakeup mode.<br>10: Instant on mode.<br>11: Full bandwidth measurement mode.<br>Disables the digital high-pass filter.<br>User selectable instant on threshold<br>select. 0 =  low threshold 1 =  high threshold.<br>1: Selects the high instant on threshold.<br>0: Selects the low instant on threshold.<br>Disables the digital low-pass filter.<br>User selectable filter settling period.<br>0 =  370 ms settle period, and 1 =  16<br>ms settle period.<br>0: Filter settling set to 370 ms.<br>1:<br>when HPF and LPF are disabled.<br>Filter settling set to 16 ms. Ideal for<br>0<br>0<br>1<br>0<br>2<br>0<br>3<br>0<br>4<br>0<br>5<br>0<br>6<br>0<br>7<br>0<br>**[ 7 ] I2C_HSM _EN ( R/W )**<br>**[ 1:0 ] M O DE ( R/W )**<br>**[ 6 ] RESERVED**<br>**[ 2] HPF_DISABLE ( R/W )**<br>**[ 5] INST ANT _O N_T HRESH ( R/W )**<br>**[ 3] LPF_DISABLE ( R/W )**<br>**[ 4 ] FILT ER_SET T LE ( R/W )**<br>**Table 66. Bit Descriptions for POWER_CTL**|**Address: 0x3F, Reset: 0x00, Name: POWER_CTL**<br>I2C speed select. 1=  High speed mode.<br>Mode of operation.<br>00: Standby.<br>01: Wakeup mode.<br>10: Instant on mode.<br>11: Full bandwidth measurement mode.<br>Disables the digital high-pass filter.<br>User selectable instant on threshold<br>select. 0 =  low threshold 1 =  high threshold.<br>1: Selects the high instant on threshold.<br>0: Selects the low instant on threshold.<br>Disables the digital low-pass filter.<br>User selectable filter settling period.<br>0 =  370 ms settle period, and 1 =  16<br>ms settle period.<br>0: Filter settling set to 370 ms.<br>1:<br>when HPF and LPF are disabled.<br>Filter settling set to 16 ms. Ideal for<br>0<br>0<br>1<br>0<br>2<br>0<br>3<br>0<br>4<br>0<br>5<br>0<br>6<br>0<br>7<br>0<br>**[ 7 ] I2C_HSM _EN ( R/W )**<br>**[ 1:0 ] M O DE ( R/W )**<br>**[ 6 ] RESERVED**<br>**[ 2] HPF_DISABLE ( R/W )**<br>**[ 5] INST ANT _O N_T HRESH ( R/W )**<br>**[ 3] LPF_DISABLE ( R/W )**<br>**[ 4 ] FILT ER_SET T LE ( R/W )**<br>**Table 66. Bit Descriptions for POWER_CTL**|||
|---|---|---|---|---|---|
|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|7|I2C_HSM_EN||I2C speed select. 1 = high speed mode.|0x0|R/W|
|6|RESERVED||Reserved.|0x0|R|
|5|INSTANT_ON_THRESH|0<br>1|User selectable instant on threshold select. 0 = low threshold, 1 = high<br>threshold.<br>Selects the low instant on threshold.<br>Selects the high instant on threshold.|0x0|R/W|
|4|FILTER_SETTLE|0<br>1|User selectable filter settling period. 0 = 370 ms settle period, and 1 = 16 ms<br>settle period.<br>Filter settling set to 370 ms.<br>Filter settling set to 16 ms. Ideal for when HPF and LPF are disabled.|0x0|R/W|
|3|LPF_DISABLE||Disables the digital low-pass filter.|0x0|R/W|
|2|HPF_DISABLE||Disables the digital high-pass filter.|0x0|R/W|
|[1:0]|MODE|11<br>10<br>01<br>00|Mode of operation.<br>Full bandwidth measurement mode.<br>Instant on mode.<br>Wake up mode.<br>Standby.|0x0|R/W|



Rev. B | Page 52 of 56 

**Data Sheet** 

**ADXL372** 

## **SELF TEST REGISTER** 

**Address: 0x40, Reset: 0x00, Name: SELF_TEST** 

Refer to the Self Test section for information on the operation of the self test feature, and see the Self Test Procedure section for guidelines on how to use this functionality. 

**==> picture [402 x 81] intentionally omitted <==**

**----- Start of picture text -----**<br>
7 6 5 4 3 2 1 0<br>0 0 0 0 0 0 0 0<br>[ 7 :3] RESERVED [ 0 ] ST  ( R/W 1)<br>Self test.<br>[ 2] USER_ST  ( R)<br>User self test pass if =  1. [ 1] ST _DO NE ( R)<br>Self test finished.<br>_TEST TEST<br>**----- End of picture text -----**<br>


**Table 67. Bit Descriptions for SELF_TEST TEST** 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:3]|RESERVED||Reserved.|0x0|R|
|2|USER_ST||User self test pass if = 1.|0x0|R|
|1|ST_DONE||Self test finished.|0x0|R|
|0|ST||Self test. Writing a 1 to this bit initiates self test. Writing a 0 clears self test.|0x0|R/W1|



## **RESET (CLEARS) REGISTER, PART IN STANDBY MODE** 

**Address: 0x41, Reset: 0x00, Name: RESET** 

7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 **[7 :0 ] RESET (W )** Writing code "0x52" resets the device. **Table 68. Bit Descriptions for RESET Bits Bit Name Settings Description Reset Access** [7:0] Reset Writing code 0x52 resets the device. 0x0 W 

## **FIFO ACCESS REGISTER** 

**Address: 0x42, Reset: 0x00, Name: FIFO_DATA** 

Read this register to access data stored in the FIFO. 

**==> picture [73 x 15] intentionally omitted <==**

**----- Start of picture text -----**<br>
7 6 5 4 3 2 1 0<br>0 0 0 0 0 0 0 0<br>**----- End of picture text -----**<br>


**[7 :0 ] FIFO_DATA (R)** FIFO Data. 

**Table 69. Bit Descriptions for FIFO_DATA** 

|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|FIFO_DATA||FIFO Data. A read to this address pops a 2-byte word of axis data from the FIFO. FIFO<br>data is formatted to 2 bytes (16 bits), most significant byte first. Two subsequent reads<br>complete the transaction of this data onto the interface. Continued reading of this field<br>continues to pop the FIFO every third read. Multibyte reads to this address do not<br>increment the address pointer. If this address is read due to an auto-increment from the<br>previous address, it does not pop the FIFO. It returns zeros and increment on to the<br>next address.|0x0|R|



Rev. B | Page 53 of 56 

**ADXL372** 

**Data Sheet** 

## **APPLICATIONS INFORMATION** 

## **APPLICATION EXAMPLES** 

This section includes a few application circuits, highlighting useful features of the ADXL372. 

## _**Power Supply Decoupling**_ 

Figure 48 shows the recommended bypass capacitors for use with the ADXL372. 

**==> picture [229 x 108] intentionally omitted <==**

**----- Start of picture text -----**<br>
VS VDD I/O<br>CS CIO<br>VS VDD I/O<br>ADXL372<br>MOSI<br>INT1 MISO SPI<br>INTERRUPTCONTROL SCLK INTERFACE<br>INT2 GND CS 15430-048<br>**----- End of picture text -----**<br>


_Figure 48. Recommended Bypass Capacitors_ 

A 0.1 µF ceramic capacitor (CS) at VS and a 0.1 µF ceramic capacitor (CIO) at VDDI/O placed as close as possible to the ADXL372 supply pins are recommended to adequately decouple the accelerometer from noise on the power supply. It is recommended that VS and VDDI/O be separate supplies to minimize digital clocking noise on the VS supply. If this is not possible, additional filtering of the supplies may be necessary. 

If additional decoupling is necessary, a resistor or ferrite bead, no larger than 100 Ω, in series with VS, is recommended. Additionally, increasing the bypass capacitance on VS to a 1 µF tantalum capacitor in parallel with a 0.1 µF ceramic capacitor may also improve noise. 

Ensure that the connection from the ADXL372 ground to the power supply ground has low impedance because noise transmitted through ground has an effect similar to noise transmitted through VS. 

## _**Using External Timing Triggers**_ 

Figure 49 shows an application diagram for using the INT1 pin as the input for an external clock. In this mode, the external clock determines all accelerometer timing, including the output data rate and bandwidth. 

Set the EXT_CLK bit in the TIMING register to enable this feature. 

**==> picture [223 x 108] intentionally omitted <==**

**----- Start of picture text -----**<br>
VS VDD I/O<br>CS CIO<br>VS VDD I/O<br>ADXL372<br>MOSI<br>EXTERNALCLOCK INT1 MISO SPI<br>SCLK INTERFACE<br>INTERRUPT<br>CONTROL INT2 GND CS 15430-049<br>**----- End of picture text -----**<br>


Figure 50 is an application diagram for using the INT2 pin as a trigger for synchronized sampling. Acceleration samples are produced every time this trigger is activated. Set the EXT_SYNC bit in the TIMING register to enable this feature. 

**==> picture [217 x 108] intentionally omitted <==**

**----- Start of picture text -----**<br>
VS VDD I/O<br>CS CIO<br>VS VDD I/O<br>ADXL372<br>MOSI<br>INTERRUPT<br>CONTROL INT1 MISO SPI<br>SCLK INTERFACE<br>SAMPLINGTRIGGER INT2 GND CS 15430-050<br>**----- End of picture text -----**<br>


_Figure 50. Using the INT2 Pin to Trigger Synchronized Sampling_ 

## **OPERATION AT VOLTAGES OTHER THAN 2.5 V** 

The ADXL372 is tested and specified at a supply voltage of VS = 2.5 V; however, it can be powered with a VS as high as 3.5 V or as low as 1.6 V. Some performance parameters change as the supply voltage changes, including the supply current, noise, offset, and sensitivity. 

## **OPERATION AT TEMPERATURES OTHER THAN AMBIENT** 

The ADXL372 is tested and specified at an ambient temperature; however, it is rated for temperatures between −40°C and +105°C. Some performance parameters change along with temperature, such as offset, sensitivity, clock performance, and current. Some of these temperature variations are characterized in Table 1, and others are shown in the figures within the Typical Performance Characteristics section. 

## **MECHANICAL CONSIDERATIONS FOR MOUNTING** 

Mount the ADXL372 on the PCB in a location close to a hard mounting point of the PCB to the case. Mounting the ADXL372 at an unsupported PCB location, as shown in Figure 51, can result in large, apparent measurement errors due to undamped PCB vibration. Locating the accelerometer near a hard mounting point ensures that any PCB vibration at the accelerometer is above the mechanical sensor resonant frequency of the accelerometer and, therefore, effectively invisible to the accelerometer. Multiple mounting points, close to the sensor, and/or a thicker PCB also help to reduce the effect of system resonance on the performance of the sensor. 

**==> picture [179 x 61] intentionally omitted <==**

**----- Start of picture text -----**<br>
ACCELEROMETERS<br>PCB<br>MOUNTING POINTS 15430-051<br>**----- End of picture text -----**<br>


_Figure 51. Incorrectly Placed Accelerometers_ 

_Figure 49. INT1 Pin as Input for External Clock_ 

Rev. B | Page 54 of 56 

**Data Sheet** 

**ADXL372** 

## **AXES OF ACCELERATION SENSITIVITY** 

**==> picture [8 x 7] intentionally omitted <==**

**----- Start of picture text -----**<br>
AZ<br>**----- End of picture text -----**<br>


**==> picture [189 x 101] intentionally omitted <==**

**----- Start of picture text -----**<br>
AY<br>AX 15430-052<br>**----- End of picture text -----**<br>


_Figure 52. Axes of Acceleration Sensitivity (Corresponding Output Increases When Accelerated Along the Sensitive Axis)_ 

**==> picture [337 x 238] intentionally omitted <==**

**----- Start of picture text -----**<br>
XOUT = 1 g<br>YOUT = 0 g<br>ZOUT = 0 g<br>TOP<br>XOUT = 0 g XOUT = 0 g<br>YOUT = –1 g TOP TOP YOUT = 1 g<br>ZOUT = 0 g ZOUT = 0 g<br>GRAVITY<br>TOP<br>XOUT = –1 g<br>YOUT = 0 g<br>ZOUT = 0 g<br>XOUT = 0 g XOUT = 0 g<br>YOUT = 0 g YOUT = 0 g<br>ZOUT = 1 g ZOUT = –1 g 15430-053<br>**----- End of picture text -----**<br>


_Figure 53. Output Response vs. Orientation to Gravity_ 

## **LAYOUT AND DESIGN RECOMMENDATIONS** 

Figure 54 shows the recommended printed wiring board land pattern. 

**==> picture [162 x 134] intentionally omitted <==**

**----- Start of picture text -----**<br>
0.9250<br>0.3000<br>3.3500<br>0.5000<br>0.8000<br>3.5000<br>15430-054<br>**----- End of picture text -----**<br>


_Figure 54. Recommended Printed Wiring Board Land Pattern (Dimensions Shown in Millimeters)_ 

Rev. B | Page 55 of 56 

**ADXL372** 

**Data Sheet** 

## **OUTLINE DIMENSIONS** 

**==> picture [289 x 160] intentionally omitted <==**

**----- Start of picture text -----**<br>
3.30<br>3.25 1.00<br>PIN 1 3.15 0.10 REF 0.25 × 0.35<br>CORNER REF REF<br>13 1<br>0.50 14 16<br>BSC<br>3.10<br>3.00<br>2.90<br>0.375REF 9 8 6 5 0.475REF × 0.25<br>TOP VIEW BOTTOM VIEW<br>0.3375<br>REF<br>1.14<br>1.06 END VIEW<br>1.00<br>SEATING<br>PLANE<br>PKG-003967 05-07-2015-C<br>**----- End of picture text -----**<br>


_Figure 55. 16-Terminal Land Grid Array [LGA] (CC-16-4) Dimensions shown in millimeters_ 

|**ORDERING GUIDE**|||||
|---|---|---|---|---|
|**Model1**|**Temperature Range **|**Package Description**|**Package Option**|**Quantity**|
|ADXL372BCCZ-RL<br>ADXL372BCCZ-RL7<br>EVAL-ADXL372Z|−40°C to +105°C<br>−40°C to +105°C<br>−40°C to +105°C|16-Terminal Land Grid Array [LGA]<br>16-Terminal Land Grid Array [LGA]<br>Breakout Board|CC-16-4<br>CC-16-4|5,000<br>1,500|



1 Z = RoHS Compliant Part. 

**©2017–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D15430-0-8/18(B)** 

Rev. B | Page 56 of 56
Updated at April 28, 2026
Since its inception in 1965, Analog Devices has established itself as a global leader in the design and manufacturing of high-performance analog, mixed-signal, and digital signal processing (DSP) integrated circuits. The company is renowned for solving complex engineering challenges by providing critical technologies that seamlessly convert real-world phenomena into precise electrical signals for the industrial, automotive, communications, and consumer markets. Within its extensive portfolio, Analog Devices provides highly reliable clock, timing, and frequency management solutions, featuring a comprehensive array of precision timers, oscillators, and pulse generators. Complementing this core lineup is a robust offering of driver and interface ICs, particularly high-performance I/O expanders that enable seamless connectivity and streamline complex electronic system architectures. Beyond these foundational integrated circuits, Analog Devices leads the industry in sensor innovation, delivering advanced MEMS accelerometers and integrated MEMS modules designed for exceptional precision in motion sensing. To support complete hardware designs, the company's specialized offerings also encompass discrete bipolar transistors, sub-2.4GHz RF transceivers, temperature-compensated oscillators, and dedicated power management components such as DC/DC converters and LED driver ICs.
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