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ADXL363BCCZ-RL7
MEMS Accelerometer, Micropower, ± 2g, ± 4g, ± 8g, X, Y, Z, SPI, LGA, 16 Pins
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- Manufacturer: ANALOG DEVICES
- Product type: MEMS Accelerometers
- SVHC: No SVHC (04-Feb-2026)
- No. of Pins: 16Pins
- Sensing Axis: X, Y, Z
- Product Range: -
- Qualification: -
- Sensitivity Typ: 1mg/LSB, 2mg/LSB, 4mg/LSB
- Output Interface: SPI
- Sensor Case Style: LGA
- MEMS Sensor Output: Digital
- Supply Voltage Max: 3.5V
- Supply Voltage Min: 1.6V
- Sensor Case / Package: LGA
- Operating Temperature Max: 85°C
- Operating Temperature Min: -40°C
- Sensing Range - Accelerometer: ± 2g, ± 4g, ± 8g
| Delivery and price | |
|---|---|
| Units per pack | 500 |
| Price | 5.59 € |
| Current stock | 1000+ |
| Lead time | 30 days |
Datasheet
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## **Micropower 3-Sensor Combination Includin Acceleration and Tem erature g p**
## **Data Sheet**
## **ADXL363**
## **FEATURES**
**Accelerometer, temperature sensor, and provision for third analog sensor input**
**All sensors sampled synchronously Up to 400 Hz ODR**
**Samples can be synchronized to external trigger Ultralow power**
**1.95 µA at 100 Hz ODR, 2.0 V supply, all sensors on 270 nA at 6 Hz motion activated wake-up mode 10 nA standby current**
## **GENERAL DESCRIPTION**
The ADXL363 is an ultralow power, three-sensor combination consisting of a 3-axis MEMS accelerometer, a temperature sensor, and an on-board analog-to-digital converter (ADC) input for synchronous conversion of an external signal. The entire system consumes less than 2 µA at a 100 Hz output data rate and 270 nA when in motion triggered wake-up mode.
The ADXL363 communicates via a serial port interface (SPI) and always provides 12-bit output resolution for all three sensors.
**12-bit resolution for all sensors**
**Acceleration scale factor down to 1 m** _**g**_ **/LSB**
**Temperature scale factor: 0.065°C/LSB (typical)**
**Built-in features for motion-based system level power savings Adjustable threshold sleep/wake modes for motion activation**
**Autonomous interrupt processing, without need for microcontroller intervention, to allow the rest of the system to be turned off completely**
**Deep embedded FIFO minimizes host processor load Awake state output enables implementation of**
**standalone, motion activated switch**
**Wide supply and I/O voltage ranges: 1.6 V to 3.5 V Operates off 1.8 V to 3.3 V rails Power can be derived from coin cell battery SPI digital interface Small and thin 3 mm × 3.25 mm × 1.06 mm package**
## **APPLICATIONS**
The ADXL363 accelerometer provides selectable measurement ranges of ±2 _g_ , ±4 _g_ , and ±8 _g_ , with a resolution of 1 m _g_ /LSB on the ±2 _g_ range. Unlike accelerometers that use power duty cycling to achieve low power consumption, the ADXL363 does not alias input signals by undersampling; it samples the full bandwidth of the sensor at all data rates.
The ADXL363 temperature sensor operates with a scale factor of 0.065°C/LSB (typical). Acceleration and temperature data can be stored in a 512-sample multimode first in, first out (FIFO) buffer, allowing up to 13 sec of data to be stored.
In addition to the accelerometer and temperature sensor, the ADXL363 also provides access to an internal ADC for synchronous conversion of an additional analog input.
The ADXL363 operates on a wide 1.6 V to 3.5 V supply range, and can interface, if necessary, to a host operating on a separate, lower supply voltage. The ADXL363 is available in a 3 mm × 3.25 mm × 1.06 mm package.
## **Home healthcare devices Wireless sensors**
## **Motion enabled metering devices**
## **FUNCTIONAL BLOCK DIAGRAM**
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VS VDD I/O<br>3-AXIS INT1<br>MEMS<br>SENSOR INT2<br>12-BITADC DIGITALFIFO MOSI<br>AND MISO<br>SPI<br>CS<br>AXIS ANTIALIASING<br>DEMODULATORS FILTERS SCLK<br>TEMPERATURE<br>SENSOR ADXL363<br>GND ADC_IN<br>Figure 1.<br>11719-001<br>**----- End of picture text -----**<br>
**Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.**
**One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com**
**ADXL363**
**Data Sheet**
## **TABLE OF CONTENTS**
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 ADXL363 Specifications .............................................................. 4 Accelerometer Specifications ...................................................... 4 Temperature Sensor Specifications ............................................ 5 12-Bit ADC Specifications .......................................................... 6 Absolute Maximum Ratings ............................................................ 7 Thermal Resistance ...................................................................... 7 Recommended Soldering Profile ............................................... 7 ESD Caution .................................................................................. 7 Pin Configuration and Function Descriptions ............................. 8 Typical Performance Characteristics ............................................. 9 Theory of Operation ...................................................................... 14 Accelerometer ............................................................................. 14 ADC ............................................................................................. 15 Temperature Sensor ................................................................... 16 Power Savings Features .................................................................. 17 Ultralow Power Consumption in All Modes, Operating All Sensors ......................................................................................... 17 Motion Detection ....................................................................... 17 FIFO ............................................................................................. 19 Communications ........................................................................ 19 Additional Features ........................................................................ 20 External Clock ............................................................................ 20 Synchronized Data Sampling .................................................... 20 Self Test ........................................................................................ 20 User Register Protection ............................................................ 20 Serial Communications ................................................................. 21 SPI Commands ........................................................................... 21 Multibyte Transfers .................................................................... 21 Invalid Addresses and Address Folding .................................. 21 Latency Restrictions ................................................................... 22 Invalid Commands ..................................................................... 22 Register Map .................................................................................... 25 Register Details ............................................................................... 26
Device ID Registers .................................................................... 26 Silicon Revision ID Register ..................................................... 26 X-Axis Data (8 MSB) Register .................................................. 26 Y-Axis Data (8 MSB) Register .................................................. 26 Z-Axis Data (8 MSB) Register .................................................. 26 Status Register ............................................................................. 27 FIFO Entries Registers ............................................................... 28 X-Axis Data Registers ................................................................ 28 Y-Axis Data Registers ................................................................ 28 Z-Axis Data Registers ................................................................ 28 Temperature Data Registers ...................................................... 28 ADC Data Registers ................................................................... 28 Soft Reset Register ...................................................................... 29 Activity Threshold Registers ..................................................... 29 Activity Time Register ............................................................... 29 Inactivity Threshold Registers .................................................. 29 Inactivity Time Registers ........................................................... 29 Activity/Inactivity Control Register ........................................ 31 FIFO Control Register ............................................................... 32 FIFO Samples Register .............................................................. 33 INT1/INT2 Function Map Registers ....................................... 33 Filter Control Register ............................................................... 35 Power Control Register ............................................................. 36 Self Test Register ......................................................................... 37 Applications Information .............................................................. 38 Application Examples ................................................................ 38 Using External Timing .............................................................. 38 Power ............................................................................................ 39 FIFO Modes ................................................................................ 40 Interrupts ..................................................................................... 41 Using Self Test ............................................................................. 42 Operation at Voltages Other Than 2.0 V ................................ 43 Mechanical Considerations for Mounting .............................. 43 Axes of Acceleration Sensitivity ............................................... 44 Layout and Design Recommendations ................................... 44 Outline Dimensions ....................................................................... 45 Ordering Guide .......................................................................... 45
Rev. A | Page 2 of 45
**ADXL363**
**Data Sheet**
## **REVISION HISTORY**
**7/2018—Rev. 0 to Rev. A** Changes to Table 12 ........................................................................ 24 Updated Outline Dimensions ........................................................ 45
## **10/2013—Revision 0: Initial Version**
Rev. A | Page 3 of 45
**ADXL363**
**Data Sheet**
## **SPECIFICATIONS**
TA = 25°C, VS = 2.0 V, VDD I/O = 2.0 V, 100 Hz ODR, acceleration = 0 _g_ , default register settings, unless otherwise noted. All minimum and maximum specifications are guaranteed. Typical specifications may not be guaranteed.
## **ADXL363 SPECIFICATIONS**
**Table 1.**
|**Table 1.**||||
|---|---|---|---|
|**Parameter**|**Test Conditions/Comments**|**Min**<br>**Typ**<br>**Max**|**Unit**|
|OUTPUT RESOLUTION<br>All Sensors||12|Bits|
|SUPPLY CURRENT<br>Measurement Mode<br>Standby|All sensors on (ADC_EN = 1)|1.95<br>10|µA<br>nA|
|OUTPUT DATA RATE (ODR)|User selectable in eight steps|12.5<br>400|Hz|
|POWER SUPPLY REJECTION (PSRR)<br>Input Frequency 100 Hz to 1 kHz<br>Input Frequency1 kHz to 250 kHz|CS= 1.0 µF, RS= 100 Ω, CIO= 1.1 µF,<br>input is 100 mV sine wave on VS|−13<br>−20|dB<br>dB|
|TURN-ON TIME<br>Power-Up to Standby<br>Measurement Mode Instruction to Valid Data|50 Hz bandwidth|5<br>4/ODR|ms|
|POWER SUPPLY REQUIREMENTS<br>Operating Voltage Range (VS) <br>I/O Voltage Range (VDD I/O)||1.6<br>2.0<br>3.5<br>1.6<br>2.0<br>VS|V<br>V|
|ENVIRONMENTAL<br>OperatingTemperature Range||−40<br>+85|°C|
## **ACCELEROMETER SPECIFICATIONS**
**Table 2.**
|**Table 2.**||||
|---|---|---|---|
|**Parameter**|**Test Conditions/Comments**|**Min**<br>**Typ**<br>**Max**|**Unit**|
|SENSOR INPUT<br>Measurement Range<br>Nonlinearity<br>Sensor Resonant Frequency<br>Cross Axis Sensitivity1|Each axis<br>User selectable<br>Percentage of full scale|±2, ±4, ±8<br>±0.5<br>3500<br>±1.5|_g_<br>%<br>Hz<br>%|
|SUPPLY CURRENT<br>Measurement Mode<br>Normal Operation<br>Accelerometer Low Noise Mode<br>Accelerometer Ultralow Noise Mode<br>Wake-UpMode|100 Hz ODR (50 Hz bandwidth)2,<br>ADC_EN = 0|1.8<br>3.3<br>13<br>270|µA<br>µA<br>µA<br>nA|
|SCALE FACTOR<br>Scale Factor Calibration Error <br>Scale Factor<br>Scale Factor Change Due to Temperature3|Each axis<br>Measured in m_g_/LSB<br>±2_g_range<br>±4_g_range<br>±8_g_range<br>Measured in LSB/_g_<br>±2_g_range<br>±4_g_range<br>±8_g_range<br>−40°C to +85°C|±10<br>1<br>2<br>4<br>1000<br>500<br>250<br>0.05|%<br>m_g_/LSB<br>m_g_/LSB<br>m_g_/LSB<br>LSB/_g_<br>LSB/_g_<br>LSB/_g_<br>%/°C|
Rev. A | Page 4 of 45
**Data Sheet ADXL363**
|**Parameter**|**Test Conditions/Comments**|**Min**<br>**Typ**<br>**Max**|**Unit**|
|---|---|---|---|
|0_g_OFFSET<br>0_g_Output|XOUT, YOUT<br>ZOUT|−150<br>±35<br>+150<br>−250<br>±50<br>+250|m_g_<br>m_g_|
|0_g_Offset vs. Temperature3<br>Normal Operation<br>Low Noise Mode and Ultralow Noise Mode|XOUT, YOUT<br>ZOUT<br>XOUT, YOUT, ZOUT|±0.5<br>±0.6<br>±0.35|m_g_/°C<br>m_g_/°C<br>m_g_/°C|
|NOISE PERFORMANCE<br>Noise Density<br>Normal Operation<br>Low Noise Mode<br>Ultralow Noise Mode|XOUT, YOUT<br>ZOUT<br>XOUT, YOUT<br>ZOUT<br>XOUT, YOUT<br>ZOUT<br>VS= 3.5 V; XOUT, YOUT<br>VS= 3.5 V; ZOUT|550<br>920<br>400<br>550<br>250<br>350<br>175<br>250|µ_g_/√Hz<br>µ_g_/√Hz<br>µ_g_/√Hz<br>µ_g_/√Hz<br>µ_g_/√Hz<br>µ_g_/√Hz<br>µ_g_/√Hz<br>µ_g_/√Hz|
|BANDWIDTH<br>Low-Pass (Antialiasing) Filter, −3 dB Corner<br>Output Data Rate (ODR)|HALF_BW = 0<br>HALF_BW = 1<br>User selectable in eight steps|ODR/2<br>ODR/4<br>12.5<br>400|Hz<br>Hz<br>Hz|
|SELF TEST<br>Output Change4|XOUT<br>YOUT<br>ZOUT|450<br>580<br>710<br>−710<br>−580<br>−450<br>350<br>500<br>650|m_g_<br>m_g_<br>m_g_|
1 Cross axis sensitivity is defined as coupling between any two axes.
2 Refer to Figure 29 for current consumption at other bandwidth settings.
3 −40°C to +25°C or +25°C to +85°C.
> 4 Self test change is defined as the output change in _g_ when self test is asserted.
## **TEMPERATURE SENSOR SPECIFICATIONS**
**Table 3.**
|**Table 3.**||||
|---|---|---|---|
|**Parameter**|**Test Conditions/Comments**|**Min**<br>**Typ**<br>**Max**|**Unit**|
|BIAS<br>Average<br>Standard Deviation|At 25°C|350<br>290|LSB<br>LSB|
|SCALE FACTOR<br>Average<br>Standard Deviation<br>Repeatability||0.065<br>0.0025<br>±0.5|°C/LSB<br>°C/LSB<br>°C|
|OUTPUT RESOLUTION||12|Bits|
Rev. A | Page 5 of 45
**ADXL363**
**Data Sheet**
## **12-BIT ADC SPECIFICATIONS**
**Table 4.**
|**Table 4.**||||
|---|---|---|---|
|**Parameter**|**Test Conditions/Comments**|**Min**<br>**Typ**<br>**Max**|**Unit**|
|ANALOG-TO-DIGITAL CONVERTER<br>Input Voltage Range<br>Integral Nonlinearity (INL)<br>Differential Nonlinearity (DNL)<br>Offset Error<br>Gain Error<br>Throughput (ODR)|VS= 1.6 V<br>VS= 2.0 V<br>VS= 3.5 V<br>VS= 1.6 V<br>VS= 2.0 V<br>VS= 3.5 V<br>VS= 1.6 V<br>VS= 2.0 V<br>VS= 3.5 V<br>VS= 1.6 V<br>VS= 2.0 V<br>VS= 3.5 V<br>User selectable in eight steps|0.1 × VS<br>0.9 × VS<br>±1.0<br>±0.8<br>±1.1<br>±1.8<br>±1.6<br>±2.1<br>1.6<br>3.4<br>9.1<br>−4.3<br>−5.3<br>−11.8<br>ODR|LSB<br>LSB<br>LSB<br>LSB<br>LSB<br>LSB<br>LSB<br>LSB<br>LSB<br>LSB<br>LSB<br>LSB|
Rev. A | Page 6 of 45
**ADXL363**
**Data Sheet**
## **ABSOLUTE MAXIMUM RATINGS**
## **Table 5.**
## **RECOMMENDED SOLDERING PROFILE**
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||||||||
|---|---|---|---|---|---|---|
|Parameter|Rating|Figure 2 and Table 7 provide details about the recommended|
|Acceleration (Any Axis, Unpowered)|5000|g|soldering profile.|
|Acceleration (Any Axis, Powered)|5000|g|CRITICAL|ZONE|
|VS|−0.3 V to +3.6 V|TP|tP|TL TO|TP|
|VDD I/O|−0.3 V to +3.6 V|RAMP-UP|
|All Other Pins Output Short-Circuit Duration|−0.3 V to VIndefinite|S|TL|TSMAX|tL|
|(Any Pin to Ground)|TSMIN|
|ESD, Human Body Model (HBM)|2000 V|
|Short Term Maximum Temperature|PREHEATtS|RAMP-DOWN|
|Four Hours|150°C|
|One Minute|260°C|
|t25°C TO|PEAK|
|Temperature Range (Powered)|−50°C to +150°C|TIME|
|Temperature Range (Storage)|−50°C to +150°C|
|Figure 2. Recommended Soldering Profile|
|Stresses at or above those listed under Absolute Maximum|
|Table 7. Recommended Soldering Profile|
|Ratings may cause permanent damage to the product. This is a|
|Condition|
|stress rating only; functional operation of the product at these|
|Profile Feature|Sn63/Pb37|Pb-Free|
|or any other conditions above those indicated in the operational|
|Average Ramp Rate (TL to TP)|3°C/sec max|3°C/sec max|
|section of this specification is not implied. Operation beyond|
|Preheat|
|the maximum operating conditions for extended periods may|
|Minimum Temperature (TSMIN)|100°C|150°C|
|affect product reliability.|
|Maximum Temperature (TSMAX)|150°C|200°C|
|THERMAL RESISTANCE|Time (TSMIN to TSMAX)(tS)|60 sec to 120 sec|60 sec to 180 sec|
|TSMAX to TL Ramp-Up Rate|3°C/sec max|3°C/sec max|
|Thermal performance is directly linked to printed circuit board|Time Maintained Above|
|(PCB) design and operating environment. Careful attention to|Liquidous (TL)|
|PCB thermal design is required.|Liquidous Temperature (TL)|183°C|217°C|
|Time (tL)|60 sec to 150 sec|60 sec to 150 sec|
|Table 6. Package Characteristics|
|Peak Temperature (TP)|240 + 0/−5°C|260 + 0/−5°C|
|Package Type|θJA|θJC|Device Weight|Time Within 5°C of Actual|10 sec to 30 sec|20 sec to 40 sec|
|16-Terminal LGA|150°C/W|85°C/W|18 mg|Peak Temperature (tP)|
|Ramp-Down Rate|6°C/sec max|6°C/sec max|
|Time (t25°C) to Peak|6 minutes max|8 minutes max|
|Temperature|
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## **ESD CAUTION**
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Rev. A | Page 7 of 45
**ADXL363**
**Data Sheet**
## **PIN CONFIGURATION AND FUNCTION DESCRIPTIONS**
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16 15 14<br>VDD I/O 1 13 GND<br>NC 2 12 GND<br>RESERVED 3 ADXL363TOP VIEW 11 INT1<br>(Not to Scale)<br>SCLK 4 10 RESERVED<br>ADC_IN 5 9 INT2<br>6 7 8<br>GND NC VS<br>MOSI MISO CS<br>**----- End of picture text -----**<br>
**NOTES 1. NC = NO CONNECT. THIS PIN IS NOT INTERNALLY CONNECTED.**
_Figure 3. Pin Configuration (Top View)_
**Table 8. Pin Function Descriptions**
|**Pin No.**|**Mnemonic**|**Description**|
|---|---|---|
|1<br>2<br>3<br>4<br>5<br>6<br>7<br>8<br>9<br>10<br>11<br>12<br>13<br>14<br>15<br>16|VDD I/O<br>NC<br>RESERVED<br>SCLK<br>ADC_IN<br>MOSI<br>MISO<br>CS<br>INT2<br>RESERVED<br>INT1<br>GND<br>GND<br>VS<br>NC<br>GND|Supply Voltage for Digital I/O.<br>No Connect. This pin is not internally connected.<br>Reserved. Leave this pin unconnected, or connect it to GND.<br>SPI Communications Clock.<br>Input to Auxiliary ADC.<br>Master Output, Slave Input. SPI serial data input.<br>Master Input, Slave Output. SPI serial data output.<br>SPI Chip Select, Active Low. Must be low during SPI communications.<br>Interrupt 2 Output. INT2 also serves as an input for synchronized sampling.<br>Reserved. Leave this pin unconnected, or connect it to GND.<br>Interrupt 1 Output. INT1 also serves as an input for external clocking.<br>Ground. Ground this pin.<br>Ground. Ground this pin.<br>Supply Voltage.<br>No Connect. This pin is not internally connected.<br>Ground. Ground thispin.|
Rev. A | Page 8 of 45
**ADXL363**
**Data Sheet**
## **TYPICAL PERFORMANCE CHARACTERISTICS**
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25<br>20<br>15<br>10<br>5<br>0<br>–80–70–60–50–40–30–20–10 0 10 20 30 40 50 60 70 80<br>ZERO g OFFSET (m g )<br>PERCENT OF POPULATION (%)<br>11719-004<br>**----- End of picture text -----**<br>
_Figure 4. Accelerometer X-Axis Zero_ g _Offset at 25°C, VS = 2 V_
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**----- Start of picture text -----**<br>
30<br>25<br>20<br>15<br>10<br>5<br>0<br>–80–70–60–50–40–30–20–10 0 10 20 30 40 50 60 70 80<br>ZERO g OFFSET (m g )<br>Figure 5. Accelerometer Y-Axis Zero g Offset at 25°C, VS = 2 V<br>20<br>18<br>16<br>14<br>12<br>10<br>8<br>6<br>4<br>2<br>0<br>–170 –140 –110 –80 –50 –20 10 40 70 100<br>ZERO g OFFSET (m g )<br>PERCENT OF POPULATION (%)<br>11719-005<br>PERCENT OF POPULATION (%)<br>11719-006<br>**----- End of picture text -----**<br>
_Figure 6. Accelerometer Z-Axis Zero_ g _Offset at 25°C, VS = 2 V_
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40<br>35<br>30<br>25<br>20<br>15<br>10<br>5<br>0<br>930 950 970 990 1010 1030 1050 1070 1090 1110 1130<br>SENSITIVITY (m g /LSB)<br>PERCENTAGE OF POPULATION (%)<br>11719-007<br>**----- End of picture text -----**<br>
_Figure 7. Accelerometer X-Axis Scale Factor at 25°C, VS = 2 V, ±2_ g _Range_
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**----- Start of picture text -----**<br>
50<br>45<br>40<br>35<br>30<br>25<br>20<br>15<br>10<br>5<br>0<br>930 950 970 990 1010 1030 1050 1070 1090 1110 1130<br>SENSITIVITY (m g /LSB)<br>PERCENTAGE OF POPULATION (%)<br>11719-008<br>**----- End of picture text -----**<br>
_Figure 8. Accelerometer Y-Axis Scale Factor at 25°C, VS = 2 V, ±2_ g _Range_
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**----- Start of picture text -----**<br>
60<br>55<br>50<br>45<br>40<br>35<br>30<br>25<br>20<br>15<br>10<br>5<br>0<br>930 950 970 990 1010 1030 1050 1070 1090 1110 1130<br>SENSITIVITY (m g /LSB)<br>PERCENTAGE OF POPULATION (%)<br>11719-009<br>**----- End of picture text -----**<br>
_Figure 9. Accelerometer Z-Axis Scale Factor at 25°C, VS = 2 V, ±2_ g _Range_
Rev. A | Page 9 of 45
**ADXL363**
**Data Sheet**
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25<br>20<br>15<br>10<br>5<br>0<br>–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0<br>ZERO g OFFSET TEMPERATURE COEFFICIENT (m g /°C)<br>PERCENT OF POPULATION (%)<br>11719-010<br>**----- End of picture text -----**<br>
_Figure 10. Accelerometer X-Axis Zero_ g _Offset Temperature Coefficient,_
_VS = 2 V_
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**----- Start of picture text -----**<br>
35<br>30<br>25<br>20<br>15<br>10<br>5<br>0<br>–1.0 –0.8 –0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0<br>ZERO g OFFSET TEMPERATURE COEFFICIENT (m g /°C)<br>PERCENT OF POPULATION (%)<br>11719-011<br>**----- End of picture text -----**<br>
_Figure 11. Accelerometer Y-Axis Zero_ g _Offset Temperature Coefficient,_
_VS = 2 V_
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**----- Start of picture text -----**<br>
25<br>20<br>15<br>10<br>5<br>0<br>–0.5 –0.3 –0.1 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9<br>ZERO g OFFSET TEMPERATURE COEFFICIENT (m g /°C)<br>PERCENT OF POPULATION (%)<br>11719-012<br>**----- End of picture text -----**<br>
_Figure 12. Accelerometer Z-Axis Zero_ g _Offset Temperature Coefficient,_
_VS = 2 V_
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50<br>40<br>30<br>20<br>10<br>0<br>–10<br>–20<br>–30<br>–40<br>–50<br>–60<br>–60 –40 –20 0 20 40 60 80 100<br>TEMPERATURE (°C)<br>) g<br>OUTPUT (m<br>11719-013<br>**----- End of picture text -----**<br>
_Figure 13. Accelerometer X-Axis Zero_ g _Offset vs. Temperature— 16 Parts Soldered to PCB, ODR = 100 Hz, VS = 2 V_
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40<br>20<br>0<br>–20<br>–40<br>–60<br>–80<br>–100<br>–60 –40 –20 0 20 40 60 80 100<br>TEMPERATURE (°C)<br>) g<br>OUTPUT (m<br>11719-014<br>**----- End of picture text -----**<br>
_Figure 14. Accelerometer Y-Axis Zero_ g _Offset vs. Temperature— 16 Parts Soldered to PCB, ODR = 100 Hz, VS = 2 V_
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150<br>100<br>50<br>0<br>–50<br>–100<br>–60 –40 –20 0 20 40 60 80 100<br>TEMPERATURE (°C)<br>) g<br>OUTPUT (m<br>11719-015<br>**----- End of picture text -----**<br>
_Figure 15. Accelerometer Z-Axis Zero_ g _Offset vs. Temperature— 16 Parts Soldered to PCB, ODR = 100 Hz, VS = 2 V_
Rev. A | Page 10 of 45
**ADXL363**
**Data Sheet**
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10<br>8<br>6<br>4<br>2<br>0<br>–2<br>–4<br>–6<br>–8<br>–10<br>–60 –40 –20 0 20 40 60 80 100<br>TEMPERATURE (°C)<br>Figure 16. Accelerometer X-Axis Scale Factor Deviation from 25°C vs.<br>Temperature—16 Parts Soldered to PCB, ODR = 100 Hz, VS = 2 V<br>10<br>8<br>6<br>4<br>2<br>0<br>–2<br>–4<br>–6<br>–8<br>–10<br>–60 –40 –20 0 20 40 60 80 100<br>TEMPERATURE (°C)<br>Figure 17. Accelerometer Y-Axis Scale Factor Deviation from 25°C vs.<br>Temperature—16 Parts Soldered to PCB, ODR = 100 Hz, VS = 2 V<br>10<br>8<br>6<br>4<br>2<br>0<br>–2<br>–4<br>–6<br>–8<br>–10<br>–60 –40 –20 0 20 40 60 80 100<br>TEMPERATURE (°C)<br>SENSITIVITY DEVIATION FROM 25°C (%)<br>11719-016<br>SENSITIVITY DEVIATION FROM 25°C (%)<br>11719-017<br>SENSITIVITY DEVIATION FROM 25°C (%)<br>11719-018<br>**----- End of picture text -----**<br>
_Figure 18. Accelerometer Z-Axis Scale Factor Deviation from 25°C vs. Temperature—16 Parts Soldered to PCB, ODR = 100 Hz, VS = 2 V_
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40<br>35<br>30<br>25<br>20<br>15<br>10<br>5<br>0<br>450 475 500 525 550 575 600 625 650 675 700<br>SELF TEST DELTA (m g )<br>PERCENT OF POPULATION (%)<br>11719-019<br>**----- End of picture text -----**<br>
_Figure 19. Accelerometer X-Axis Self Test Response at 25°C, VS = 2 V_
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40<br>35<br>30<br>25<br>20<br>15<br>10<br>5<br>0<br>–700 –675 –650 –625 –600 –575 –550 –525 –500 –475 –450<br>SELF TEST DELTA (m g )<br>Figure 20. Accelerometer Y-Axis Self Test Response at 25°C, VS = 2 V<br>40<br>35<br>30<br>25<br>20<br>15<br>10<br>5<br>0<br>350 375 400 425 450 475 500 525 550 575 600 625 650<br>SELF TEST DELTA (m g )<br>PERCENT OF POPULATION (%)<br>11719-020<br>PERCENT OF POPULATION (%)<br>11719-021<br>**----- End of picture text -----**<br>
_Figure 21. Accelerometer Z-Axis Self Test Response at 25°C, VS = 2 V_
Rev. A | Page 11 of 45
**ADXL363**
**Data Sheet**
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35<br>30<br>25<br>20<br>15<br>10<br>5<br>0<br>1.50 1.55 1.60 1.65 1.70 1.75 1.80 1.85 1.90 1.95 2.00 2.05<br>CURRENT CONSUMPTION (µA)<br>PERCENT OF POPULATION (%)<br>11719-022<br>**----- End of picture text -----**<br>
_Figure 22. Current Consumption at 25°C, Normal Mode, ADC Disabled, ODR = 100 Hz, VS = 2 V_
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30<br>25<br>20<br>15<br>10<br>5<br>0<br>2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8<br>CURRENT CONSUMPTION (µA)<br>Figure 23. Current Consumption at 25°C, Low Noise Mode, ADC Disabled,<br>ODR = 100 Hz, VS = 2 V<br>PERCENT OF POPULATION (%)<br>11719-023<br>**----- End of picture text -----**<br>
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35<br>30<br>25<br>20<br>15<br>10<br>5<br>0<br>8 9 10 11 12 13 14 15 16<br>CURRENT CONSUMPTION (µA)<br>PERCENT OF POPULATION (%)<br>11719-024<br>**----- End of picture text -----**<br>
_Figure 24. Current Consumption at 25°C, Ultralow Noise Mode, ADC Disabled, ODR = 100 Hz, VS = 2 V_
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70<br>60<br>50<br>40<br>30<br>20<br>10<br>0<br>50 100 150 200 250 300 350 400<br>CURRENT CONSUMPTION (nA)<br>PERCENT OF POPULATION (%)<br>11719-025<br>**----- End of picture text -----**<br>
_Figure 25. Current Consumption at 25°C, Wake-Up Mode, ADC Disabled, VS = 2 V_
Rev. A | Page 12 of 45
**ADXL363**
**Data Sheet**
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12<br>10<br>8<br>6<br>4<br>2<br>0<br>–200 0 200 400 600 800 1000<br>TEMPERATURE SENSOR BIAS AT 25°C (LSB)<br>Figure 26. Temperature Sensor Response at 25°C, VS = 2 V<br>40<br>35<br>30<br>25<br>20<br>15<br>10<br>5<br>0<br>14.4 14.6 14.8 15.0 15.2 15.4 15.6 15.8 16.0 16.2 16.4 16.6 16.8<br>TEMPERATURE SENSOR SCALE FACTOR (LSB/°C)<br>PERCENT OF POPULATION (%)<br>11719-026<br>PERCENT OF POPULATION (%)<br>11719-027<br>**----- End of picture text -----**<br>
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30<br>25<br>20<br>15<br>10<br>5<br>0<br>–20 –16 –12 –8 –4 0 4 8 12 16 20<br>CLOCK FREQUENCY DEVIATION FROM IDEAL (%)<br>PERCENT OF POPULATION (%)<br>11719-028<br>**----- End of picture text -----**<br>
_Figure 28. Clock Frequency Deviation from Ideal at 25°C, VS = 2 V_
_Figure 27. Temperature Sensor Scale Factor, VS = 2 V_
Rev. A | Page 13 of 45
**Data Sheet**
## **ADXL363**
## **THEORY OF OPERATION**
The ADXL363 is a complete sensor suite consisting of an accelerometer, an ADC for synchronous conversion of input from a third sensor, and a temperature sensor. The entire system operates at extremely low power consumption levels.
## **ACCELEROMETER**
The ADXL363 measures both dynamic acceleration, resulting from motion or shock, and static acceleration, such as tilt. Acceleration is reported digitally and the device communicates via the SPI protocol. Built-in digital logic enables autonomous operation and implements functionality that enhances system level power savings.
## _**Mechanical Device Operation**_
The moving component of the sensor is a polysilicon surfacemicromachined structure that is built on top of a silicon wafer. Polysilicon springs suspend the structure over the surface of the wafer and provide a resistance against acceleration forces.
Deflection of the structure is measured using differential capacitors that consist of independent fixed plates and plates attached to the moving mass. Acceleration deflects the structure and unbalances the differential capacitor, resulting in a sensor output whose amplitude is proportional to acceleration. Phase sensitive demodulation determines the magnitude and polarity of the acceleration.
## _**Operating Modes**_
The ADXL363 has two operating modes: measurement mode for continuous, wide bandwidth sensing; and wake-up mode for limited bandwidth activity detection. In addition, measurement is suspended altogether by placing the device in standby.
## **Measurement Mode**
Measurement mode is the normal operating mode of the ADXL363. In this mode, acceleration data is read continuously and the accelerometer consumes less than 3.5 µA across its entire range of output data rates of up to 400 Hz using a 2.0 V supply (see Figure 29). All features described in this data sheet are available when operating the ADXL363 in this mode.
The ability to continuously output data from the minimum 12.5 Hz to the maximum 400 Hz data rate while still delivering less than 3.5 µA of current consumption is what defines the ADXL363 as an ultralow power accelerometer. Other accelerometers derive low current by using a specific low power mode that power cycles acceleration sensing. The result is a small effective bandwidth in the low power modes and undersampling of input data; therefore, unwanted aliasing can occur. Undersampling and aliasing do not occur with the ADXL363 because it continuously samples the full bandwidth of its sensor at all data rates.
## **Wake-Up Mode**
Wake-up mode is ideal for simple detection of the presence or absence of motion at extremely low power consumption (270 nA at a 2.0 V supply voltage). Wake-up mode is useful particularly for implementation of a motion activated on/off switch, allowing the rest of the system to power down until activity is detected.
Wake-up mode reduces current consumption to a very low level by measuring acceleration only about six times per second to determine whether motion is present. If motion is detected, the accelerometer can respond autonomously in the following ways:
- Switch into full bandwidth measurement mode
- Signal an interrupt to a microcontroller
- Wake up downstream circuitry, depending on the configuration
In wake-up mode, all accelerometer features are available with the exception of the activity timer. All registers can be accessed, and real-time data can be read and/or stored in the FIFO.
## **Standby**
Placing the ADXL363 in standby suspends measurement and reduces the current consumption to 10 nA (typical). Pending interrupts and data are preserved, and no new interrupts are generated.
The ADXL363 powers up in standby with all sensor functions turned off.
## _**Selectable Measurement Ranges**_
The ADXL363 has selectable measurement ranges of ±2 _g_ , ±4 _g_ , and ±8 _g_ . Acceleration samples are always converted by a 12-bit ADC; therefore, the scale factor scales with _g_ range. Ranges and corresponding scale factor values are listed in Table 2.
When acceleration exceeds the measurement extremes, data is clipped at the full-scale value (0x0FFF), and no damage is caused to the accelerometer. Table 5 lists the absolute maximum ratings for acceleration, indicating the acceleration level that can cause permanent damage to the device.
## _**Selectable Output Data Rates**_
The ADXL363 can report acceleration data at various data rates ranging from 12.5 Hz to 400 Hz. The internal low-pass filter pole is automatically set to ¼ or ½ the selected ODR (based on the HALF_BW setting) to ensure that the Nyquist sampling criterion is met and no aliasing occurs.
Current consumption varies somewhat with output data rate as shown in Figure 29, remaining below approximately 5.0 µA over the entire range of data rates and operating voltages.
Rev. A | Page 14 of 45
**ADXL363**
## **Data Sheet**
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6<br>VS = 1.6V<br>VS = 2.0V<br>VS = 2.5V<br>5 VS = 3.0V<br>VS = 3.5V<br>4<br>3<br>2<br>1<br>0<br>0 100 200 300 400<br>OUTPUT DATA RATE (Hz)<br>CURRENT CONSUMPTION (µA)<br>11719-029<br>**----- End of picture text -----**<br>
_Figure 29. Current Consumption vs. Output Data Rate at Several Supply Voltages, ADC_EN = 0_
## **Antialiasing**
The analog-to-digital converter (ADC) of the ADXL363 samples at the user selected output data rate. In the absence of antialiasing filtering, it aliases any input signals whose frequency is more than half the data rate. To mitigate this, a two-pole lowpass filter is provided at the input of the ADC.
The user can set this antialiasing filter to a bandwidth that is at ½ the output data rate or ¼ the output data rate. Setting the antialiasing filter pole to ½ of the output data rate provides less aggressive antialiasing filtering, but maximizes bandwidth and is adequate for most applications. Setting the pole to ¼ of the data rate reduces bandwidth for a given data rate, but provides more aggressive antialiasing.
The antialiasing filter of the ADXL363 defaults to the more conservative setting, where bandwidth is set to ¼ the output data rate.
## _**Power/Noise Tradeoff**_
The ADXL363 offers a few options for decreasing noise at the expense of only a small increase in current consumption.
The noise performance of the ADXL363 in normal operation, typically 7 LSB rms at 100 Hz bandwidth, is adequate for most applications, depending on bandwidth and the desired resolution. For cases where lower noise is needed, the ADXL363 provides two lower noise operating modes that trade reduced noise for a somewhat higher current consumption.
Table 9 lists the noise densities and current consumption obtained for normal operation and the two lower noise modes at a typical 2.0 V supply.
**Table 9. Noise and Current Consumption: Normal Operation, Low Noise Mode, and Ultralow Noise Mode at VS = 2.0 V, ODR = 100 Hz**
|**Low Noise Mode, a**<br>**ODR = 100 Hz**|**nd Ultralow Noise**|**Mode at VS = 2.0 V,**|
|---|---|---|
|**Mode**|**Noise (µ****_g_/√Hz)**<br>**Typical**|**Current Consumption**<br>**(µA) Typical**|
|Normal Operation<br>Low Noise<br>Ultralow Noise|550<br>400<br>250|1.8<br>3.3<br>13|
Operating the ADXL363 at a higher supply voltage also decreases noise. Table 10 lists the noise densities and current consumption obtained for normal operation and the two lower noise modes at the highest recommended supply, 3.3 V.
**Table 10. Noise and Current Consumption: Normal Operation, Low Noise Mode, and Ultralow Noise Mode at VS = 3.3 V, ODR = 100 Hz**
|**Mode**|**Noise (µ****_g_/√Hz)**<br>**Typical**|**Current Consumption**<br>**(µA) Typical**|
|---|---|---|
|Normal Operation<br>Low Noise<br>Ultralow Noise|380<br>280<br>175|2.7<br>4.5<br>15|
## _**Free Fall Detection**_
Many digital output accelerometers include a built-in free fall detection feature. In the ADXL363, this function can be implemented using the inactivity interrupt. Refer to the Applications Information section for more details, including suggested threshold and timing values.
## **ADC**
In addition to a built-in accelerometer and temperature sensor, the ADXL363 incorporates a 12-bit analog-to-digital converter (ADC) for digitization of an external analog input. The ADC is best suited for use with a sensor input due to its synchronization with the accelerometer and temperature sensor.
Use of the ADC adds approximately 150 nA to the total current consumption when operating at 100 Hz ODR. The ADXL363 enables the user to power down the ADC to save power when it is not needed.
## _**Analog Inputs**_
The ADXL363 ADC can convert analog inputs ranging from 10% to 90% of the supply voltage. For example, when VS = 2 V, the acceptable voltage range of the analog input is 0.2 V to 1.8 V.
Figure 30 shows an equivalent circuit of the input structure of the ADXL363.
The two diodes, D1 and D2, provide ESD protection for the analog input, ADC_IN. Take care to ensure that the analog input signal never exceeds the supply rails by more than 0.3 V because this causes these diodes to begin to forward bias and start conducting current.
During the acquisition phase, the impedance of the analog input (ADC_IN) can be modeled by the series connection of RIN and CIN. RIN is typically 1 kΩ and is a lumped component made up of some serial resistors and the on resistance of the switches. CIN is typically 23 pF and is mainly the ADC sampling capacitor.
The acquisition time required is calculated using the following formula:
_tACQ_ = 8.5 × (( _RSOURCE_ + _RIN_ ) _CIN_ )
where _RSOURCE_ is the source impedance.
Rev. A | Page 15 of 45
**ADXL363**
**Data Sheet**
For 12-bit settling, tACQ must be less than 75 µs. The acquisition time, tACQ, sets an upper limit on the source impedance, RSOURCE, of approximately 380 kΩ.
During the conversion phase, the switches are opened and the input impedance is limited to the pin capacitance, typically 1 pF to 2 pF. RIN and CIN make a one-pole, low-pass filter that reduces undesirable aliasing effects and limits the noise.
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VS<br>D1 RIN CIN<br>ADC_IN<br>D2<br>GND 11719-033<br>**----- End of picture text -----**<br>
_Figure 30. Equivalent Analog Input Circuit_
## _**Digital Output**_
The 12-bit digitized signal is in twos complement format and is stored in output registers, accessible via the SPI interface. ADC samples are always captured and updated concurrently with accelerometer and temperature samples. The maximum throughput of the ADC is 400 samples per second when using the internal timer, although a slightly faster throughput can be achieved when supplying the ADXL363 with an external trigger.
## **TEMPERATURE SENSOR**
The ADXL363 includes an integrated 12-bit temperature sensor, which the system designer can use to monitor internal system temperature or to improve the temperature stability of the device via calibration. For example, acceleration outputs vary with temperature at a rate of ±0.5 m _g_ /°C (typical), but the relationship of the outputs to temperature is repeatable and the designer can use the temperature sensor output to calibrate the acceleration temperature drift.
To use the temperature sensor to monitor absolute temperature, measure and calibrate its initial bias (its output at some known temperature).
To use the temperature sensor for calibration of the acceleration signal, it is sufficient to correlate acceleration to temperature sensor output, rather than to absolute temperature. In this case it is not necessary to convert the temperature reading to an absolute temperature; therefore, calibration of initial bias is not required.
The designer can configure the device to save data from the temperature sensor in the FIFO. Temperature samples, whether read from the output registers or from the FIFO, always update concurrently with acceleration (and ADC) samples.
The ADC data is provided in output registers only and is not saved in the FIFO.
Rev. A | Page 16 of 45
**ADXL363**
**Data Sheet**
## **POWER SAVINGS FEATURES**
Designed for the most power conscious applications, the ADXL363 includes several features (as described in this section) for enabling power savings at the system level, as well as at the device level.
## **ULTRALOW POWER CONSUMPTION IN ALL MODES, OPERATING ALL SENSORS**
At the device level, the most obvious power saving feature of the ADXL363 is its ultralow current consumption in all configurations. The ADXL363 consumes between 1.1 µA (typical) and 5 µA (typical) across all data rates up to 400 Hz and all supply voltages up to 3.5 V (see Figure 29). An even lower power, 270 nA (typical) motion triggered wake-up mode is provided for simple motion detection applications that require a power consumption lower than 1 µA.
At these current levels, the ADXL363 consumes less power in full operation than the standby currents of many other system components, and is, therefore, optimal for applications that require continuous acceleration monitoring and very long battery life. Because the accelerometer is always on, it can act as a motionactivated switch. The accelerometer signals to the rest of the system when to turn on, thereby managing power at the system level.
As important as its low operating current, the 10 nA (typical) standby current of the ADXL363 contributes to a much longer battery life in applications that spend most of their time in a sleep state and wake up via an external trigger.
## **MOTION DETECTION**
The ADXL363 features built-in logic that detects activity (presence of acceleration above a threshold) and inactivity (lack of acceleration above a threshold). Activity and inactivity events can be used as triggers to manage the accelerometer mode of operation, trigger an interrupt to a host processor, and/or autonomously drive a motion switch.
Detection of an activity or inactivity event is indicated in the status register and can be configured to generate an interrupt. In addition, the activity status of the device, that is, whether it is moving or stationary, is indicated by the awake bit, described in the Using the Awake Bit section.
Activity and inactivity detection can be used when the accelerometer is in either measurement mode or wake-up mode.
## _**Activity Detection**_
An activity event is detected when acceleration remains above a specified threshold for a specified time period.
## **Referenced and Absolute Configurations**
Activity detection can be configured as referenced or absolute.
When using absolute activity detection, acceleration samples are compared to a user set threshold to determine whether motion is present. For example, if a threshold of 0.5 _g_ is set and the acceleration on the z-axis is 1 _g_ for longer than the user defined activity time, the activity status asserts.
In many applications, it is advantageous for activity detection to be based not on an absolute threshold, but on a deviation from a reference point or orientation. This is particularly useful because it removes the effect on activity detection of the static 1 _g_ imposed by gravity. When an accelerometer is stationary, its output can reach 1 _g_ , even when it is not moving. In absolute activity, when the threshold is set to less than 1 _g_ , activity is immediately detected in this case.
In the referenced configuration, activity is detected when acceleration samples are at least a user set amount above an internally defined reference for the user defined amount of time, as described in Equation 1.
_|Acceleration_ – _Reference_ | > _Threshold_ (1)
Consequently, activity is detected only when the acceleration has deviated sufficiently from the initial orientation. The reference for activity detection is calculated when activity detection is engaged in one of the following scenarios:
- When the activity function is turned on and measurement mode is engaged
- If link mode is enabled: when inactivity is detected and activity detection begins
- If link mode is not enabled: when activity is detected and activity detection repeats
The referenced configuration results in a very sensitive activity detection that detects even the most subtle motion events.
## **Fewer False Positives**
Ideally, the intent of activity detection is to wake up a system only when motion is intentional, ignoring noise or small, unintentional movements. In addition to being sensitive to subtle motion events, the ADXL363 activity detection algorithm is robust in filtering out undesired triggers.
The ADXL363 activity detection functionality includes a timer to filter out unwanted motion and ensure that only sustained motion is recognized as activity. The duration of this timer, as well as the acceleration threshold, are user adjustable from one sample (that is, no timer) to up to 20 seconds of motion.
Note that the activity timer is operational in measurement mode only. In wake-up mode, one-sample activity detection is used.
## _**Inactivity Detection**_
An inactivity event is detected when acceleration remains below a specified threshold for a specified time. Inactivity detection is also configurable as referenced or absolute.
When using absolute inactivity detection, acceleration samples are compared to a user set threshold for the user set time to determine the absence of motion. Inactivity is detected when a large enough number of consecutive samples are below the threshold. Use the absolute configuration of inactivity for implementing free fall detection.
Rev. A | Page 17 of 45
**Data Sheet**
## **ADXL363**
When using referenced inactivity detection, inactivity is detected when acceleration samples are within a user specified amount of an internally defined reference (as described by Equation 2) for a user defined amount of time.
_|Acceleration_ – _Reference|_ < _Threshold_
(2)
The reference for inactivity detection is updated every time a sample is detected that violates the inactivity condition; that is,
## ( _Sample_ – _Reference_ ) ≥ _Threshold_ .
Referenced inactivity, like referenced activity, is particularly useful for eliminating the effects of the static acceleration due to gravity. With absolute inactivity, if the inactivity threshold is set lower than 1 _g_ , a device resting motionless may never detect inactivity. With referenced inactivity, the same device under the same configuration detects inactivity.
The inactivity timer can be set to anywhere from 2.5 ms (a single sample at 400 Hz ODR) to almost 90 minutes (65,535 samples at 12.5 Hz ODR) of inactivity. A requirement for inactivity detection is that, for whatever period of time the inactivity timer has been configured, the accelerometer detects inactivity only when it has been stationary for that amount of time.
For example, if the accelerometer is configured for 90 minutes, the accelerometer detects inactivity when it is stationary for 90 minutes. The wide range of timer settings means that in applications where power conservation is critical, the system can be put to sleep after very short periods of inactivity. In applications where continuous operation is critical, the system stays on for as long as any motion is present.
## _**Linking Activity and Inactivity Detection**_
The activity and inactivity detection functions can be used independently and processed manually by a host processor, or they can be configured to interact in linked mode, loop mode, and autosleep.
## **Default Mode**
The user must enable the activity and inactivity functions because these functions are not automatically enabled by default. After the user enables the activity and inactivity functions, the ADXL363 exhibits the following behavior when it enters default mode:
Similarly, when inactivity is detected, the device is assumed stationary (or asleep). Thus, activity is expected as the next event; therefore, only activity detection operates.
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WAIT FOR WAIT FOR<br>ACTIVITY PROCESSOR TO<br>EVENT CLEAR INTERRUPT<br>AWAKE = 1<br>INACTIVITY<br>INTERRUPT<br>TRIGGERS<br>ACTIVITY<br>INTERRUPT<br>TRIGGERS<br>AWAKE = 1<br>WAIT FOR WAIT FOR<br>PROCESSOR TO INACTIVITY<br>CLEAR INTERRUPT EVENT<br>**----- End of picture text -----**<br>
**NOTES 1. THE AWAKE BIT DEFAULTS TO 1 WHEN ACTIVITY AND INACTIVITY ARE NOT LINKED.**
_Figure 31. Flowchart Illustrating Activity and Inactivity Operation in Default Mode_
In linked mode, each interrupt must be serviced by a host processor before the next interrupt is enabled.
Linked mode operation is illustrated in the flowchart in Figure 32.
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WAIT FOR WAIT FOR AWAKE = 0 INACTIVITY<br>ACTIVITY PROCESSOR TO<br>INTERRUPT<br>EVENT CLEAR INTERRUP<br>AWAKE = 1 WAIT FOR WAIT FOR<br>ACTIVITY<br>PROCESSOR TO INACTIVITY<br>INTERRUPT CLEAR INTERRUPT EVENT<br>11719-035<br>**----- End of picture text -----**<br>
_Figure 32. Flowchart Illustrating Activity and Inactivity Operation in Linked Mode_
## **Loop Mode**
In loop mode, motion detection operates as described in the Linked Mode section, but interrupts do not need servicing by a host processor. This configuration simplifies the implementation of commonly used motion detection and enhances power savings by reducing the amount of power used in bus communication.
Loop mode operation is illustrated in the flowchart in Figure 33.
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AWAKE = 1<br>**----- End of picture text -----**<br>
- Both activity and inactivity detection remain enabled
- All interrupts must be serviced by a host processor; that is, a processor must read each interrupt before it is cleared and can be used again.
Default mode operation is illustrated in the flowchart in Figure 31.
## **Linked Mode**
In linked mode, activity and inactivity detection are linked to each other such that only one of the functions is enabled at any given time. As soon as activity is detected, the device is assumed moving (or awake) and stops looking for activity; rather, inactivity is expected as the next event. Therefore, only inactivity detection operates.
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WAIT FOR WAIT FOR<br>ACTIVITY INACTIVITY<br>EVENT EVENT<br>AWAKE = 0 11719-036<br>**----- End of picture text -----**<br>
_Figure 33. Flowchart Illustrating Activity and Inactivity Operation in Loop Mode_
Rev. A | Page 18 of 45
**ADXL363**
**Data Sheet**
## **Autosleep**
When in linked or loop mode, enabling autosleep causes the device to enter wake-up mode autonomously (see the Wake-Up Mode section) when inactivity is detected, and to reenter measurement mode when activity is detected.
The autosleep configuration is active only if linked or loop modes are enabled. In the default mode, the autosleep setting is ignored.
## _**Using the Awake Bit**_
The awake bit is a status bit that indicates whether the ADXL363 is awake or asleep. The device is awake upon experiencing an activity condition, and it is asleep when upon experiencing an inactivity condition.
Used in conjunction with loop mode, the awake bit makes an autonomous motion activated switch easy to implement: simply map the bit to the INT1 or INT2 pin, and tie this pin to the gate of a switch (see Figure 43). When the ADXL363 detects activity, the awake bit becomes high, causing the switch to close and current to flow to downstream circuitry. When the ADXL363 detects inactivity, the awake bit deasserts and the switch opens, disconnecting downstream circuitry from power entirely.
If the system can tolerate the turn-on time of downstream circuitry, this motion switch configuration saves significant system level power by eliminating the standby current consumption of the remainder of the application. This standby current often exceeds the full operating current of the ADXL363.
## **FIFO**
The ADXL363 includes a deep 512-sample first in, first out (FIFO) buffer that stores acceleration and, if desired, temperature data. The FIFO provides two primary benefits: system level power savings and data recording/event context.
## _**System Level Power Savings**_
Appropriate use of the FIFO enables system level power savings by enabling the host processor to sleep for extended periods of time while the accelerometer autonomously collects data. Alternatively, using the FIFO to collect data unburdens the host while it tends to other tasks.
## _**Data Recording/Event Context**_
The FIFO can be used in trigger mode to record all data leading up to an activity detection event, thereby providing context for the event. In the case of a system that identifies impact events, for example, the accelerometer can keep the entire system off while it stores acceleration data in its FIFO and looks for an activity event. When the impact event occurs, data collected prior to the event is frozen in the FIFO. The accelerometer then wakes the rest of the system and transfers this data to the host processor, thereby providing context for the impact event.
Generally, more context enables more intelligent decisions, making a deep FIFO especially useful. The ADXL363 FIFO stores up to more than 13 seconds of data, providing a clear picture of events prior to an activity trigger.
All FIFO modes of operation, as well as the structure of the FIFO and instructions for retrieving data from it, are described in further detail in the FIFO Modes section.
## **COMMUNICATIONS**
## _**SPI Instructions**_
The digital interface of the ADXL363 is implemented with system level power savings in mind. The following features enhance power savings:
- Burst reads and writes reduce the number of SPI communication cycles required to configure the device and retrieve data.
- Concurrent operation of activity and inactivity detection enables set it and forget it operation. Loop mode further reduces communications power by enabling the clearing of interrupts without processor intervention.
- The FIFO is implemented such that consecutive samples can be read continuously via a multibyte read of unlimited length; thus, one FIFO read instruction can clear the entire contents of the FIFO. In many other accelerometers, each read instruction retrieves a single sample only. In addition, the ADXL363 FIFO construction allows the use of direct memory access (DMA) to read the FIFO contents.
## _**Bus Keepers**_
The ADXL363 includes bus keepers on all digital interface pins: MISO, MOSI, SCLK, CS, INT1, and INT2. Bus keepers prevent tristate bus lines from floating when nothing is driving them, thus preventing through current in any gate inputs that are on the bus.
## _**MSB Registers**_
Acceleration and temperature measurements are converted to 12-bit values and transmitted via the SPI using two registers per measurement. To read a full sample set of 3-axis acceleration data, six registers must be read.
Many applications do not require the accuracy that 12-bit data provides and prefer, instead, to save system level power. The MSB registers (XDATA, YDATA, and ZDATA) enable this trade-off. These registers contain the eight MSBs of the x-, y-, and z-axis acceleration data; reading them effectively provides 8-bit acceleration values. Only three (consecutive) registers must be read to retrieve a full data set, significantly reducing the time during which the SPI bus is active and drawing current.
12-bit and 8-bit data are available simultaneously so that both data formats can be used in a single application, depending on the needs of the application at a given time. For example, the processor reads 12-bit data when higher resolution is required and switches to 8-bit data (simply by reading a different set of registers) when application requirements change.
Rev. A | Page 19 of 45
**Data Sheet**
## **ADXL363**
## **ADDITIONAL FEATURES EXTERNAL CLOCK**
The ADXL363 has a built-in 51.2 kHz (typical) clock that, by default, serves as the time base for internal operations.
ODR and bandwidth scale proportionally with the clock. The ADXL363 provides a discrete number of options for ODR, such as 100 Hz, 50 Hz, 25 Hz, and so forth, in factors of 2 (see the Filter Control Register section for a complete listing). To achieve data rates other than those provided, an external clock can be used at the appropriate clock frequency. The output data rate scales with the clock frequency, as shown in Equation 3.
**==> picture [227 x 21] intentionally omitted <==**
For example, to achieve an 80 Hz ODR, select the 100 Hz ODR setting and provide a clock frequency that is 80% of nominal, or 41.0 kHz.
The ADXL363 can operate with external clock frequencies ranging from the nominal 51.2 kHz down to 25.6 kHz to allow the user to achieve any desired output data rate.
Alternatively, use an external clock where improved clock frequency accuracy is required. The distribution of clock frequencies among a sampling of >1000 parts has a standard deviation of approximately 3%. To achieve tighter tolerances, a more accurate clock can be provided externally.
Accelerometer bandwidth automatically scales to ½ or ¼ of the ODR (based on the HALF_BW setting), and this ratio is preserved, regardless of clock frequency. Power consumption also scales with clock frequency; higher clock rates increase power consumption. Figure 34 shows how power consumption varies with clock rate.
The ODR setting applies to the ADC and temperature sensor data rates but does not affect their bandwidth. Especially in the case of the ADC, the system designer must ensure that the bandwidth of the signal input into the ADC is appropriate for the selected ODR.
## **SYNCHRONIZED DATA SAMPLING**
For applications that require a precisely timed acceleration measurement, the ADXL363 features an option to synchronize acceleration sampling to an external trigger.
## **SELF TEST**
The ADXL363 incorporates a self test feature that effectively tests its mechanical and electronic systems simultaneously. When the self test function is invoked, an electrostatic force is applied to the mechanical sensor. This electrostatic force moves the mechanical sensing element in the same manner as acceleration, and it is additive to the acceleration experienced by the device. This added electrostatic force results in an output change on all three axes.
## **USER REGISTER PROTECTION**
The ADXL363 includes user register protection for single event upsets (SEUs). An SEU is a change of state caused by ions or electromagnetic radiation striking a sensitive node in a microelectronic device. The state change is a result of the free charge created by ionization in or near an important node of a logic element (for example, a memory bit). The SEU, itself, is not considered permanently damaging to transistor or circuit functionality, but it can create erroneous register values. The ADXL363 registers that are protected from SEUs are Register 0x20 to Register 0x2E.
SEU protection is implemented via a 99-bit error correcting (Hamming-type) code that detects both single-bit and doublebit errors. The check bits are recomputed any time a write to any of the protected registers occurs. At any time, if the stored version of the check bits is not in agreement with the current check bit calculation, the ERR_USER_REGS status bit is set.
The ERR_USER_REGS bit in the status register is set upon power-up prior to device configuration; it clears upon the first register write to that device.
**==> picture [219 x 167] intentionally omitted <==**
**----- Start of picture text -----**<br>
3.0<br>2.5<br>2.0<br>1.5<br>1.0<br>0.5<br>VS = 1.6V<br>VS = 2.0V<br>VS = 3.5V<br>0<br>43 44 45 46 47 48 49 50 51 52<br>EXTERNAL CLOCK FREQUENCY (kHz)<br>CURRENT CONSUMPTION (µA)<br>11719-037<br>**----- End of picture text -----**<br>
_Figure 34. Current Consumption vs. External Clock Frequency_
Rev. A | Page 20 of 45
**ADXL363**
**Data Sheet**
## **SERIAL COMMUNICATIONS**
The ADXL363 communicates via a 4-wire SPI and operates as a slave. Ignore data that is transmitted from the ADXL363 to the master device during writes to the ADXL363.
As shown in Figure 36 to Figure 40, the MISO pin is in a high impedance state, held by a bus keeper, except when the ADXL363 is sending read data (to conserve bus power).
Wire the ADXL363 for SPI communication as shown in the connection diagram in Figure 35. The recommended SPI clock speeds are 1 MHz to 8 MHz, with 12 pF maximum loading.
The SPI timing scheme follows CPHA = CPOL = 0.
Figure 36 to Figure 40 show the data sequences for SPI transactions. For correct operation of the part, the logic thresholds and timing parameters in Table 11 and Table 12 must be met at all times. Figure 36 to Figure 40 are divided into send (shaded) and receive portions. Refer to Figure 41 and Figure 42 for visual diagrams of the timing parameters for the receive and send portions, respectively.
**==> picture [151 x 80] intentionally omitted <==**
**----- Start of picture text -----**<br>
ADXL363 PROCESSOR<br>CS DOUT<br>MOSI DOUT<br>MISO DIN<br>SCLK DOUT<br>11719-038<br>**----- End of picture text -----**<br>
_Figure 35. 4-Wire SPI Connection Diagram_
## **SPI COMMANDS**
The SPI port uses a multibyte structure wherein the first byte is a command. The ADXL363 command set is
- 0x0A: write register
- 0x0B: read register
- 0x0D: read FIFO
## _**Read and Write Register Commands**_
The command structure for the read register and write register commands is as follows (see Figure 36 and Figure 37):
```
<[CS] down>
<command byte (0x0A or 0x0B)>
<address byte>
<data byte>
<additional data bytes for multi-byte>
```
```
…
```
```
<[CS] up>
```
## _**Read FIFO Command**_
Reading from the FIFO buffer is a command structure that does not have an address.
```
<[CS] down>
<command byte (0x0D)>
<data byte> <data byte>
```
```
…
```
```
<[CS] up>
```
It is recommended that an even number of bytes be read (using a multibyte transaction) because each sample consists of two bytes: two bits of axis information and 14 bits of data. If an odd number of bytes is read, it is assumed that the desired data was read; therefore, the second half of the last sample is discarded so that a read from the FIFO always starts on a properly aligned even-byte boundary. Data is presented least significant byte first, followed by the most significant byte.
## **MULTIBYTE TRANSFERS**
Multibyte transfers, also known as burst transfers, are supported for all SPI commands: register read, register write, and FIFO read commands. It is recommended that data be read using multibyte transfers to ensure that a concurrent and complete set of x-, y-, and z-acceleration (and temperature, where applicable) data is read.
The FIFO runs on the serial port clock during FIFO reads and sustains bursting at the SPI clock rate as long as the SPI clock is 1 MHz or faster.
## _**Register Read/Write Auto-Increment**_
A register read or write command begins with the address specified in the command and auto-increments for each additional byte in the transfer. To avoid address wrapping and side effects of reading registers multiple times, the autoincrement halts at the invalid Register Address 63 (0x3F).
## **INVALID ADDRESSES AND ADDRESS FOLDING**
The ADXL363 has a 6-bit address bus, mapping only 64 registers in the possible 256 register address space. The addresses do not fold to repeat the registers at addresses above 64. Attempted access to register addresses above 64 map to the invalid register at 63 (0x3F) and have no functional effect.
Address 0x00 to Address 0x2E are for customer access, as described in the Register Map section. Address 0x2F to Address 0x3F are reserved for factory use.
The read and write register commands support multibyte (burst) read/write access. The waveform diagrams for multibyte read and write commands are shown in Figure 38 and Figure 39.
Rev. A | Page 21 of 45
**Data Sheet**
## **ADXL363**
## **LATENCY RESTRICTIONS**
Reading any of the data registers (Register 0x08 to Register 0x0A or Register 0x0E to Register 0x15) clears the data ready interrupt. There can be as much as an 80 µs delay from reading a register to the clearing of the data ready interrupt.
## **INVALID COMMANDS**
Commands other than 0x0A, 0x0B, and 0x0D have no effect. The MISO output remains in a high impedance state, and the bus keeper holds the MISO line at its last value.
Other register reads, register writes, and FIFO reads have no latency restrictions.
**==> picture [508 x 510] intentionally omitted <==**
**----- Start of picture text -----**<br>
CS<br>0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23<br>SCLK<br>INSTRUCTION 8-BIT ADDRESS<br>MOSI 0 0 0 0 1 0 1 1 7 6 5 4 3 2 1 0<br>DATA OUT<br>MISO<br>7 6 5 4 3 2 1 0<br>Figure 36. Register Read<br>CS<br>0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23<br>SCLK<br>INSTRUCTION 8-BIT ADDRESS DATA BYTE<br>MOSI 0 0 0 0 1 0 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0<br>MISO HIGH IMPEDANCE<br>Figure 37. Register Write (Receive Instruction Only)<br>CS<br>0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23<br>SCLK<br>INSTRUCTION 8-BIT ADDRESS<br>MOSI 0 0 0 0 1 0 1 1 7 6 5 4 3 2 1 0<br>OUTPUT BYTE 1 OUTPUT BYTE n<br>MISO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0<br>Figure 38. Burst Read<br>CS<br>0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23<br>SCLK<br>INSTRUCTION 8-BIT ADDRESS DATA BYTE 1 DATA BYTE n<br>MOSI 0 0 0 0 1 0 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0<br>HIGH IMPEDANCE<br>MISO<br>11719-039<br>11719-040<br>11719-041<br>11719-042<br>**----- End of picture text -----**<br>
_Figure 39. Burst Write (Receive Instruction Only)_
Rev. A | Page 22 of 45
**==> picture [535 x 674] intentionally omitted <==**
**----- Start of picture text -----**<br>
Data Sheet ADXL363<br>CS<br>0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15<br>SCLK<br>INSTRUCTION<br>MOSI 0 0 0 0 1 1 0 1<br>OUTPUT BYTE 1 OUTPUT BYTE n<br>MISO<br>7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0<br>Figure 40. FIFO Read<br>tCSD<br>CS<br>CSS tR tF tCSH tCLDtCLE<br>SCLK<br>tSU<br>tHD<br>MOSI MSB IN LSB IN<br>HIGH IMPEDANCE<br>MISO<br>Figure 41. Timing Diagram for SPI Receive Instructions<br>CS<br>tHIGH tLOW tCSH<br>SCLK<br>DON’T CARE<br>MOSI<br>tV tHO tDIS<br>MISO MSB OUT LSB OUT<br>Figure 42. Timing Diagram for SPI Send Instructions (Shaded Portions of Figure 36, Figure 38, and Figure 40)<br>Table 11. SPI Digital Input/Output<br>Limit [1]<br>Parameter Test Conditions/Comments Min Max Unit<br>Digital Input<br>Low Level Input Voltage (VIL) 0.3 × VDD I/O V<br>High Level Input Voltage (VIH) 0.7 × VDD I/O V<br>Low Level Input Current (IIL) VIN = VDD I/O 0.1 µA<br>High Level Input Current (IIH) VIN = 0 V −0.1 µA<br>Digital Output<br>Low Level Output Voltage (VOL) IOL = 10 mA 0.2 × VDD I/O V<br>High Level Output Voltage (VOH) IOH = −4 mA 0.8 × VDD I/O V<br>Low Level Output Current (IOL) VOL = VOL, max 10 mA<br>High Level Output Current (IOH) VOH = VOH, min −4 mA<br>11719-043<br>11719-044<br>11719-045<br>**----- End of picture text -----**<br>
1 Limits based on characterization results; not production tested.
Rev. A | Page 23 of 45
**ADXL363 Data Sheet**
**Table 12. SPI Timing (TA = 25°C, VS = 2.0 V, VDD I/O = 2.0 V)**
|**Table 12. SPI**|**iming (TA = 25C, VS**|**iming (TA = 25C, VS**|**= 2.0 V,**|**VDD I/O = 2.0 V)**|
|---|---|---|---|---|
|**Parameter**|**Limit1, 2**||**Unit**|**Description**|
||**Min**|**Max**|||
|fCLK3<br>CSS<br>tCSH<br>tCSD<br>tSU<br>tHD<br>tR<br>tF<br>tHIGH<br>tLOW<br>tCLD<br>tCLE<br>tV<br>tHO<br>tDIS|2.4<br>100<br>100<br>20<br>20<br>20<br>0<br>0<br>50<br>50<br>100<br>25<br>0<br>0<br>0|8000<br>100<br>100<br>35<br>200<br>25|kHz<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns|SCLK Frequency<br>CS<br>Setup Time<br>CS<br>Hold Time<br>CS<br>Disable Time<br>Data Setup Time<br>Data Hold Time<br>SCLK Rise Time<br>SCLK Fall Time<br>SCLK High Time<br>SCLK Low Time<br>SCLK Delay Time<br>SCLK Enable Time<br>Output Valid from SCLK Low<br>Output Hold Time<br>Output Disable Time|
- 1 Limits based on design targets; not production tested.
- 2 The timing values are measured corresponding to the input thresholds (VIL and VIH) given in Table 11.
- 3 The minimum limit is only necessary when using FIFO.
Rev. A | Page 24 of 45
**Data Sheet ADXL363**
## **REGISTER MAP**
**Table 13. Register Summary**
|**Reg**|**Name**|**Bits**|**Bit 7**|**Bit 6**|**Bit 5**|**Bit 4**|**Bit 3**|**Bit 2**|**Bit 1**|**Bit 0**|**Reset**|**RW**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|
|0x00|DEVID_AD|[7:0]|DEVID_AD[7:0]||||||||0xAD|R|
|0x01|DEVID_MST|[7:0]|DEVID_MST[7:0]||||||||0x1D|R|
|0x02|DEVID|[7:0]|DEVID[7:0]||||||||0xF3|R|
|0x03|REVID|[7:0]|REVID[7:0]||||||||0x01|R|
|0x08|XDATA|[7:0]|XDATA[7:0]||||||||0x00|R|
|0x09|YDATA|[7:0]|YDATA[7:0]||||||||0x00|R|
|0x0A|ZDATA|[7:0]|ZDATA[7:0]||||||||0x00|R|
|0x0B|STATUS|[7:0]|ERR_USER_<br>REGS|AWAKE|INACT|ACT|FIFO_<br>OVERRUN|FIFO_<br>WATERMARK|FIFO_READY|DATA_READY|0x40|R|
|0x0C|FIFO_ENTRIES_L|[7:0]|FIFO_ENTRIES_L[7:0]||||||||0x00|R|
|0x0D|FIFO_ENTRIES_H|[7:0]|UNUSED||||||FIFO_ENTRIES_H[1:0]||0x00|R|
|0x0E|XDATA_L|[7:0]|XDATA_L[7:0]||||||||0x00|R|
|0x0F|XDATA_H|[7:0]|SX||||XDATA_H[3:0]||||0x00|R|
|0x10|YDATA_L|[7:0]|YDATA_L[7:0]||||||||0x00|R|
|0x11|YDATA_H|[7:0]|SX||||YDATA_H[3:0]||||0x00|R|
|0x12|ZDATA_L|[7:0]|ZDATA_L[7:0]||||||||0x00|R|
|0x13|ZDATA_H|[7:0]|SX||||ZDATA_H[3:0]||||0x00|R|
|0x14|TEMP_L|[7:0]|TEMP_L[7:0]||||||||0x00|R|
|0x15|TEMP_H|[7:0]|SX||||TEMP_H[3:0]||||0x00|R|
|0x16|ADC_DATA_L|[7:0]|ADC_DATA_L[7:0]||||||||0x00|R|
|0x17|ADC_DATA_H|[7:0]|SX||||ADC_DATA_H[2:0]||||0x00|R|
|0x1F|SOFT_RESET|[7:0]|SOFT_RESET[7:0]||||||||0x00|W|
|0x20|THRESH_ACT_L|[7:0]|THRESH_ACT_L[7:0]||||||||0x00|RW|
|0x21|THRESH_ACT_H|[7:0]|UNUSED|||||THRESH_ACT_H[2:0]|||0x00|RW|
|0x22|TIME_ACT|[7:0]|TIME_ACT[7:0]||||||||0x00|RW|
|0x23|THRESH_INACT_L|[7:0]|THRESH_INACT_L[7:0]||||||||0x00|RW|
|0x24|THRESH_INACT_H|[7:0]|UNUSED|||||THRESH_INACT_H[2:0]|||0x00|RW|
|0x25|TIME_INACT_L|[7:0]|TIME_INACT_L[7:0]||||||||0x00|RW|
|0x26|TIME_INACT_H|[7:0]|TIME_INACT_H[7:0]||||||||0x00|RW|
|0x27|ACT_INACT_CTL|[7:0]|UNUSED||LINKLOOP||INACT_REF|INACT_EN|ACT_REF|ACT_EN|0x00|RW|
|0x28|FIFO_CONTROL|[7:0]|UNUSED||||AH|FIFO_TEMP|FIFO_MODE||0x00|RW|
|0x29|FIFO_SAMPLES|[7:0]|FIFO_SAMPLES[7:0]||||||||0x80|RW|
|0x2A|INTMAP1|[7:0]|INT_LOW|AWAKE|INACT|ACT|FIFO_<br>OVERRUN|FIFO_<br>WATERMARK|FIFO_READY|DATA_READY|0x00|RW|
|0x2B|INTMAP2|[7:0]|INT_LOW|AWAKE|INACT|ACT|FIFO_<br>OVERRUN|FIFO_WATER-<br>MARK|FIFO_READY|DATA_READY|0x00|RW|
|0x2C|FILTER_CTL|[7:0]|RANGE||RES|HALF_BW|EXT_SAMPLE|ODR|||0x13|RW|
|0x2D|POWER_CTL|[7:0]|ADC_EN|EXT_CLK|LOW_NOISE||WAKEUP|AUTOSLEEP|MEASURE||0x00|RW|
|0x2E|SELF_TEST|[7:0]|UNUSED|||||||ST|0x00|RW|
Rev. A | Page 25 of 45
**ADXL363**
**Data Sheet**
## **REGISTER DETAILS**
This section describes the functions of the ADXL363 registers. The ADXL363 powers up with default register values as shown in the reset column of Table 13 in the Register Map section.
Make any changes to the registers before the POWER_CTL register (Register 0x00 to Register 0x2C) with the device in standby. If changes are made while the ADXL363 is in measurement mode, they may be effective for only part of a measurement.
## **X-AXIS DATA (8 MSB) REGISTER**
## **Address: 0x08, Reset: 0x00, Name: XDATA**
This register holds the eight most significant bits of the x-axis acceleration data. This limited resolution data register is used in power conscious applications where eight bits of data are sufficient: energy can be conserved by reading only one byte of data per axis, rather than two.
## **DEVICE ID REGISTERS**
## **Address: 0x00, Reset: 0xAD, Name: DEVID_AD**
This register contains the Analog Devices, Inc., accelerometer ID, 0xAD.
**Address: 0x01, Reset: 0x1D, Name: DEVID_MST**
This register contains the Analog Devices MEMS device ID, 0x1D.
## **Y-AXIS DATA (8 MSB) REGISTER**
**Address: 0x09, Reset: 0x00, Name: YDATA**
This register holds the eight most significant bits of the y-axis acceleration data. This limited resolution data register is used in power conscious applications where eight bits of data are sufficient: energy can be conserved by reading only one byte of data per axis, rather than two.
## **Z-AXIS DATA (8 MSB) REGISTER**
**Address: 0x02, Reset: 0xF3, Name: DEVID**
This register contains the device ID, 0xF3 (363 octal).
**Address: 0x0A, Reset: 0x00, Name: ZDATA**
This register holds the eight most significant bits of the z-axis acceleration data. This limited resolution data register is used in power conscious applications where eight bits of data are sufficient: energy can be conserved by reading only one byte of data per axis, rather than two.
## **SILICON REVISION ID REGISTER**
## **Address: 0x03, Reset: 0x01, Name: REVID**
This register contains the product revision ID, beginning with 0x01 and incrementing for each subsequent revision.
Rev. A | Page 26 of 45
**ADXL363**
**Data Sheet**
## **STATUS REGISTER**
## **Address: 0x0B, Reset: 0x40, Name: STATUS**
This register includes the following bits that describe various conditions of the ADXL363.
**Table 14. Bit Descriptions for STATUS**
|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|7|ERR_USER_REGS||SEU Error Detect. 1 indicates one of two conditions: either an SEU event,<br>such as an alpha particle of a power glitch, has disturbed a user register<br>setting or theADXL363is not configured. This bit is high upon both<br>startup and soft reset, and resets as soon as any register write commands<br>areperformed.|0x0|R|
|6|AWAKE||Indicates whether the accelerometer is in an active (awake = 1) or<br>inactive (awake = 0) state, based on the activity and inactivity<br>functionality. To enable autosleep, activity and inactivity detection must<br>be in linked mode or loop mode (LINKLOOP bits in the ACT_INACT_CTL<br>register); otherwise, this bit defaults to 1.|0x1|R|
|5|INACT||Inactivity. 1 indicates that the inactivity detection function has detected<br>an inactivityor a free fall condition.|0x0|R|
|4|ACT||Activity. 1 indicates that the activity detection function has detected an<br>overthreshold condition.|0x0|R|
|3|FIFO_OVERRUN||FIFO Overrun. 1 indicates that the FIFO has overrun or overflowed, such<br>that new data replaces unread data. See the Using FIFO Interrupts<br>section for details.|0x0|R|
|2|FIFO_WATERMARK||FIFO Watermark. 1 indicates that the FIFO contains at least the desired<br>number of samples, as set in the FIFO_SAMPLES register. See the Using<br>FIFO Interrupts section for details.|0x0|R|
|1|FIFO_READY||FIFO Ready. 1 indicates that there is at least one sample available in the<br>FIFO output buffer. See the UsingFIFO Interrupts section for details.|0x0|R|
|0|DATA_READY||Data Ready. 1 indicates that a new valid sample is available to be read.<br>This bit clears when a FIFO read is performed. See the Data Ready<br>Interrupt section for more details.|0x0|R|
Rev. A | Page 27 of 45
**Data Sheet**
## **ADXL363**
## **FIFO ENTRIES REGISTERS**
These registers indicate the number of valid data samples present in the FIFO buffer. This number ranges from 0 to 512 or 0x00 to 0x200. FIFO_ENTRIES_L contains the least significant byte. FIFO_ENTRIES_H contains the two most significant bits. Bits[15:10] of FIFO_ENTRIES_H are unused (represented as X = don’t care).
**Address: 0x0C, Reset: 0x00, Name: FIFO_ENTRIES_L**
**Address: 0x0D, Reset: 0x00, Name: FIFO_ENTRIES_H**
## **X-AXIS DATA REGISTERS**
These two registers contain the twos complement, sign extended (SX) x-axis acceleration data. XDATA_L contains the eight least significant bits (LSBs), and XDATA_H contains the four most significant bits (MSBs) of the 12-bit value.
The sign extension bits (B[15:12], denoted as SX in the XDATA_H bit map that follows) have the same value as the MSB (B11).
**Address: 0x0E, Reset: 0x00, Name: XDATA_L**
**Address: 0x0F, Reset: 0x00, Name: XDATA_H**
## **Y-AXIS DATA REGISTERS**
These two registers contain the twos complement, sign extended (SX) y-axis acceleration data. YDATA_L contains the eight LSBs and YDATA_H contains the four MSBs of the 12-bit value.
The sign extension bits (B[15:12], denoted as SX in the YDATA_H bit map that follows) have the same value as the MSB (B11).
**Address: 0x10, Reset: 0x00, Name: YDATA_L**
## **Z-AXIS DATA REGISTERS**
These two registers contain the twos complement, sign extended (SX) z-axis acceleration data. ZDATA_L contains the eight LSBs, and ZDATA_H contains the four MSBs of the 12-bit value.
The sign extension bits (Bits[15:12], denoted as SX in the ZDATA_H bit map that follows) have the same value as the MSB (B11).
**Address: 0x12, Reset: 0x00, Name: ZDATA_L**
**Address: 0x13, Reset: 0x00, Name: ZDATA_H**
## **TEMPERATURE DATA REGISTERS**
These two registers contain the twos complement, sign extended (SX) temperature sensor output data. TEMP_L contains the eight LSBs, and TEMP_H contains the four MSBs of the 12-bit value. The value is sign extended; therefore, Bits[B15:B12] of TEMP_H are all 0s or all 1s, based on the value of Bit B11.
The sign extension bits (B[15:12], denoted as SX in the TEMP_H bit map that follows) have the same value as the MSB (B11).
**Address: 0x14, Reset: 0x00, Name: TEMP_L**
**Address: 0x15, Reset: 0x00, Name: TEMP_H**
## **ADC DATA REGISTERS**
These two registers contain the twos complement, sign extended (SX) output of the auxiliary ADC.
ADC_DATA_L contains the eight LSBs, and ADC_DATA_H contains the four MSBs of the 12-bit value.
The sign extension bits (B[15:12], denoted as SX in the ADC_DATA_H bit map that follows) have the same value as the MSB (B11).
**Address: 0x16, Reset: 0x00, Name: ADC_DATA_L**
**Address: 0x11, Reset: 0x00, Name: YDATA_H**
**Address: 0x17, Reset: 0x00, Name: ADC_DATA_H** Bi Bi4 B12 B12 Bil B10 BS 88
Rev. A | Page 28 of 45
**ADXL363**
**Data Sheet**
## **SOFT RESET REGISTER**
**Address: 0x1F, Reset: 0x00, Name: SOFT_RESET**
Writing Code 0x52 (representing the letter, R, in ASCII or unicode) to this register immediately resets the ADXL363. All register settings are cleared, and the sensor is placed in standby. Interrupt pins are configured to a high output impedance mode and held to a valid state by bus keepers.
Setting the activity time to 0x00 has the same result as setting this time to 0x01: activity is detected when a single acceleration sample has at least one axis greater than the activity threshold (THRESH_ACT).
When the accelerometer is in wake-up mode, the TIME_ACT value is ignored, and activity is detected based on a single acceleration sample.
This is a write-only register. If read, data in it is always 0x00. B7 «BG OBS) BSB
## **INACTIVITY THRESHOLD REGISTERS**
## **ACTIVITY THRESHOLD REGISTERS**
To detect activity, the ADXL363 compares the absolute value of the 12-bit (signed) acceleration data with the 11-bit (unsigned) THRESH_ACT value. See the Motion Detection section for more information on activity detection.
The term, THRESH_ACT, refers to an 11-bit unsigned value comprising the THRESH_ACT_L register, which holds its eight LSBs; and the THRESH_ACT_H register, which holds its three MSBs.
THRESH_ACT is set in codes; the value in _g_ depends on the measurement range setting that is selected.
_THRESH_ACT_ [ _g_ ] = _THRESH_ACT_ [codes]/ _Scale Factor_ [codes per _g_ ]
**Address: 0x20, Reset: 0x00, Name: THRESH_ACT_L**
**Address: 0x21, Reset: 0x00, Name: THRESH_ACT_H**
## **ACTIVITY TIME REGISTER**
## **Address: 0x22, Reset: 0x00, Name: TIME_ACT**
The activity timer implements a robust activity detection that minimizes false positive motion triggers. When the timer is used, only sustained motion can trigger activity detection. Refer to the Fewer False Positives section for additional information.
The value in this register sets the number of consecutive samples that must have at least one axis greater than the activity threshold (set by THRESH_ACT) for an activity event to be detected.
The time (in seconds) is given by the following equation:
## _Time = TIME_ACT_ / _ODR_
## where:
_TIME_ACT_ is the value set in this register. _ODR_ is the output data rate set in the FILTER_CTL register (Address 0x2C).
To detect inactivity, the absolute value of the 12-bit acceleration data is compared with the 11-bit (unsigned) THRESH_INACT value. See the Motion Detection section for more information.
The term, THRESH_INACT, refers to an 11-bit unsigned value comprising the THRESH_INACT_L registers, which holds its eight LSBs, and the THRESH_INACT_H register, which holds its three MSBs.
This 11-bit unsigned value sets the threshold for inactivity detection. This value is set in codes; the value (in _g_ ) depends on the measurement range setting selected:
_THRESH_INACT_ [ _g_ ] =
_THRESH_INACT_ [codes]/ _Scale Factor_ [codes per _g_ ]
**Address: 0x23, Reset: 0x00, Name: THRESH_INACT_L**
**Address: 0x24, Reset: 0x00, Name: THRESH_INACT_H**
## **INACTIVITY TIME REGISTERS**
The 16-bit value in these registers sets the number of consecutive samples that must have all axes lower than the inactivity threshold (set by THRESH_INACT) for an inactivity event to be detected.
The TIME_INACT_L register holds the eight LSBs, and the TIME_INACT_H register holds the eight MSBs of the 16-bit TIME_INACT value.
The time in seconds can be calculated as
_Time = TIME_INACT_ / _ODR_
## where:
_TIME_INACT_ is the 16-bit value set by the TIME_INACT_L register (eight LSBs) and the TIME_INACT_H register (eight MSBs). _ODR_ is the output data rate set in the FILTER_CTL register (Address 0x2C).
Rev. A | Page 29 of 45
**Data Sheet**
## **ADXL363**
The 16-bit value allows for long inactivity detection times. The maximum value is 0xFFFF or 65,535 samples. At the lowest output data rate, 12.5 Hz, this equates to almost 90 minutes. In this configuration, the accelerometer must be stationary for 90 minutes before putting its system to sleep.
**Address: 0x25, Reset: 0x00, Name: TIME_INACT_L**
**Address: 0x26, Reset: 0x00, Name: TIME_INACT_H**
Setting the inactivity time to 0x00 has the same result as setting this time to 0x01: inactivity is detected when a single acceleration sample has all axes lower than the inactivity threshold (THRESH_INACT).
Rev. A | Page 30 of 45
**ADXL363**
**Data Sheet**
## **ACTIVITY/INACTIVITY CONTROL REGISTER**
**Address: 0x27, Reset: 0x00, Name: ACT_INACT_CTL**
**Table 15. Bit Descriptions for ACT_INACT_CTL**
|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:6]|UNUSED||Unused Bits.|0x0|RW|
|[5:4]|LINKLOOP|X0<br>01<br>11|Link/Loop Mode Enable.<br>Default Mode.<br>Activity and inactivity detection are both enabled, and their interrupts (if<br>mapped) must be acknowledged by the host processor by reading the<br>status register. Autosleep is disabled in this mode. Use this mode for free<br>fall detection applications.<br>Linked Mode.<br>Activity and inactivity detection are linked sequentially such that only one<br>is enabled at a time. Their interrupts (if mapped) must be acknowledged<br>by the host processor by reading the status register.<br>Loop Mode.<br>Activity and inactivity detection are linked sequentially such that only one<br>is enabled at a time, and their interrupts are internally acknowledged (do<br>not need to be serviced by the host processor).<br>To use either linked or looped mode, both ACT_EN (Bit 0) and INACT_EN<br>(Bit 2) must be set to 1; otherwise, the default mode is used. For additional<br>information, refer to the LinkingActivityand InactivityDetection section.|0x0|RW|
|3|INACT_REF||Inactivity Referenced/Absolute Select.<br>1 = inactivity detection function operates in referenced mode.<br>0 = inactivitydetection function operates in absolute mode.|0x0|RW|
|2|INACT_EN||Inactivity Enable.<br>1 = enables the inactivity(underthreshold) functionality.|0x0|RW|
|1|ACT_REF||Activity Referenced/Absolute Select.<br>1 = activity detection function operates in referenced mode.<br>0 = activitydetection function operates in absolute mode.|0x0|RW|
|0|ACT_EN||Activity Enable.<br>1 = enables the activity(overthreshold) functionality.|0x0|RW|
Rev. A | Page 31 of 45
**ADXL363**
**Data Sheet**
## **FIFO CONTROL REGISTER**
**Address: 0x28, Reset: 0x00, Name: FIFO_CONTROL**
**Table 16. Bit Descriptions for FIFO_CONTROL**
|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:4]|UNUSED||Unused Bits.|0x0|RW|
|3|AH||Above Half.<br>This bit is the MSB of the FIFO_SAMPLES register, allowing FIFO samples a<br>range of 0 to 511.|0x0|RW|
|2|FIFO_TEMP||Enables storing temperature data in the FIFO.<br>1 = temperature data is stored in the FIFO together with x-, y-, and z-axis<br>acceleration data.|0x0|RW|
|[1:0]|FIFO_MODE|00<br>01<br>10<br>11|Enable the FIFO and selects the mode.<br>FIFO is disabled.<br>Oldest saved mode.<br>Stream mode.<br>Triggered mode.|0x0|RW|
Rev. A | Page 32 of 45
**ADXL363**
**Data Sheet**
## **FIFO SAMPLES REGISTER**
**Address: 0x29, Reset: 0x80, Name: FIFO_SAMPLES**
The value in this register specifies the number of samples to store in the FIFO. The AH bit in the FIFO_CONTROL register (Address 0x28) is used as the MSB of this value. The full range of FIFO samples is 0 to 511.
The default value of this register is 0x80 to avoid triggering the FIFO watermark interrupt (see the FIFO Watermark section for more information).
The following bit map is duplicated from the FIFO Control Register section to indicate the AH bit.
## **INT1/INT2 FUNCTION MAP REGISTERS**
The INT1 and INT2 registers configure the INT1 and INT2 interrupt pins, respectively. Bits[6:0] select which function(s) generate an interrupt on the pin. If its corresponding bit is set to 1, the function generates an interrupt on the INTx pin. Bit B7 configures whether the pin operates in active high (B7 = 0) or active low (B7 = 1) mode.
Any number of functions can be selected simultaneously for each pin. If multiple functions are selected, their conditions are OR'ed together to determine the INTx pin state. The status of each individual function can be determined by reading the status register. If no interrupts are mapped to an INTx pin, the pin remains in a high impedance state, held to a valid logic state by a bus keeper.
**Address: 0x2A, Reset: 0x00, Name: INTMAP1**
**Table 17. Bit Descriptions for INTMAP1**
|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|7|INT_LOW||Interrupt Active Low. 1 = INT1pin is active low.|0x0|RW|
|6|AWAKE||Awake Interrupt. 1 = maps the awake status to INT1pin.|0x0|RW|
|5|INACT||InactivityInterrupt. 1 = maps the inactivitystatus to INT1pin.|0x0|RW|
|4|ACT||ActivityInterrupt. 1 = maps the activitystatus to INT1pin.|0x0|RW|
|3|FIFO_OVERRUN||FIFO Overrun Interrupt. 1 = maps the FIFO overrun status to INT1pin.|0x0|RW|
|2|FIFO_WATERMARK||FIFO Watermark Interrupt. 1 = maps the FIFO watermark status to INT1pin.|0x0|RW|
|1|FIFO_READY||FIFO ReadyInterrupt. 1 = maps the FIFO readystatus to INT1pin.|0x0|RW|
|0|DATA_READY||Data ReadyInterrupt. 1 = maps the data readystatus to INT1pin.|0x0|RW|
Rev. A | Page 33 of 45
**ADXL363**
**Data Sheet**
**Address: 0x2B, Reset: 0x00, Name: INTMAP2**
**Table 18. Bit Descriptions for INTMAP2**
|**Bit Name**|**Settings**|**Description**|**Reset**|
|---|---|---|---|
|INT_LOW||Interrupt Active Low. 1 = INT2pin is active low.|0x0|
|AWAKE||Awake Interrupt. 1 = maps the awake status to INT2pin.|0x0|
|INACT||InactivityInterrupt. 1 = maps the inactivitystatus to INT2pin.|0x0|
|ACT||ActivityInterrupt. 1 = maps the activitystatus to INT2pin.|0x0|
|FIFO_OVERRUN||FIFO Overrun Interrupt. 1 = maps the FIFO overrun status to INT2pin.|0x0|
|FIFO_WATERMARK||FIFO Watermark Interrupt. 1 = maps the FIFO watermark status to INT2pin.|0x0|
|FIFO_READY||FIFO ReadyInterrupt. 1 = maps the FIFO readystatus to INT2pin.|0x0|
|DATA_READY||Data ReadyInterrupt. 1 = maps the data readystatus to INT2pin.|0x0|
Rev. A | Page 34 of 45
**ADXL363**
**Data Sheet**
## **FILTER CONTROL REGISTER**
**Address: 0x2C, Reset: 0x13, Name: FILTER_CTL**
## **Table 19. Bit Descriptions for FILTER_CTL**
|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:6]|RANGE|00<br>01<br>1X|Measurement Range Selection.<br>±2_g_(reset default).<br>±4_g_.<br>±8_g_.|0x0|RW|
|5|RES||Reserved.|0x0|RW|
|4|HALF_BW||Halved Bandwidth. Additional information is provided in the Antialiasing section.<br>1 = the bandwidth of the antialiasing filters is set to ¼ the output data rate (ODR) for<br>more conservative filtering.<br>0 = the bandwidth of the filters is set to ½ the ODR for a wider bandwidth.|0x1||
|3|EXT_SAMPLE||External Sampling Trigger. 1 = the INT2 pin is used for external conversion timing<br>control. Refer to the Using Synchronized Data Sampling section for more<br>information.|0x0|RW|
|[2:0]|ODR|000<br>001<br>010<br>011<br>100<br>101…111|Output Data Rate. Selects the ODR and configures internal filters to a bandwidth of ½<br>or ¼ the selected ODR, depending on the HALF_BW bit setting.<br>12.5 Hz.<br>25 Hz.<br>50 Hz.<br>100 Hz (reset default).<br>200 Hz.<br>400 Hz.|0x3|RW|
Rev. A | Page 35 of 45
**ADXL363**
**Data Sheet**
## **POWER CONTROL REGISTER**
**Address: 0x2D, Reset: 0x00, Name: POWER_CTL**
**Table 20. Bit Descriptions for POWER_CTL**
|**Bits**|**Bit Name**|**Settings**|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|7|ADC_EN||ADC Enable.<br>1 = ADC is enabled. The signal on the ADC input pin is converted and the<br>corresponding digital value is made available in the ADC_DATA_H and<br>ADC_DATA_L registers. Data in these registers is updated at the ODR<br>selected in the FILTER_CTL register.<br>0 = ADC is disabled.|0x0|RW|
|6|EXT_CLK||External Clock. See the Using an External Clock section for additional details.<br>1 = the accelerometer runs off the external clockprovided on the INT1pin.|0x0|RW|
|[5:4]|LOW_NOISE|00<br>01<br>10<br>11|Selects Power vs. Noise Tradeoff:<br>Normal operation (reset default).<br>Low noise mode.<br>Ultralow noise mode.<br>Reserved.|0x0|RW|
|3|WAKEUP||Wake-Up Mode. See the Operating Modes section for a detailed<br>description of wake-up mode.<br>1 = the device operates in wake-upmode.|0x0|RW|
|2|AUTOSLEEP||Autosleep. Activity and inactivity detection must be in linked mode or<br>loop mode (LINK/LOOP bits in ACT_INACT_CTL register) to enable<br>autosleep; otherwise, the bit is ignored. See the Motion Detection section<br>for details.<br>1 = autosleep is enabled, and the device enters wake-up mode<br>automaticallyupon detection of inactivity.|0x0|RW|
|[1:0]|MEASURE|00<br>01<br>10<br>11|Selects Measurement Mode or Standby.<br>Standby.<br>Reserved.<br>Measurement mode.<br>Reserved.|0x0|RW|
Rev. A | Page 36 of 45
**ADXL363**
**Data Sheet**
## **SELF TEST REGISTER**
## **Address: 0x2E, Reset: 0x00, Name: SELF_TEST**
Refer to the Self Test section for information on the operation of the self test feature, and see the Using Self Test section for guidelines on how to use this functionality.
|**Bit Name**|**Settings**|**Description**|**Reset**|
|---|---|---|---|
|UNUSED||Unused Bits.|0x0|
|ST||Self Test.<br>1 = a self test force is applied to the x-,y-, and z-axes.|0x0|
Rev. A | Page 37 of 45
**Data Sheet**
## **ADXL363**
## **APPLICATIONS INFORMATION**
## **APPLICATION EXAMPLES**
This section includes a few application circuits, highlighting useful features of the ADXL363.
## _**Device Configuration**_
This section outlines the procedure for configuring the device and acquiring data. In general, the procedure follows the sequence of the register map, starting with Register 0x20, THRESH_ACT_L.
1. Set activity and inactivity thresholds and timers.
- a. Write to Register 0x20 to Register 0x26.
- b. To minimize false positive motion triggers, set the TIME_ACT register greater than 1.
2. Configure activity and inactivity functions.
- a. Write to Register 0x27.
3. Configure FIFO.
- a. Write to Register 0x28 and Register 0x29.
4. Map interrupts.
- a. Write to Register 0x2A and Register 0x2B.
5. Configure general device settings.
- a. Write to Register 0x2C.
6. Turn measurement on.
power. In this example, the awake signal, mapped to the INT2 pin, drives a high-side power switch, such as the ADP195, to control power to the downstream circuitry.
## **Startup Routine**
This routine assumes a ±2 _g_ measurement range and operation in wake-up mode.
1. Write 250 decimal (0xFA) to Register 0x20, and write 0 to Register 0x21 to set activity threshold to 250 m _g_ .
2. Write 150 decimal (0x96) to Register 0x23, and write 0 to Register 0x24 to set inactivity threshold to 150 m _g_ .
3. Write 30 decimal (0x1E) to Register 0x25 to set inactivity timer to 30 samples or about 5 seconds.
4. Write 0x3F to Register 0x27 to configure motion detection in loop mode and enables referenced activity and inactivity detection.
5. Configure FIFO as desired.
6. Write 0x40 to Register 0x2B to map the awake bit to INT2. The INT2 pin is tied to the gate of the switch.
7. Write 0x8A to Register 0x2D to begin the measurement in wake-up mode (six samples per second), with ADC enabled.
- a. Write to Register 0x2D.
7. Wait 4/ODR for data to settle before reading the data registers.
Settings for each of the registers vary based on application requirements. For more information, see the Register Details section.
**==> picture [226 x 212] intentionally omitted <==**
**----- Start of picture text -----**<br>
VS VDD I/O<br>CS CIO<br>VS VDD I/O<br>ADXL363<br>MOSI<br>INTERRUPTCONTROL INT1 MISO SPI<br>SCLK INTERFACE<br>AWAKE INT2 GND CS<br>ADP195 REVERSE<br>POLARITY<br>PROTECTION<br>VIN VOUT<br>VS<br>GND<br>EN LEVEL SHIFT LOAD<br>AND SLEW<br>RATE CONTROL<br>11719-046<br>**----- End of picture text -----**<br>
_Figure 43. Awake Signal to Control Power to Downstream Circuitry_
## _**Autonomous Motion Switch**_
The features of the ADXL363 make it ideal for use as an autonomous motion switch. The example outlined here implements a switch that, once configured, operates without the intervention of a host processor to intelligently manage system
## **USING EXTERNAL TIMING**
## _**Using an External Clock**_
The ADXL363 has a built-in clock that, by default, is used for clocked internal operations, including for setting the ODR. Where a more accurate frequency setting is desired, an external clock can be provided and used.
Figure 44 shows an application diagram for using the INT1 pin as the input for an external clock. In this mode, the external clock determines all accelerometer timing, including the output data rate and bandwidth. The external clock must operate at or below 51.2 kHz. Additional information is provided in the External Clock section.
To enable this feature, at the end of the desired start-up routine, set Bit 6 in the POWER_CTL register; for example, write 0x42 to this register to enable the use of an external clock and place the accelerometer in measurement mode.
**==> picture [223 x 109] intentionally omitted <==**
**----- Start of picture text -----**<br>
VS VDD I/O<br>CS CIO<br>VS VDD I/O<br>ADXL363<br>MOSI<br>EXTERNALCLOCK INT1 MISO SPI<br>SCLK INTERFACE<br>INTERRUPT<br>CONTROL INT2 GND CS 10776-047<br>**----- End of picture text -----**<br>
_Figure 44.Using the INT1 Pin as External Clock Input_
Rev. A | Page 38 of 45
**ADXL363**
**Data Sheet**
## _**Using Synchronized Data Sampling**_
For applications that require a precisely timed measurement, the ADXL363 features an option to synchronize data sampling of all its sensors to an external trigger. The EXT_SAMPLE bit (Bit 3) in the FILTER_CTL Register (Address 0x2C) enables this feature. When the EXT_SAMPLE bit is set to 1, the INT2 pin is automatically reconfigured for use as the sync trigger input.
When external triggering is enabled, it is up to the system designer to ensure that the sampling frequency meets system requirements. Sampling too infrequently causes aliasing. Noise can be lowered by oversampling; however, sampling at too high a frequency may not allow enough time for the accelerometer to process the acceleration data and convert it to valid digital output.
When Nyquist criteria are met, signal integrity is maintained. An internal antialiasing filter is available in the ADXL363 and can assist the system designer in maintaining signal integrity. To prevent aliasing, set the filter bandwidth to a frequency that is no greater than ½ the sampling rate. For example, when sampling at 100 Hz, set the filter pole to no higher than 50 Hz. The filter pole is set via the ODR bits in the FILTER_CTL register (Address 0x2C). The filter bandwidth is set to ½ the ODR and is set via these bits. Even though the ODR is ignored (because the data rate is set by the external trigger), the filter is still applied at the specified bandwidth.
Because of internal timing requirements, the trigger signal applied to Pin INT2 must meet the following criteria:
- The trigger signal is active high.
- The pulse width of the trigger signal must be at least 25 µs.
- The trigger must be deasserted for at least 25 µs before it is reasserted.
- The maximum sampling frequency that is supported is 625 Hz (typical). The minimum sampling frequency is set only by system requirements. Samples do not need to be polled at any minimum rate; however, if samples are polled at a rate lower than the bandwidth set by the antialiasing filter, then aliasing may occur.
## **How to Set Up Synchronized Data Sampling**
The ADXL363 includes a provision for a sample trigger input. Figure 45 shows an application diagram for using the INT2 pin as a trigger for synchronized sampling. Acceleration samples are produced every time this trigger is activated.
To use the sample trigger feature, near the end of the desired start-up routine, set Bit 3 in the FILTER_CTL register; for example, write 0x4B to this register to enable the trigger and configure the accelerometer for ±8 _g_ measurement range and 100 Hz ODR. A sample is acquired every time a pulse is transmitted to the sampling trigger input (INT2 pin). The pulse is active high, and the sampling trigger input idles in the low state.
**==> picture [223 x 109] intentionally omitted <==**
**----- Start of picture text -----**<br>
VS VDD I/O<br>CS CIO<br>VS VDD I/O<br>ADXL363<br>MOSI<br>INTERRUPT<br>CONTROL INT1 MISO SPI<br>SCLK INTERFACE<br>SAMPLINGTRIGGER INT2 GND CS 11719-048<br>**----- End of picture text -----**<br>
_Figure 45. Using the INT2 Pin to Trigger Synchronized Sampling_
## **POWER**
## _**Power Supply Decoupling**_
Figure 46 shows the recommended bypass capacitors for use with the ADXL363.
**==> picture [229 x 109] intentionally omitted <==**
**----- Start of picture text -----**<br>
VS VDD I/O<br>CS CIO<br>VS VDD I/O<br>ADXL363<br>MOSI<br>INT1 MISO SPI<br>INTERRUPT SCLK INTERFACE<br>CONTROL<br>INT2 GND CS 11719-049<br>**----- End of picture text -----**<br>
_Figure 46. Recommended Bypass Capacitors_
A 0.1 µF ceramic capacitor (CS) at VS and a 0.1 µF ceramic capacitor (CIO) at VDD I/O is placed as near the ADXL363 as possible. Supply pins are recommended to adequately decouple the accelerometer from noise on the power supply. It is also recommended that VS and VDD I/O be separate supplies to minimize digital clocking noise on the VS supply. If this is not possible, additional filtering of the supplies may be necessary.
If additional decoupling is necessary, place a resistor or ferrite bead, no larger than 100 Ω, in series with VS. Additionally, increasing the bypass capacitance on VS to a 1 µF tantalum capacitor in parallel with a 0.1 µF ceramic capacitor may also improve noise.
Ensure that the connection from the ADXL363 ground to the power supply ground has low impedance because noise transmitted through ground has an effect similar to noise transmitted through VS.
## _**Power Supply Requirements**_
The ADXL363 is designed to operate using supply voltage rails ranging from 1.8 V to 3.3 V. The operating voltage range (VS), specified in Table 1, ranges from 1.6 V to 3.5 V to account for inaccuracies and transients of up to ±10% on the supply voltage.
The ADXL363 does not require any particular start-up transient characteristics, except that it must always be started up from 0 V. When the device is in operation, any time power is removed from the ADXL363 or falls below the operating voltage range, the supplies (VS, VDD I/O, and any bypass capacitors) must be discharged completely before power is reapplied. To enable supply discharge, it is recommended to power the device from a microcontroller GPIO, connect a shutdown discharge switch
Rev. A | Page 39 of 45
**ADXL363**
**Data Sheet**
to the supply (see Figure 47), or use a voltage regulator with a shutdown discharge feature, such as the ADP160.
**==> picture [229 x 105] intentionally omitted <==**
**----- Start of picture text -----**<br>
VS VDD I/O<br>VIN<br>CS CIO<br>VS VDD I/O<br>R1 ADXL363<br>MOSI<br>INT1 MISO SPI<br>SCLK INTERFACE<br>SHUTDOWN INT2 GND CS<br>**----- End of picture text -----**<br>
## **NOTES**
**1. THE ADXL363 SUPPLIES MUST BE DISCHARGED FULLY EACH TIME THE VOLTAGE ON THEM DROPS BELOW THE SPECIFIED OPERATING RANGE. A SHUTDOWN SWITCH IS ONE WAY TO DISCHARGE THE SUPPLIES.**
_Figure 47. Using a Switch to Discharge the ADXL363 Supplies_
## **FIFO MODES**
The FIFO is a 512-sample memory buffer that can be used to save power, unburden the host processor, and autonomously record data.
The 512 FIFO samples can be allotted as one of the following:
- 170 sample sets of concurrent 3-axis data
- 128 sample sets of concurrent 3-axis and temperature data
The FIFO operates in one of the four modes (FIFO disabled, oldest saved mode, stream mode, and triggered mode) described in this section.
## _**FIFO Disabled**_
When the FIFO is disabled, no data is stored in it and any data already stored in it is cleared.
The FIFO is disabled by setting the FIFO_MODE bits in the FIFO_CONTROL register (Address 0x28) to Binary Value 0b00.
## _**Oldest Saved Mode**_
In oldest saved mode, the FIFO accumulates data until it is full and then stops. Additional data is collected only when space is made available by reading samples out of the FIFO buffer. (This mode of operation is sometimes referred to as first N.)
The FIFO is placed into oldest saved mode by setting the FIFO_MODE bits in the FIFO_CONTROL register (Address 0x28) to Binary Value 0b01.
## _**Stream Mode**_
In stream mode, the FIFO always contains the most recent data. The oldest sample is discarded when space is needed to make room for a newer sample. (This mode of operation is sometimes referred to as last N.)
the host processor can read the contents of the entire FIFO and then return to its other tasks as the FIFO fills again.
The FIFO is placed into stream mode by setting the FIFO_MODE bits in the FIFO_CONTROL register (Address 0x28) to Binary Value 0b10.
## _**Triggered Mode**_
In triggered mode, the FIFO saves samples surrounding an activity detection event. The operation is similar to a one-time run trigger on an oscilloscope. The number of samples to be saved prior to the activity event is specified in FIFO_SAMPLES (Register 0x29, along with the AH bit in the FIFO_CONTROL register, Address 0x28).
Place the FIFO in triggered mode by setting the FIFO_MODE bits in the FIFO_CONTROL register (Address 0x28) to Binary Value 0b11.
## _**FIFO Configuration**_
The FIFO is configured via Register 0x28 and Register 0x29. Settings are described in detail in the FIFO Control Register section.
## _**FIFO Interrupts**_
The FIFO can generate interrupts to indicate when samples are available, when a specified number of samples has been collected, and when the FIFO overflows and samples are lost. See the Using FIFO Interrupts section for more information.
## _**Retrieving Data from FIFO**_
FIFO data is read by issuing a FIFO read command, described in the SPI Commands section. Data is formatted as a 16-bit value as represented in Table 22.
When reading data, the least significant byte (Bits[7:0]) is read first, followed by the most significant byte (Bits[B15:B8]). Bits[11:0] represent the 12-bit, twos complement acceleration or temperature data. Bits[13:12] are sign extension bits, and Bits[15:14] indicate the type of data, as listed in Table 22. See Table 23 for a description of Bits[15:14].
**Table 22. FIFO Buffer Data Format**
|**B15**|**B14**|**B13**|**B13**|**B12**|**B11 (MSB)**|**B10 to B1**|**B0 (LSB)**|
|---|---|---|---|---|---|---|---|
|Data type||Sign extension|||Data|||
|**Table 23. Data Type Bits**||||||||
|**Bits[15:14]**|||**Type of Data**|||||
|00<br>01<br>10<br>11|||X-axis<br>Y-axis<br>Z-axis<br>Temperature|||||
Stream mode is useful for unburdening a host processor. The processor can tend to other tasks while data is being collected in the FIFO. When the FIFO fills to a certain number of samples (specified by the FIFO_SAMPLES register along with the AH bit in the FIFO_CONTROL register), it triggers a FIFO watermark interrupt (if this interrupt is enabled). At this point,
Rev. A | Page 40 of 45
**ADXL363**
## **Data Sheet**
Because the data format is 16-bit, the data must be read from the FIFO two bytes at a time. When a multibyte read is performed, the number of bytes read must always be an even number. Multibyte reads of FIFO data can be performed with no limit on the number of bytes read. If additional bytes are read after the FIFO is empty, the data in the additional bytes are read as 0x00.
As each sample set is acquired, it is written into the FIFO in the following order:
- X-axis
- Y-axis
- Z-axis
- Temperature (optional)
Note that ADC data is not stored in the FIFO.
This pattern repeats until the FIFO is full, at which point the behavior depends on the FIFO mode (see the FIFO section). If the FIFO has insufficient space for four data entries (or three entries if temperature is not being stored), an incomplete sample set can be stored.
FIFO data is output on a per datum basis. As each data item is read, the same amount of space is freed up in the stack, which can lead to incomplete sample sets being present in the FIFO.
For additional system level FIFO applications, refer to the AN-1025 Application Note, _Utilization of the First In, First Out (FIFO) Buffer in Analog Devices, Inc. Digital Accelerometers_ .
## **INTERRUPTS**
Several of the built-in functions of the ADXL363 can trigger interrupts to alert the host processor of certain status conditions. This section describes the functionality of these interrupts.
## _**Interrupt Pins**_
Interrupts can be mapped to either (or both) of two designated output pins, INT1 and INT2, by setting the appropriate bits in the INTMAP1 and INTMAP2 registers, respectively. All functions can be used simultaneously. If multiple interrupts are mapped
to one pin, the OR combination of the interrupts determines the status of the pin.
If no functions are mapped to an interrupt pin, that pin is automatically configured to a high impedance (high-Z) state. The pins are also placed in the high-Z state upon a reset.
When a certain status condition is detected, the pin that condition is mapped to is activated. The configuration of the pin is active high by default so that, when it is activated, the pin goes high. However, this configuration can be switched to active low by setting the INT_LOW bit in the appropriate INTMAPx register.
The INTx pins can be connected to the interrupt input of a host processor where interrupts are responded to with an interrupt routine. Because multiple functions can be mapped to the same pin, the status register can be used to determine which condition caused the interrupt to trigger.
Clear interrupts in one of several ways, as follows:
- Read the status register (Address 0x0B) clears activity and inactivity interrupts.
- Read from the data registers. Address 0x08 to Address 0x0A or Address 0x0E to Address 0x15 clears the data ready interrupt.
- Read enough data from the FIFO buffer so that interrupt conditions are no longer met clears the FIFO ready, FIFO watermark, and FIFO overrun interrupts.
Both interrupt pins are push-pull low impedance pins with an output impedance of about 500 Ω (typical) and digital output specifications, as shown in Table 24. Both pins have bus keepers that hold them to a valid logic state when they are in a high impedance mode.
To prevent interrupts from being falsely triggered during configuration, disable interrupts while their settings, such as thresholds, timings, or other values, are configured.
**Table 24. Interrupt Pin Digital Output**
|**Table 24. Interrupt Pin Digital Output**|||||
|---|---|---|---|---|
|**Parameter**|**Test Conditions**|**Limit1**||**Unit**|
|||**Min**|**Max**||
|OUTPUT VOLTAGE<br>Low Level (VOL)<br>High Level (VOH)<br>OUTPUT CURRENT<br>Low Level (IOL)<br>High Level (IOH)|IOL= 500 µA<br>IOH= −300 µA<br>VOL= VOL, max<br>VOH= VOH, min|0.8 × VDD I/O<br>500|0.2 × VDD I/O<br>−300|V<br>V<br>µA<br>µA|
1 Limits based on design; not production tested.
Rev. A | Page 41 of 45
**ADXL363**
**Data Sheet**
## _**Alternate Functions of Interrupt Pins**_
The INT1 and INT2 pins can be configured for use as input pins instead of for signaling interrupts. INT1 is used as an external clock input when the EXT_CLK bit (Bit 6) in the POWER_CTL register (Address 0x2D) is set. INT2 is used as the trigger input for synchronized sampling when the EXT_SAMPLE bit (Bit 3) in the FILTER_CTL register (Address 0x2C) is set. One or both of these alternate functions can be used concurrently; however, if an interrupt pin is used for its alternate function, it cannot simultaneously be used for its primary function, to signal interrupts.
External clocking and data synchronization are described in the Using External Timing section.
## _**Activity and Inactivity Interrupts**_
The ACT bit (Bit 4) and INACT bit (Bit 5) in the status register (Address 0x0B) are set when activity and inactivity are detected, respectively. Detection procedures and criteria are described in the Motion Detection section.
## _**Data Ready Interrupt**_
The DATA_READY bit (Bit 0) in the status register (Address 0x0B) is set when new valid data is available, and it is cleared when no new data is available.
The DATA_READY bit is not set while any of the data registers, Address 0x08 to Address 0x0A and Address 0x0E to Address 0x15, are being read. If DATA_READY = 0 prior to a register read and new data becomes available during the register read, DATA_READY remains at 0 until the read is complete and, only then, is set to 1.
If DATA_READY = 1 prior to a register read, it is cleared at the start of the register read.
If DATA_READY = 1 prior to a register read and new data becomes available during the register read, DATA_READY is cleared to 0 at the start of the register read and remains at 0 throughout the read. When the read is complete, DATA_READY is set to 1.
## _**Using FIFO Interrupts**_
## **FIFO Watermark**
The FIFO_WATERMARK bit (Bit 2) in the status register (Address 0x0B) is set when the number of samples stored in the FIFO is equal to or exceeds the number specified in the FIFO_SAMPLES register (Address 0x29) together with the AH bit (Bit 3) in the FIFO_CONTROL register (Address 0x28). The FIFO_WATERMARK bit is cleared automatically when enough samples are read from the FIFO, such that the number of samples remaining is lower than that specified.
If the number of FIFO samples is set to 0, the FIFO watermark interrupt is set. To avoid unexpectedly triggering this interrupt, the default value of the FIFO_SAMPLES register is 0x80.
## **FIFO Ready**
The FIFO_READY bit (Bit 1) in Register 0x2A and Register 0x2B is set when there is at least one valid sample available in the FIFO output buffer. This bit is cleared when no valid data is available in the FIFO.
## **Overrun**
The FIFO_OVERRUN bit (Bit 3) in the status register (Address 0x0B) is set when the FIFO has overrun or overflowed, such that new data replaces unread data. This may indicate a full FIFO that has not been emptied or a clocking error caused by a slow SPI transaction. If the FIFO is configured to oldest saved mode, an overrun event indicates that there is insufficient space available for a new sample.
The FIFO_OVERRUN bit is cleared automatically when the contents of the FIFO are read. Likewise, when the FIFO is disabled, the FIFO_OVERRUN bit is cleared.
## **USING SELF TEST**
The self test function, described in the Self Test section, is enabled via the ST bit in the SELF_TEST register, Address 0x2E. The recommended procedure for using the self test functionality is as follows:
1. Read acceleration data for the x-, y-, and z-axes.
2. Assert self test by setting the ST bit in the SELF_TEST register, Address 0x2E.
3. Wait 1/ODR for the output to settle to its new value.
4. Read acceleration data for the x-, y-, and z-axes. Compare to the values from Step 1, and convert the difference from LSB to m _g_ by multiplying by the scale factor. If the observed difference falls within the self test output change specification listed in Table 2, the device passes self test and is deemed operational.
5. Deassert self test by clearing the ST bit in the SELF_TEST register, Address 0x2E.
The self test output change specification is given for VS = 2.0 V. Because the electrostatic force is proportional to VS[2] and the scale factor of the device is ratiometric to VS, the output change varies with VS. The scale factors shown in Table 25 can be used to adjust the expected self test output limits for different supply voltages, VS.
Note that at higher voltages, self test deltas may exceed 1 _g_ . If the measurement is performed with one axis experiencing 1 _g_ due to gravity, and if the accelerometer is configured for a ±2 _g_ measurement range, the axis that is aligned with the field of gravity may reach 2 _g_ and its output clips (saturates to its fullscale value). To alleviate this, self test can be measured with the y-axis aligned with gravity (where the y-axis self test output change is negative), or with the accelerometer configured for a ±4 _g_ or ±8 _g_ measurement range.
Rev. A | Page 42 of 45
**ADXL363**
## **Data Sheet**
|**Data Sheet**||
|---|---|
|**Table 25. Self Test Output**<br>**Voltages, VS**|**Scale Factors for Different Supply**|
|**Supply Voltage, VS (V)**|**Self Test Output Scale Factor**|
|1.6<br>2.0<br>2.5<br>3.0<br>3.5|0.62<br>1.0<br>1.6<br>2.4<br>3.4|
## **OPERATION AT VOLTAGES OTHER THAN 2.0 V**
The ADXL363 is tested and specified at a supply voltage of VS = 2.0 V; however, it can be powered with a VS as high as 3.3 V nominal (3.5 V maximum) or as low as 1.8 V nominal (1.6 V minimum). Some performance parameters change as the supply voltage changes, including the supply current (see Figure 29), noise (see Table 9 and Table 10), offset, scale factor, and self test output change (see Table 25).
Figure 48 shows the potential effect on 0 _g_ offset at varying supply voltage. Data for this figure was calibrated to show 0 m _g_ offset at 2.0 V.
## **MECHANICAL CONSIDERATIONS FOR MOUNTING**
Mount the ADXL363 on the printed circuit board (PCB) in a location near a hard mounting point of the PCB to the case. Mounting the ADXL363 at an unsupported PCB location, as shown in Figure 49, can result in large, apparent measurement errors due to undampened PCB vibration. Locating the accelerometer near a hard mounting point ensures that any PCB vibration at the accelerometer is above the mechanical sensor resonant frequency of the accelerometer and, therefore, effectively invisible to the accelerometer. Multiple mounting points, near the sensor, and/or a thicker PCB also help to reduce the effect of system resonance on the performance of the sensor.
**==> picture [179 x 76] intentionally omitted <==**
**----- Start of picture text -----**<br>
ACCELEROMETERS<br>PCB<br>MOUNTING POINTS<br>Figure 49. Incorrectly Placed Accelerometers<br>11719-052<br>**----- End of picture text -----**<br>
**==> picture [216 x 169] intentionally omitted <==**
**----- Start of picture text -----**<br>
200<br>X-AXIS<br>Y-AXIS<br>Z-AXIS<br>150<br>100<br>50<br>0<br>–50<br>–100<br>1.5 2.0 2.5 3.0 3.5<br>VS (V)<br>) g<br> OFFSET (m<br> g<br>ZERO<br>11719-051<br>**----- End of picture text -----**<br>
_Figure 48. 0 g Offset vs. Supply Voltage_
Rev. A | Page 43 of 45
**ADXL363**
**Data Sheet**
## **AXES OF ACCELERATION SENSITIVITY**
**==> picture [192 x 152] intentionally omitted <==**
**----- Start of picture text -----**<br>
AZ<br>AY<br>AX 11719-053<br>**----- End of picture text -----**<br>
_Figure 50. Axes of Acceleration Sensitivity (Corresponding Output Increases when Accelerated Along the Sensitive Axis)_
**==> picture [338 x 239] intentionally omitted <==**
**----- Start of picture text -----**<br>
XOUT = 1 g<br>YOUT = 0 g<br>ZOUT = 0 g<br>TOP<br>XOUT = 0 g XOUT = 0 g<br>YOUT = –1 g TOP TOP YOUT = 1 g<br>ZOUT = 0 g ZOUT = 0 g<br>GRAVITY<br>TOP<br>XOUT = –1 g<br>YOUT = 0 g<br>ZOUT = 0 g<br>XOUT = 0 g XOUT = 0 g<br>YOUT = 0 g YOUT = 0 g<br>ZOUT = 1 g ZOUT = –1 g 11719-054<br>**----- End of picture text -----**<br>
_Figure 51. Output Response vs. Orientation to Gravity_
## **LAYOUT AND DESIGN RECOMMENDATIONS**
Figure 52 shows the recommended PCB land pattern.
**==> picture [162 x 155] intentionally omitted <==**
**----- Start of picture text -----**<br>
0.9250<br>0.3000<br>3.3500<br>0.5000<br>0.8000<br>3.5000<br>Figure 52. Recommended PCB Land Pattern<br>(Dimensions shown in millimeters)<br>11719-055<br>**----- End of picture text -----**<br>
Rev. A | Page 44 of 45
**ADXL363**
**Data Sheet**
## **OUTLINE DIMENSIONS**
**==> picture [289 x 159] intentionally omitted <==**
**----- Start of picture text -----**<br>
3.30<br>3.25 1.00<br>PIN 1 3.15 0.10 REF 0.25 × 0.35<br>CORNER REF REF<br>13 1<br>0.50 14 16<br>BSC<br>3.10<br>3.00<br>2.90<br>0.375REF 9 8 6 5 0.475REF × 0.25<br>TOP VIEW BOTTOM VIEW<br>0.3375<br>REF<br>1.14<br>1.06 END VIEW<br>1.00<br>SEATING<br>PLANE<br>PKG-003967 05-07-2015-C<br>**----- End of picture text -----**<br>
_Figure 53. 16-Terminal Land Grid Array [LGA] (CC-16-4) Dimensions shown in millimeters_
## **ORDERING GUIDE**
|**ORDERING GUIDE**|||||
|---|---|---|---|---|
|**Model1**|**Temperature Range **|**Package Description**|**Package Option**|**Quantity**|
|ADXL363BCCZ-RL<br>ADXL363BCCZ-RL7<br>EVAL-ADXL363Z<br>EVAL-ADXL363Z-MLP<br>EVAL-ADXL363Z-S|−40°C to +85°C<br>−40°C to +85°C|16-Terminal Land Grid Array [LGA]<br>16-Terminal Land Grid Array [LGA]<br>Breakout Board<br>Low Power Real-Time Evaluation System<br>Satellite Board for Evaluation System|CC-16-4<br>CC-16-4|5,000<br>1,500|
1 Z = RoHS Compliant Part.
**©2013–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11719-0-7/18(A)**
Rev. A | Page 45 of 45
Updated at April 28, 2026
Since its inception in 1965, Analog Devices has established itself as a global leader in the design and manufacturing of high-performance analog, mixed-signal, and digital signal processing (DSP) integrated circuits. The company is renowned for solving complex engineering challenges by providing critical technologies that seamlessly convert real-world phenomena into precise electrical signals for the industrial, automotive, communications, and consumer markets. Within its extensive portfolio, Analog Devices provides highly reliable clock, timing, and frequency management solutions, featuring a comprehensive array of precision timers, oscillators, and pulse generators. Complementing this core lineup is a robust offering of driver and interface ICs, particularly high-performance I/O expanders that enable seamless connectivity and streamline complex electronic system architectures. Beyond these foundational integrated circuits, Analog Devices leads the industry in sensor innovation, delivering advanced MEMS accelerometers and integrated MEMS modules designed for exceptional precision in motion sensing. To support complete hardware designs, the company's specialized offerings also encompass discrete bipolar transistors, sub-2.4GHz RF transceivers, temperature-compensated oscillators, and dedicated power management components such as DC/DC converters and LED driver ICs.
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