ADXL357BBEZ-RL7

MEMS Accelerometer, ± 10g, ± 20g, ± 40g, X, Y, Z, I2C, SPI, LCC, 14 Pins

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Manufacturer: ANALOG DEVICES
Product type: MEMS Accelerometers
SVHC: Lead (04-Feb-2026)
No. of Pins: 14Pins
Sensing Axis: X, Y, Z
Product Range: -
Qualification: -
Sensitivity Typ: 51200LSB/g, 25600LSB/g, 12800LSB/g
Output Interface: I2C, SPI
Supply Voltage Max: 3.6V
Supply Voltage Min: 2.25V
Sensor Case / Package: LCC
Operating Temperature Max: 125°C
Operating Temperature Min: -40°C
Sensing Range - Accelerometer: ± 10g, ± 20g, ± 40g
Delivery and price
Units per pack	500
Price	56.54 €
Current stock	500+
Lead time	30 days
Datasheet
Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

**==> picture [111 x 32] intentionally omitted <==**

## Low Noise, Low Drift, Low Power, 3-Axis MEMS Accelerometers 

## **FEATURES** 

## **FUNCTIONAL BLOCK DIAGRAMS** 

- 0 _g_ offset vs. temperature (all axes): 0.75 m _g_ /°C maximum 

- Ultralow noise spectral density (all axes): 75 µ _g_ /√Hz 

- Low power, VSUPPLY (LDO regulator enabled) 

- ADXL356 in measurement mode: 150 µA 

- ADXL357/ADXL357B in measurement mode: 200 µA 

- ADXL356/ADXL357/ADXL357B in standby mode: 21 µA 

- ADXL356 has user adjustable analog output bandwidth 

- ADXL357/ADXL357B digital output features 

- Digital SPI and limited I[2] C interfaces supported 

- 20-bit ADC 

- Data interpolation routine for synchronous sampling 

- Programmable high- and low-pass digital filters 

- Integrated temperature sensor 

- Voltage range options 

- VSUPPLY with internal regulators: 2.25 V to 3.6 V 

- V1P8ANA, V1P8DIG with internal LDO regulator bypassed: 1.8 V typical ± 10% 

- Operating temperature range: −40°C to +125°C 

- 14-terminal, 6 mm × 5.6 mm × 2.2 mm, LCC package 

**==> picture [212 x 117] intentionally omitted <==**

_**Figure 1. ADXL356**_ 

**==> picture [213 x 97] intentionally omitted <==**

_**Figure 2. ADXL357 and ADXL357B**_ 

## **APPLICATIONS** 

## **GENERAL DESCRIPTION** 

- Inertial measurement units (IMUs)/attitude and heading reference systems (AHRSs) 

- Platform stabilization systems 

- Structural health monitoring 

- Seismic imaging 

- Tilt sensing 

- Robotics 

- Condition monitoring 

The analog output ADXL356 and the digital outputs ADXL357 and ADXL357B are low noise density, low 0 _g_ offset drift, low power, 3-axis accelerometers with selectable measurement ranges. The ADXL356B supports the ±10 _g_ and ±20 _g_ ranges, the ADXL356C supports the ±10 _g_ and ±40 _g_ ranges, and the ADXL357 and ADXL357B support the ±10 _g_ , ±20 _g_ , and ±40 _g_ ranges. 

The ADXL356/ADXL357/ADXL357B[1] offer industry leading noise, minimal offset drift over temperature, and long-term stability, enabling precision applications with minimal calibration. 

The low drift, low noise, and low power ADXL357 and ADXL357B enable accurate tilt measurement. The ADXL357B is more robust/suitable for tilt sensing in high vibration environments. The low noise of the ADXL356 over higher frequencies is ideal for condition-based monitoring and other vibration sensing applications. 

The ADXL357 and ADXL357B multifunction pin names may be referenced only by their relevant function for either the serial peripheral interface (SPI) or limited I[2] C interface. 

> 1 Protected by U.S. Patents 8,472,270; 9,041,462; 8,665,627; 8,917,099; 6,892,576; 9,297,825; and 7,956,621. **Rev. C** 

Information furnished by Analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **TABLE OF CONTENTS** 

Features................................................................ 1 Applications........................................................... 1 Functional Block Diagrams....................................1 General Description...............................................1 Specifications........................................................ 4 ADXL356 (Analog Output)..................................4 ADXL357 (Digital Output)...................................5 ADXL357B (Digital Output)................................ 7 SPI Digital Interface Characteristics for the ADXL357 and ADXL357B................................ 9 I[2] C Digital Interface Characteristics for the ADXL357 and ADXL357B.............................. 10 Absolute Maximum Ratings.................................12 Thermal Resistance......................................... 12 Recommended Soldering Profile......................12 ESD Caution.....................................................12 Pin Configurations and Function Descriptions.....13 Typical Performance Characteristics...................15 ADXL356..........................................................15 ADXL357..........................................................19 ADXL357B........................................................23 Root Allan Variance (RAV) ADXL357/ ADXL357B Characteristics.............................27 Theory of Operation.............................................28 Applications Information...................................... 29 Analog Output.................................................. 29 Digital Output....................................................29 Axes of Acceleration Sensitivity....................... 30 Power Sequencing........................................... 30 Power Supply Description................................ 30 Overrange Protection....................................... 30 Mechanical Headroom vs. Frequency..............31 Self Test............................................................31 Filter................................................................. 31 Serial Communications........................................34 SPI Protocol..................................................... 34 SPI Bus Sharing...............................................34 I[2] C Protocol......................................................35 Reading Acceleration or Temperature Data From the Interface..........................................35 FIFO.................................................................... 37 

Interrupts............................................................. 38 DATA_RDY.......................................................38 DRDY Pin.........................................................38 FIFO_FULL...................................................... 38 FIFO_OVR....................................................... 38 Activity..............................................................38 External Synchronization and Interpolation......38 ADXL357/ADXL357B Register Map....................41 Register Definitions............................................. 42 Analog Devices ID Register............................. 42 Analog Devices MEMS ID Register..................42 Device ID Register........................................... 42 Product Revision ID Register........................... 42 Status Register.................................................42 FIFO Entries Register.......................................43 Temperature Data Registers............................ 43 X-Axis Data Registers...................................... 43 Y-Axis Data Registers...................................... 44 Z-Axis Data Registers...................................... 44 FIFO Access Register...................................... 45 X-Axis Offset Trim Registers............................ 45 Y-Axis Offset Trim Registers............................ 45 Z-Axis Offset Trim Registers............................ 46 Activity Enable Register................................... 46 Activity Threshold Registers.............................46 Activity Count Register.....................................47 Filter Settings Register.....................................47 FIFO Samples Register....................................47 Interrupt Pin (INTx) Function Map Register......48 Data Synchronization....................................... 48 I[2] C Speed, Interrupt Polarity, and Range Register..........................................................48 Power Control Register.................................... 49 Self Test Register............................................. 49 Reset Register..................................................49 PCB Footprint Pattern......................................... 50 Outline Dimensions............................................. 51 Ordering Guide.................................................51 Output Mode, Measurement Range, and Specified Voltage Options.............................. 51 Evaluation Boards............................................ 52 

## **REVISION HISTORY** 

## **9/2024—Rev. B to Rev. C** 

Changed Master to Main and Slave to Subordinate (Throughout).................................................................. 1 Changes to General Description Section.........................................................................................................1 Changes to Velocity Random Walk Parameter, Table 3...................................................................................7 Changes to Figure 82 and Figure 83............................................................................................................. 29 

**Rev. C | 2 of 52** 

**analog.com** 

Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **TABLE OF CONTENTS** 

Changes to Mechanical Headroom vs. Frequency Section and Figure 87....................................................31 Change to EXT_SYNC = 00, EXT_CLK = 0—No External Synchronization or Interpolation Section........... 39 Changes to Table 48......................................................................................................................................48 Change to Address: 0x2E, Reset: 0x00, Name: SELF_TEST Section..........................................................49 **3/2024—Rev. A to Rev. B** Added ADXL357B (Universal)......................................................................................................................... 1 Changes to Features Section.......................................................................................................................... 1 Changes to General Description Section.........................................................................................................1 Changed Analog Output for the ADXL356 Section to ADXL356 (Analog Output) Section..............................4 Changes to Resonant Frequency Parameter, Quality Factor Parameter, and Standards Deviation Parameter, Table 1.........................................................................................................................................4 Changed Digital Output for the ADXL357 Section to ADXL357 (Digital Output) Section................................ 5 Changes to Resonant Frequency Parameter, Quality Factor Parameter, and Standards Deviation Parameter, Table 2.........................................................................................................................................5 Added Note 1, Table 2..................................................................................................................................... 5 Added ADXL357B (Digital Output) Section and Table 3; Renumbered Sequentially.......................................7 Changes to Table 6........................................................................................................................................12 Changes to Typical Performance Characteristics Section.............................................................................15 Added ADXL356 Section............................................................................................................................... 15 Moved Figure 8 to Figure 30..........................................................................................................................15 Added ADXL357 Section............................................................................................................................... 19 Moved Figure 31 to Figure 54........................................................................................................................19 Added ADXL357B Section and Figure 55 to Figure 78; Renumbered Sequentially......................................23 Changes to Figure 79 Caption to Figure 81 Caption..................................................................................... 27 Changes to Power Sequencing Section........................................................................................................ 30 Changes to Overrange Protection Section.................................................................................................... 30 Added Figure 85............................................................................................................................................ 31 Added Mechanical Headroom vs. Frequency Section and Figure 86 to Figure 87 .......................................31 Changes to I[2] C PROTOCOL Section ........................................................................................................... 35 Changes to Table 16......................................................................................................................................41 Changed Address: 0x02, Reset: 0xED, Name: PARTID Section to Address: 0x02, Reset: 0xED/0xE9, Name: PARTID Section................................................................................................................................42 Changes to Table 19......................................................................................................................................42 Changes to Table 20......................................................................................................................................42 Changes to Address: 0x2F, Reset: 0x00, Name: Reset Section....................................................................49 Changes to Ordering Guide...........................................................................................................................51 Added Output Mode, Measurement Range, and Specified Voltage Options.................................................51 Changes to Evaluation Boards...................................................................................................................... 52 

**Rev. C | 3 of 52** 

**analog.com** 

Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **SPECIFICATIONS** 

## **ADXL356 (ANALOG OUTPUT)** 

TA = 25°C, VSUPPLY = 3.3 V, x-axis acceleration and y-axis acceleration = 0 _g_ , z-axis acceleration = 1 _g_ , and full-scale range = ±10 _g_ , unless otherwise noted. 

_**Table 1.**_ 

|**_Table 1._**|**_Table 1._**|**_Table 1._**|**_Table 1._**|
|---|---|---|---|
|**Parameter**<br>**Test Conditions/Comments**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**||||
|SENSOR INPUT<br>Output Full-Scale Range (FSR)<br>Resonant Frequency1<br>Quality Factor<br>Nonlinearity<br>Cross Axis Sensitivity|Each axis<br>ADXL356B supports two ranges<br>ADXL356C supports two ranges<br>X-axis and y-axis<br>Z-axis<br>X-axis<br>Y-axis<br>Z-axis<br>±10_g_<br>±40_g_|±10, ±20<br>±10, ±40<br>5.5<br>5.1<br>17<br>14<br>4<br>0.1<br>1.3<br>1|_g_<br>_g_<br>kHz<br>kHz<br>% FSR<br>% FSR<br>%|
|SENSITIVITY<br>Sensitivity at XOUT, YOUT, ZOUT<br>Sensitivity Change Due to Temperature<br>Repeatability2|Ratiometric to V1P8ANA<br>±10_g_<br>±20_g_<br>±40_g_<br>TA= −40°C to +125°C<br>X-axis and y-axis<br>Z-axis|73.6<br>80<br>86.4<br>36.8<br>40<br>43.2<br>18.4<br>20<br>21.6<br>±0.01<br>0.1<br>0.2|mV/_g_<br>mV/_g_<br>mV/_g_<br>%/°C<br>%<br>%|
|0_g_OFFSET<br>0_g_Output for XOUT, YOUT, ZOUT<br>0_g_Offset vs. Temperature (X-Axis, Y-Axis, and<br>Z-Axis)3<br>Repeatability2<br>Vibration Rectification Error (VRE)4|Each axis, ±10_g_<br>Referred to V1P8ANA/2<br>TA= −40°C to +125°C<br>X-axis and y-axis<br>Z-axis<br>Offset due to 7.5_g_rms vibration, ±10_g_range, in a 1<br>_g_orientation|−375<br>±125<br>+375<br>−0.75<br>±0.2<br>+0.75<br>±4.25<br>±5<br><0.1|m_g_<br>m_g_/°C<br>m_g_<br>m_g_<br>_g_|
|NOISE<br>Spectral Density5<br>X-Axis, Y-Axis, and Z-Axis<br>Velocity Random Walk<br>X-Axis and Y-Axis<br>Z-Axis|±10_g_<br>±40_g_<br>±10_g_|75<br>110<br>38.2<br>26.5|µ_g_/√Hz<br>µ_g_/√Hz<br>mm/sec/√hr<br>mm/sec/√hr|
|BANDWIDTH|−3 dB, overall transfer function6|2.4|kHz|
|SELF TEST<br>Output Change<br>Z-Axis|±10_g_range7|0.5<br>1.25<br>3.0|_g_|
|POWER SUPPLY<br>Voltage Range<br>VSUPPLY<br>8<br>VDDIO<br>V1P8ANA, V1P8DIG|Internal low dropout (LDO) regulator bypassed,<br>VSUPPLY= 0 V|2.25<br>2.5<br>3.6<br>V1P8DIG<br>2.5<br>3.6<br>1.62<br>1.8<br>1.98|V<br>V<br>V|



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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **SPECIFICATIONS** 

_**Table 1. (Continued)**_ 

|**_Table 1.(Continued)_**|**_Table 1.(Continued)_**|**_Table 1.(Continued)_**|**_Table 1.(Continued)_**|
|---|---|---|---|
|**Parameter**<br>**Test Conditions/Comments**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**||||
|Current<br>Measurement Mode<br>VSUPPLY<br>V1P8ANA<br>V1P8DIG<br>Standby Mode<br>VSUPPLY<br>V1P8ANA<br>V1P8DIG<br>Turn On Time9|LDO regulator enabled<br>LDO regulator disabled<br>LDO regulator disabled<br>LDO regulator enabled<br>LDO regulator disabled<br>LDO regulator disabled<br>10_g_range<br>Power-off to standby|150<br>138<br>12<br>21<br>7<br>10<br>10<br><10|µA<br>µA<br>µA<br>µA<br>µA<br>µA<br>ms<br>ms|
|OUTPUT AMPLIFIER<br>Swing<br>Output Series Resistance|XOUT, YOUT, ZOUT, and TEMP pins<br>No load|0.03<br>V1P8ANA− 0.03<br>32|V<br>kΩ|
|TEMPERATURE SENSOR<br>Output at 25°C<br>Standard Deviation<br>Scale Factor||967<br>6<br>3.0|mV<br>mV<br>mV/°C|
|TEMPERATURE<br>Operating Temperature Range||−40<br>+125|°C|



- 1 The resonant frequency is a sensor characteristic. 

> 2 Repeatability is predicted for a 10 year life and includes shifts due to the high temperature operating life (HTOL) (TA = 150°C, VSUPPLY = 3.6 V, and 1000 hours), temperature cycling (−55°C to +125°C and 1000 cycles), velocity random walk, broadband noise, and temperature hysteresis. Repeatability in relation to time follows the square root law. For example, to obtain offset repeatability of the x-axis for 2.5 years, use the following equation: ±4.25 m _g_ × √(2.5 years/10 years) = ±2.125 m _g_ . 

- 3 The temperature change is −40°C to +25°C, or +25°C to +125°C. 

- 4 The VRE measurement is the shift in dc offset while the device is subject to 7.5 _g_ rms of random vibration from 50 Hz to 2 kHz. The device under test (DUT) is configured for the ±10 _g_ range and an output data rate of 4 kHz. The VRE scales with the range setting. 

- 5 Based on characterization. 

- 6 Overall transfer function includes the sensor mechanical response and all other filters on the signal chain. 

- 7 ±10 _g_ indicates a test condition. The self test result converted to the acceleration value is independent of the selected range. 

- 8 When V1P8ANA and V1P8DIG are generated internally, VSUPPLY is valid. To disable the LDO regulator and drive V1P8ANA and V1P8DIG externally, connect VSUPPLY to VSS. 

- 9 Standby to measurement mode. This specification is valid when the output is within 5 m _g_ of the final value. 

## **ADXL357 (DIGITAL OUTPUT)** 

TA = 25°C, VSUPPLY = 3.3 V, x-axis acceleration and y-axis acceleration = 0 _g_ , z-axis acceleration = 1 _g_ , full-scale range = ±10 _g_ , and output data rate (ODR) = 500 Hz, unless otherwise noted. Note that multifunction pin names may be referenced only by their relevant function. 

_**Table 2.**_ 

|**_Table 2._**|**_Table 2._**|**_Table 2._**|**_Table 2._**|
|---|---|---|---|
|**Parameter**<br>**Test Conditions/Comments**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**||||
|SENSOR INPUT<br>Output Full-Scale Range (FSR)<br>Resonant Frequency1<br>Quality Factor|Each axis<br>User selectable, supports three ranges<br>X-axis and y-axis<br>Z-axis<br>X-axis<br>Y-axis|±10<br>±20<br>±40<br>5.5<br>5.1<br>18<br>15|_g_<br>_g_<br>_g_<br>kHz<br>kHz|



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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **SPECIFICATIONS** 

_**Table 2. (Continued)**_ 

|**_Table 2.(Continued)_**|**_Table 2.(Continued)_**|**_Table 2.(Continued)_**|**_Table 2.(Continued)_**|
|---|---|---|---|
|**Parameter**<br>**Test Conditions/Comments**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**||||
|Nonlinearity<br>Cross Axis Sensitivity|Z-axis<br>±10_g_<br>±40_g_|4<br>0.1<br>1.3<br>1|% FSR<br>% FSR<br>%|
|SENSITIVITY2<br>X-Axis, Y-Axis, and Z-Axis Sensitivity<br>X-Axis, Y-Axis, and Z-Axis Scale Factor<br>Sensitivity Change due to Temperature<br>Repeatability3|Each axis<br>±10_g_<br>±20_g_<br>±40_g_<br>±10_g_<br>±20_g_<br>±40_g_<br>TA= −40°C to +125°C<br>X-axis and y-axis<br>Z-axis|47,104<br>51,200<br>55,296<br>23,552<br>25,600<br>27,648<br>11,776<br>12,800<br>13,824<br>19.5<br>39<br>78<br>±0.01<br>0.1<br>0.2|LSB/_g_<br>LSB/_g_<br>LSB/_g_<br>µ_g/_LSB<br>µ_g/_LSB<br>µ_g/_LSB<br>%/°C<br>%<br>%|
|0_g_OFFSET<br>X-Axis, Y-Axis, and Z-Axis 0_g_Output<br>0_g_Offset vs. Temperature (X-Axis, Y-Axis, and Z-Axis)4<br>Repeatability3<br>VRE5|Each axis, ±10_g_<br>TA= −40°C to +125°C<br>X-axis and y-axis<br>Z-axis<br>Offset due to 7.5_g_rms vibration, ±10_g_range, in a 1_g_<br>orientation|−375<br>±125<br>+375<br>−0.75<br>±0.20<br>+0.75<br>±4.25<br>±5<br><0.1|m_g_<br>m_g_/°C<br>m_g_<br>m_g_<br>_g_|
|NOISE<br>Spectral Density6<br>X-Axis, Y-Axis, and Z-Axis<br>Velocity Random Walk<br>X-Axis and Y-Axis<br>Z-Axis|±10_g_<br>±40_g_<br>±10_g_|75<br>90<br>38.2<br>26.5|µ_g_/√Hz<br>µ_g_/√Hz<br>mm/sec/√hr<br>mm/sec/√hr|
|BANDWIDTH AND OUTPUT DATA RATE<br>Analog-to-Digital Converter (ADC) Resolution<br>Low-Pass Filter Passband Frequency<br>High-Pass Filter Passband Frequency When Enabled<br>(Disabled by Default)|User programmable, Register 0x28<br>User programmable, Register 0x28 for 4 kHz ODR|20<br>0.977<br>1000<br>0.0095<br>10|Bits<br>Hz<br>Hz|
|SELF TEST<br>Output Change<br>Z-Axis|±10_g_range7|0.5<br>1.25<br>3.0|_g_|
|POWER SUPPLY<br>Voltage Range<br>VSUPPLYOperating8<br>VDDIO<br>V1P8ANAand V1P8DIG<br>Current<br>Measurement Mode<br>VSUPPLY<br>V1P8ANA<br>V1P8DIG<br>Standby Mode<br>VSUPPLY<br>V1P8ANA|Internal LDO regulator bypassed, VSUPPLY= 0 V<br>LDO regulator enabled<br>LDO regulator disabled<br>LDO regulator disabled<br>LDO regulator enabled<br>LDO regulator disabled|2.25<br>2.5<br>3.6<br>V1P8DIG<br>2.5<br>3.6<br>1.62<br>1.8<br>1.98<br>200<br>160<br>35.5<br>21<br>7|V<br>V<br>V<br>µA<br>µA<br>µA<br>µA<br>µA|



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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **SPECIFICATIONS** 

_**Table 2. (Continued)**_ 

|**_Table 2.(Continued)_**|**_Table 2.(Continued)_**|**_Table 2.(Continued)_**|**_Table 2.(Continued)_**|
|---|---|---|---|
|**Parameter**<br>**Test Conditions/Comments**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**||||
|V1P8DIG<br>Turn On Time9|LDO regulator disabled<br>±10_g_range<br>Power-off to standby|10<br><10<br><10|µA<br>ms<br>ms|
|TEMPERATURE SENSOR<br>Output at 25°C<br>Standard Deviation<br>Scale Factor||1885<br>28.5<br>−9.05|LSB<br>LSB<br>LSB/°C|
|TEMPERATURE<br>Operating Temperature Range||−40<br>+125|°C|



- 1 The resonant frequency is a sensor characteristic. 

- 2 Characterized but not 100% tested. 

- 3 Repeatability is predicted for a 10 year life and includes shifts due to the HTOL (TA = 150°C, VSUPPLY = 3.6 V, and 1000 hours), temperature cycling (−55°C to +125°C and 1000 cycles), velocity random walk, broadband noise, and temperature hysteresis. Repeatability in relation to time follows the square root law. For example, to obtain offset repeatability of the x-axis for 2.5 years, use the following equation: ±4.25 m _g_ × √(2.5 years/10 years) = ±2.125 m _g_ . 

- 4 The temperature change is −40°C to +25°C or +25°C to +125°C. 

- 5 The VRE measurement is the shift in dc offset while the device is subject to 7.5 _g_ rms random vibration from 50 Hz to 2 kHz. The DUT is configured for the ±10 _g_ range and an output data rate of 4 kHz. The VRE scales with the range setting. 

- 6 Based on characterization. 

- 7 ±10 _g_ indicates a test condition. The self test result converted to the acceleration value is independent of the selected range. 

- 8 When V1P8ANA and V1P8DIG are generated internally, VSUPPLY is valid. To disable the LDO regulator and drive V1P8ANA and V1P8DIG externally, connect VSUPPLY to VSS. 

- 9 Standby to measurement mode. This specification is valid when the output is within 1 m _g_ of final value. 

## **ADXL357B (DIGITAL OUTPUT)** 

TA = 25°C, VSUPPLY = 3.3 V, x-axis acceleration and y-axis acceleration = 0 _g_ , z-axis acceleration = 1 _g_ , full-scale range = ±10 _g_ , and ODR = 500 Hz, unless otherwise noted. Note that multifunction pin names may be referenced only by their relevant function. 

_**Table 3.**_ 

|**_Table 3._**|**_Table 3._**|**_Table 3._**|**_Table 3._**|
|---|---|---|---|
|**Parameter**<br>**Test Conditions/Comments**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**||||
|SENSOR INPUT<br>Output Full-Scale Range (FSR)<br>Resonant Frequency1<br>Quality Factor (Q)<br>Nonlinearity<br>Cross Axis Sensitivity|Each axis<br>User selectable, supports three ranges<br>X-axis and y-axis<br>Z-axis<br>X-axis and y-axis<br>Z-axis<br>±10_g_<br>±40_g_|±10<br>±20<br>±40<br>5.3<br>4.8<br>1.9<br>0.7<br>0.1<br>1.6<br>1|_g_<br>_g_<br>_g_<br>kHz<br>KHz<br>%FSR<br>%FSR<br>%|
|SENSITIVITY2<br>X-Axis, Y-Axis, and Z-Axis Sensitivity<br>X-Axis, Y-Axis, and Z-Axis Scale Factor<br>Sensitivity Change due to Temperature|Each axis<br>±10_g_<br>±20_g_<br>±40_g_<br>±10_g_<br>±20_g_<br>±40_g_<br>TA= −40°C to +125°C|47,104<br>51,200<br>55,296<br>23,552<br>25,600<br>27,648<br>11,520<br>12,800<br>14,080<br>19.5<br>39<br>78<br>±0.01|LSB/_g_<br>LSB/_g_<br>LSB/_g_<br>µ_g/_LSB<br>µ_g/_LSB<br>µ_g/_LSB<br>%/°C|



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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **SPECIFICATIONS** 

_**Table 3. (Continued)**_ 

|**_Table 3.(Continued)_**|**_Table 3.(Continued)_**|**_Table 3.(Continued)_**|**_Table 3.(Continued)_**|
|---|---|---|---|
|**Parameter**<br>**Test Conditions/Comments**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**||||
|Repeatability3|X-axis and y-axis<br>Z-axis|0.1<br>0.2|%<br>%|
|0_g_OFFSET<br>X-Axis, Y-Axis, and Z-Axis 0_g_Output<br>0_g_Offset vs. Temperature (X-Axis, Y-Axis, and Z-Axis)4<br>Repeatability3<br>VRE5|Each axis, ±10_g_<br>TA= −40°C to +125°C<br>X-axis and y-axis<br>Z-axis<br>Offset due to 12.5_g_rms vibration, ±40_g_range, in a 1_g_<br>orientation|−375<br>±125<br>+375<br>−0.75<br>±0.20<br>+0.75<br>±4.25<br>±5<br><0.1|m_g_<br>m_g_/°C<br>m_g_<br>m_g_<br>_g_|
|NOISE<br>Spectral Density6<br>X-Axis, Y-Axis, and Z-Axis<br>Velocity Random Walk<br>X-Axis and Y-Axis<br>Z-Axis|±10_g_<br>±40_g_<br>±40_g_|75<br>85<br>38.2<br>26.5|µ_g_/√Hz<br>µ_g_/√Hz<br>mm/sec/√hr<br>mm/sec/√hr|
|BANDWIDTH AND OUTPUT DATA RATE<br>Analog-to-Digital Converter (ADC) Resolution<br>Low-Pass Filter Passband Frequency<br>High-Pass Filter Passband Frequency when Enabled<br>(Disabled by Default)|User programmable, Register 0x28<br>User programmable, Register 0x28 for 4 kHz ODR|20<br>1.1<br>942<br>0.0095<br>10|Bits<br>Hz<br>Hz|
|SELF TEST<br>Output Change<br>X-axis and Y-axis<br>Z-Axis|±40_g_range7|0.18<br>0.33<br>0.48<br>0.875<br>1.25<br>1.825|_g_<br>_g_|
|POWER SUPPLY<br>Voltage Range<br>VSUPPLYOperating8<br>VDDIO<br>V1P8ANAand V1P8DIG<br>Current<br>Measurement Mode<br>VSUPPLY<br>V1P8ANA<br>V1P8DIG<br>Standby Mode<br>VSUPPLY<br>V1P8ANA<br>V1P8DIG<br>Turn On Time9|Internal LDO regulator bypassed, VSUPPLY= 0 V<br>LDO regulator enabled<br>LDO regulator disabled<br>LDO regulator disabled<br>LDO regulator enabled<br>LDO regulator disabled<br>LDO regulator disabled<br>±10_g_range<br>Power-off to standby|2.25<br>3.3<br>3.6<br>V1P8DIG<br>3.3<br>3.6<br>1.62<br>1.8<br>1.98<br>200<br>160<br>35.5<br>21<br>7<br>10<br><10<br><10|V<br>V<br>V<br>µA<br>µA<br>µA<br>µA<br>µA<br>µA<br>ms<br>ms|
|TEMPERATURE SENSOR<br>Output at 25°C<br>Standard Deviation<br>Scale Factor||1829<br>24.3<br>−9.05|LSB<br>LSB<br>LSB/°C|
|TEMPERATURE<br>Operating Temperature Range||−40<br>+125|°C|



**Rev. C | 8 of 52** 

**analog.com** 

Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **SPECIFICATIONS** 

- 1 The resonant frequency is a sensor characteristic. 

- 2 Characterized but not 100% tested. 

- 3 Repeatability is predicted for a 10 year life and includes shifts due to the HTOL (TA = 150°C, VSUPPLY = 3.6 V, and 1000 hours), temperature cycling (−55°C to +125°C and 1000 cycles), velocity random walk, broadband noise, and temperature hysteresis. Repeatability in relation to time follows the square root law. For example, to obtain offset repeatability of the x-axis for 2.5 years, use the following equation: ±4.25 m _g_ × √(2.5 years/10 years) = ±2.125 m _g_ . 

- 4 The temperature change is −40°C to +25°C or +25°C to +125°C. 

- 5 The VRE measurement is the shift in dc offset while the device is subject to 12.5 _g_ rms random vibration from 50 Hz to 2 kHz. The DUT is configured for the ±40 _g_ range and an output data rate of 4 kHz. The VRE scales with the range setting. 

- 6 Based on characterization. 

- 7 ±40 _g_ indicates a test condition. The self test result converted to the acceleration value is independent of the selected range. 

- 8 When V1P8ANA and V1P8DIG are generated internally, VSUPPLY is valid. To disable the LDO regulator and drive V1P8ANA and V1P8DIG externally, connect VSUPPLY to VSS. 

- 9 Standby to measurement mode. This specification is valid when the output is within 1 m _g_ of final value. 

## **SPI DIGITAL INTERFACE CHARACTERISTICS FOR THE ADXL357 AND ADXL357B** 

Note that multifunction pin names may be referenced by their relevant function only. 

_**Table 4.**_ 

|**_Table 4._**|**_Table 4._**|**_Table 4._**|**_Table 4._**|**_Table 4._**|
|---|---|---|---|---|
|**Parameter**<br>**Symbol**<br>**Test Conditions/Comments**<br>**Min**<br>**Typ**<br>**Max**<br>**Unit**|||||
|DC INPUT LEVELS<br>Input Voltage<br>Low Level<br>High Level<br>Input Current<br>Low Level<br>High Level|VIL<br>VIH<br>IIL<br>IIH|Input voltage (VIN) = 0 V<br>VIN= VDDIO|0.3 × VDDIO<br>0.7 × VDDIO<br>−0.2<br>0.2|V<br>V<br>µA<br>µA|
|DC OUTPUT LEVELS<br>Output Voltage<br>Low Level<br>High Level<br>Output Current<br>Low Level<br>High Level|VOL<br>VOH<br>IOL<br>IOH|IOL= IOL, MIN<br>IOH= IOH, MAX<br>VOL= VOL, MAX<br>VOH= VOH, MIN|0.2 × VDDIO<br>0.8 × VDDIO<br>−10<br>4|V<br>V<br>mA<br>mA|
|AC INPUT LEVELS<br>SCLK Frequency<br>SCLK High Time<br>SCLK Low Time<br>CS Setup Time<br>CS Hold Time<br>CS Disable Time<br>Rising SCLK Setup Time<br>MOSI Setup Time<br>MOSI Hold Time|tHIGH<br>tLOW<br>tCSS<br>tCSH<br>tCSD<br>tSCLKS<br>tSU<br>tHD||0.1<br>10<br>40<br>40<br>20<br>20<br>40<br>20<br>20<br>20|MHz<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns|
|AC OUTPUT LEVELS<br>Propagation Delay<br>Enable MISO Time<br>Disable MISO Time|tP<br>tEN<br>tDIS|Load capacitance (CLOAD) = 30 pF|30<br>30<br>20|ns<br>ns<br>ns|



**Rev. C | 9 of 52** 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **SPECIFICATIONS** 

_**Figure 3. SPI Interface Timing Diagram**_ 

## **I[2] C DIGITAL INTERFACE CHARACTERISTICS FOR THE ADXL357 AND ADXL357B** 

Note that multifunction pin names may be referenced only by their relevant function. 

_**Table 5.**_ 

|**_Table 5._**|**_Table 5._**|**_Table 5._**||||
|---|---|---|---|---|---|
|**Parameter**<br>**Symbol**<br>**Test Conditions/**<br>**Comments**|||**I2C_HS = 0 (Fast Mode)**<br>**I2C_HS = 1 (High Speed Mode)**<br>**Unit**<br>**Min**<br>**Typ**<br>**Max**<br>**Min**<br>**Typ**<br>**Max**|||
|DC INPUT LEVELS<br>Input Voltage<br>Low Level<br>High Level<br>Hysteresis of Schmitt<br>Triggered Inputs<br>Input Current|VIL<br>VIH<br>VHYS<br>IIL|0.1 × VDDIO< VIN< 0.9 ×<br>VDDIO|0.3 × VDDIO<br>0.7 × VDDIO<br>0.05 × VDDIO<br>−10<br>+10|0.3 × VDDIO<br>0.7 × VDDIO<br>0.1 × VDDIO|V<br>V<br>V<br>µA|
|DC OUTPUT LEVELS<br>Output Voltage<br>Low Level<br>Output Current<br>Low Level|VOL1<br>VOL2<br>IOL|IOL= 3 mA<br>VDDIO> 2 V<br>VDDIO≤ 2 V<br>VOL= 0.4 V<br>VOL= 0.6 V|0.4<br>0.2 × VDDIO<br>20<br>6|0.4<br>0.2 × VDDIO<br>20<br>6|V<br>V<br>mA<br>mA|
|AC INPUT LEVELS<br>SCL Frequency<br>SCL High Time<br>SCL Low Time<br>Start Setup Time<br>Start Hold Time<br>SDA Setup Time<br>SDA Hold Time<br>Stop Setup Time<br>Bus Free Time<br>SCL Input Rise Time<br>SCL Input Fall Time<br>SDA Input Rise Time<br>SDA Input Fall Time<br>Width of Spikes to Suppress|tHIGH<br>tLOW<br>tSUSTA<br>tHDSTA<br>tSUDAT<br>tHDDAT<br>tSUSTO<br>tBUF<br>tRCL<br>tFCL<br>tRDA<br>tFDA<br>tSP|Not shown inFigure 4|0<br>1<br>260<br>500<br>260<br>260<br>50<br>0<br>260<br>500<br>120<br>120<br>120<br>120<br>50|0<br>3.4<br>60<br>160<br>160<br>160<br>10<br>0<br>160<br>80<br>80<br>160<br>160<br>10|MHz<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns|
|AC OUTPUT LEVELS<br>Propagation Delay<br>Data<br>Acknowledge|tVDDAT<br>tVDACK|CLOAD= 500 pF|97<br>450<br>450|27<br>135|ns<br>ns|



**Rev. C | 10 of 52** 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **SPECIFICATIONS** 

_**Table 5. (Continued)**_ 

|**_Table 5.(Continued)_**|**_Table 5.(Continued)_**|**_Table 5.(Continued)_**||||
|---|---|---|---|---|---|
|**Parameter**<br>**Symbol**<br>**Test Conditions/**<br>**Comments**|||**I2C_HS = 0 (Fast Mode)**<br>**I2C_HS = 1 (High Speed Mode)**<br>**Unit**<br>**Min**<br>**Typ**<br>**Max**<br>**Min**<br>**Typ**<br>**Max**|||
|Output Fall Time|tF|Not shown inFigure 4|20 × (VDDIO/5.5)<br>120||ns|



_**Figure 4. I[2] C Interface Timing Diagram**_ 

**Rev. C | 11 of 52** 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **ABSOLUTE MAXIMUM RATINGS** 

_**Table 6.**_ 

|**_Table 6._**|**_Table 6._**|
|---|---|
|**Parameter**<br>**Rating**||
|Half Sine-Wave Shock (Any Axis)<br>Unpowered<br>Powered<br>Vibration (Any Axis)<br>VSUPPLY, VDDIO<br>V1P8ANA, V1P8DIGConfigured as Inputs<br>ADXL356<br>Digital Inputs (RANGE, ST1, ST2,<br>STBY )<br>Analog Outputs (XOUT, YOUT, ZOUT, TEMP)<br>ADXL357/ADXL357B<br>Digital Pins (<br>CS , SCL, SCLK/VSSIO, MOSI/<br>SDA, MISO/ASEL, INT1, INT2, DRDY)<br>Operating Temperature Range<br>Storage Temperature Range|10,000_g_, 0.1 ms shock<br>duration<br>10,000_g_, 0.1 ms shock<br>duration<br>Per MIL-STD-883 Method<br>2007, Test Condition C1<br>5.4 V<br>1.98 V<br>−0.3 V to VDDIO+ 0.3 V<br>−0.3 V to V1P8ANA+ 0.3 V<br>−0.3 V to VDDIO+ 0.3 V<br>−40°C to +125°C<br>−55°C to +150°C|



> 1 Sine-wave excitation swept logarithmically from 20 Hz to 2 kHz, 70 _g_ peak amplitude. Sweep duration of 4 minutes. Repeat sweep four times per axis. 

Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. 

## **THERMAL RESISTANCE** 

Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. 

θJA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. ψJB is the junction to board thermal resistance. 

_**Table 7. Thermal Resistance**_ 

|**_Table 7. Thermal Resistance_**|**_Table 7. Thermal Resistance_**|**_Table 7. Thermal Resistance_**|**_Table 7. Thermal Resistance_**|
|---|---|---|---|
|**Package Type**<br>**θJA**<br>**ψJB**<br>**Unit**||||
|E-14-11|42|17.6|°C/W|



> 1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal test board with four thermal vias. See JEDEC JESD51. 

## **RECOMMENDED SOLDERING PROFILE** 

Figure 5 and Table 8 provide details about the recommended soldering profile. 

**==> picture [205 x 115] intentionally omitted <==**

_**Figure 5. Recommended Soldering Profile**_ 

_**Table 8. Recommended Soldering Profile**_ 

|**Profile Feature**|**Condition**|**Condition**|
|---|---|---|
||**Sn63/Pb37**<br>**Pb-Free**||
|Average Ramp Rate from Liquid<br>Temperature (TL) to Peak Temperature<br>(TP)<br>Preheat<br>Minimum Temperature (TSMIN)<br>Maximum Temperature (TSMAX)<br>Time from TSMINto TSMAX(tS)<br>TSMAXto TLRamp-Up Rate<br>Liquid Temperature (TL)<br>Time Maintained Above TL(tL)<br>Peak Temperature (TP)<br>Time of Actual TP− 5°C (tP)<br>Ramp-Down Rate<br>Time from 25°C to Peak Temperature<br>(t25°C TO PEAK)|3°C/sec<br>maximum<br>100°C<br>150°C<br>60 sec to 120<br>sec<br>3°C/sec<br>maximum<br>183°C<br>60 sec to 150<br>sec<br>240°C + 0°C/<br>−5°C<br>10 sec to 30 sec<br>6°C/sec<br>maximum<br>6 minutes<br>maximum|3°C/sec maximum<br>150°C<br>200°C<br>60 sec to 180 sec<br>3°C/sec maximum<br>217°C<br>60 sec to 150 sec<br>260°C + 0°C/−5°C<br>20 sec to 40 sec<br>6°C/sec maximum<br>8 minutes<br>maximum|



## **ESD CAUTION** 

**ESD (electrostatic discharge) sensitive device** . Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. 

**Rev. C | 12 of 52** 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS** 

**==> picture [77 x 80] intentionally omitted <==**

_**Figure 6. ADXL356 Pin Configuration**_ 

_**Table 9. ADXL356 Pin Function Descriptions**_ 

|**_Table 9. ADXL356 Pin Function Descriptions_**|**_Table 9. ADXL356 Pin Function Descriptions_**|**_Table 9. ADXL356 Pin Function Descriptions_**|
|---|---|---|
|**Pin No.**<br>**Mnemonic**<br>**Description**|||
|1<br>2<br>3<br>4<br>5<br>6<br>7<br>8<br>9<br>10<br>11<br>12<br>13<br>14|RANGE<br>ST1<br>ST2<br>TEMP<br>VDDIO<br>VSSIO<br>STBY<br>V1P8DIG<br>VSS<br>V1P8ANA<br>VSUPPLY<br>XOUT<br>YOUT<br>ZOUT|Range Selection Pin. Set this pin to ground to select the ±10_g_range, or set this pin to VDDIOto select the ±20_g_or ±40_g_range. This<br>pin is model dependent (see theOrdering Guidesection).<br>Self Test Pin 1. This pin enables self test mode. This pin must be forced low when not in self test mode.<br>Self Test Pin 2. This pin activates electromechanical self test actuation. This pin must be forced low when not in self test mode.<br>Temperature Sensor Output.<br>Digital Interface Supply Voltage.<br>Digital Ground.<br>Standby or Measurement Mode Selection Pin. Set this pin to ground to enter standby mode, or set this pin to VDDIOto enter<br>measurement mode.<br>Digital Supply. This pin requires a decoupling capacitor. If VSUPPLYconnects to VSS, supply the voltage to this pin externally.<br>Analog Ground.<br>Analog Supply. This pin requires a decoupling capacitor. If VSUPPLYconnects to VSS, supply the voltage to this pin externally.<br>Supply Voltage. When VSUPPLYequals 2.25 V to 3.6 V, VSUPPLYenables the internal LDO regulators to generate V1P8DIGand V1P8ANA.<br>For VSUPPLY= VSS, V1P8DIGand V1P8ANAare externally supplied.<br>X-Axis Output.<br>Y-Axis Output.<br>Z-Axis Output.|



**==> picture [87 x 76] intentionally omitted <==**

_**Figure 7. ADXL357 and ADXL357B Pin Configuration (SPI/I[2] C)**_ 

_**Table 10. ADXL357 and ADXL357B Pin Function Descriptions**_ 

|**_Table 10. ADXL357 and ADXL357B Pin Function Descriptions_**|**_Table 10. ADXL357 and ADXL357B Pin Function Descriptions_**|**_Table 10. ADXL357 and ADXL357B Pin Function Descriptions_**|
|---|---|---|
|**Pin No.**<br>**Mnemonic**<br>**Description**|||
|1<br>2<br>3<br>4|CS /SCL<br>SCLK/VSSIO<br>MOSI/SDA<br>MISO/ASEL|Chip Select for SPI (<br>CS ).<br>Serial Communications Clock for I2C (SCL).<br>Serial Communications Clock for SPI (SCLK).<br>I2C Mode Enable (VSSIO). Connect this pin to Pin 6 (VSSIO) to enable I2C mode.<br>Main Output, Subordinate Input for SPI (MOSI).<br>Serial Data for I2C (SDA).<br>Main Input, Subordinate Output for SPI (MISO).<br>Alternate I2C Address Select for I2C (ASEL).|



**Rev. C | 13 of 52** 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS** 

_**Table 10. ADXL357 and ADXL357B Pin Function Descriptions (Continued)**_ 

|**_Table 10. ADXL357 and ADXL357B Pin Function Descriptions(Continued)_**|**_Table 10. ADXL357 and ADXL357B Pin Function Descriptions(Continued)_**|**_Table 10. ADXL357 and ADXL357B Pin Function Descriptions(Continued)_**|
|---|---|---|
|**Pin No.**<br>**Mnemonic**<br>**Description**|||
|5<br>6<br>7<br>8<br>9<br>10<br>11<br>12<br>13<br>14|VDDIO<br>VSSIO<br>RESERVED<br>V1P8DIG<br>VSS<br>V1P8ANA<br>VSUPPLY<br>INT1<br>INT2<br>DRDY|Digital Interface Supply Voltage.<br>Digital Ground.<br>Reserved. This pin can be connected to ground or left open.<br>Digital Supply. This pin requires a decoupling capacitor. If VSUPPLYconnects to VSS, supply the voltage to this pin externally.<br>Analog Ground.<br>Analog Supply. This pin requires a decoupling capacitor. If VSUPPLYconnects to VSS, supply the voltage to this pin externally.<br>Supply Voltage. When VSUPPLYequals 2.25 V to 3.6 V, VSUPPLYenables the internal LDO regulators to generate V1P8DIGand V1P8ANA.<br>For VSUPPLY= VSS, V1P8DIGand V1P8ANAare externally supplied.<br>Interrupt Pin 1.<br>Interrupt Pin 2.<br>Data Ready Pin.|



**Rev. C | 14 of 52** 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

All figures include data for multiple devices and multiple lots, and they were taken in the ±10 _g_ range and TA = 25°C, unless otherwise noted. For Figure 52 and Figure 76 , the ODR is derived from a main clock, with a frequency of 1.024 MHz and ±1.4% device to device variation (similar to ODR device to device variation). For a given device, however, clock frequency variation over the temperature range (−40°C to +125°C) is no more than ±1.2%, guaranteed by design. 

## **ADXL356** 

**==> picture [206 x 162] intentionally omitted <==**

_**Figure 8. Frequency Response for X-Axis**_ 

**==> picture [207 x 162] intentionally omitted <==**

_**Figure 10. Frequency Response for Z-Axis**_ 

**==> picture [206 x 162] intentionally omitted <==**

_**Figure 9. Frequency Response for Y-Axis**_ 

**==> picture [207 x 158] intentionally omitted <==**

_**Figure 11. Zero g Offset Normalized Relative to 25°C vs. Temperature, X-Axis**_ 

**==> picture [207 x 158] intentionally omitted <==**

_**Figure 12. Zero g Offset Normalized Relative to 25°C vs. Temperature, Y-Axis**_ 

**Rev. C | 15 of 52** 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

**==> picture [207 x 158] intentionally omitted <==**

_**Figure 13. Zero g Offset Normalized Relative to 25°C vs. Temperature, Z-Axis**_ 

**==> picture [177 x 158] intentionally omitted <==**

_**Figure 14. Sensitivity Normalized Relative to 25°C vs. Temperature X-Axis**_ 

**==> picture [177 x 158] intentionally omitted <==**

_**Figure 15. Sensitivity Normalized Relative to 25°C vs. Temperature, Y-Axis**_ 

**==> picture [177 x 158] intentionally omitted <==**

_**Figure 16. Sensitivity Normalized Relative to 25°C vs. Temperature, Z-Axis**_ 

**==> picture [201 x 165] intentionally omitted <==**

_**Figure 17. Zero g Offset Histogram at 25°C, X-Axis**_ 

**==> picture [175 x 163] intentionally omitted <==**

_**Figure 18. Zero g Offset Histogram at 25°C, Y-Axis**_ 

**Rev. C | 16 of 52** 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

**==> picture [176 x 163] intentionally omitted <==**

_**Figure 19. Zero g Offset Histogram at 25°C, Z-Axis**_ 

**==> picture [174 x 163] intentionally omitted <==**

_**Figure 20. Sensitivity Histogram at 25°C, X-Axis**_ 

**==> picture [174 x 164] intentionally omitted <==**

_**Figure 21. Sensitivity Histogram at 25°C, Y-Axis**_ 

**==> picture [174 x 163] intentionally omitted <==**

_**Figure 22. Sensitivity Histogram at 25°C, Z-Axis**_ 

**==> picture [180 x 163] intentionally omitted <==**

_**Figure 23. VRE, X-Axis Offset from +1 g, ±10 g Range, X-Axis Orientation = +1 g**_ 

**==> picture [180 x 164] intentionally omitted <==**

_**Figure 24. VRE, Y-Axis Offset from +1 g, ±10 g Range, Y-Axis Orientation = +1 g**_ 

**Rev. C | 17 of 52** 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

**==> picture [180 x 163] intentionally omitted <==**

_**Figure 25. VRE, Z-Axis Offset from +1 g, ±10 g Range, Z-Axis Orientation = +1 g**_ 

**==> picture [180 x 163] intentionally omitted <==**

_**Figure 26. VRE, X-Axis Offset from −1 g, ±40 g Range, X-Axis Orientation = −1 g**_ 

**==> picture [180 x 164] intentionally omitted <==**

**==> picture [180 x 163] intentionally omitted <==**

_**Figure 28. VRE, Z-Axis Offset from −1 g, ±40 g Range, Z-Axis Orientation = −1 g**_ 

**==> picture [183 x 147] intentionally omitted <==**

_**Figure 29. Temperature Sensor Output and Linear Offset vs. Temperature**_ 

**==> picture [176 x 162] intentionally omitted <==**

_**Figure 30. Total Supply Current, 3.3 V**_ 

_**Figure 27. VRE, Y-Axis Offset from −1 g, ±40 g Range, Y-Axis Orientation = −1 g**_ 

**Rev. C | 18 of 52** 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

**TYPICAL PERFORMANCE CHARACTERISTICS** 

**ADXL357** 

**==> picture [206 x 163] intentionally omitted <==**

_**Figure 31. Frequency Response for X-Axis at 4 kHz ODR**_ 

**==> picture [206 x 163] intentionally omitted <==**

_**Figure 32. Frequency Response for Y-Axis at 4 kHz ODR**_ 

**==> picture [206 x 162] intentionally omitted <==**

**==> picture [181 x 9] intentionally omitted <==**

**----- Start of picture text -----**<br>
Figure 33. Frequency Response for Z-Axis at 4 kHz ODR<br>**----- End of picture text -----**<br>


**==> picture [207 x 158] intentionally omitted <==**

_**Figure 34. Zero g Offset Normalized Relative to 25°C vs. Temperature, X-Axis**_ 

**==> picture [181 x 161] intentionally omitted <==**

_**Figure 35. Zero g Offset Normalized Relative to 25°C vs. Temperature, Y-Axis**_ 

**==> picture [181 x 161] intentionally omitted <==**

_**Figure 36. Zero g Offset Normalized Relative to 25°C vs. Temperature, Z-Axis**_ 

**Rev. C | 19 of 52** 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

**==> picture [207 x 158] intentionally omitted <==**

_**Figure 37. Sensitivity Normalized Relative to 25°C vs. Temperature X-Axis**_ 

**==> picture [207 x 157] intentionally omitted <==**

**==> picture [175 x 163] intentionally omitted <==**

_**Figure 40. Zero g Offset Histogram at 25°C, X-Axis**_ 

**==> picture [201 x 165] intentionally omitted <==**

_**Figure 38. Sensitivity Normalized Relative to 25°C vs. Temperature Y-Axis**_ 

_**Figure 41. Zero g Offset Histogram at 25°C, Y-Axis**_ 

**==> picture [207 x 157] intentionally omitted <==**

_**Figure 39. Sensitivity Normalized Relative to 25°C vs. Temperature Z-Axis**_ 

**==> picture [175 x 164] intentionally omitted <==**

_**Figure 42. Zero g Offset Histogram at 25°C, Z-Axis**_ 

**Rev. C | 20 of 52** 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

**==> picture [201 x 165] intentionally omitted <==**

_**Figure 43. Sensitivity Histogram at 25°C, X-Axis**_ 

**==> picture [201 x 165] intentionally omitted <==**

_**Figure 44. Sensitivity Histogram at 25°C, Y-Axis**_ 

**==> picture [176 x 164] intentionally omitted <==**

_**Figure 45. Sensitivity Histogram at 25°C, Z-Axis**_ 

**==> picture [180 x 163] intentionally omitted <==**

_**Figure 46. VRE, X-Axis Offset from +1 g, ±10 g Range, X-Axis Orientation = +1 g**_ 

**==> picture [180 x 163] intentionally omitted <==**

_**Figure 47. VRE, Y-Axis Offset from +1 g, ±10 g Range, Y-Axis Orientation = +1 g**_ 

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_**Figure 48. VRE, Z-Axis Offset from +1 g, ±10 g Range, Z-Axis Orientation = +1 g**_ 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

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_**Figure 49. VRE, X-Axis Offset from −1 g, ±40 g Range, X-Axis Orientation = −1 g**_ 

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_**Figure 50. VRE, Y-Axis Offset from −1 g, ±40 g Range, Y-Axis Orientation = −1 g**_ 

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_**Figure 52. Output Data Rate (Internal Clock) Histogram**_ 

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_**Figure 53. Temperature Sensor Output and Linear Offset vs. Temperature**_ 

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_**Figure 54. Total Supply Current, 3.3 V**_ 

_**Figure 51. VRE, Z-Axis Offset from +1 g, ±40 g Range, Z-Axis Orientation = +1 g**_ 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

## **ADXL357B** 

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_**Figure 55. Frequency Response for X-Axis at 4 kHz ODR**_ 

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_**Figure 56. Frequency Response for Y-Axis at 4 kHz ODR**_ 

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_**Figure 58. Zero g Offset Normalized Relative to 25°C vs. Temperature, X-Axis**_ 

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_**Figure 59. Zero g Offset Normalized Relative to 25°C vs. Temperature, Y-Axis**_ 

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_**Figure 57. Frequency Response for Z-Axis at 4 kHz ODR**_ 

_**Figure 60. Zero g Offset Normalized Relative to 25°C vs. Temperature, Z-Axis**_ 

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**ADXL356/ADXL357/ADXL357B** 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

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_**Figure 61. Sensitivity Normalized Relative to 25°C vs. Temperature X-Axis**_ 

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_**Figure 62. Sensitivity Normalized Relative to 25°C vs. Temperature Y-Axis**_ 

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_**Figure 63. Sensitivity Normalized Relative to 25°C vs. Temperature Z-Axis**_ 

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_**Figure 64. Zero g Offset Histogram at 25°C, X-Axis**_ 

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_**Figure 65. Zero g Offset Histogram at 25°C, Y-Axis**_ 

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_**Figure 66. Zero g Offset Histogram at 25°C, Z-Axis**_ 

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**ADXL356/ADXL357/ADXL357B** 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

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_**Figure 67. Sensitivity Histogram at 25°C, X-Axis**_ 

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_**Figure 68. Sensitivity Histogram at 25°C, Y-Axis**_ 

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_**Figure 69. Sensitivity Histogram at 25°C, Z-Axis**_ 

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_**Figure 70. VRE, X-Axis Offset from +1 g, ±10 g Range, X-Axis Orientation = +1 g**_ 

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_**Figure 71. VRE, Y-Axis Offset from +1 g, ±10 g Range, Y-Axis Orientation = +1 g**_ 

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_**Figure 72. VRE, Z-Axis Offset from +1 g, ±10 g Range, Z-Axis Orientation = +1 g**_ 

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**ADXL356/ADXL357/ADXL357B** 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

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_**Figure 73. VRE, X-Axis Offset from −1 g, ±40 g Range, X-Axis Orientation = −1 g**_ 

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_**Figure 74. VRE, Y-Axis Offset from −1 g, ±40 g Range, X-Axis Orientation = −1 g**_ 

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_**Figure 76. Output Data Rate (Internal Clock) Histogram**_ 

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_**Figure 77. Temperature Sensor Output and Linear Offset vs. Temperature**_ 

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_**Figure 78. Total Supply Current, 3.3 V**_ 

_**Figure 75. VRE, Z-Axis Offset from −1 g, ±40 g Range, Z-Axis Orientation = −1 g**_ 

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**ADXL356/ADXL357/ADXL357B** 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

## **ROOT ALLAN VARIANCE (RAV) ADXL357/ADXL357B CHARACTERISTICS** 

Figure 79 to Figure 81 include data for multiple devices and multiple lots, and they were taken in the ±10 _g_ range, unless otherwise noted. 

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_**Figure 79. RAV, X-Axis**_ 

_**Figure 81. RAV, Z-Axis**_ 

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_**Figure 80. RAV, Y-Axis**_ 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **THEORY OF OPERATION** 

The ADXL356 is a complete 3-axis, ultralow noise and ultrastable offset microelectromechanical systems (MEMS) accelerometer with outputs ratiometric to the analog 1.8 V supply, V1P8ANA. The ADXL357 and ADXL357B add three high resolution ADCs that use the analog 1.8 V supply as a reference to provide digital outputs insensitive to the supply voltage. The ADXL356B is pin selectable for ±10 _g_ or ±20 _g_ full scale, the ADXL356C is pin selectable for ±10 _g_ or ±40 _g_ full scale, and the ADXL357 and ADXL357B are programmable for ±10 _g_ , ±20 _g_ , or ±40 _g_ full scale and offer both SPI and I[2] C communications ports. 

The micromachined, sensing elements are fully differential, comprising the lateral x-axis and y-axis sensors and the vertical, teeter totter z-axis sensors. The x-axis and y-axis sensors and the z-axis sensors go through separate signal paths that minimize offset 

drift and noise. The signal path is fully differential, except for a differential to single-ended conversion at the analog outputs of the ADXL356. 

The analog accelerometer outputs of the ADXL356 are ratiometric to V1P8ANA. Therefore, digitize them carefully. The temperature sensor output is not ratiometric. The XOUT, YOUT, and ZOUT analog outputs are filtered internally with an antialiasing filter. These analog outputs also have an internal 32 kΩ series resistor that can be used with an external capacitor to set the bandwidth of the output. 

The ADXL357 includes antialias filters before and after the high resolution Σ-Δ ADC. User-selectable output data rates and filter corners are provided. The temperature sensor is digitized with a 12-bit successive approximation register (SAR) ADC. 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **APPLICATIONS INFORMATION** 

## **ANALOG OUTPUT** 

Figure 82 shows the ADXL356 application circuit. The analog outputs (XOUT, YOUT, and ZOUT) are ratiometric to the 1.8 V analog voltage from the V1P8ANA pin. V1P8ANA can be powered with an on-chip LDO regulator that is powered from VSUPPLY. V1P8ANA can also be supplied externally by forcing VSUPPLY to VSS, which disables the LDO regulator. Due to the ratiometric response, the analog output requires referencing to the V1P8ANA supply when digitizing to achieve the inherent noise and offset performance of the ADXL356. The 0 _g_ bias output is nominally equal to V1P8ANA/2. The recommended option is to use the ADXL356 with a ratiometric ADC (for example, the Analog Devices, Inc., AD7682) and V1P8ANA providing the voltage reference. This configuration results in self cancellation of errors due to minor supply variations. 

The ADXL356 outputs two forms of filtering: internal anti-aliasing filtering with a cutoff frequency of approximately 1.5 kHz, and external filtering. The external filter uses a fixed, on-chip, 32 kΩ resistance in series with each output in conjunction with the external capacitors to implement the low-pass filter antialiasing and noise reduction prior to the external ADC. The antialias filter 

cutoff frequency must be significantly higher than the desired signal bandwidth. If the antialias filter corner is too low, ratiometricity can degrade where the signal attenuation is different from the reference attenuation. 

## **DIGITAL OUTPUT** 

Figure 83 shows the ADXL357 and ADXL357B application circuit with the recommended bypass capacitors. The communications interface is either SPI or I[2] C (see the Serial Communications section for additional information). 

The ADXL357/ADXL357B include an internal configurable digital band-pass filter. Both the high-pass and low-pass poles of the filter are adjustable, as detailed in the Filter Settings Register section and Table 45. At power-up, the default conditions for the filters are as follows: 

- High-pass filter (HPF) = dc (off) 

- Low-pass filter (LPF) = 1000 Hz 

- Output data rate = 4000 Hz 

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_**Figure 82. ADXL356 Application Circuit**_ 

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_**Figure 83. ADXL357/ADXL357B Application Circuit**_ 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **APPLICATIONS INFORMATION** 

## **AXES OF ACCELERATION SENSITIVITY** 

Figure 84 shows the axes of acceleration sensitivity. Note that the output voltage increases when accelerated along the sensitive axis. 

outputs (V1P8ANA and V1P8DIG) and ground (0 V), especially when power cycling at temperatures below −20℃. See the recommended application circuits shown in Figure 82 and Figure 83 for reference. 

## **POWER SUPPLY DESCRIPTION** 

The ADXL356/ADXL357/ADXL357B have four different power supply domains: VSUPPLY, V1P8ANA, V1P8DIG, and VDDIO. The internal analog and digital circuitry operates at 1.8 V nominal. 

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## **VSUPPLY** 

VSUPPLY is 2.25 V to 3.6 V, which is the input range to the two LDO regulators that generate the nominal 1.8 V outputs for V1P8ANA and V1P8DIG. Connect VSUPPLY to VSS to disable the LDO regulators, which allows driving V1P8ANA and V1P8DIG from an external source. 

## **V1P8ANA** 

_**Figure 84. Axes of Acceleration Sensitivity**_ 

## **POWER SEQUENCING** 

There are two methods for applying power to the device. Typically, internal LDO regulators generate the 1.8 V power for the analog and digital supplies, V1P8ANA and V1P8DIG, respectively. Optionally, the internal LDO regulators can be disabled and V1P8ANA and V1P8DIG are driven by external 1.8 V supplies. 

When using the internal LDO regulators, connect VSUPPLY to a voltage source between 2.25 V and 3.6 V. In this case, the recommended power sequence is to apply power to VDDIO, followed by applying power to VSUPPLY approximately 10 µs later. If necessary, VSUPPLY and VDDIO can be powered from the same voltage source, so that both are powered at the same time. However, VSUPPLY cannot be powered before VDDIO. 

To disable the internal LDO regulators, tie VSUPPLY to ground and use external 1.8 V supplies to power V1P8ANA and V1P8DIG. V1P8ANA and V1P8DIG must have the same voltage level. The maximum acceptable tolerance between the external V1P8ANA and V1P8DIG voltage levels is 50 mV. In the case of bypassing the LDO regulators, the recommended power sequence is to apply power to VDDIO, followed by applying power to V1P8DIG approximately 10 µs later, and then applying power to V1P8ANA approximately 10 µs later. If necessary, V1P8DIG and VDDIO can be powered from the same external 1.8 V supply, which can also be tied to V1P8ANA with proper isolation, so that all are powered at the same time. In this case, proper decoupling and low frequency isolation are important to maintain the noise performance of the sensor. 

When power cycling the ADXL356/ADXL357/ADXL357B, it is highly recommended to fully discharge the device to ground level (VSUPPLY and VDDIO = 0 V), for at least 200 ms, on each power cycle. It is also highly recommended to help the LDO discharge properly by adding external resistors of approximately 100 kΩ between the LDO 

All sensor and analog signal processing circuitry operates in this domain. Offset and sensitivity of the analog output ADXL356 are ratiometric to this supply voltage. When using external ADCs, use V1P8ANA as the reference voltage. The ADXL357/ADXL357B include ADCs that are ratiometric to V1P8ANA, thereby rendering the offset and sensitivity of the ADXL357/ADXL357B digital output is insensitive to the value of V1P8ANA. V1P8ANA can be an input or an output as defined by the state of the VSUPPLY voltage. 

## **V1P8DIG** 

V1P8DIG is the supply voltage for the internal logic circuitry. A separate LDO regulator decouples the digital supply noise from the analog signal path. V1P8ANA can be an input or an output as defined by the state of the VSUPPLY voltage. If driven externally, V1P8DIG must be the same voltage as the V1P8ANA voltage. 

## **VDDIO** 

The VDDIO value determines the logic high levels. On the analog output ADXL356, VDDIO sets the logic high level for the self test pins, ST1 and ST2, as well as theSTBY pin. On the digital output ADXL357/ADXL357B, VDDIO sets the logic high level for communications interface ports, as well as the interrupt and DRDY outputs. 

The LDO regulators are operational when VSUPPLY is between 2.25 V and 3.6 V. V1P8ANA and V1P8DIG are the regulator outputs in this mode. Alternatively, when tying VSUPPLY to VSS, V1P8ANA and V1P8DIG are supply voltage inputs with a 1.62 V to 1.98 V range. 

## **OVERRANGE PROTECTION** 

To avoid electrostatic capture of the proof mass when the accelerometer is subject to input acceleration beyond its full-scale range, all sensor drive clocks turn off for 0.5 ms. In the ±10 _g_ range setting, the overrange protection activates for input signals beyond approximately ±40 _g_ (±25%), and for the ±20 _g_ and ±40 _g_ range settings, the threshold corresponds to about ±80 _g_ (±25%). 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **APPLICATIONS INFORMATION** 

When overrange protection occurs, the XOUT, YOUT, and ZOUT pins on the ADXL356 begin to drive to midscale, whereas the ADXL357/ ADXL357B float toward zero LSB, and the first in, first out (FIFO) buffer begins filling with this data. Figure 85 shows the ADXL356 overrange behavior for a 150 _g_ , 5 ms width, half sine-wave shock event. The ADXL356 range is set to ±20 _g_ . 

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_**Figure 85. ADXL356 Overrange Behavior for ±20 g Range Setting**_ 

## **MECHANICAL HEADROOM VS. FREQUENCY** 

The mechanical headroom defines the level of acceleration at which the proof mass makes contact with the mechanical stops. Repetitive contact can introduce both operational and reliability problems. 

Figure 86 and Figure 87 show a comparison of the mechanical headroom for the ADXL356, ADXL357, and ADXL357B over frequency. 

Refer to the vibration operation limits in the Absolute Maximum Ratings section for more details. 

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_**Figure 86. X-Axis and Y-Axis Mechanical Headroom vs. Frequency Comparison for ADXL356/ADXL357/ADXL357B**_ 

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_**Figure 87. Z-Axis Mechanical Headroom vs. Frequency Comparison for ADXL356/ADXL357/ADXL357B**_ 

## **SELF TEST** 

The ADXL356 and ADXL357/ADXL357B incorporate a self test feature that effectively tests the mechanical and electronic system. Enabling self test stimulates the sensor electrostatically to produce an output corresponding to the test signal applied as well as the mechanical force exerted. Only the z-axis response is specified to validate device functionality. 

In the ADXL356, drive the ST1 pin to VDDIO to invoke self test mode. Then, by driving the ST2 pin to VDDIO, the ADXL356 applies an electrostatic force to the mechanical sensor and induces a change in output in response to the force. The self test delta (or ‑ response) is the difference in output voltage in the z axis when ST2 is high vs. ST2 is low, while ST1 is asserted. After the self test measurement is complete, bring both pins low to resume normal operation. 

The self test operation is similar in the ADXL357/ADXL357B, except ST1 and ST2 can be accessed through the SELF_TEST register (Register 0x2E). 

The self test feature rejects externally applied acceleration and only responds to the self test force, which allows an accurate measurement of the self test, even in the presence of external mechanical noise. When the self test feature is not used, both ST1 and ST2 must be kept low. 

## **FILTER** 

The ADXL356/ADXL357/ADXL357B use an analog, low-pass, antialiasing filter to reduce out of band noise and to limit bandwidth. The ADXL357/ADXL357B provide further digital filtering options to maintain optimal noise performance at various ODRs. 

The analog, low-pass antialiasing filter in the ADXL356/ADXL357/ ADXL357B provides a fixed 3 dB bandwidth of approximately 1.5 kHz, the frequency at which the voltage output response is attenuated by approximately 30%. The shape of the filter response in the frequency domain is that of a sinc filter. While the analog 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **APPLICATIONS INFORMATION** 

antialiasing filter attenuates the output response around and above its cutoff frequency, the MEMS sensor has a resonance at 5.5 kHz and mechanically amplifies the output response at around 2 kHz and above. These competing trends are apparent in the overall transfer function of the ADXL356, as shown in Figure 8 to Figure 10. Therefore, the overall −3 dB bandwidth of the ADXL356 is 2.4 kHz, and the overall bandwidth with ±4 dB flatness is about 4.4 kHz. 

The ADXL356 x-axis, y-axis, and z-axis analog outputs include an amplifier followed by a series 32 kΩ resistor, and output to the XOUT, the YOUT, and the ZOUT pins, respectively. 

The ADXL357/ADXL357B provide an internal 20-bit, Σ-Δ ADC to digitize the filtered analog signal. Additional digital filtering (beyond the analog, low-pass, antialiasing filter) consists of a low-pass digital decimation filter and a bypassable high-pass filter that supports output data rates between 4 kHz and 3.906 Hz. The decimation filter consists of two stages. The first stage is fixed decimation with a 4 kHz ODR and a low-pass filter cutoff (3 dB) at about 1 kHz. A variable second stage decimation filter is used for the 2 kHz output data rate and below (it is bypassed for 4 kHz ODR). Figure 88 shows the low-pass filter response with a 1 kHz corner (4 kHz ODR) for the ADXL357/ADXL357B. Note that Figure 88 does not include the fixed frequency analog, low-pass, antialiasing filter with a fixed 3 dB bandwidth of approximately 1.5 kHz. 

The ADXL357/ADXL357B pass band of the signal path relates to the combined filter responses, including the analog filter previously described, and the digital decimation filter/ODR setting. Table 11 shows the delay associated with the decimation filter for each setting and provides the attenuation at the ODR/4 corner. 

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_**Figure 88. ADXL357 Digital LPF Response for 4 kHz ODR**_ 

The ADXL357/ADXL357B also include an optional digital high-pass filter with a programmable corner frequency. By default, the highpass filter is disabled. The high-pass corner frequency, where 

the output is attenuated by 3 dB, is related to the ODR, and the HPF_CORNER setting in the filter register (Register 0x28, Bits[6:4]). Table 12 shows the HPF_CORNER response. Figure 89 and Figure 90 show the simulated high-pass filter pass-band and delay responses for a 9.88 Hz cutoff. 

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_**Figure 89. High-Pass Filter Pass-Band Response for a 4 kHz ODR and an HPF_CORNER Setting of 001 (Register 0x28, Bits[6:4])**_ 

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_**Figure 90. High-Pass Filter Delay Response for a 4 kHz ODR and an HPF_CORNER Setting of 001 (Register 0x28, Bits[6:4])**_ 

The ADXL357/ADXL357B also include an interpolation filter after the decimation filters that produces oversampled/upconverted data and provides an external synchronization option. See the Data Synchronization section for more details. Table 13 shows the delay and attenuation relative to the programmed ODR. 

Group delay is the digital filter delay from the input to the ADC until data is available at the interface (see the Filter section). This delay is the largest component of the total delay from sensor to serial interface. 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **APPLICATIONS INFORMATION** 

_**Table 11. Digital Filter Group Delay and Profile**_ 

|**_Table 11. Digital Filter Group Delay and Profile_**|||||
|---|---|---|---|---|
|**Programmed ODR (Hz)**|**Delay**<br>**Attenuation**||||
||**ODR (Cycles)**<br>**Time (ms)**<br>**Decimator at ODR/4 (dB)**<br>**Full Path at ODR/4 (dB)**||||
|4000<br>4000/2 = 2000<br>4000/4 = 1000<br>4000/8 = 500<br>4000/16 = 250<br>4000/32 = 125<br>4000/64 = 62.5<br>4000/128 ≈ 31<br>4000/256 ≈ 16<br>4000/512 ≈ 8<br>4000/1024 ≈ 4|2.52<br>2.00<br>1.78<br>1.63<br>1.57<br>1.54<br>1.51<br>1.49<br>1.50<br>1.50<br>1.50|0.63<br>1.00<br>1.78<br>3.26<br>6.27<br>12.34<br>24.18<br>47.59<br>96.25<br>189.58<br>384.31|−3.44<br>−2.21<br>−1.92<br>−1.83<br>−1.83<br>−1.83<br>−1.83<br>−1.83<br>−1.83<br>−1.83<br>−1.83|−3.63<br>−2.26<br>−1.93<br>−1.83<br>−1.83<br>−1.83<br>−1.83<br>−1.83<br>−1.83<br>−1.83<br>−1.83|



_**Table 12. Digital High-Pass Filter Response**_ 

|**_Table 12. Digital High-Pass Filter Response_**|**_Table 12. Digital High-Pass Filter Response_**|**_Table 12. Digital High-Pass Filter Response_**|
|---|---|---|
|**HPF_CORNER Register Setting (Register**<br>**0x28, Bits[6:4])**<br>**HPF_CORNER Frequency, −3 dB Point Relative to ODR Setting**<br>**−3 dB at 4 kHz ODR (Hz)**|||
|000<br>001<br>010<br>011<br>100<br>101<br>110|Not applicable, no high-pass filter enabled<br>24.7 × 10−4× ODR<br>6.2084 × 10−4× ODR<br>1.5545 × 10−4× ODR<br>0.3862 × 10−4× ODR<br>0.0954 × 10−4× ODR<br>0.0238 × 10−4× ODR|Off<br>9.88<br>2.48<br>0.62<br>0.1545<br>0.03816<br>0.00952|



_**Table 13. Combined Digital Interpolation Filter and Decimation Filter Response**_ 

|**_Table 13. Combined Digital Interpolation Filter and Decimation Filter Response_**|**_Table 13. Combined Digital Interpolation Filter and Decimation Filter Response_**|**_Table 13. Combined Digital Interpolation Filter and Decimation Filter Response_**|**_Table 13. Combined Digital Interpolation Filter and Decimation Filter Response_**|
|---|---|---|---|
|**Interpolator Data Rate Resolution Relative**<br>**to 64 × ODR (Hz)**<br>**Combined Interpolator/ Decimator**<br>**Delay (ODR Cycles)**<br>**Combined Interpolator/**<br>**Decimator Delay (ms)**<br>**Combined Interpolator/Decimator Output**<br>**Attenuation at ODR/4 (dB)**||||
|64 × 4000 = 256,000<br>64 × 2000 = 128,000<br>64 × 1000 = 64,000<br>64 × 500 = 32,000<br>64 × 250 = 16,000<br>64 × 125 = 8000<br>64 × 62.5 = 4000<br>64 × 31.25 = 2000<br>64 × 15.625 = 1000<br>64 × 7.8125 = 500<br>64 × 3.90625 = 250|3.51661<br>3.0126<br>2.752<br>2.6346<br>2.5773<br>2.5473<br>2.53257<br>2.52452<br>2.52045<br>2.5194<br>2.51714|0.88<br>1.51<br>2.75<br>5.27<br>10.31<br>20.38<br>40.52<br>80.78<br>161.31<br>322.48<br>644.39|−6.18<br>−4.93<br>−4.66<br>−4.58<br>−4.55<br>−4.55<br>−4.55<br>−4.55<br>−4.55<br>−4.55<br>−4.55|



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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **SERIAL COMMUNICATIONS** 

The 4-wire serial interface communicates in either the SPI or I[2] C protocol. The interface affectively autodetects the format being used, requiring no configuration control to select the format. 

The ADXL357/ADXL357B multifunction pins are referred to by a single function of the pin, for example, CS , when only that function is relevant. 

## **SPI PROTOCOL** 

Wire the ADXL357/ADXL357B for SPI communication as shown in the connection diagram in Figure 91. The SPI protocol timing is shown in Figure 93 to Figure 96. The timing scheme follows the clock polarity (CPOL) = 0 and clock phase (CPHA) = 0. The SPI clock speed ranges from 100 kHz to 10 MHz. 

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## **SPI BUS SHARING** 

Use a gated buffer on the SCLK line for the ADXL357/ADXL357B device to achieve the ultralow noise performance and possibly offset shift when the ADXL357/ADXL357B must share a SPI bus with another subordinate device. This gated SCLK allows the clock signal through only when the chip select (CS) line is low. See Figure 92 for the example circuit that provides this type of protection. 

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_**Figure 92. SCLK Protection Example**_ 

_**Figure 91. 4-Wire SPI Connection**_ 

_**Figure 93. SPI Timing Diagram—Single-Byte Read**_ 

_**Figure 94. SPI Timing Diagram—Single-Byte Write**_ 

_**Figure 95. SPI Timing Diagram—Multibyte Read**_ 

_**Figure 96. SPI Timing Diagram—Multibyte Write**_ 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **SERIAL COMMUNICATIONS** 

## **I[2] C PROTOCOL** 

The ADXL357/ADXL357B support point to point I[2] C communication. However, when sharing an SDA bus, the ADXL357 may prevent communication with other devices on that bus. If at any point, even when the ADXL357 is not being addressed, the 0x3A and 0x3B bytes (when the ADXL357 device address is set to 0x1D), or the 0xA6 and 0xA7 bytes (when the ADXL357 device address is set to 0x53) are transmitted on the SDA bus, the ADXL357 responds with an acknowledge bit and pulls the SDA line down. For example, this response can occur when reading or writing the data bytes (0x3A/0x3B or 0xA6/0xA7) to another sensor on the bus. When the ADXL357 pulls the SDA line down, communication with other devices on the bus may be interrupted. To resolve this interruption, the ADXL357 must be connected to a separate SDA bus, or the CS/SCL pin must be switched high when communication with the ADXL357 is not desired (it is normally grounded). 

The ADXL357/ADXL357B support standard (100 kHz), fast (up to 1 MHz) and high speed (up to 3.4 MHz) data transfer modes when the bus parameters in Table 5 are met. There is no minimum SCL frequency, with the exception that, when reading data, the clock must be fast enough to read an entire sample set before new data overwrites it. Single-byte or multiple byte reads/writes are supported. With the MISO/ASEL pin low, the I[2] C address for the device is 0x1D and an alternate I[2] C address of 0x53 can be chosen by pulling the MISO/ASEL pin high. 

There are no internal pull-up or pull-down resistors for any unused pins. Therefore, there is no known state or default state for the pins if left floating or unconnected. SCLK/VSSIO must be connected to ground when communicating to the ADXL357/ADXL357B using I[2] C. 

Due to communication speed limitations, the maximum output data rate when using the 400 kHz I[2] C mode is 800 Hz, and it scales linearly with a change in the I[2] C communication speed. For example, using I[2] C at 100 kHz limits the maximum ODR to 200 Hz. Operation at an output data rate above the recommended maximum may result in an undesirable effect on the acceleration data, including missing samples or additional noise. Figure 97 to Figure 99 show the detail of the I[2] C protocol timing. The I[2] C interface can be used 

on most buses operating in I[2] C standard mode (100 kHz), fast mode (400 kHz), fast mode plus (1 MHz), and high speed mode (3.4 MHz). The ADXL357/ADXL357B I[2] C device ID is as follows: 

- MISO/ASEL pin = 0, device address = 0x1D 

- MISO/ASEL pin = 1, device address = 0x53 

If other devices are connected to the same I[2] C bus, the nominal operating voltage level of these other devices cannot exceed VDDIO by more than 0.3 V. External pull-up resistors, RP, are necessary for proper I[2] C operation. 

## **READING ACCELERATION OR TEMPERATURE DATA FROM THE INTERFACE** 

Acceleration data is left justified and has a register address order of most significant data to least significant data, which allows the user to use multibyte transfers and to take only as much data as required—8 bits, 16 bits, or 20 bits, plus the marker. Temperature data is 12 bits unsigned, right justified. The ADXL357/ADXL357B temperature value is split over two bytes, but is not double buffered, meaning the value can update between readings of the two registers. The data in XDATA, YDATA, and ZDATA is always the most recent available. It is not guaranteed that XDATA, YDATA, and ZDATA form a set corresponding to one sample point in time. The routine used to retrieve the data from the device controls this data set continuity. If data transfers are initiated when the DATA_RDY bit goes high and completes in a time approximately equal to 1/ODR, XDATA, YDATA, and ZDATA apply to the same data set. 

For multibyte read or write transactions through either serial interface, the internal register address auto-increments. When the top of the register address range, 0x3FF, is reached, the auto-increment stops and does not wrap back to Address 0x00. 

The address auto-increment function disables when the FIFO address is used, so that data can be read continuously from the FIFO as a multibyte transaction. In cases where the starting address of a multibyte transaction is less than the FIFO address, the address auto-increments until reaching the FIFO address, and then stops at the FIFO address. 

_**Figure 97. I[2] C Timing Diagram—Single-Byte Read**_ 

_**Figure 98. I[2] C Timing Diagram—Single-Byte Write**_ 

**Rev. C | 35 of 52** 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **SERIAL COMMUNICATIONS** 

_**Figure 99. I[2] C Timing Diagram—Multibyte Write**_ 

**Rev. C | 36 of 52** 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **FIFO** 

The FIFO operates in a stream mode. That is, when the FIFO overruns, new data overwrites the oldest data in the FIFO. A read from the FIFO address guarantees that the three bytes associated with the acceleration measurement on an axis all pertain to the same measurement. The FIFO never overflows, and the data is always taken out in sets (multiples of three data points). 

There are 96 21-bit locations in the FIFO. Each location contains 20 bits of data and a marker bit for the x-axis data. A single-byte read from the FIFO address pops one location from the FIFO. A multibyte read to the FIFO location pops the FIFO on the read of the first byte and every third byte read thereafter. 

logic inserts the two virtual bits (0b00) between the data bits and the empty indicator bit. Bit 1 indicates that an attempt was made to read an empty FIFO, and that the data is not valid acceleration data. Bit 0 is a marker bit to identify the x-axis, which allows a user to verify that the FIFO data was correctly read. An acceleration data point for a given axis occupies one FIFO location. The read pointer, RD_PTR, points to the oldest stored data that was not read already from the interface (see Figure 100). There are no physical x-acceleration, y-acceleration, or z-acceleration data registers. The data read from data registers (Register 0x08 to Register 0x10) also comes directly from the most recent data set in the FIFO, which is pointed to by the z pointer, Z_PTR (see Figure 100). 

Figure 100 shows the organization of the data in the FIFO. The acceleration data is twos complement, 20-bit data. The FIFO control 

_**Figure 100. FIFO Data Organization**_ 

**Rev. C | 37 of 52** 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **INTERRUPTS** 

The status register (Register 0x04) contains five individual bits, four of which can be mapped to either the INT1 pin, the INT2 pin, or both. The polarity of the interrupt, active high or active low, is also selectable via the INT_POL bit in the range (Register 0x2C) register. In general, the status register clears when read, but this is not the case if the condition that caused the interrupt persists after the read of the register. The definition of persist varies slightly in each case, but it is described in the DATA_RDY, DRDY Pin, FIFO_FULL, FIFO_OVR, and Activity sections. The DRDY pin is similar to an interrupt pins (INTx) but clears differently. This case is also described. 

## **DATA_RDY** 

The DATA_RDY bit is set when new acceleration data is available to the interface and clears on a read of the status register. This bit is not set again until acceleration data that is newer than the status register read is available. 

Special logic on the clearing of the DATA_RDY bit covers the corner case where new data arrives during the read of the status register. In this case, the data ready condition may be missed completely. This logic results in a delay of the clearing of DATA_RDY of up to four 512 kHz cycles. 

## **DRDY PIN** 

The DRDY pin is not a status register bit. DRDY instead behaves similar to an unmaskable interrupt. DRDY is set when new acceleration data is available to the interface. DRDY clears on a read of the FIFO, on a read of XDATA, YDATA, or ZDATA, or by an autoclear function that occurs approximately halfway between output acceleration data sets. 

DRDY is always active high. The INT_POL bit does not affect DRDY. In external synchronization modes (EXT_SYNC = 01, EXT_SYNC = 10), the first few DRDY pulses after initial synchronization can be lost or corrupted. The length of this potential corruption is equal to or less than the group delay. Therefore, the samples within one group delay is lost or corrupted after the first synchronization signal. Depending on the decimation setting and interpolation setting (see Table 13), between one and three samples after the first synchronization pulse is lost, provided that all the restrictions set in the External Synchronization and Interpolation section is met. 

## **FIFO_FULL** 

The FIFO_FULL bit is set when the entries in the FIFO are equal to the setting of the FIFO_SAMPLES bits. FIFO_FULL clears as follows: 

- If the number of entries in the FIFO is less than the number of samples indicated by the FIFO_SAMPLES bits, which is only the case if sufficient data is read from the FIFO. 

## **FIFO_OVR** 

The FIFO_OVR bit is set when the FIFO is so far overrange that data is lost. The specified size of the FIFO is 96 locations. The FIFO_OVR bit is set only when there is an attempt to write past this 96-location limit. 

A read of the status register clears FIFO_OVR. FIFO_OVR is not set again until data is lost subsequent to this status register read. 

## **ACTIVITY** 

The activity bit (Register 0x04, Bit 3) is set when the measured acceleration on any axis is above the value set in the ACT_ THRESH bits for ACT_COUNT consecutive measurements. An overthreshold condition can shift from one axis to another on successive measurements and is still counted toward the consecutive ACT_COUNT count. 

A read of the status register clears the activity bit (Register 0x04, Bit 3), but the bit sets again at the end of the next measurement if the activity bit (Register 0x04, Bit 3) conditions are still satisfied. 

## **NVM_BUSY** 

The NVM_BUSY bit indicates that the nonvolatile memory (NVM) controller is busy and, therefore, the NVM cannot be accessed to read or write. The interrupt functionality requires the NVM_BUSY bit to be cleared to function. 

A status register read that occurs after the NVM controller is no longer busy clears NVM_BUSY. 

## **EXTERNAL SYNCHRONIZATION AND INTERPOLATION** 

There are four possible synchronization options for the ADXL357/ ADXL357B, three of which are shown in Figure 101 to Figure 103. For clarity, the clock frequencies and delays are drawn to scale. The labels in Figure 101 to Figure 103 are defined as follows: 

- Internal ODR is the alignment of the decimated output data based on the internal clock. 

- ADC modulator clock shows the internal main clock rate. 

- DRDY is an output indicator signaling a sample is ready. 

The four possible synchronization options are as follows: 

   - No external synchronization (internal clocks used) 

   - Synchronization with an external synchronization signal and internal clock, interpolation filter enabled 

   - Synchronization with external synchronization and clock signals, no interpolation filter 

   - Synchronization with external synchronization and clock signals, interpolation filter enabled 

- On a read of the status register, but only when the entries in the FIFO are less than the FIFO_SAMPLES bits. 

**Rev. C | 38 of 52** 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **INTERRUPTS** 

## **EXT_SYNC = 00, EXT_CLK = 0—No External Synchronization or Interpolation** 

This is the default mode of operation for the device. The sensor runs on an internal ODR and an internal clock that is generated by an internal oscillator. The internal ODR serves as the synchronization controller, which generates the data. Register 0x28 is used to program the ODR. No external signals are required, and this mode is used typically when the external processor retrieves data from the device asynchronously and absolute synchronization to an external source is not required. 

The device outputs a DRDY (active high) to signal that a new sample is available, and data is retrieved from the real-time registers or the FIFO. The group delay is based on the decimation setting, as shown in Table 11. This mode is shown in Figure 101. 

## **EXT_SYNC = 10, EXT_CLK = 0—External Synchronization With Interpolation** 

Synchronization using interpolation filters and an external ODR clock is commonly used when the external processor can provide a synchronization signal, SYNC, that is asynchronous to the internal clock at the desired ODR. In this case, an interpolation filter provides additional time resolution of 64 times the programmed ODR (see Table 13). Synchronization with the interpolation filter enabled (EXT_SYNC = 10) allows the sensor to operate on an internal clock and output data most closely associated with the SYNC rising edge. 

The advantage of this mode is that data is available at an arbitrary user defined SYNC sample rate and is asynchronous to the internal clock oscillator. The maximum sample rate cannot exceed 4000 SPS. The disadvantage of this mode is that the group delay is increased, with increased attenuation at the band edge. Additionally, because there is a limit to the time resolution, there is some distortion related to the mismatch of the external synchronization relative to the internal clock oscillator. This mismatch degrades spectral performance. The group delay is based on the decimation setting and interpolation setting (see Table 13). Figure 102 schematically shows the timings in this mode, and Table 14 shows the delay between the SYNC signal (input) to DRDY (output). 

_**Table 14. EXT_SYNC = 10, DRDY Delay**_ 

|**_Table 14. EXT_SYNC = 10, DRDY Delay_**|**_Table 14. EXT_SYNC = 10, DRDY Delay_**|
|---|---|
|**ODR_LPF**<br>**SYNC to DRDY Delay (Oscillator Cycles)**||
|0x0<br>0x1<br>0x2<br>0x3<br>0x4<br>0x5<br>0x6<br>0x7|8<br>10<br>14<br>22<br>38<br>70<br>134<br>262|



_**Table 14. EXT_SYNC = 10, DRDY Delay (Continued)**_ 

|**_Table 14. EXT_SYNC = 10, DRDY Delay (Continued)_**|**_Table 14. EXT_SYNC = 10, DRDY Delay (Continued)_**|
|---|---|
|**ODR_LPF**<br>**SYNC to DRDY Delay (Oscillator Cycles)**||
|0x8<br>0x9<br>0xA|1031<br>2054<br>4102|



## **EXT_SYNC = 01, EXT_CLK = 1—External Synchronization and External Clock, No Interpolation Filter** 

When configured for EXT_SYNC = 01 and EXT_CLK = 1 (sync register, see Table 48), the user must supply an external clock (enabled via the EXT_CLK bit) at 1.024 MHz on the INT2 pin (Pin 13) and an external synchronization signal, SYNC, on the DRDY pin (Pin 14), as shown in Table 15. If configured in this mode and an external clock is not supplied, the device does not process any data and reading from the output results in null values. This mode is schematically shown in Figure 103. 

Special restrictions when using this mode include the following: 

- The external clock frequency on INT2 (Pin 13, see Table 15) must be 1.024 MHz. 

- The pulse width of the SYNC signal must be at least 3.91 µs, which represents four cycles of the external clock (4 ÷ 1.024 MHz = ~3.91 µs). 

- The phase of SYNC must meet an approximate 25 ns setup time to the external clock rising edge. 

When using the EXT_SYNC mode and without providing the SYNC signal, the device runs on its own internal ODR. Similarly, after external synchronization, the device continues to run synchronized to the last SYNC pulse it received, which means that EXT_SYNC = 01 mode can be used with only a single synchronization pulse. 

For more information about the lost sample in Figure 103, see the DRDY Pin section. 

## **EXT_SYNC = 10, EXT_CLK = 1—External Synchronization and External Clock, With Interpolation Filter** 

This mode can be used to run the device on an external clock and synchronization with an arbitrary sample rate set by the SYNC signal rate. Conditions for external SYNC and external clock signals is the same as EXT_SYNC = 01, EXT_CLK = 1 mode. The interpolation filter provides a frequency resolution related to the ODR (see Table 13). In this case, the data provided corresponds to the external SYNC signal, which can be greater than the set ODR and less than 4000 SPS, but the output pass band remains the same it was prior to the interpolation filter. 

**Rev. C | 39 of 52** 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **INTERRUPTS** 

_**Table 15. Multiplexing of INT2 and DRDY**_ 

|**_Table 15. Multiplexing of INT2 and DRDY_**|**_Table 15. Multiplexing of INT2 and DRDY_**|**_Table 15. Multiplexing of INT2 and DRDY_**|
|---|---|---|
|**Register or Bit Fields**<br>**Pins**<br>**Comments**<br>**EXT_CLK**<br>**EXT_SYNC,**<br>**Bits[1:0]**<br>**INT_MAP,**<br>**Bits[7:4]**<br>**INT2 (Pin 13)**<br>**DRDY (Pin 14)**|||
|0<br>0<br>1<br>1|00<br>0000<br>Low<br>DR<br>00<br>Not 0000<br>INT2<br>DR<br>00<br>0000<br>EXT_CLK<br>DR<br>00<br>Not 00001<br>EXT_CLK<br>DR|DY<br>Synchronization is to the internal clocks, and there is no external<br>clock synchronization.<br>DY<br>DY<br>DY|
|0<br>0|01<br>0000<br>DRDY2<br>SYN<br>013<br>Not 0000<br>INT2<br>SYN|C<br>These options reset the digital filters on every synchronization pulse<br>and are not recommended.<br>C|
|1<br>1|013<br>0000<br>EXT_CLK<br>SYN<br>013<br>Not 00001<br>EXT_CLK<br>SYN|C<br>External synchronization, no interpolation filter, and DRDY (active<br>high) signals that data is ready. Data represents a sample point<br>group delay earlier in time.<br>C|
|0<br>0<br>1<br>1|10<br>0000<br>DRDY2<br>SYN<br>103<br>Not 0000<br>INT2<br>SYN<br>103<br>0000<br>EXT_CLK<br>SYN<br>103<br>Not 0000<br>EXT_CLK<br>SYN|C<br>External synchronization, interpolation filter, and DRDY (active high)<br>signals that data is ready. Data sample group delay earlier in time.<br>C<br>C<br>C|



> 1 No INT2, even though it is enabled. 

> 2 DRDY routing through the INT_MAP register takes precedence over the default, per Table 14. 

> 3 No DRDY. 

_**Figure 101. EXT_SYNC = 00, EXT_CLK = 0, Internal Synchronization, Internal Clock**_ 

_**Figure 102. EXT_SYNC = 10, EXT_CLK = 0, External Synchronization, Internal Clock, Interpolation Filter**_ 

**==> picture [57 x 45] intentionally omitted <==**

_**Figure 103. EXT_SYNC = 01, EXT_CLK = 1, External Synchronization, External Clock, No Interpolation Filter**_ 

**Rev. C | 40 of 52** 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **ADXL357/ADXL357B REGISTER MAP** 

Note that while configuring the ADXL357/ADXL357B in an application, all configuration registers must be programmed before enabling measurement mode in the POWER_CTL register. When the ADXL357/ADXL357B are in measurement mode, only the following configurations can change: the HPF_CORNER bits in the filter register, the INT_MAP register, the ST1 and ST2 bits in the SELF_TEST register, and the reset register. 

_**Table 16. ADXL357/ADXL357B Register Map**_ 

|**_Table 16. ADXL357/ADXL357B Register Map_**|**_Table 16. ADXL357/ADXL357B Register Map_**|**_Table 16. ADXL357/ADXL357B Register Map_**|**_Table 16. ADXL357/ADXL357B Register Map_**|**_Table 16. ADXL357/ADXL357B Register Map_**|**_Table 16. ADXL357/ADXL357B Register Map_**|**_Table 16. ADXL357/ADXL357B Register Map_**|**_Table 16. ADXL357/ADXL357B Register Map_**|**_Table 16. ADXL357/ADXL357B Register Map_**|**_Table 16. ADXL357/ADXL357B Register Map_**|||
|---|---|---|---|---|---|---|---|---|---|---|---|
|**Hex. Addr.**<br>**Register Name**<br>**Bit 7**<br>**Bit 6**<br>**Bit 5**<br>**Bit 4**<br>**Bit 3**<br>**Bit 2**<br>**Bit 1**<br>**Bit 0**||||||||||**Reset**<br>**R/W**||
|0x00|DEVID_AD|DEVID_AD||||||||0xAD|R|
|0x01|DEVID_MST|DEVID_MST||||||||0x1D|R|
|0x02|PARTID|PARTID||||||||0xED1|R|
|||||||||||0xE92|R|
|0x03|REVID|REVID||||||||0x011|R|
|||||||||||0x002|R|
|0x04|Status|Reserved|||NVM_<br>BUSY|Activity|FIFO_OVR|FIFO_FULL|DATA_RDY|0x00|R|
|0x05|FIFO_ENTRIES|Reserved|FIFO_ENTRIES|||||||0x00|R|
|0x06|TEMP2|Reserved||||Temperature, Bits[11:8]||||0x00|R|
|0x07|TEMP1|Temperature, Bits[7:0]||||||||0x00|R|
|0x08|XDATA3|XDATA, Bits[19:12]||||||||0x00|R|
|0x09|XDATA2|XDATA, Bits[11:4]||||||||0x00|R|
|0x0A|XDATA1|XDATA, Bits[3:0]||||Reserved||||0x00|R|
|0x0B|YDATA3|YDATA, Bits[19:12]||||||||0x00|R|
|0x0C|YDATA2|YDATA, Bits[11:4]||||||||0x00|R|
|0x0D|YDATA1|YDATA, Bits[3:0]||||Reserved||||0x00|R|
|0x0E|ZDATA3|ZDATA, Bits[19:12]||||||||0x00|R|
|0x0F|ZDATA2|ZDATA, Bits[11:4]||||||||0x00|R|
|0x10|ZDATA1|ZDATA, Bits[3:0]||||Reserved||||0x00|R|
|0x11|FIFO_DATA|FIFO_DATA||||||||0x00|R|
|0x1E|OFFSET_X_H|OFFSET_X, Bits[15:8]||||||||0x00|R/W|
|0x1F|OFFSET_X_L|OFFSET_X, Bits[7:0]||||||||0x00|R/W|
|0x20|OFFSET_Y_H|OFFSET_Y, Bits[15:8]||||||||0x00|R/W|
|0x21|OFFSET_Y_L|OFFSET_Y, Bits[7:0]||||||||0x00|R/W|
|0x22|OFFSET_Z_H|OFFSET_Z, Bits[15:8]||||||||0x00|R/W|
|0x23|OFFSET_Z_L|OFFSET_Z, Bits[7:0]||||||||0x00|R/W|
|0x24|ACT_EN|Reserved|||||ACT_Z|ACT_Y|ACT_X|0x00|R/W|
|0x25|ACT_THRESH_H|ACT_THRESH, Bits[15:8]||||||||0x00|R/W|
|0x26|ACT_THRESH_L|ACT_THRESH, Bits[7:0]||||||||0x00|R/W|
|0x27|ACT_COUNT|ACT_COUNT||||||||0x01|R/W|
|0x28|Filter|Reserved|HPF_CORNER|||ODR_LPF||||0x00|R/W|
|0x29|FIFO_SAMPLES|Reserved|FIFO_SAMPLES|||||||0x60|R/W|
|0x2A|INT_MAP|ACT_EN2|OVR_EN2|FULL_EN2|RDY_EN2|ACT_EN1|OVR_EN1|FULL_EN1|RDY_EN1|0x00|R/W|
|0x2B|Sync|Reserved|||||EXT_CLK|EXT_SYNC||0x00|R/W|
|0x2C|Range|I2C_HS|INT_POL|Reserved||||Range||0x81|R/W|
|0x2D|POWER_CTL|Reserved|||||DRDY_OFF|TEMP_OFF|Standby|0x01|R/W|
|0x2E|SELF_TEST|Reserved||||||ST2|ST1|0x00|R/W|
|0x2F|Reset|Reset||||||||0x00|W|



> 1 For the ADXL357. 

> 2 For the ADXL357B. 

**Rev. C | 41 of 52** 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **REGISTER DEFINITIONS** 

This section describes the functions of the ADXL357/ADXL357B registers. The ADXL357/ADXL357B power up with the default register values, as shown in the reset column of Table 16. 

## **ANALOG DEVICES ID REGISTER** 

This register contains the Analog Devices ID, 0xAD. 

## **Address: 0x00, Reset: 0xAD, Name: DEVID_AD** 

_**Table 17. Bit Descriptions for DEVID_AD**_ 

|**_Table 17. Bit Descriptions for DEVID_AD_**|**_Table 17. Bit Descriptions for DEVID_AD_**|**_Table 17. Bit Descriptions for DEVID_AD_**|**_Table 17. Bit Descriptions for DEVID_AD_**|**_Table 17. Bit Descriptions for DEVID_AD_**|**_Table 17. Bit Descriptions for DEVID_AD_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|DEVID_AD||Analog Devices ID|0xAD|R|



## **ANALOG DEVICES MEMS ID REGISTER** 

This register contains the Analog Devices MEMS ID, 0x1D. 

## **Address: 0x01, Reset: 0x1D, Name: DEVID_MST** 

_**Table 18. Bit Descriptions for DEVID_MST**_ 

|**_Table 18. Bit Descriptions for DEVID_MST_**|**_Table 18. Bit Descriptions for DEVID_MST_**|**_Table 18. Bit Descriptions for DEVID_MST_**|**_Table 18. Bit Descriptions for DEVID_MST_**|**_Table 18. Bit Descriptions for DEVID_MST_**|**_Table 18. Bit Descriptions for DEVID_MST_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|DEVID_MST||Analog Devices MEMS ID|0x1D|R|



## **DEVICE ID REGISTER** 

This register contains the device ID, 0xED (355 octal). 

## **Address: 0x02, Reset: 0xED/0xE9, Name: PARTID** 

_**Table 19. Bit Descriptions for PARTID**_ 

|**_Table 19. Bit Descriptions for PARTID_**|**_Table 19. Bit Descriptions for PARTID_**|**_Table 19. Bit Descriptions for PARTID_**|**_Table 19. Bit Descriptions for PARTID_**|**_Table 19. Bit Descriptions for PARTID_**|**_Table 19. Bit Descriptions for PARTID_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|PARTID||Device ID|0xED (for the<br>ADXL357), 0xE9<br>(for the<br>ADXL357B)|R|



## **PRODUCT REVISION ID REGISTER** 

This register contains the product revision ID, beginning with 0x00 and incrementing for each subsequent revision. 

## **Address: 0x03, Reset: 0x01, Name: REVID** 

_**Table 20. Bit Descriptions for REVID**_ 

|**_Table 20. Bit Descriptions for REVID_**|**_Table 20. Bit Descriptions for REVID_**|**_Table 20. Bit Descriptions for REVID_**|**_Table 20. Bit Descriptions for REVID_**|**_Table 20. Bit Descriptions for REVID_**|**_Table 20. Bit Descriptions for REVID_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|REVID||Mask revision|0x01 (for the<br>ADXL357); 0x00 (for<br>the ADXL357B)|R|



## **STATUS REGISTER** 

This register includes bits that describe the various conditions of the ADXL357/ADXL357B. 

**Rev. C | 42 of 52** 

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Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **REGISTER DEFINITIONS** 

## **Address: 0x04, Reset: 0x00, Name: Status** 

_**Table 21. Bit Descriptions for Status**_ 

|**_Table 21. Bit Descriptions for Status_**|**_Table 21. Bit Descriptions for Status_**|**_Table 21. Bit Descriptions for Status_**|**_Table 21. Bit Descriptions for Status_**|**_Table 21. Bit Descriptions for Status_**|**_Table 21. Bit Descriptions for Status_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:5]<br>4<br>3<br>2<br>1<br>0|Reserved<br>NVM_BUSY<br>Activity<br>FIFO_OVR<br>FIFO_FULL<br>DATA_RDY||Reserved.<br>NVM controller is busy with a refresh, programming, or a built in self test (BIST).<br>Activity, as defined in the ACT_THRESH_x and ACT_COUNT registers, is detected.<br>FIFO has overrun, and the oldest data is lost.<br>FIFO watermark is reached.<br>A complete x-axis, y-axis, and z-axis measurement was made and results can be read.|0x0<br>0x0<br>0x0<br>0x0<br>0x0<br>0x0|R<br>R<br>R<br>R<br>R<br>R|



## **FIFO ENTRIES REGISTER** 

This register indicates the number of valid data samples present in the FIFO buffer. This number ranges from 0 to 96. 

## **Address: 0x05, Reset: 0x00, Name: FIFO_ENTRIES** 

_**Table 22. Bit Descriptions for FIFO_ENTRIES**_ 

|**_Table 22. Bit Descriptions for FIFO_ENTRIES_**|**_Table 22. Bit Descriptions for FIFO_ENTRIES_**|**_Table 22. Bit Descriptions for FIFO_ENTRIES_**|**_Table 22. Bit Descriptions for FIFO_ENTRIES_**|**_Table 22. Bit Descriptions for FIFO_ENTRIES_**|**_Table 22. Bit Descriptions for FIFO_ENTRIES_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|7|Reserved||Reserved|0x0|R|
|[6:0]|FIFO_ENTRIES||Number of data samples stored in the FIFO|0x0|R|



## **TEMPERATURE DATA REGISTERS** 

These two registers contain the uncalibrated temperature data. The nominal intercept is 1885 LSB at 25°C and the nominal slope is −9.05 LSB/°C. TEMP2 contains the four most significant bits, and TEMP1 contains the eight least significant bits of the 12-bit value. The ADXL357/ADXL357B temperature value is not double buffered, meaning the value can update between reading of the two registers. 

## **Address: 0x06, Reset: 0x00, Name: TEMP2** 

_**Table 23. Bit Descriptions for TEMP2**_ 

|**_Table 23. Bit Descriptions for TEMP2_**|**_Table 23. Bit Descriptions for TEMP2_**|**_Table 23. Bit Descriptions for TEMP2_**|**_Table 23. Bit Descriptions for TEMP2_**|**_Table 23. Bit Descriptions for TEMP2_**|**_Table 23. Bit Descriptions for TEMP2_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:4]|Reserved||Reserved|||
|[3:0]|Temperature, Bits[11:8]||Uncalibrated temperature data|0x0|R|



## **Address: 0x07, Reset: 0x00, Name: TEMP1** 

_**Table 24. Bit Descriptions for TEMP1**_ 

|**_Table 24. Bit Descriptions for TEMP1_**|**_Table 24. Bit Descriptions for TEMP1_**|**_Table 24. Bit Descriptions for TEMP1_**|**_Table 24. Bit Descriptions for TEMP1_**|**_Table 24. Bit Descriptions for TEMP1_**|**_Table 24. Bit Descriptions for TEMP1_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|Temperature, Bits[7:0]||Uncalibrated temperature data|0x00|R|



## **X-AXIS DATA REGISTERS** 

These three registers contain the x-axis acceleration data. Data is left justified and formatted as twos complement. 

## **Address: 0x08, Reset: 0x00, Name: XDATA3** 

_**Table 25. Bit Descriptions for XDATA3**_ 

|**_Table 25. Bit Descriptions for XDATA3_**|**_Table 25. Bit Descriptions for XDATA3_**|**_Table 25. Bit Descriptions for XDATA3_**|**_Table 25. Bit Descriptions for XDATA3_**|**_Table 25. Bit Descriptions for XDATA3_**|**_Table 25. Bit Descriptions for XDATA3_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|XDATA, Bits[19:12]||X-axis data|0x00|R|



**Rev. C | 43 of 52** 

**analog.com** 

Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **REGISTER DEFINITIONS** 

## **Address: 0x09, Reset: 0x00, Name: XDATA2** 

_**Table 26. Bit Descriptions for XDATA2**_ 

|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|
|---|---|---|---|---|---|
|[7:0]|XDATA, Bits[11:4]||X-axis data|0x00|R|



## **Address: 0x0A, Reset: 0x00, Name: XDATA1** 

## _**Table 27. Bit Descriptions for XDATA1**_ 

|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|
|---|---|---|---|---|---|
|[7:4]|XDATA, Bits[3:0]||X-axis data|0x0|R|
|[3:0]|Reserved||Reserved|0x0|R|



## **Y-AXIS DATA REGISTERS** 

These three registers contain the y-axis acceleration data. Data is left justified and formatted as twos complement. 

## **Address: 0x0B, Reset: 0x00, Name: YDATA3** 

## _**Table 28. Bit Descriptions for YDATA3**_ 

|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|
|---|---|---|---|---|---|
|[7:0]|YDATA, Bits[19:12]||Y-axis data|0x00|R|



## **Address: 0x0C, Reset: 0x00, Name: YDATA2** 

_**Table 29. Bit Descriptions for YDATA2**_ 

|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|
|---|---|---|---|---|---|
|[7:0]|YDATA, Bits[11:4]||Y-axis data|0x00|R|



## **Address: 0x0D, Reset: 0x00, Name: YDATA1** 

_**Table 30. Bit Descriptions for YDATA1**_ 

|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|
|---|---|---|---|---|---|
|[7:4]|YDATA, Bits[3:0]||Y-axis data|0x0|R|
|[3:0]|Reserved||Reserved|0x0|R|



## **Z-AXIS DATA REGISTERS** 

These three registers contain the z-axis acceleration data. Data is left justified and formatted as twos complement. 

## **Address: 0x0E, Reset: 0x00, Name: ZDATA3** 

_**Table 31. Bit Descriptions for ZDATA3**_ 

|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|
|---|---|---|---|---|---|---|---|
|[7:0]|ZDATA, Bits[19:12]||||Z-axis data|0x00|R|
|**Address: 0x0F, Reset: 0x00, Name: ZDATA2**<br>**_Table 32. Bit Descriptions for ZDATA2_**||||||||
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||||
|[7:0]|ZDATA, Bits[11:4]|||Z-axis data||0x00|R|



**Rev. C | 44 of 52** 

**analog.com** 

Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **REGISTER DEFINITIONS** 

## **Address: 0x10, Reset: 0x00, Name: ZDATA1** 

_**Table 33. Bit Descriptions for ZDATA1**_ 

|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|
|---|---|---|---|---|---|
|[7:4]|ZDATA, Bits[3:0]||Z-axis data|0x0|R|
|[3:0]|Reserved||Reserved|0x0|R|



## **FIFO ACCESS REGISTER** 

## **Address: 0x11, Reset: 0x00, Name: FIFO_DATA** 

Read this register to access data stored in the FIFO. 

_**Table 34. Bit Descriptions for FIFO_DATA**_ 

|**_Table 34. Bit Descriptions for FIFO_DATA_**|**_Table 34. Bit Descriptions for FIFO_DATA_**|**_Table 34. Bit Descriptions for FIFO_DATA_**|**_Table 34. Bit Descriptions for FIFO_DATA_**|**_Table 34. Bit Descriptions for FIFO_DATA_**|**_Table 34. Bit Descriptions for FIFO_DATA_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|FIFO_DATA||FIFO data is formatted to 24 bits, three bytes, most significant byte first. A read to this address pops an<br>effective three equal byte words of axis data from the FIFO. Two subsequent reads or a multibyte read<br>completes the transaction of this data onto the interface. Continued reading or a sustained multibyte read<br>of this field continues to pop the FIFO every third byte. Multibyte reads to this address do not increment<br>the address pointer. If this address is read due to an auto-increment from the previous address, it does<br>not pop the FIFO. Instead, it returns zeros and increments on to the next address.|0x0|R|



## **X-AXIS OFFSET TRIM REGISTERS** 

## **Address: 0x1E, Reset: 0x00, Name: OFFSET_X_H** 

_**Table 35. Bit Descriptions for OFFSET_X_H**_ 

|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|
|---|---|---|---|---|---|
|[7:0]|OFFSET_X,<br>Bits[15:8]||Offset added to x-axis data after all other signal processing. Data is in twos complement format. The<br>significance of OFFSET_X, Bits[15:0] matches the significance of XDATA, Bits[19:4].|0x0|R/W|



## **Address: 0x1F, Reset: 0x00, Name: OFFSET_X_L** 

_**Table 36. Bit Descriptions for OFFSET_X_L**_ 

|**_Table 36. Bit Descriptions for OFFSET_X_L_**|**_Table 36. Bit Descriptions for OFFSET_X_L_**|**_Table 36. Bit Descriptions for OFFSET_X_L_**|**_Table 36. Bit Descriptions for OFFSET_X_L_**|**_Table 36. Bit Descriptions for OFFSET_X_L_**|**_Table 36. Bit Descriptions for OFFSET_X_L_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|OFFSET_X,<br>Bits[7:0]||Offset added to x-axis data after all other signal processing. Data is in twos complement format. The<br>significance of OFFSET_X, Bits[15:0] matches the significance of XDATA, Bits[19:4].|0x0|R/W|



## **Y-AXIS OFFSET TRIM REGISTERS** 

## **Address: 0x20, Reset: 0x00, Name: OFFSET_Y_H** 

_**Table 37. Bit Descriptions for OFFSET_Y_H**_ 

|**_Table 37. Bit Descriptions for OFFSET_Y_H_**|**_Table 37. Bit Descriptions for OFFSET_Y_H_**|**_Table 37. Bit Descriptions for OFFSET_Y_H_**|**_Table 37. Bit Descriptions for OFFSET_Y_H_**|**_Table 37. Bit Descriptions for OFFSET_Y_H_**|**_Table 37. Bit Descriptions for OFFSET_Y_H_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|OFFSET_Y,<br>Bits[15:8]||Offset added to y-axis data after all other signal processing. Data is in twos complement format. The<br>significance of OFFSET_Y, Bits[15:0] matches the significance of YDATA, Bits[19:4].|0x0|R/W|



## **Address: 0x21, Reset: 0x00, Name: OFFSET_Y_L** 

## _**Table 38. Bit Descriptions for OFFSET_Y_L**_ 

|**_Table 38. Bit Descriptions for OFFSET_Y_L_**|**_Table 38. Bit Descriptions for OFFSET_Y_L_**|**_Table 38. Bit Descriptions for OFFSET_Y_L_**|**_Table 38. Bit Descriptions for OFFSET_Y_L_**|**_Table 38. Bit Descriptions for OFFSET_Y_L_**|**_Table 38. Bit Descriptions for OFFSET_Y_L_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|OFFSET_Y,<br>Bits[7:0]||Offset added to y-axis data after all other signal processing. Data is in twos complement format. The<br>significance of OFFSET_Y, Bits[15:0] matches the significance of YDATA, Bits[19:4].|0x0|R/W|



**Rev. C | 45 of 52** 

**analog.com** 

Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **REGISTER DEFINITIONS** 

## **Z-AXIS OFFSET TRIM REGISTERS** 

## **Address: 0x22, Reset: 0x00, Name: OFFSET_Z_H** 

## _**Table 39. Bit Descriptions for OFFSET_Z_H**_ 

|**_Table 39. Bit Descriptions for OFFSET_Z_H_**|**_Table 39. Bit Descriptions for OFFSET_Z_H_**|**_Table 39. Bit Descriptions for OFFSET_Z_H_**|**_Table 39. Bit Descriptions for OFFSET_Z_H_**|**_Table 39. Bit Descriptions for OFFSET_Z_H_**|**_Table 39. Bit Descriptions for OFFSET_Z_H_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|OFFSET_Z,<br>Bits[15:8]||Offset added to z-axis data after all other signal processing. Data is in twos complement format. The<br>significance of OFFSET_Z, Bits[15:0] matches the significance of ZDATA, Bits[19:4].|0x0|R/W|



## **Address: 0x23, Reset: 0x00, Name: OFFSET_Z_L** 

_**Table 40. Bit Descriptions for OFFSET_Z_L**_ 

|**_Table 40. Bit Descriptions for OFFSET_Z_L_**|**_Table 40. Bit Descriptions for OFFSET_Z_L_**|**_Table 40. Bit Descriptions for OFFSET_Z_L_**|**_Table 40. Bit Descriptions for OFFSET_Z_L_**|**_Table 40. Bit Descriptions for OFFSET_Z_L_**|**_Table 40. Bit Descriptions for OFFSET_Z_L_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|OFFSET_Z,<br>Bits[7:0]||Offset added to z-axis data after all other signal processing. Data is in twos complement format. The<br>significance of OFFSET_Z, Bits[15:0] matches the significance of ZDATA, Bits[19:4].|0x0|R/W|



## **ACTIVITY ENABLE REGISTER** 

## **Address: 0x24, Reset: 0x00, Name: ACT_EN** 

_**Table 41. Bit Descriptions for ACT_EN**_ 

|**_Table 41. Bit Descriptions for ACT_EN_**|**_Table 41. Bit Descriptions for ACT_EN_**|**_Table 41. Bit Descriptions for ACT_EN_**|**_Table 41. Bit Descriptions for ACT_EN_**|**_Table 41. Bit Descriptions for ACT_EN_**|**_Table 41. Bit Descriptions for ACT_EN_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:3]|Reserved||Reserved.|0x0|R|
|2|ACT_Z||Z-axis data is a component of the activity detection algorithm.|0x0|R/W|
|1|ACT_Y||Y-axis data is a component of the activity detection algorithm.|0x0|R/W|
|0|ACT_X||X-axis data is a component of the activity detection algorithm.|0x0|R/W|



## **ACTIVITY THRESHOLD REGISTERS** 

## **Address: 0x25, Reset: 0x00, Name: ACT_THRESH_H** 

_**Table 42. Bit Descriptions for ACT_THRESH_H**_ 

|**_Table 42. Bit Descriptions for ACT_THRESH_H_**|**_Table 42. Bit Descriptions for ACT_THRESH_H_**|**_Table 42. Bit Descriptions for ACT_THRESH_H_**|**_Table 42. Bit Descriptions for ACT_THRESH_H_**|**_Table 42. Bit Descriptions for ACT_THRESH_H_**|**_Table 42. Bit Descriptions for ACT_THRESH_H_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|ACT_THRESH,<br>Bits[15:8]||Threshold for activity detection. Acceleration magnitude must be above ACT_THRESH to<br>trigger the activity counter. ACT_THRESH is an unsigned magnitude. The significance of<br>ACT_THRESH, Bits[15:0] matches the significance of Bits[18:3] of XDATA, YDATA, and<br>ZDATA.|0x0|R/W|



## **Address: 0x26, Reset: 0x00, Name: ACT_THRESH_L** 

_**Table 43. Bit Descriptions for ACT_THRESH_L**_ 

|**_Table 43. Bit Descriptions for ACT_THRESH_L_**|**_Table 43. Bit Descriptions for ACT_THRESH_L_**|**_Table 43. Bit Descriptions for ACT_THRESH_L_**|**_Table 43. Bit Descriptions for ACT_THRESH_L_**|**_Table 43. Bit Descriptions for ACT_THRESH_L_**|**_Table 43. Bit Descriptions for ACT_THRESH_L_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|ACT_THRESH,<br>Bits[7:0]||Threshold for activity detection. The acceleration magnitude must be greater than the value<br>in ACT_THRESH to trigger the activity counter. ACT_THRESH is an unsigned magnitude.<br>The significance of ACT_THRESH, Bits[15:0] matches the significance of Bits[18:3] of XDATA,<br>YDATA, and ZDATA.|0x0|R/W|



**Rev. C | 46 of 52** 

**analog.com** 

Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **REGISTER DEFINITIONS** 

## **ACTIVITY COUNT REGISTER** 

## **Address: 0x27, Reset: 0x01, Name: ACT_COUNT** 

_**Table 44. Bit Descriptions for ACT_COUNT**_ 

|**_Table 44. Bit Descriptions for ACT_COUNT_**|**_Table 44. Bit Descriptions for ACT_COUNT_**|**_Table 44. Bit Descriptions for ACT_COUNT_**|**_Table 44. Bit Descriptions for ACT_COUNT_**|**_Table 44. Bit Descriptions for ACT_COUNT_**|**_Table 44. Bit Descriptions for ACT_COUNT_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|ACT_COUNT||Number of consecutive events above threshold (from ACT_THRESH) required to detect activity|0x1|R/W|



## **FILTER SETTINGS REGISTER** 

## **Address: 0x28, Reset: 0x00, Name: Filter** 

Use this register to specify parameters for the internal high-pass and low-pass filters. 

_**Table 45. Bit Descriptions for Filter**_ 

|**_Table 45. Bit Descriptions for Filter_**|**_Table 45. Bit Descriptions for Filter_**|**_Table 45. Bit Descriptions for Filter_**|**_Table 45. Bit Descriptions for Filter_**|**_Table 45. Bit Descriptions for Filter_**|**_Table 45. Bit Descriptions for Filter_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|7|Reserved||Reserved|0x0|R|
|[6:4]|HPF_CORNER|000<br>001<br>010<br>011<br>100<br>101<br>110|−3 dB filter corner for the first-order, high-pass filter relative to the ODR<br>Not applicable, no high-pass filter enabled<br>24.7 × 10−4× ODR<br>6.2084 × 10−4× ODR<br>1.5545 × 10−4× ODR<br>0.3862 × 10−4× ODR<br>0.0954 × 10−4× ODR<br>0.0238 × 10−4× ODR|0x0|R/W|
|[3:0]|ODR_LPF|0000<br>0001<br>0010<br>0011<br>0100<br>0101<br>0110<br>0111<br>1000<br>1001<br>1010|ODR and low-pass filter corner<br>4000 Hz and 1000 Hz<br>2000 Hz and 500 Hz<br>1000 Hz and 250 Hz<br>500 Hz and 125 Hz<br>250 Hz and 62.5 Hz<br>125 Hz and 31.25 Hz<br>62.5 Hz and 15.625 Hz<br>31.25 Hz and 7.813 Hz<br>15.625 Hz and 3.906 Hz<br>7.813 Hz and 1.953 Hz<br>3.906 Hz and 0.977 Hz|0x0|R/W|



## **FIFO SAMPLES REGISTER** 

## **Address: 0x29, Reset: 0x60, Name: FIFO_SAMPLES** 

Use the FIFO_SAMPLES value to specify the number of samples to store in the FIFO. The default value of this register is 0x60 to avoid triggering the FIFO watermark interrupt. 

_**Table 46. Bit Descriptions for FIFO_SAMPLES**_ 

|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|
|---|---|---|---|---|---|
|7|Reserved||Reserved.|0x0|R|
|[6:0]|FIFO_SAMPLES||Watermark number of samples stored in the FIFO that triggers a FIFO_FULL condition. Values range<br>from 1 to 96.|0x60|R/W|



**Rev. C | 47 of 52** 

**analog.com** 

Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

**REGISTER DEFINITIONS** 

## **INTERRUPT PIN (INTX) FUNCTION MAP REGISTER** 

## **Address: 0x2A, Reset: 0x00, Name: INT_MAP** 

The INT_MAP register configures the interrupt pins. Bits[7:0] select which functions generate an interrupt on the INT1 and INT2 pins. Multiple events can be configured. If the corresponding bit is set to 1, the function generates an interrupt on the interrupt pins. 

_**Table 47. Bit Descriptions for INT_MAP**_ 

|**_Table 47. Bit Descriptions for INT_MAP_**|**_Table 47. Bit Descriptions for INT_MAP_**|**_Table 47. Bit Descriptions for INT_MAP_**|**_Table 47. Bit Descriptions for INT_MAP_**|**_Table 47. Bit Descriptions for INT_MAP_**|**_Table 47. Bit Descriptions for INT_MAP_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|7|ACT_EN2||Activity interrupt enable on INT2|0x0|R/W|
|6|OVR_EN2||FIFO_OVR interrupt enable on INT2|0x0|R/W|
|5|FULL_EN2||FIFO_FULL interrupt enable on INT2|0x0|R/W|
|4|RDY_EN2||DATA_RDY interrupt enable on INT2|0x0|R/W|
|3|ACT_EN1||Activity interrupt enable on INT1|0x0|R/W|
|2|OVR_EN1||FIFO_OVR interrupt enable on INT1|0x0|R/W|
|1|FULL_EN1||FIFO_FULL interrupt enable on INT1|0x0|R/W|
|0|RDY_EN1||DATA_RDY interrupt enable on INT1|0x0|R/W|



## **DATA SYNCHRONIZATION** 

## **Address: 0x2B, Reset: 0x00, Name: Sync** 

Use this register to control the external timing triggers. 

_**Table 48. Bit Descriptions for Sync**_ 

|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|
|---|---|---|---|---|---|
|[7:3]|Reserved||Reserved.|0x0|R|
|2|EXT_CLK||Enable external clock. SeeTable 15for configuration details.|0x0|R/W|
|[1:0]|EXT_SYNC|00<br>01<br>10<br>11|Enable external synchronization control.<br>Internal synchronization.<br>External synchronization, no interpolation filter. After synchronization, and for EXT_SYNC within<br>specification, DATA_RDY occurs on EXT_SYNC.<br>External synchronization, interpolation filter, next available data indicated by DATA_RDY 8 to 4102<br>oscillator cycles later (longer delay for higher ODR_LPF setting), data represents a sample point group<br>delay earlier in time.<br>Reserved.|0x0|R/W|



## **I[2] C SPEED, INTERRUPT POLARITY, AND RANGE REGISTER** 

## **Address: 0x2C, Reset: 0x81, Name: Range** 

_**Table 49. Bit Descriptions for Range**_ 

|**_Table 49. Bit Descriptions for Range_**|**_Table 49. Bit Descriptions for Range_**|**_Table 49. Bit Descriptions for Range_**|**_Table 49. Bit Descriptions for Range_**|**_Table 49. Bit Descriptions for Range_**|**_Table 49. Bit Descriptions for Range_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|7|I2C_HS|1<br>0|I2C speed.<br>High speed mode.<br>Fast mode.|0x1|R/W|
|6|INT_POL|0<br>1|Interrupt polarity.<br>INT1 and INT2 are active low.<br>INT1 and INT2 are active high.|0x0|R/W|
|[5:2]|Reserved||Reserved.|0x0|R|
|[1:0]|Range|01|Range.<br>±10_g_.|0x1|R/W|



**Rev. C | 48 of 52** 

**analog.com** 

Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **REGISTER DEFINITIONS** 

_**Table 49. Bit Descriptions for Range (Continued)**_ 

|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**|
|---|---|---|---|---|---|
|||10<br>11|±20_g_.<br>±40_g_.|||



## **POWER CONTROL REGISTER** 

## **Address: 0x2D, Reset: 0x01, Name: POWER_CTL** 

_**Table 50. Bit Descriptions for POWER_CTL**_ 

|**_Table 50. Bit Descriptions for POWER_CTL_**|**_Table 50. Bit Descriptions for POWER_CTL_**|**_Table 50. Bit Descriptions for POWER_CTL_**|**_Table 50. Bit Descriptions for POWER_CTL_**|**_Table 50. Bit Descriptions for POWER_CTL_**|**_Table 50. Bit Descriptions for POWER_CTL_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:3]|Reserved||Reserved.|0x0|R|
|2|DRDY_OFF||Set to 1 to force the DRDY output to 0 in modes where it is normally signal data ready.|0x0|R/W|
|1|TEMP_OFF||Set to 1 to disable temperature processing. Temperature processing is also disabled when standby = 1.|0x0|R/W|
|0|Standby|1<br>0|Standby or measurement mode.<br>Standby mode. In standby mode, the device is in a low power state, and the temperature and acceleration<br>datapaths are not operating. In addition, digital functions, including FIFO pointers, reset. Changes to the<br>configuration setting of the device must be made when standby = 1. An exception is a high-pass filter that<br>can be changed when the device is operating.<br>Measurement mode.|0x1|R/W|



## **SELF TEST REGISTER** 

## **Address: 0x2E, Reset: 0x00, Name: SELF_TEST** 

Refer to the Self Test section for more information on the operation of the self test feature. 

_**Table 51. Bit Descriptions for SELF_TEST**_ 

|**_Table 51. Bit Descriptions for SELF_TEST_**|**_Table 51. Bit Descriptions for SELF_TEST_**|**_Table 51. Bit Descriptions for SELF_TEST_**|**_Table 51. Bit Descriptions for SELF_TEST_**|**_Table 51. Bit Descriptions for SELF_TEST_**|**_Table 51. Bit Descriptions for SELF_TEST_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:2]<br>1<br>0|Reserved<br>ST2<br>ST1||Reserved.<br>Set to 1 to enable self test force<br>Set to 1 to enable self test mode|0x0<br>0x0<br>0x0|R<br>R/W<br>R/W|



## **RESET REGISTER** 

## **Address: 0x2F, Reset: 0x00, Name: Reset** 

_**Table 52. Bit Descriptions for Reset**_ 

|**_Table 52. Bit Descriptions for Reset_**|**_Table 52. Bit Descriptions for Reset_**|**_Table 52. Bit Descriptions for Reset_**|**_Table 52. Bit Descriptions for Reset_**|**_Table 52. Bit Descriptions for Reset_**|**_Table 52. Bit Descriptions for Reset_**|
|---|---|---|---|---|---|
|**Bits**<br>**Bit Name**<br>**Settings**<br>**Description**<br>**Reset**<br>**Access**||||||
|[7:0]|Reset||Write Code 0x52 to reset the device, similar to a power-on reset (POR)|0x0|W|



For the ADXL357 (fixed on the ADXL357B), in case of a software reset, an unlikely race condition may occur. If the race condition occurs, some factory settings in the NVM load incorrectly to shadow registers (the registers from which the internal logic configures the sensor and calculates the output after a power-on or a software reset). The incorrect loading of the NVM affects overall performance of the sensor, such as an incorrect _0 g_ bias and other performance issues. The incorrect loading of NVM does not occur from a power-on or after a power cycle. To guarantee reliable operation of the sensor after a software reset, the user can access the shadow registers after a power-on, read and store the values on the host microprocessor, and compare the values read from the same shadow registers after a software reset. This method guarantees proper operation in all devices and under all conditions. The recommended steps are as follows: 

**1.** Read the shadow registers, Register 0x50 to Register 0x54 (five 8-bit registers) after power-up, but before any software reset. 

**2.** Store these values in a host device (for example, a host microprocessor). 

**3.** After each software reset, read the same five registers. If the values differ, perform a software reset again until they match. 

**Rev. C | 49 of 52** 

**analog.com** 

Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **PCB FOOTPRINT PATTERN** 

Figure 104 shows the PCB footprint pattern and dimensions in millimeters. 

**==> picture [219 x 180] intentionally omitted <==**

_**Figure 104. PCB Footprint Pattern and Dimensions in Millimeters**_ 

**Rev. C | 50 of 52** 

**analog.com** 

Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **OUTLINE DIMENSIONS** 

|**Package Drawing (Option)**<br>**Package Type**<br>**Package Description**|**Package Drawing (Option)**<br>**Package Type**<br>**Package Description**|**Package Drawing (Option)**<br>**Package Type**<br>**Package Description**|
|---|---|---|
|E-14-1|LCC|14-Terminal Ceramic Leadless Chip Carrier|



For the latest package outline information and land patterns (footprints), go to Package Index. 

Updated: March 13, 2024 

## **ORDERING GUIDE** 

|**ORDERING GUIDE**|**ORDERING GUIDE**|**ORDERING GUIDE**|**ORDERING GUIDE**|**ORDERING GUIDE**|
|---|---|---|---|---|
|**Model1**<br>**Temperature Range**<br>**Package Description**<br>**Packing Quantity**<br>**Package**<br>**Option**|||||
|ADXL356BEZ<br>ADXL356BEZ-RL<br>ADXL356BEZ-RL7<br>ADXL356CEZ<br>ADXL356CEZ-RL<br>ADXL356CEZ-RL7<br>ADXL357BEZ<br>ADXL357BEZ-RL<br>ADXL357BEZ-RL7<br>ADXL357BBEZ<br>ADXL357BBEZ-RL<br>ADXL357BBEZ-RL7|+40°C to +125°C<br>+40°C to +125°C<br>+40°C to +125°C<br>+40°C to +125°C<br>+40°C to +125°C<br>+40°C to +125°C<br>-40°C to +125°C<br>-40°C to +125°C<br>-40°C to +125°C<br>-40°C to +125°C<br>-40°C to +125°C<br>-40°C to +125°C|14-Lead LCC (6mm x 6mm)<br>14-Lead LCC (6mm x 6mm)<br>14-Lead LCC (6mm x 6mm)<br>14-Lead LCC (6mm x 6mm)<br>14-Lead LCC (6mm x 6mm)<br>14-Lead LCC (6mm x 6mm)<br>14-Lead LCC (6mm x 6mm)<br>14-Lead LCC (6mm x 6mm)<br>14-Lead LCC (6mm x 6mm)<br>14-Lead LCC (6mm x 6mm)<br>14-Lead LCC (6mm x 6mm)<br>14-Lead LCC (6mm x 6mm)|Tray, 280<br>Reel, 2000<br>Reel, 500<br>Tray, 280<br>Reel, 2000<br>Reel, 500<br>Tray, 280<br>Reel, 2000<br>Reel, 500<br>Tray, 280<br>Reel, 2000<br>Reel, 500|E-14-1<br>E-14-1<br>E-14-1<br>E-14-1<br>E-14-1<br>E-14-1<br>E-14-1<br>E-14-1<br>E-14-1<br>E-14-1<br>E-14-1<br>E-14-1|



> 1 Z = RoHS Compliant Part. 

## **OUTPUT MODE, MEASUREMENT RANGE, AND SPECIFIED VOLTAGE OPTIONS** 

|**OUTPUT MODE, MEASUREMENT RANGE, AND SPECIFIED VOLTAGE OPTIONS**|**OUTPUT MODE, MEASUREMENT RANGE, AND SPECIFIED VOLTAGE OPTIONS**|**OUTPUT MODE, MEASUREMENT RANGE, AND SPECIFIED VOLTAGE OPTIONS**|**OUTPUT MODE, MEASUREMENT RANGE, AND SPECIFIED VOLTAGE OPTIONS**|
|---|---|---|---|
|**Model1**<br>**Output Mode**<br>**Measurement Range (****_g_)**<br>**Specified Voltage (V)**||||
|ADXL356BEZ<br>ADXL356BEZ-RL<br>ADXL356BEZ-RL7<br>ADXL356CEZ<br>ADXL356CEZ-RL<br>ADXL356CEZ-RL7<br>ADXL357BEZ<br>ADXL357BEZ-RL<br>ADXL357BEZ-RL7<br>ADXL357BBEZ<br>ADXL357BBEZ-RL<br>ADXL357BBEZ-RL7|Analog<br>Analog<br>Analog<br>Analog<br>Analog<br>Analog<br>Digital<br>Digital<br>Digital<br>Digital<br>Digital<br>Digital|±10, ±20<br>±10, ±20<br>±10, ±20<br>±10, ±40<br>±10, ±40<br>±10, ±40<br>±10, ±20, ±40<br>±10, ±20, ±40<br>±10, ±20, ±40<br>±10, ±20, ±40<br>±10, ±20, ±40<br>±10, ±20, ±40|3.3<br>3.3<br>3.3<br>3.3<br>3.3<br>3.3<br>3.3<br>3.3<br>3.3<br>3.3<br>3.3<br>3.3|



> 1 Z = RoHS Compliant Part. 

**Rev. C | 51 of 52** 

**analog.com** 

Data Sheet 

**ADXL356/ADXL357/ADXL357B** 

## **OUTLINE DIMENSIONS** 

## **EVALUATION BOARDS** 

|**EVALUATION BOARDS**|**EVALUATION BOARDS**|
|---|---|
|**Model1**<br>**Description**||
|EVAL-ADXL356BZ<br>EVAL-ADXL356CZ<br>EVAL-ADXL357Z<br>EVAL-ADXL357BZ|Evaluation Board for ADXL356B<br>Evaluation Board for ADXL356C<br>Evaluation Board for ADXL357<br>Evaluation Board for ADXL357B|



> 1 Z = RoHS Compliant Part. 

I[2] C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). 

**==> picture [111 x 32] intentionally omitted <==**

©2017-2024 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. One Analog Way, Wilmington, MA 01887-2356, U.S.A. 

**Rev. C | 52 of 52**
Updated at April 28, 2026
Since its inception in 1965, Analog Devices has established itself as a global leader in the design and manufacturing of high-performance analog, mixed-signal, and digital signal processing (DSP) integrated circuits. The company is renowned for solving complex engineering challenges by providing critical technologies that seamlessly convert real-world phenomena into precise electrical signals for the industrial, automotive, communications, and consumer markets. Within its extensive portfolio, Analog Devices provides highly reliable clock, timing, and frequency management solutions, featuring a comprehensive array of precision timers, oscillators, and pulse generators. Complementing this core lineup is a robust offering of driver and interface ICs, particularly high-performance I/O expanders that enable seamless connectivity and streamline complex electronic system architectures. Beyond these foundational integrated circuits, Analog Devices leads the industry in sensor innovation, delivering advanced MEMS accelerometers and integrated MEMS modules designed for exceptional precision in motion sensing. To support complete hardware designs, the company's specialized offerings also encompass discrete bipolar transistors, sub-2.4GHz RF transceivers, temperature-compensated oscillators, and dedicated power management components such as DC/DC converters and LED driver ICs.
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