ADXL354BEZ-RL

MEMS Accelerometer, ± 2g, ± 4g, X, Y, Z, LCC, 14 Pins, 400mV/g, 200mV/g

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Manufacturer: ANALOG DEVICES
Product type: MEMS Accelerometers
SVHC: Lead (04-Feb-2026)
No. of Pins: 14Pins
Sensing Axis: X, Y, Z
Product Range: -
Qualification: -
Sensitivity Max: 432mV/g, 216mV/g
Sensitivity Min: 368mV/g, 184mV/g
Sensitivity Typ: 400mV/g, 200mV/g
Sensor Case Style: LCC
MEMS Sensor Output: Analogue
Supply Voltage Max: 3.6V
Supply Voltage Min: 2.25V
Sensor Case / Package: LCC
Sensing Range - Accelerometer: ± 2g, ± 4g
Delivery and price
Units per pack	2000
Price	39.52 €
Current stock	10+
Lead time	30 days
Datasheet
**==> picture [160 x 45] intentionally omitted <==**

## **Low Noise, Low Drift, Low Power, 3-Axis MEMS Accelerometers** 

## **Data Sheet** 

## **ADXL354/ADXL355** 

## **FEATURES** 

## **Hermetic package offers optimal long-term stability** 

- **0** _**g**_ **offset vs. temperature (all axes): 0.15 m** _**g**_ **/°C maximum Ultralow noise spectral density, all axes: 22.5 μ** _**g**_ **/√Hz** 

- **Low power, VSUPPLY (LDO regulator enabled)** 

- **ADXL354 in measurement mode: 150 μA ADXL355 in measurement mode: 200 μA ADXL354/ADXL355 in standby mode: 21 μA** 

- **ADXL354 has user adjustable analog output bandwidth ADXL355 digital output features** 

- **Digital SPI and I[2] C interfaces supported 20-bit ADC** 

**Data interpolation routine for synchronous sampling Programmable high- and low-pass digital filters** 

## **Electromechanical self test Integrated temperature sensor Voltage range options** 

- **VSUPPLY with internal regulators: 2.25 V to 3.6 V** 

- **V1P8ANA, V1P8DIG with internal LDO regulator bypassed: 1.8 V typical ± 10%** 

**Operating temperature range: −40°C to +125°C** 

**14-terminal, 6 mm × 5.6 mm × 2.2 mm, LCC package** 

## **FUNCTIONAL BLOCK DIAGRAMS** 

**==> picture [231 x 254] intentionally omitted <==**

**----- Start of picture text -----**<br>
V1P8ANA V1P8DIG RANGE<br>VSUPPLY LDO LDO MANAGEMENTPOWER<br>XOUT<br>YOUT ANALOGFILTER ST1<br>3-AXIS<br>OUT SENSOR CONTROL ST2<br>LOGIC STBY<br>TEMP SENSORTEMP ADXL354 VDDIO<br>VSSIO VSS<br>Figure 1. ADXL354<br>V1P8ANA V1P8DIG VDDIO<br>POWER<br>VSUPPLY LDO LDO ADXL355 MANAGEMENT<br>ADC INT1<br>ANALOG ADC DIGITAL CONTROLLOGIC INT2<br>FILTER FILTER DRDY<br>3-AXIS ADC CS/SCL<br>SENSOR<br>SCLK/VSSIO<br>SENSORTEMP ADC FIFO SERIALI/O MOSI/SDA<br>MISO/ASEL<br>VSSIO VSS<br>Figure 2. ADXL355<br>14205-002<br>14205-001<br>**----- End of picture text -----**<br>


## **APPLICATIONS** 

## **Inertial measurement units (IMUs)/attitude and heading reference systems (AHRSs)** 

## **Platform stabilization systems Structural health monitoring Seismic imaging** 

## **Tilt sensing Robotics Condition monitoring** 

## **GENERAL DESCRIPTION** 

The analog output ADXL354 and the digital output ADXL355 are low noise density, low 0 _g_ offset drift, low power, 3-axis accelerometers with selectable measurement ranges. The ADXL354B supports the ±2 _g_ and ±4 _g_ ranges, the ADXL354C supports the ±2 _g_ and ±8 _g_ ranges, and the ADXL355 supports the ±2 _g_ , ±4 _g_ , and ±8 _g_ ranges. The ADXL354/ADXL355 offer industry leading noise, minimal offset drift over temperature, and long-term stability enabling precision applications with minimal calibration. 

Highly integrated in a compact form factor, the low power ADXL355 is ideal in an Internet of Things (IoT) sensor node and other wireless product designs. 

The ADXL355 multifunction pin names may be referenced by their relevant function only for either the serial peripheral interface (SPI) or I[2] C interface. 

1 Protected by U.S. Patents 8,472,270; 9,041,462; 8,665,627; 8,917,099; 6,892,576; 9,297,825; and 7,956,621. 

**Document Feedback** 

**Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.** 

**One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016–2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com** 

**ADXL354/ADXL355** 

**Data Sheet** 

## **TABLE OF CONTENTS** 

Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagrams ............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 Analog Output for the ADXL354 ............................................... 4 Digital Output for the ADXL355 ............................................... 5 SPI Digital Interface Characteristics for the ADXL355 .......... 7 I[2] C Digital Interface Characteristics for the ADXL355 ........... 8 Absolute Maximum Ratings ............................................................ 9 Thermal Resistance ...................................................................... 9 Recommended Soldering Profile ............................................... 9 ESD Caution .................................................................................. 9 Pin Configurations and Function Descriptions ......................... 10 Typical Performance Characteristics ........................................... 12 Root Allan Variance (RAV) ADXL355 Characteristics ......... 20 Theory of Operation ...................................................................... 21 Applications Information .............................................................. 22 Analog Output ............................................................................ 22 Digital Output ............................................................................. 22 Axes of Acceleration Sensitivity ............................................... 23 Power Sequencing ...................................................................... 23 Power Supply Description ......................................................... 23 Overrange Protection ................................................................. 23 Self Test ........................................................................................ 23 Filter ............................................................................................. 24 Serial Communications ................................................................. 26 SPI Protocol ................................................................................. 26 SPI Bus Sharing ........................................................................... 26 I[2] C Protocol ................................................................................. 27 Reading Acceleration or Temperature Data from the Interface ....................................................................................................... 27 FIFO ................................................................................................. 28 Interrupts ......................................................................................... 29 DATA_RDY ................................................................................. 29 

DRDY Pin .................................................................................... 29 FIFO_FULL ................................................................................. 29 FIFO_OVR .................................................................................. 29 Activity ......................................................................................... 29 NVM_BUSY ............................................................................... 29 External Synchronization and Interpolation .......................... 29 ADXL355 Register Map ................................................................. 32 Register Definitions........................................................................ 33 Analog Devices ID Register ...................................................... 33 Analog Devices MEMS ID Register ......................................... 33 Device ID Register ..................................................................... 33 Product Revision ID Register ................................................... 33 Status Register ............................................................................. 33 FIFO Entries Register ................................................................ 34 Temperature Data Registers ...................................................... 34 X-Axis Data Registers ................................................................ 34 Y-Axis Data Registers ................................................................ 35 Z-Axis Data Registers ................................................................ 35 FIFO Access Register ................................................................. 36 X-Axis Offset Trim Registers .................................................... 36 Y-Axis Offset Trim Registers .................................................... 36 Z-Axis Offset Trim Registers .................................................... 37 Activity Enable Register ............................................................ 37 Activity Threshold Registers ..................................................... 37 Activity Count Register ............................................................. 37 Filter Settings Register ............................................................... 38 FIFO Samples Register .............................................................. 38 Interrupt Pin (INTx) Function Map Register......................... 38 Data Synchronization ................................................................ 39 I[2] C Speed, Interrupt Polarity, and Range Register ................. 39 Power Control Register ............................................................. 39 Self Test Register ......................................................................... 40 Reset Register .............................................................................. 40 PCB Footprint Pattern ................................................................... 41 Outline Dimensions ....................................................................... 42 Ordering Guide .......................................................................... 42 

Rev. B | Page 2 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

## **REVISION HISTORY** 

## **6/2020—Rev. A to Rev. B** 

Changed VDD to VDDIO ................................................... Throughout Changes to Features Section, Applications Section, and General Description Section ........................................................................... 1 Changes to Table 1 ............................................................................ 4 Changes to Table 2 ............................................................................ 5 Change to Hysteresis of Schmitt Triggered Inputs parameter, Table 4 ................................................................................................. 6 Changes to Input Current Parameter, Table 3 ............................... 7 Changes to Acceleration (Any Axis, 0.5 ms) Parameter; Table 5, Thermal Resistance Section; and Table 6 ....................................... 9 Moved Recommended Soldering Profile Section, Figure 5, and Table 7 ................................................................................................. 9 Changes to Table 8 and Table 9 ..................................................... 10 Changes to Typical Performance Section and Figure 8 to Figure 13 ........................................................................................... 12 Changes to Figure 14 to Figure 19 ................................................ 13 Changes to Figure 20 to Figure 25 ................................................ 14 Changes to Figure 32 to Figure 37 ................................................ 16 Changes to Figure 38 to Figure 43 ................................................ 17 Changes to Figure 44 Caption and Figure 47 Caption ............... 18 Changes to Figure 50 to Figure 54 ................................................ 19 Changes to Theory of Operation Section .................................... 21 Added Applications Information Section .................................... 22 Changes to Power Sequencing Section, Overrange Protection Section, and Self Test Section ........................................................ 23 Changes to Filter Section, Figure 62, and Figure 63 ................... 24 Changes to Figure 64 ...................................................................... 26 Added SPI Bus Sharing Section and Figure 65; Renumbered Sequentially ...................................................................................... 26 Changes to I[2] C Protocol Section and Reading Acceleration or Temperature Data from The Interface Section ........................... 27 Changes to FIFO Section ............................................................... 28 Changes to DRDY Pin Section, FIFO_FULL Section, FIFO_OVR Section, Activity Section, NVM_BUSY Section, and External Synchronization and Interpolation Section ................. 29 Changed EXT_SYNC = 00—No External Sync or Interpolation Section to EXT_SYNC = 00, EXT_CLK = 0—No External 

Synchronization or Interpolation Section; EXT_SYNC = 10— External Sync with Interpolation Section to EXT_SYNC = 10, EXT_CLK = 0—External Synchronization with Interpolation Section; and EXT_SYNC = 01—External Sync and External Clock, No Interpolation Filter Section to EXT_SYNC = 01, EXT_CLK = 1—External Synchronization and External Clock, No Interpolation Filter Section ..................................................... 30 Changes to EXT_SYNC = 00, EXT_CLK = 0—No External Synchronization or Interpolation Section, EXT_SYNC = 10, EXT_CLK = 0—External Synchronization with Interpolation Section, Table 13, and EXT_SYNC = 01, EXT_CLK = 1— External Synchronization and External Clock, No Interpolation Filter Section .................................................................................... 30 Added EXT_SYNC = 10, EXT_CLK = 1—External Synchronization and External Clock, with Interpolation Filter Section .............................................................................................. 30 Changes to Table 14 ........................................................................ 31 Changes to Figure 74, Figure 75 Caption, and Figure 76 .......... 31 Changes to Table 20 ........................................................................ 33 Changes to Temperature Data Registers Section, Table 23, Table 24, and Table 25 ..................................................................... 34 Changes to Table 27, Table 28, Table 30, and Table 31 ............... 35 Change to Table 42 Title ................................................................. 37 Changes to Table 43 ........................................................................ 38 Changes to Table 44 ........................................................................ 39 Changes to Reset Register Section ................................................ 40 Changes to Figure 77 ...................................................................... 41 Deleted Figure 78; Renumbered Sequentially ............................. 42 Changes to Ordering Guide ........................................................... 42 

**4/2018—Rev. 0 to Rev. A** Added Vibration Parameter, Table 5 .............................................. 8 Changes to Overrange Protection Section ................................... 22 

## **8/2016—Revision 0: Initial Version** 

Rev. B | Page 3 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

## **SPECIFICATIONS** 

## **ANALOG OUTPUT FOR THE ADXL354** 

TA = 25°C, VSUPPLY = 3.3 V, x-axis acceleration and y-axis acceleration = 0 _g_ , and z-axis acceleration = 1 _g_ , unless otherwise noted. 

**Table 1.** 

|**Table 1.**||||
|---|---|---|---|
|**Parameter**|**Test Conditions/Comments**|**Min**<br>**Typ**<br>**Max**|**Unit**|
|SENSOR INPUT<br>Output Full-Scale Range (FSR)<br>Resonant Frequency1<br>Nonlinearity<br>Cross Axis Sensitivity|Each axis<br>ADXL354B supports two ranges<br>ADXL354C supports two ranges<br>±2_g_<br>±8_g_|±2, ±4<br>±2, ±8<br>2.4<br>0.1<br>1.15<br>1|_g_<br>_g_<br>kHz<br>%<br>%<br>%|
|SENSITIVITY<br>Sensitivity at XOUT, YOUT, ZOUT<br>Sensitivity Change Due to Temperature<br>Repeatability2|Ratiometric to V1P8ANA<br>±2_g_<br>±4_g_<br>±8_g_<br>−40°C to +125°C<br>X-axis and y-axis<br>Z-axis|368<br>400<br>432<br>184<br>200<br>216<br>92<br>100<br>108<br>±0.01<br>0.16<br>0.3|mV/_g_<br>mV/_g_<br>mV/_g_<br>%/°C<br>%<br>%|
|0_g_OFFSET<br>0_g_Output for XOUT, YOUT, ZOUT<br>0_g_Offset vs. Temperature (X-Axis, Y-Axis,<br>and Z-Axis)3<br>Repeatability2<br>Vibration Rectification Error (VRE)4|Each axis, ±2_g_<br>Referred to V1P8ANA/2<br>−40°C to +125°C<br>X-axis and y-axis<br>Z-axis<br>±2_g_range, in a 1_g_orientation,<br>offset due to 2.5_g_rms vibration|−75<br>±25<br>+75<br>−0.15<br>±0.1<br>+0.15<br>±2<br>±3<br><0.4|m_g_<br>m_g_/°C<br>m_g_<br>m_g_<br>_g_|
|NOISE<br>Spectral Density5<br>X-Axis, Y-Axis, and Z-Axis6<br>Velocity Random Walk<br>X-Axis and Y-Axis<br>Z-Axis|±2_g_<br>±2_g_|22.5<br>5.3<br>7.7|μ_g_/√Hz<br>mm/sec/Hr<br>mm/sec/Hr|
|BANDWIDTH|3 dB, overall transfer function7|1.9|kHz|
|SELF TEST<br>Output Change8<br>X-Axis<br>Y-Axis<br>Z-Axis||0.1<br>0.3<br>0.6<br>0.1<br>0.3<br>0.6<br>0.5<br>1.5<br>3.0|_g_<br>_g_<br>_g_|
|POWER SUPPLY<br>Voltage Range<br>VSUPPLY9<br>VDDIO<br>V1P8ANA, V1P8DIG<br>Current<br>Measurement Mode<br>VSUPPLY<br>V1P8ANA<br>V1P8DIG|Internal low dropout (LDO) regulator<br>bypassed, VSUPPLY= 0 V<br>LDO regulator enabled<br>LDO regulator disabled<br>LDO regulator disabled|2.25<br>2.5<br>3.6<br>V1P8DIG<br>2.5<br>3.6<br>1.62<br>1.8<br>1.98<br>150<br>138<br>12|V<br>V<br>V<br>μA<br>μA<br>μA|



Rev. B | Page 4 of 42 

**ADXL354/ADXL355** 

## **Data Sheet** 

|**Parameter**|**Test Conditions/Comments**|**Min**<br>**Typ**<br>**Max**|**Unit**|
|---|---|---|---|
|Standby Mode<br>VSUPPLY<br>V1P8ANA<br>V1P8DIG<br>Turn On Time10|LDO regulator enabled<br>LDO regulator disabled<br>LDO regulator disabled<br>2_g_range<br>Power-off to standby|21<br>7<br>10<br><10<br><10|μA<br>μA<br>μA<br>ms<br>ms|
|OUTPUT AMPLIFIER<br>Swing<br>Output Series Resistance|XOUT, YOUT, ZOUT, and TEMP pins<br>No load|0.03<br>V1P8ANA− 0.03<br>32|V<br>kΩ|
|TEMPERATURE SENSOR<br>Output at 25°C<br>Scale Factor||967<br>3.0|mV<br>mV/°C|
|TEMPERATURE<br>OperatingTemperature Range||−40<br>+125|°C|



- 1 The resonant frequency is a sensor characteristic. 

2 Repeatability is predicted for a 10 year life and includes shifts due to the high temperature operating life test (HTOL) (TA = 150°C, VSUPPLY = 3.6 V, and 1000 hours), temperature cycling (−55°C to +125°C and 1000 cycles), velocity random walk, broadband noise, and temperature hysteresis. Repeatability in relation to time follows the square root law. For example, to obtain offset repeatability of the x-axis for 2.5 years, use the following equation: ±2 m _g_ × √(2.5 years/10 years) = ±1 m _g_ . 

3 The temperature change is −40°C to +25°C, or +25°C to +125°C. 

> 4 The VRE measurement is the shift in dc offset while the device is subject to 2.5 _g_ rms of random vibration from 50 Hz to 2 kHz. The device under test (DUT) is configured for the ±2 _g_ range and an output data rate of 4 kHz. The VRE scales with the range setting. 

- 5 Based on characterization. 

- 6 The noise spectral density for ±8 _g_ range is estimated by design to be 50% more than that of the ±2 _g_ range. 

- 7 Overall transfer function includes the sensor mechanical response and all other filters on the signal chain. 

- 8 The self test result converted to the acceleration value is independent of the selected range. 

9 When V1P8ANA and V1P8DIG are generated internally, VSUPPLY is valid. To disable the LDO regulator and drive V1P8ANA and V1P8DIG externally, connect VSUPPLY to VSS. 

> 10 Standby to measurement mode. This specification is valid when the output is within 1 m _g_ of the final value. 

## **DIGITAL OUTPUT FOR THE ADXL355** 

TA = 25°C, VSUPPLY = 3.3 V, x-axis acceleration and y-axis acceleration = 0 _g_ , and z-axis acceleration = 1 _g_ , and output data rate (ODR) = 500 Hz, unless otherwise noted. Note that multifunction pin names may be referenced by their relevant function only. 

**Table 2.** 

|**Table 2.**||||
|---|---|---|---|
|**Parameter**|**Test Conditions/Comments**|**Min**<br>**Typ**<br>**Max**|**Unit**|
|SENSOR INPUT<br>Output Full-Scale Range (FSR)<br>Nonlinearity<br>Cross Axis Sensitivity|Each axis<br>User selectable, supports three<br>ranges<br>±2_g_<br>±8_g_|±2, ±4, ±8<br>0.1<br>1.6<br>1|_g_<br>% FS<br>%<br>%|
|SENSITIVITY1<br>X-Axis, Y-Axis, and Z-Axis Sensitivity<br>X-Axis, Y-Axis, and Z-Axis Scale Factor<br>Sensitivity Change due to Temperature<br>Repeatability2|Each axis<br>±2_g_<br>±4_g_<br>±8_g_<br>±2_g_<br>±4_g_<br>±8_g_<br>−40°C to +125°C<br>X-axis and y-axis<br>Z-axis|235,520<br>256,000<br>276,480<br>117,760<br>128,000<br>138,240<br>58,880<br>64,000<br>69,120<br>3.9<br>7.8<br>15.6<br>±0.01<br>0.16<br>0.3|LSB/_g_<br>LSB/_g_<br>LSB/_g_<br>μ_g/_LSB<br>μ_g/_LSB<br>μ_g/_LSB<br>%/°C<br>%<br>%|
|0_g_OFFSET<br>X-Axis, Y-Axis, and Z-Axis 0_g_Output<br>0_g_Offset vs. Temperature (X-Axis, Y-Axis, and<br>Z-Axis)3|Each axis, ±2_g_<br>−40°C to +125°C|−75<br>±25<br>+75<br>−0.15<br>±0.02<br>+0.15|m_g_<br>m_g_/°C|



Rev. B | Page 5 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

|**Parameter**|**Test Conditions/Comments**|**Min**<br>**Typ**<br>**Max**|**Unit**|
|---|---|---|---|
|Repeatability2<br>VRE4|X-axis and y-axis<br>Z-axis<br>±2_g_range, in a 1_g_orientation,<br>offset due to 2.5_g_rms vibration|±2<br>±3<br><0.4|m_g_<br>m_g_<br>_g_|
|NOISE<br>Spectral Density5<br>X-Axis, Y-Axis, and Z-Axis<br>Velocity Random Walk<br>X-Axis and Y-Axis<br>Z-Axis|±2_g_<br>±8_g_<br>±2_g_|22.5<br>25<br>5.3<br>7.7|μ_g_/√Hz<br>μ_g_/√Hz<br>mm/sec/Hr<br>mm/sec/Hr|
|BANDWIDTH AND OUTPUT DATA RATE<br>Analog-to-Digital Converter (ADC) Resolution<br>Low-Pass Filter Passband Frequency<br>High-Pass Filter Passband Frequency When<br>Enabled (Disabled byDefault)|User programmable, Register 0x28<br>User programmable, Register 0x28 for<br>4 kHz ODR|20<br>0.977<br>1000<br>0.0095<br>10|Bits<br>Hz<br>Hz|
|SELF TEST<br>Output Change6<br>X-Axis<br>Y-Axis<br>Z-Axis||0.1<br>0.3<br>0.6<br>0.1<br>0.3<br>0.6<br>0.5<br>1.5<br>3.0|_g_<br>_g_<br>_g_|
|POWER SUPPLY<br>Voltage Range<br>VSUPPLYOperating7<br>VDDIO<br>V1P8ANAand V1P8DIG<br>Current<br>Measurement Mode<br>VSUPPLY<br>V1P8ANA<br>V1P8DIG<br>Standby Mode<br>VSUPPLY<br>V1P8ANA<br>V1P8DIG<br>Turn On Time8|Internal LDO regulator bypassed,<br>VSUPPLY= 0 V<br>LDO regulator enabled<br>LDO regulator disabled<br>LDO regulator disabled<br>LDO regulator enabled<br>LDO regulator disabled<br>LDO regulator disabled<br>2_g_range<br>Power-off to standby|2.25<br>2.5<br>3.6<br>V1P8DIG<br>2.5<br>3.6<br>1.62<br>1.8<br>1.98<br>200<br>160<br>35.5<br>21<br>7<br>10<br><10<br><10|V<br>V<br>V<br>μA<br>μA<br>μA<br>μA<br>μA<br>μA<br>ms<br>ms|
|TEMPERATURE SENSOR<br>Output at 25°C<br>Scale Factor||1885<br>−9.05|LSB<br>LSB/°C|
|TEMPERATURE<br>OperatingTemperature Range||−40<br>+125|°C|



1 Characterized but not 100% tested. 

2 Repeatability is predicted for a 10 year life and includes shifts due to the HTOL (TA = 150°C, VSUPPLY = 3.6 V, and 1000 hours), temperature cycling (−55°C to +125°C and 1000 cycles), velocity random walk, broadband noise, and temperature hysteresis. Repeatability in relation to time follows the square root law. For example, to obtain offset repeatability of the x-axis for 2.5 years, use the following equation: ±2 m _g_ × √(2.5 years/10 years) = ±1 m _g_ . 

3 The temperature change is −40°C to +25°C or +25°C to +125°C. 

> 4 The VRE measurement is the shift in dc offset while the device is subject to 2.5 _g_ rms random vibration from 50 Hz to 2 kHz. The DUT is configured for the ±2 _g_ range and an output data rate of 4 kHz. The VRE scales with the range setting. 

5 Based on characterization. 

6 The self test result converted to the acceleration value is independent of the selected range. 

7 When V1P8ANA and V1P8DIG are generated internally, VSUPPLY is valid. To disable the LDO regulator and drive V1P8ANA and V1P8DIG externally, connect VSUPPLY to VSS. 

> 8 Standby to measurement mode. This specification is valid when the output is within 1 m _g_ of final value. 

Rev. B | Page 6 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

## **SPI DIGITAL INTERFACE CHARACTERISTICS FOR THE ADXL355** 

Note that multifunction pin names may be referenced only by their relevant function. 

**Table 3.** 

|**Table 3.**|||||
|---|---|---|---|---|
|**Parameter**|**Symbol**|**Test Conditions/Comments**|**Min**<br>**Typ**<br>**Max**|**Unit**|
|DC INPUT LEVELS<br>Input Voltage<br>Low Level<br>High Level<br>Input Current<br>Low Level<br>High Level|VIL<br>VIH<br>IIL<br>IIH|Input voltage (VIN) = 0 V<br>VIN= VDDIO|0.3 × VDDIO<br>0.7 × VDDIO<br>−0.2<br>0.2|V<br>V<br>μA<br>μA|
|DC OUTPUT LEVELS<br>Output Voltage<br>Low Level<br>High Level<br>Output Current<br>Low Level<br>High Level|VOL<br>VOH<br>IOL<br>IOH|IOL= IOL, MIN<br>IOH= IOH, MAX<br>VOL= VOL, MAX<br>VOH= VOH, MIN|0.2 × VDDIO<br>0.8 × VDDIO<br>−10<br>4|V<br>V<br>mA<br>mA|
|AC INPUT LEVELS<br>SCLK Frequency<br>SCLK High Time<br>SCLK Low Time<br>CS<br>Setup Time<br>CS<br>Hold Time<br>CS<br>Disable Time<br>Rising SCLK Setup Time<br>MOSI Setup Time<br>MOSI Hold Time|tHIGH<br>tLOW<br>tCSS<br>tCSH<br>tCSD<br>tSCLKS<br>tSU<br>tHD||0.1<br>10<br>40<br>40<br>20<br>20<br>40<br>20<br>20<br>20|MHz<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns|
|AC OUTPUT LEVELS<br>Propagation Delay<br>Enable MISO Time<br>Disable MISO Time|tP<br>tEN<br>tDIS|Load capacitance (CLOAD) = 30 pF|30<br>30<br>20|ns<br>ns<br>ns|



**==> picture [403 x 122] intentionally omitted <==**

**----- Start of picture text -----**<br>
tCSD<br>CS tCSS tHIGH tLOW tCSH tSCLKS<br>SCLK<br>tSU tHD<br>MOSI<br>tEN tP tDIS<br>MISO<br>14205-003<br>**----- End of picture text -----**<br>


_Figure 3. SPI Interface Timing Diagram_ 

Rev. B | Page 7 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

## **I[2] C DIGITAL INTERFACE CHARACTERISTICS FOR THE ADXL355** 

Note that multifunction pin names may be referenced by their relevant function only. 

**Table 4.** 

|**Table 4.**|||||||
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Test Conditions/**<br>**Comments**|**I2C_HS =**<br>**Min**|**0 (Fast Mode)**<br>**Typ**<br>**Max**|**I2C_HS = 1 (High Speed Mode)**<br>**Min**<br>**Typ**<br>**Max**|**Unit**|
|DC INPUT LEVELS<br>Input Voltage<br>Low Level<br>High Level<br>Hysteresis of Schmitt<br>Triggered Inputs<br>Input Current|VIL<br>VIH<br>VHYS<br>IIL|0.1 × VDDIO< VIN<<br>0.9 × VDDIO|0.7 × VDDIO<br>0.05 × VDDIO<br>−10|0.3 × VDDIO<br>+10|0.3 × VDDIO<br>0.7 × VDDIO<br>0.1 × VDDIO|V<br>V<br>V<br>μA|
|DC OUTPUT LEVELS<br>Output Voltage<br>Low Level<br>Output Current<br>Low Level|VOL1<br>VOL2<br>IOL|IOL= 3 mA<br>VDDIO> 2 V<br>VDDIO≤ 2 V<br>VOL= 0.4 V<br>VOL= 0.6 V|20<br>6|0.4<br>0.2 × VDDIO|0.4<br>0.2 × VDDIO<br>20<br>6|V<br>V<br>mA<br>mA|
|AC INPUT LEVELS<br>SCL Frequency<br>SCL High Time<br>SCL Low Time<br>Start Setup Time<br>Start Hold Time<br>SDA Setup Time<br>SDA Hold Time<br>Stop Setup Time<br>Bus Free Time<br>SCL Input Rise Time<br>SCL Input Fall Time<br>SDA Input Rise Time<br>SDA Input Fall Time<br>Width of Spikes to<br>Suppress|tHIGH<br>tLOW<br>tSUSTA<br>tHDSTA<br>tSUDAT<br>tHDDAT<br>tSUSTO<br>tBUF<br>tRCL<br>tFCL<br>tRDA<br>tFDA<br>tSP|Not shown in Figure 4|0<br>260<br>500<br>260<br>260<br>50<br>0<br>260<br>500|1<br>120<br>120<br>120<br>120<br>50|0<br>3.4<br>60<br>160<br>160<br>160<br>10<br>0<br>160<br>80<br>80<br>160<br>160<br>10|MHz<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns|
|AC OUTPUT LEVELS<br>Propagation Delay<br>Data<br>Acknowledge<br>Output Fall Time|tVDDAT<br>tVDACK<br>tF|CLOAD= 500 pF<br>Not shown in Figure 4|97<br>20 × (VDD/5.5)|450<br>450<br>120|27<br>135|ns<br>ns<br>ns|



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**----- Start of picture text -----**<br>
tFDA tRDA tBUF<br>SDA<br>tSUSTA tHDSTA tVDDAT tVDACK tSUSTO tSUSTA<br>tSUDAT tHDDAT tLOW tHIGH tFCL<br>tVDDAT tRCL<br>SCL<br>14205-004<br>**----- End of picture text -----**<br>


_Figure 4. I[2] C Interface Timing Diagram_ 

Rev. B | Page 8 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

## **ABSOLUTE MAXIMUM RATINGS** 

## **RECOMMENDED SOLDERING PROFILE** 

## **Table 5.** 

Figure 5 and Table 7 provide details about the recommended soldering profile. 

**==> picture [534 x 204] intentionally omitted <==**

**----- Start of picture text -----**<br>
|||||||
|---|---|---|---|---|---|
|Parameter|Rating|Figure 5 and Table 7 provide details about the recommended|
|soldering profile.|
|Acceleration (Any Axis, 0.5 ms)|
|CRITICAL ZONE|
|Vibration  Unpowered|Per MIL-STD-883 5000|g|TP|tP|TL TO TP|
|RAMP-UP|
|Method 2007,|
|Test Condition A|TL|TSMAX|tL|
|VSUPPLY, VDDIO|5.4 V|
|V1P8ANA, V1P8DIG Configured as Inputs|1.98 V|TSMIN|
|ADXL354|
|Digital Inputs (RANGE, ST1, ST2, STBY)|−0.3 V to VDDIO + 0.3 V|PREHEATtS|RAMP-DOWN|
|Analog Outputs (XOUT, YOUT, ZOUT, TEMP)|−0.3 V to V1P8ANA + 0.3 V|
|ADXL355|t25°C|TO PEAK|
|Digital Pins (CS/SCL, SCLK/VSSIO,|−0.3 V to VDDIO + 0.3 V|TIME|
|MOSI/SDA, MISO/ASEL, INT1, INT2,|Figure 5. Recommended Soldering Profile|
|DRDY)|
|Operating Temperature Range|−40°C to +125°C|Table 7. Recommended Soldering Profile|
|Storage Temperature Range|−55°C to +150°C|Condition|

**----- End of picture text -----**<br>


**==> picture [255 x 263] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||
|---|---|---|
|Condition|
|Profile Feature|Sn63/Pb37|Pb-Free|
|Average Ramp Rate from Liquid|3°C/sec|3°C/sec|
|Temperature (TL) to Peak|maximum|maximum|
|Temperature (TP)|
|Preheat|
|Minimum Temperature (TSMIN)|100°C|150°C|
|Maximum Temperature (TSMAX)|150°C|200°C|
|Time from TSMIN to TSMAX (tS)|60 sec to|60 sec to|
|120 sec|180 sec|
|TSMAX to TL Ramp-Up Rate|3°C/sec|3°C/sec|
|maximum|maximum|
|Liquid Temperature (TL)|183°C|217°C|
|Time Maintained Above TL (tL)|60 sec to|60 sec to|
|150 sec|150 sec|
|Peak Temperature (TP)|240°C +|260°C +|
|0°C/−5°C|0°C/−5°C|
|Time of Actual TP − 5°C (tP)|10 sec to|20 sec to|
|30 sec|40 sec|
|Ramp-Down Rate|6°C/sec|6°C/sec|
|maximum|maximum|
|Time from 25°C to Peak Temperature|6 minutes|8 minutes|
|(t25°C TO PEAK)|maximum|maximum|

**----- End of picture text -----**<br>


Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. 

## **THERMAL RESISTANCE** 

Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. 

θJA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. ψJB is the junction to board thermal resistance. 

**Table 6. Thermal Resistance** 

**==> picture [255 x 26] intentionally omitted <==**

**----- Start of picture text -----**<br>
||||||
|---|---|---|---|---|
|Package Type|θJA|ψJB|Unit|
|E-14-1|[1]|42|17.6|°C/W|

**----- End of picture text -----**<br>


1 Thermal impedance simulated values are based on a JEDEC 2S2P thermal test board with four thermal vias. See JEDEC JESD51. 

## **ESD CAUTION** 

**==> picture [242 x 58] intentionally omitted <==**

Rev. B | Page 9 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

## **PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS** 

**==> picture [216 x 142] intentionally omitted <==**

**----- Start of picture text -----**<br>
RANGE 1 11 VSUPPLY Y<br>ST1 2 ADXL354 10 V1P8ANA<br>TOP VIEW<br>ST2 3 (Not to Scale) 9 VSS X<br>TEMP 4 8 V1P8DIG Z<br>Figure 6. ADXL354 Pin Configuration<br>OUT OUT OUT<br>Z Y X<br>14 13 12<br>5 6 7<br>DDIO SSIO<br>V V STBY 14205-007<br>**----- End of picture text -----**<br>


**Table 8. ADXL354 Pin Function Descriptions** 

|**Pin No.**|**Mnemonic**|**Description**|
|---|---|---|
|1<br>2<br>3<br>4<br>5<br>6<br>7<br>8<br>9<br>10<br>11<br>12<br>13<br>14|RANGE<br>ST1<br>ST2<br>TEMP<br>VDDIO<br>VSSIO<br>STBY<br>V1P8DIG<br>VSS<br>V1P8ANA<br>VSUPPLY<br>XOUT<br>YOUT<br>ZOUT|Range Selection Pin. Set this pin to ground to select the ±2_g_range, or set this pin to VDDIOto select the ±4_g_<br>or ±8_g_range. This pin is model dependent (see the Ordering Guide section).<br>Self Test Pin 1. This pin enables self test mode. This pin must be forced low when not in self test mode.<br>Self Test Pin 2. This pin activates electromechanical self test actuation. This pin must be forced low when not<br>in self test mode.<br>Temperature Sensor Output.<br>Digital Interface Supply Voltage.<br>Digital Ground.<br>Standby or Measurement Mode Selection Pin. Set this pin to ground to enter standby mode, or set this pin<br>to VDDIOto enter measurement mode.<br>Digital Supply. This pin requires a decoupling capacitor. If VSUPPLYconnects to VSS, supply the voltage to this<br>pin externally.<br>Analog Ground.<br>Analog Supply. This pin requires a decoupling capacitor. If VSUPPLYconnects to VSS, supply the voltage to this<br>pin externally.<br>Supply Voltage. When VSUPPLYequals 2.25 V to 3.6 V, VSUPPLYenables the internal LDO regulators to generate<br>V1P8DIGand V1P8ANA. For VSUPPLY= VSS, V1P8DIGand V1P8ANAare externally supplied.<br>X-Axis Output.<br>Y-Axis Output.<br>Z-Axis Output.|



Rev. B | Page 10 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

**==> picture [223 x 145] intentionally omitted <==**

**----- Start of picture text -----**<br>
CS/SCL 1 11 VSUPPLY Y<br>SCLK/VSSIO 2 ADXL355 10 V1P8ANA<br>TOP VIEW<br>MOSI/SDA 3 (Not to Scale) 9 VSS X<br>MISO/ASEL 4 8 V1P8DIG<br>Z<br>DRDY INT2 INT1<br>14 13 12<br>5 6 7<br>DDIO SSIO<br>V V<br>RESERVED 14205-006<br>**----- End of picture text -----**<br>


_Figure 7. ADXL355 Pin Configuration_ 

**Table 9. ADXL355 Pin Function Descriptions** 

|**Pin No.**|**Mnemonic**|**Description**|
|---|---|---|
|1<br>2<br>3<br>4<br>5<br>6<br>7<br>8<br>9<br>10<br>11<br>12<br>13<br>14|CS<br>/SCL<br>SCLK/VSSIO<br>MOSI/SDA<br>MISO/ASEL<br>VDDIO<br>VSSIO<br>RESERVED<br>V1P8DIG<br>VSS<br>V1P8ANA<br>VSUPPLY<br>INT1<br>INT2<br>DRDY|Chip Select for SPI (CS<br>).<br>Serial Communications Clock for I2C (SCL).<br>Serial Communications Clock for SPI (SCLK).<br>I2C Mode Enable (VSSIO). Connect this pin to Pin 6 (VSSIO) to enable I2C mode.<br>Master Output, Slave Input for SPI (MOSI).<br>Serial Data for I2C (SDA).<br>Master Input, Slave Output for SPI (MISO).<br>Alternate I2C Address Select for I2C (ASEL).<br>Digital Interface Supply Voltage.<br>Digital Ground.<br>Reserved. This pin can be connected to ground or left open.<br>Digital Supply. This pin requires a decoupling capacitor. If VSUPPLYconnects to VSS, supply the voltage to this<br>pin externally.<br>Analog Ground.<br>Analog Supply. This pin requires a decoupling capacitor. If VSUPPLYconnects to VSS, supply the voltage to this<br>pin externally.<br>Supply Voltage. When VSUPPLYequals 2.25 V to 3.6 V, VSUPPLYenables the internal LDO regulators to generate<br>V1P8DIGand V1P8ANA. For VSUPPLY= VSS, V1P8DIGand V1P8ANAare externally supplied.<br>Interrupt Pin 1.<br>Interrupt Pin 2.<br>Data ReadyPin.|



Rev. B | Page 11 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

## **TYPICAL PERFORMANCE CHARACTERISTICS** 

All figures include data for multiple devices and multiple lots, and they were taken in the ±2 _g_ range and TA = 25°C, unless otherwise noted. For Figure 52, the ODR is derived from a master clock, with a frequency of 1.024 MHz and ±1.4% device to device variation (similar to ODR device to device variation). For a given device, however, clock frequency variation over the temperature range (−40°C to +125°C) is no more than ±1.2%, guaranteed by design. 

**==> picture [212 x 167] intentionally omitted <==**

**----- Start of picture text -----**<br>
10<br>1<br>0.1<br>0.01<br>10 100 1000<br>FREQUENCY (Hz)<br>) g<br> (<br>OUT<br>RELATIVE X<br>14205-207<br>**----- End of picture text -----**<br>


_Figure 8. ADXL354 Frequency Response for X-Axis_ 

**==> picture [211 x 167] intentionally omitted <==**

**----- Start of picture text -----**<br>
1<br>0.1<br>0.01<br>10 100 1000<br>FREQUENCY (Hz)<br>) g<br> (<br>OUT<br>RELATIVE X<br>14205-210<br>**----- End of picture text -----**<br>


_Figure 11. ADXL355 Frequency Response for X-Axis at 4 kHz ODR_ 

**==> picture [210 x 365] intentionally omitted <==**

**----- Start of picture text -----**<br>
10<br>1<br>0.1<br>0.01<br>10 100 1000<br>FREQUENCY (Hz)<br>Figure 9. ADXL354 Frequency Response for Y-Axis<br>10<br>1<br>0.1<br>10 100 1000<br>FREQUENCY (Hz)<br>) g<br> (<br>OUT<br>RELATIVE Y<br>14205-208<br>) g<br> (<br>OUT<br>RELATIVE Z<br>14205-209<br>**----- End of picture text -----**<br>


_Figure 10. ADXL354 Frequency Response for Z-Axis_ 

**==> picture [212 x 365] intentionally omitted <==**

**----- Start of picture text -----**<br>
1<br>0.1<br>0.01<br>10 100 1000<br>FREQUENCY (Hz)<br>Figure 12. ADXL355 Frequency Response for Y-Axis at 4 kHz ODR<br>1<br>0.1<br>0.01<br>10 100 1000<br>FREQUENCY (Hz)<br>) g<br> (<br>OUT<br>RELATIVE Y<br>14205-211<br>) g<br> (<br>OUT<br>RELATIVE Z<br>14205-212<br>**----- End of picture text -----**<br>


_Figure 13. ADXL355 Frequency Response for Z-Axis at 4 kHz ODR_ 

Rev. B | Page 12 of 42 

**ADXL354/ADXL355** 

## **Data Sheet** 

**==> picture [218 x 562] intentionally omitted <==**

**----- Start of picture text -----**<br>
15.00<br>MAXIMUM CHANGE = 1.69m g<br>AVERAGE CHANGE = 1.18m g<br>10.00<br>5.00<br>0<br>–5.00<br>–9.75<br>–45 5 55 105<br>TEMPERATURE (°C)<br>Figure 14. ADXL354 Zero g Offset Normalized Relative to 25°C vs.<br>Temperature, X-Axis<br>15.00<br>MAXIMUM CHANGE = 3.12m g<br>AVERAGE CHANGE = 1.85m g<br>10.00<br>5.00<br>0<br>–5.00<br>–9.75<br>–45 5 55 105<br>TEMPERATURE (°C)<br>Figure 15. ADXL354 Zero g Offset Normalized Relative to 25°C vs.<br>Temperature, Y-Axis<br>15.00<br>MAXIMUM CHANGE = 3.12m g<br>AVERAGE CHANGE = 1.85m g<br>10.00<br>5.00<br>0<br>–5.00<br>–9.75<br>–45 5 55 105<br>TEMPERATURE (°C)<br>) g<br> OFFSET NORMALIZED<br> g<br>RELATIVE TO 25°C (m<br>ZERO<br>14205-213<br>) g<br> OFFSET NORMALIZED<br> g<br>RELATIVE TO 25°C (m<br>ZERO<br>14205-214<br>) g<br> OFFSET NORMALIZED<br> g<br>RELATIVE TO 25°C (m<br>ZERO<br>14205-215<br>**----- End of picture text -----**<br>


_Figure 16. ADXL354 Zero g Offset Normalized Relative to 25°C vs. Temperature, Z-Axis_ 

**==> picture [220 x 563] intentionally omitted <==**

**----- Start of picture text -----**<br>
1.00<br>MAXIMUM CHANGE = 0.60%<br>AVERAGE CHANGE = 0.34%<br>0.50<br>0<br>–0.50<br>–0.65<br>–45 5 55 105<br>TEMPERATURE (°C)<br>Figure 17. ADXL354 Sensitivity Normalized Relative to 25°C vs. Temperature<br>X-Axis<br>1.00<br>MAXIMUM CHANGE = 0.54%<br>AVERAGE CHANGE = 0.28%<br>0.50<br>0<br>–0.50<br>–0.65<br>–45 5 55 105<br>TEMPERATURE (°C)<br>Figure 18. ADXL354 Sensitivity Normalized Relative to 25°C vs. Temperature<br>Y-Axis<br>1.00<br>MAXIMUM CHANGE = 0.99%<br>AVERAGE CHANGE = 0.51%<br>0.50<br>0<br>–0.50<br>–0.65<br>–40 10 60 110<br>TEMPERATURE (°C)<br>RELATIVE TO 25°C (%)<br>SENSITIVITY NORMALIZED<br>14205-216<br>RELATIVE TO 25°C (%)<br>SENSITIVITY NORMALIZED<br>14205-217<br>RELATIVE TO 25°C (%)<br>SENSITIVITY NORMALIZED<br>14205-218<br>**----- End of picture text -----**<br>


_Figure 17. ADXL354 Sensitivity Normalized Relative to 25°C vs. Temperature X-Axis_ 

_Figure 18. ADXL354 Sensitivity Normalized Relative to 25°C vs. Temperature Y-Axis_ 

_Figure 19. ADXL354 Sensitivity Normalized Relative to 25°C vs. Temperature Z-Axis_ 

Rev. B | Page 13 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

**==> picture [217 x 168] intentionally omitted <==**

**----- Start of picture text -----**<br>
17.5<br>15.0<br>12.5<br>10.0<br>7.5<br>5.0<br>2.5<br>0<br>X-AXIS OFFSET AT 25°C (m g )<br>PERCENT OF POPULATION (%)<br>75 70 65 60 55 50 45 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 14205-219<br>**----- End of picture text -----**<br>


_Figure 20. ADXL354 Zero_ g _Offset Histogram at 25°C, X-Axis_ 

**==> picture [220 x 169] intentionally omitted <==**

**----- Start of picture text -----**<br>
20.0<br>17.5<br>15.0<br>12.5<br>10.0<br>7.5<br>5.0<br>2.5<br>0<br>Y-AXIS OFFSET AT 25°C (m g )<br>PERCENT OF POPULATION (%)<br>75 70 65 60 55 50 45 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 14205-220<br>**----- End of picture text -----**<br>


_Figure 21. ADXL354 Zero_ g _Offset Histogram at 25°C, Y-Axis_ 

**==> picture [221 x 176] intentionally omitted <==**

**----- Start of picture text -----**<br>
11.25<br>10.00<br>8.75<br>7.50<br>6.25<br>5.00<br>3.75<br>2.50<br>1.25<br>0<br>Z-AXIS OFFSET AT 25°C (m g )<br>PERCENT OF POPULATION (%)<br>75 70 65 60 55 50 45 –40 –35 –30 –25 –20 –15 –10 –5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75<br>14205-221<br>**----- End of picture text -----**<br>


_Figure 22. ADXL354 Zero_ g _Offset Histogram at 25°C, Z-Axis_ 

**==> picture [217 x 588] intentionally omitted <==**

**----- Start of picture text -----**<br>
20.0<br>17.5<br>15.0<br>12.5<br>10.0<br>7.5<br>5.0<br>2.5<br>0<br>X-AXIS SENSITIVITY AT 25°C (V/ g )<br>Figure 23. ADXL354 Sensitivity Histogram at 25°C, X-Axis<br>20.0<br>17.5<br>15.0<br>12.5<br>10.0<br>7.5<br>5.0<br>2.5<br>0<br>Y-AXIS SENSITIVITY AT 25°C (V/ g )<br>Figure 24. ADXL354 Sensitivity Histogram at 25°C, Y-Axis<br>17.5<br>15.0<br>12.5<br>10.0<br>7.5<br>5.0<br>2.5<br>0<br>Z-AXIS SENSITIVITY AT 25°C (V/ g )<br>PERCENT OF POPULATION (%)<br>0.368 0.370 0.372 0.374 0.376 0.378 0.380 0.382 0.384 0.386 0.388 0.390 0.392 0.394 0.396 0.398 0.400 0.402 0.404 0.406 0.408 0.410 0.412 0.414 0.416 0.418 0.420 0.422 0.424 0.426 0.428 0.430 0.432<br>14205-222<br>PERCENT OF POPULATION (%)<br>0.368 0.370 0.372 0.374 0.376 0.378 0.380 0.382 0.384 0.386 0.388 0.390 0.392 0.394 0.396 0.398 0.400 0.402 0.404 0.406 0.408 0.410 0.412 0.414 0.416 0.418 0.420 0.422 0.424 0.426 0.428 0.430 0.432<br>14205-223<br>PERCENT OF POPULATION (%)<br>0.368 0.370 0.372 0.374 0.376 0.378 0.375 0.377 0.379 0.381 0.383 0.385 0.387 0.389 0.391 0.393 0.395 0.397 0.399 0.401 0.403 0.405 0.407 0.409 0.416 0.418 0.420 0.422 0.424 0.426 0.428 0.430 0.432<br>14205-224<br>**----- End of picture text -----**<br>


_Figure 25. ADXL354 Sensitivity Histogram at 25°C, Z-Axis_ 

Rev. B | Page 14 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

**==> picture [216 x 558] intentionally omitted <==**

**----- Start of picture text -----**<br>
0.7<br>0.6<br>0.5<br>0.4<br>0.3<br>0.2<br>0.1<br>0<br>0 1 2 3 4<br>INPUT VIBRATION ( g  rms)<br>Figure 26. ADXL354 VRE, X-Axis Offset from −1  g , ±2  g  Range,<br>X-Axis Orientation = −1  g<br>0<br>–0.1<br>–0.2<br>–0.3<br>–0.4<br>–0.5<br>–0.6<br>–0.7<br>0 1 2 3 4<br>INPUT VIBRATION ( g  rms)<br>Figure 27. ADXL354 VRE, Y-Axis Offset from +1  g , ±2  g  Range,<br>Y-Axis Orientation = +1  g<br>0<br>–0.1<br>–0.2<br>–0.3<br>–0.4<br>–0.5<br>–0.6<br>–0.7<br>0 1 2 3 4<br>INPUT VIBRATION ( g  rms)<br>) g<br>OFFSET SHIFT (<br>14205-225<br>) g<br>OFFSET SHIFT (<br>14205-226<br>)OFFSET SHIFT ( g<br>14205-227<br>**----- End of picture text -----**<br>


_Figure 28. ADXL354 VRE, Z-Axis Offset from +1_ g _, ±2_ g _Range, Z-Axis Orientation = +1_ g 

**==> picture [214 x 559] intentionally omitted <==**

**----- Start of picture text -----**<br>
0.68<br>0.58<br>0.48<br>0.38<br>0.28<br>0.18<br>0.08<br>–0.02<br>0 2 4 6 8 10<br>INPUT VIBRATION ( g  rms)<br>Figure 29. ADXL354 VRE, X-Axis Offset from −1  g , ±8  g  Range,<br>X-Axis Orientation = −1  g<br>0<br>–0.1<br>–0.2<br>–0.3<br>–0.4<br>–0.5<br>–0.6<br>–0.7<br>0 2 4 6 8 10<br>INPUT VIBRATION ( g  rms)<br>Figure 30. ADXL354 VRE, Y-Axis Offset from +1  g , ±8  g  Range,<br>Y-Axis Orientation = +1  g<br>0<br>–0.1<br>–0.2<br>–0.3<br>–0.4<br>–0.5<br>–0.6<br>–0.7<br>0 2 4 6 8 10<br>INPUT VIBRATION ( g  rms)<br>)OFFSET SHIFT ( g<br>14205-228<br>) g<br>OFFSET SHIFT (<br>14205-229<br>)OFFSET SHIFT ( g<br>14205-230<br>**----- End of picture text -----**<br>


_Figure 31. ADXL354 VRE, Z-Axis Offset from +1_ g _, ±8_ g _Range, Z-Axis Orientation = +1_ g 

Rev. B | Page 15 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

**==> picture [224 x 561] intentionally omitted <==**

**----- Start of picture text -----**<br>
15.00<br>MAXIMUM DELTA = 6.5m g<br>AVERAGE DELTA = 1.7m g<br>10.00<br>5.00<br>0<br>–5.00<br>–9.75<br>–45 5 55 105<br>TEMPERATURE (°C)<br>Figure 32. ADXL355 Zero g Offset Normalized Relative to 25°C vs.<br>Temperature, X-Axis<br>15.00<br>MAXIMUM DELTA = 3.2m g<br>AVERAGE DELTA = 1.4m g<br>10.00<br>5.00<br>0<br>–5.00<br>–9.75<br>–45 5 55 105<br>TEMPERATURE (°C)<br>Figure 33. ADXL355 Zero g Offset Normalized Relative to 25°C vs.<br>Temperature, Y-Axis<br>15.00<br>MAXIMUM DELTA = 10.6m g<br>AVERAGE DELTA = 5.3m g<br>10.00<br>5.00<br>0<br>–5.00<br>–9.75<br>–45 5 55 105<br>TEMPERATURE (°C)<br>) g<br> OFFSET NORMALIZED<br> g<br>RELATIVE TO 25°C (m<br>ZERO<br>14205-231<br>) g<br> OFFSET NORMALIZED<br> g<br>RELATIVE TO 25°C (m<br>ZERO<br>14205-232<br>) g<br> OFFSET NORMALIZED<br> g<br>RELATIVE TO 25°C (m<br>ZERO<br>14205-233<br>**----- End of picture text -----**<br>


_Figure 34. ADXL355 Zero g Offset Normalized Relative to 25°C vs. Temperature, Z-Axis_ 

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1.00<br>MAXIMUM CHANGE = 0.78%<br>AVERAGE CHANGE = 0.72%<br>0.50<br>0<br>–0.50<br>–0.65<br>–45 5 55 105<br>TEMPERATURE (°C)<br>Figure 35. ADXL355 Sensitivity Normalized Relative to 25°C vs. Temperature<br>X-Axis<br>1.00<br>MAXIMUM CHANGE = 0.78%<br>AVERAGE CHANGE = 0.72%<br>0.50<br>0<br>–0.50<br>–0.65<br>–45 5 55 105<br>TEMPERATURE (°C)<br>Figure 36. ADXL355 Sensitivity Normalized Relative to 25°C vs. Temperature<br>Y-Axis<br>1.00<br>MAXIMUM CHANGE = 0.47%<br>AVERAGE CHANGE = 0.3%<br>0.50<br>0<br>–0.50<br>–0.65<br>–45 5 55 105<br>TEMPERATURE (°C)<br>RELATIVE TO 25°C (%)<br>SENSITIVITY NORMALIZED<br>14205-234<br>RELATIVE TO 25°C (%)<br>SENSITIVITY NORMALIZED<br>14205-235<br>RELATIVE TO 25°C (%)<br>SENSITIVITY NORMALIZED<br>14205-236<br>**----- End of picture text -----**<br>


_Figure 35. ADXL355 Sensitivity Normalized Relative to 25°C vs. Temperature X-Axis_ 

_Figure 36. ADXL355 Sensitivity Normalized Relative to 25°C vs. Temperature Y-Axis_ 

_Figure 37. ADXL355 Sensitivity Normalized Relative to 25°C vs. Temperature Z-Axis_ 

Rev. B | Page 16 of 42 

**ADXL354/ADXL355** 

## **Data Sheet** 

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20.0<br>17.5<br>15.0<br>12.5<br>10.0<br>7.5<br>5.0<br>2.5<br>0<br>X-AXIS OFFSET AT 25°C (m g )<br>PERCENT OF POPULATION (%)<br>–75 –69 –63 –57 –51 –45 –39 –33 –27 –21 –15 –9 –3 3 9 15 21 27 33 39 45 51 57 63 69 75 14205-237<br>**----- End of picture text -----**<br>


_Figure 38. ADXL355 Zero_ g _Offset Histogram at 25°C, X-Axis_ 

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20.0<br>17.5<br>15.0<br>12.5<br>10.0<br>7.5<br>5.0<br>2.5<br>0<br>Y-AXIS OFFSET AT 25°C (m g )<br>Figure 39. ADXL355 Zero  g  Offset Histogram at 25°C, Y-Axis<br>11.25<br>10.00<br>8.75<br>7.50<br>6.25<br>5.00<br>3.75<br>2.50<br>1.25<br>0<br>Z-AXIS OFFSET AT 25°C (m g )<br>PERCENT OF POPULATION (%)<br>–75 –69 –63 –57 –51 –45 –39 –33 –27 –21 –15 –9 –3 3 9 15 21 27 33 39 45 51 57 63 69 75 14205-238<br>PERCENT OF POPULATION (%)<br>–75 –69 –63 –57 –51 –45 –39 –33 –27 –21 –15 –9 –3 3 9 15 21 27 33 39 45 51 57 63 69 75 14205-239<br>**----- End of picture text -----**<br>


_Figure 40. ADXL355 Zero_ g _Offset Histogram at 25°C, Z-Axis_ 

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15.0<br>12.5<br>10.0<br>7.5<br>5.0<br>2.5<br>0<br>X-AXIS SENSITIVITY AT 25°C (LSB/ g )<br>Figure 41. ADXL355 Sensitivity Histogram at 25°C, X-Axis<br>15.0<br>12.5<br>40<br>30<br>5.0<br>2.5<br>0<br>Y-AXIS SENSITIVITY AT 25°C (LSB/ g )<br>Figure 42. ADXL355 Sensitivity Histogram at 25°C, Y-Axis<br>15.0<br>12.5<br>10.0<br>7.5<br>5.0<br>2.5<br>0<br>Z-AXIS SENSITIVITY AT 25°C (LSB/ g )<br>PERCENT OF POPULATION (%)<br>235520 237158 238797 240435 242074 243712 245350 246989 248627 250266 251904 253542 255181 256819 258458 260096 261734 263373 265011 266650 268288 269926 271565 273203 274842 276480<br>14205-240<br>PERCENT OF POPULATION (%)<br>235520 237158 238797 240435 242074 243712 245350 246989 248627 250266 251904 253542 255181 256819 258458 260096 261734 263373 265011 266650 268288 269926 271565 273203 274842 276480<br>14205-241<br>PERCENT OF POPULATION (%)<br>235520 237158 238797 240435 242074 243712 245350 246989 248627 250266 251904 253542 255181 256819 258458 260096 261734 263373 265011 266650 268288 269926 271565 273203 274842 276480<br>14205-242<br>**----- End of picture text -----**<br>


_Figure 43. ADXL355 Sensitivity Histogram at 25°C, Z-Axis_ 

Rev. B | Page 17 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

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0.7<br>0.6<br>0.5<br>0.4<br>0.3<br>0.2<br>0.1<br>0<br>0 1 2 3 4<br>INPUT VIBRATION ( g  rms)<br>Figure 44. ADXL355 VRE, X-Axis Offset from −1  g , ±2  g  Range,<br>X-Axis Orientation = −1  g<br>0<br>–0.1<br>–0.2<br>–0.3<br>–0.4<br>–0.5<br>–0.6<br>–0.7<br>0 1 2 3 4<br>INPUT VIBRATION ( g  rms)<br>Figure 45. ADXL355 VRE, Y-Axis Offset from +1  g , ±2  g  Range,<br>Y-Axis Orientation = +1  g<br>0<br>–0.1<br>–0.2<br>–0.3<br>–0.4<br>–0.5<br>–0.6<br>–0.7<br>0 1 2 3 4<br>INPUT VIBRATION ( g  rms)<br>) g<br>OFFSET CHANGE (<br>14205-243<br>) g<br>OFFSET CHANGE (<br>14205-244<br>) g<br>OFFSET CHANGE (<br>14205-245<br>**----- End of picture text -----**<br>


_Figure 46. ADXL355 VRE, Z-Axis Offset from +1_ g _, ±2_ g _Range, Z-Axis Orientation = +1_ g 

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0.68<br>0.58<br>0.48<br>0.38<br>0.28<br>0.18<br>0.08<br>–0.02<br>0 2 4 6 8 10<br>INPUT VIBRATION ( g  rms)<br>Figure 47. ADXL355 VRE, X-Axis Offset from −1  g , ±8  g  Range,<br>X-Axis Orientation = −1  g<br>0<br>–0.1<br>–0.2<br>–0.3<br>–0.4<br>–0.5<br>–0.6<br>–0.7<br>0 2 4 6 8 10<br>INPUT VIBRATION ( g  rms)<br>Figure 48. ADXL355 VRE, Y-Axis Offset from +1  g , ±8  g  Range,<br>Y-Axis Orientation = +1  g<br>0<br>–0.1<br>–0.2<br>–0.3<br>–0.4<br>–0.5<br>–0.6<br>–0.7<br>0 2 4 6 8 10<br>INPUT VIBRATION ( g  rms)<br>Figure 49. ADXL355 VRE, Z-Axis Offset from +1  g , ±8  g  Range,<br>Z-Axis Orientation = +1  g<br>)OFFSET SHIFT ( g<br>14205-246<br>)OFFSET SHIFT ( g<br>14205-247<br>)OFFSET SHIFT ( g<br>14205-248<br>**----- End of picture text -----**<br>


Rev. B | Page 18 of 42 

**ADXL354/ADXL355** 

## **Data Sheet** 

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**----- Start of picture text -----**<br>
1.35 0.006<br>TEMPERATURE SENSOR OUTPUT<br>LINEAR OFFSET<br>1.25 0.004<br>1.15 0.002<br>1.05 0<br>0.95 –0.002<br>0.85 –0.004<br>0.75 –0.006<br>–40 –20 0 20 40 60 80 100 120<br>TEMPERATURE (°C)<br> LINEAR OFFSET (V)<br>TEMPERATURE SENSOR OUTPUT (V)<br>14205-249<br>**----- End of picture text -----**<br>


_Figure 50. ADXL354 Temperature Sensor Output and Linear Offset vs. Temperature_ 

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25.0<br>22.5<br>20.0<br>17.5<br>15.0<br>12.5<br>10.0<br>7.5<br>5.0<br>2.5<br>0 125 129 133 137 141 145 149 153 157 161 165 169 173<br>TOTAL SUPPLY CURRENT AT 25°C (µA)<br>PERCENT OF POPULATION (%)<br>14205-251<br>**----- End of picture text -----**<br>


_Figure 51. ADXL354 Total Supply Current, 3.3 V_ 

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2500 5<br>2300 4<br>3<br>2100<br>2<br>1900<br>1<br>1700<br>0<br>1500<br>–1<br>1300<br>–2<br>1100 –3<br>900 TEMPERATURE SENSOR OUTPUT –4<br>LINEAR OFFSET<br>700 –5<br>–40 –20 0 20 40 60 80 100 120<br>TEMPERATURE (°C)<br> LINEAR OFFSET (LSB)<br>TEMPERATURE SENSOR OUTPUT (LSB)<br>14205-250<br>**----- End of picture text -----**<br>


_Figure 53. ADXL355 Temperature Sensor Output and Linear Offset vs. Temperature_ 

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25.0<br>22.5<br>20.0<br>17.5<br>15.0<br>12.5<br>10.0<br>7.5<br>5.0<br>2.5<br>0<br>180 184 188 192 196 200 204 208 212 216 220 224 228<br>TOTAL SUPPLY CURRENT AT 25°C (µA)<br>Figure 54. ADXL355 Total Supply Current, 3.3 V<br>PERCENT OF POPULATION (%)<br>14205-253<br>**----- End of picture text -----**<br>


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35<br>30<br>25<br>20<br>15<br>10<br>5<br>0<br>3800 3840 3880 3920 3960 4000 4040 4080 4120 4160 4200<br>ODR FREQUENCY (Hz)<br>PERCENT OF POPULATION (%)<br>14205-252<br>**----- End of picture text -----**<br>


_Figure 52. ADXL355 Output Data Rate (Internal Clock) Histogram_ 

Rev. B | Page 19 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

## **ROOT ALLAN VARIANCE (RAV) ADXL355 CHARACTERISTICS** 

All figures include data for multiple devices and multiple lots, and they were taken in the ±2 _g_ range, unless otherwise noted. 

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1000<br>100<br>10<br>1<br>0.01 0.1 1 10 100 1000<br>INTEGRATION TIME (Seconds)<br>Figure 55. ADXL355 RAV, X-Axis<br>1000<br>100<br>10<br>1<br>0.01 0.1 1 10 100 1000<br>INTEGRATION TIME (Seconds)<br>Figure 56. ADXL355 RAV, Y-Axis<br>) g<br>RAV (µ<br>14205-254<br>) g<br>RAV (µ<br>14205-255<br>**----- End of picture text -----**<br>


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1000<br>100<br>10<br>1<br>0.01 0.1 1 10 100 1000<br>INTEGRATION TIME (Seconds)<br>Figure 57. ADXL355 RAV, Z-Axis<br>) g<br>RAV (µ<br>14205-256<br>**----- End of picture text -----**<br>


Rev. B | Page 20 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

## **THEORY OF OPERATION** 

The ADXL354 is a complete 3-axis, ultralow noise and ultrastable offset microelectromechanical systems (MEMS) accelerometer with outputs ratiometric to the analog 1.8 V supply, V1P8ANA. The ADXL355 adds three high resolution analog-to-digital converters (ADCs) that use the analog 1.8 V supply as a reference to provide digital outputs insensitive to the supply voltage. The ADXL354B is pin selectable for ±2 _g_ or ±4 _g_ full scale, the ADXL354C is pin selectable for ±2 _g_ or ±8 _g_ full scale, and the ADXL355 is programmable for ±2 _g_ , ±4 _g_ , or ±8 _g_ full scale. The ADXL355 offers both SPI and I[2] C communications ports. 

The micromachined, sensing elements are fully differential, comprising the lateral x-axis and y-axis sensors and the vertical, teeter totter z-axis sensors. The x-axis and y-axis sensors and the z-axis sensors go through separate signal paths that minimize 

offset drift and noise. The signal path is fully differential, except for a differential to single-ended conversion at the analog outputs of the ADXL354. 

The analog accelerometer outputs of the ADXL354 are ratiometric to V1P8ANA. Therefore, digitize them carefully. The temperature sensor output is not ratiometric. The XOUT, YOUT, and ZOUT analog outputs are filtered internally with an antialiasing filter. These analog outputs also have an internal 32 kΩ series resistor that can be used with an external capacitor to set the bandwidth of the output. 

The ADXL355 includes antialias filters before and after the high resolution Σ-Δ ADC. User-selectable output data rates and filter corners are provided. The temperature sensor is digitized with a 12-bit successive approximation register (SAR) ADC. 

Rev. B | Page 21 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

## **APPLICATIONS INFORMATION** 

## **ANALOG OUTPUT** 

Figure 58 shows the ADXL354 application circuit. The analog outputs (XOUT, YOUT, and ZOUT) are ratiometric to the 1.8 V analog voltage from the V1P8ANA pin. V1P8ANA can be powered with an on-chip LDO regulator that is powered from VSUPPLY. V1P8ANA can also be supplied externally by forcing VSUPPLY to VSS, which disables the LDO regulator. Due to the ratiometric response, the analog output requires referencing to the V1P8ANA supply when digitizing to achieve the inherent noise and offset performance of the ADXL354. The 0 _g_ bias output is nominally equal to V1P8ANA/2. The recommended option is to use the ADXL354 with a ratiometric ADC (for example, the Analog Devices, Inc., AD7682) and V1P8ANA providing the voltage reference. This configuration results in self cancellation of errors due to minor supply variations. 

The ADXL354 outputs two forms of filtering: internal antialiasing filtering with a cutoff frequency of approximately 1.5 kHz, and external filtering. The external filter uses a fixed, on-chip, 32 kΩ resistance in series with each output in conjunction with the external capacitors to implement the low-pass filter antialiasing 

and noise reduction prior to the external ADC. The antialias filter cutoff frequency must be significantly higher than the desired signal bandwidth. If the antialias filter corner is too low, ratiometricity can degrade where the signal attenuation is different from the reference attenuation. 

## **DIGITAL OUTPUT** 

Figure 59 shows the ADXL355 application circuit with the recommended bypass capacitors. The communications interface is either SPI or I[2] C (see the Serial Communications section for additional information). 

The ADXL355 includes an internal configurable digital bandpass filter. Both the high-pass and low-pass poles of the filter are adjustable, as detailed in the Filter Settings Register section and Table 44. At power-up, the default conditions for the filters are as follows: 

- High-pass filter (HPF) = dc (off) 

- Low-pass filter (LPF) = 1000 Hz 

- Output data rate = 4000 Hz 

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**----- Start of picture text -----**<br>
2.25V TO 3.6V<br>VDDIO (±4 g , ±8 g )<br>GND ( ± 2 g )<br>RANGE 1 11 VSUPPLY 0.1µF 1µF<br>ST1 2 10 V1P8ANA 0.1µF 1µF ADC VREF<br>ST2 3 ADXL354 9 VSS<br>TEMP 4 8 V1P8DIG<br>VDDIO (MEASUREMENT)<br>GND (STANDBY)<br>1µF 1µF<br>2.25V TO 3.6V<br>0.1µF 0.1µF<br>Figure 58. ADXL354 Application Circuit<br>2.25V TO 3.6V<br>CS/SCL 1 11 VSUPPLY 0.1µF 1µF<br>SCLK/VSSIO 2 10 V1P8ANA<br>ADXL355 0.1µF 1µF<br>MOSI/SDA 3 TOP VIEW 9 VSS<br>(Not to Scale)<br>MISO/ASEL 4 8 V1P8DIG<br>1µF 1µF<br>2.25V TO 3.6V<br>0.1µF 0.1µF<br>Figure 59. ADXL355 Application Circuit<br>OUT OUT OUT<br>Z Y X<br>14 13 12<br>5 6 7<br>VDDIO VSSIO STBY<br>14205-022<br>DRDY INT2 INT1<br>14 13 12<br>2CSPI/I<br>INTERFACE<br>5 6 7<br>DDIO SSIO<br>V V<br>RESERVED<br>14205-021<br>**----- End of picture text -----**<br>


Rev. B | Page 22 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

## **AXES OF ACCELERATION SENSITIVITY** 

Figure 60 shows the axes of acceleration sensitivity. Note that the output voltage increases when accelerated along the sensitive axis. 

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Z<br>Y<br>X 14205-005<br>**----- End of picture text -----**<br>


_Figure 60. Axes of Acceleration Sensitivity_ 

## **POWER SEQUENCING** 

There are two methods for applying power to the device. Typically, internal LDO regulators generate the 1.8 V power for the analog and digital supplies, V1P8ANA and V1P8DIG, respectively. Optionally, the internal LDO regulators can be disabled and V1P8ANA and V1P8DIG are driven by external 1.8 V supplies. 

When using the internal LDO regulators, connect VSUPPLY to a voltage source between 2.25 V and 3.6 V. In this case, the recommended power sequence is to apply power to VDDIO, followed by applying power to VSUPPLY approximately 10 μs later. If necessary, VSUPPLY and VDDIO can be powered from the same voltage source, so that both are powered at the same time. However, VSUPPLY cannot be powered before VDDIO. 

To disable the internal LDO regulators, tie VSUPPLY to ground and use external 1.8 V supplies to power V1P8ANA and V1P8DIG. V1P8ANA and V1P8DIG must have the same voltage level. The maximum acceptable tolerance between the external V1P8ANA and V1P8DIG voltage levels is 50 mV. In the case of bypassing the LDO regulators, the recommended power sequence is to apply power to VDDIO, followed by applying power to V1P8DIG approximately 10 μs later, and then applying power to V1P8ANA approximately 10 μs later. If necessary, V1P8DIG and VDDIO can be powered from the same external 1.8 V supply, which can also be tied to V1P8ANA with proper isolation, so that all are powered at the same time. In this case, proper decoupling and low frequency isolation are important to maintain the noise performance of the sensor. 

## **POWER SUPPLY DESCRIPTION** 

The ADXL354/ADXL355 have four different power supply domains: VSUPPLY, V1P8ANA, V1P8DIG, and VDDIO. The internal analog and digital circuitry operates at 1.8 V nominal. 

## _**VSUPPLY**_ 

VSUPPLY is 2.25 V to 3.6 V, which is the input range to the two LDO regulators that generate the nominal 1.8 V outputs for V1P8ANA and V1P8DIG. Connect VSUPPLY to VSS to disable the LDO regulators, which allows driving V1P8ANA and V1P8DIG from an external source. 

## _**V1P8ANA**_ 

All sensor and analog signal processing circuitry operates in this domain. Offset and sensitivity of the analog output ADXL354 are ratiometric to this supply voltage. When using external ADCs, use V1P8ANA as the reference voltage The ADXL354 includes ADCs that are ratiometric to V1P8ANA, thereby rendering the offset and sensitivity of the digital output ADXL354 insensitive to the value of V1P8ANA. V1P8ANA can be an input or an output as defined by the state of the VSUPPLY voltage. 

## _**V1P8DIG**_ 

V1P8DIG is the supply voltage for the internal logic circuitry. A separate LDO regulator decouples the digital supply noise from the analog signal path. V1P8ANA can be an input or an output as defined by the state of the VSUPPLY voltage. If driven externally, V1P8DIG must be the same voltage as the V1P8ANA voltage. 

## _**VDDIO**_ 

The VDDIO value determines the logic high levels. On the analog output ADXL354, VDDIO sets the logic high level for the self test pins, ST1 and ST2, as well as the STBY pin. On the digital output ADXL355, VDDIO sets the logic high level for communications interface ports, as well as the interrupt and DRDY outputs. 

The LDO regulators are operational when VSUPPLY is between 2.25 V and 3.6 V. V1P8ANA and V1P8DIG are the regulator outputs in this mode. Alternatively, when tying VSUPPLY to VSS, V1P8ANA and V1P8DIG are supply voltage inputs with a 1.62 V to 1.98 V range. 

## **OVERRANGE PROTECTION** 

The maximum nominal measurement range for the ADXL354/ ADXL355 is ±8 _g_ . Do not subject the device to (or use the device in) applications or assembly processes that reasonably expect to exceed this level of acceleration, particularly for long durations or on an ongoing basis. In such applications, the ADXL356/ ADXL357 offer higher _g_ ranges that may be better suited for such applications. 

To avoid electrostatic capture of the proof mass when the accelerometer is subject to input acceleration beyond its fullscale range, all sensor drive clocks turn off for 0.5 ms. In the ±2 _g_ range setting, the overrange protection activates for input signals beyond approximately ±8 _g_ (±25%), and for the ±4 _g_ and ±8 _g_ range settings, the threshold corresponds to about ±16 _g_ (±25%). 

When overrange protection occurs, the XOUT, YOUT, and ZOUT pins on the ADXL354 begin to drive to midscale, whereas the ADXL355 floats toward zero, and the first in, first out (FIFO) buffer begins filling with this data. 

## **SELF TEST** 

The ADXL354 and ADXL355 incorporate a self test feature that effectively tests their mechanical and electronic systems simultaneously. Enabling self test stimulates the sensor electrostatically to produce an output corresponding to the test signal applied as well as the mechanical force exerted. 

Rev. B | Page 23 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

In the ADXL354, drive the ST1 pin to VDDIO to invoke self test mode. Then, by driving the ST2 pin to VDDIO, the ADXL354 applies an electrostatic force to the mechanical sensor and induces a change in output in response to the force. The self test delta (or response) is the difference in output voltages between when ST2 is high vs. ST2 is low, while ST1 is asserted. After the self test measurement is complete, bring both pins low to resume normal operation. 

The self test operation is similar in the ADXL355, except ST1 and ST2 can be accessed through the SELF_TEST register (Register 0x2E). 

The self test feature rejects externally applied acceleration and only responds to the self test force, which allows an accurate measurement of the self test, even in the presence of external mechanical noise. When the self test feature is not used, both ST1 and ST2 must be kept low. 

## **FILTER** 

The ADXL354/ADXL355 use an analog, low-pass, antialiasing filter to reduce out of band noise and to limit bandwidth. The ADXL355 provides further digital filtering options to maintain optimal noise performance at various ODRs. 

The analog, low-pass antialiasing filter in the ADXL354/ADXL355 provides a fixed 3 dB bandwidth of approximately 1.5 kHz, the frequency at which the voltage output response is attenuated by approximately 30%. The shape of the filter response in the frequency domain is that of a sinc filter. While the analog antialiasing filter attenuates the output response around and above its cutoff frequency, the MEMS sensor has a resonance at 2.4 kHz and mechanically amplifies the output response at around 1 kHz and above. These competing trends are apparent in the overall transfer function of the ADXL354, as shown in Figure 8 to Figure 10. Therefore, the overall 3 dB bandwidth of the ADXL354 is 1.9 kHz. 

The ADXL354 x-axis, y-axis, and z-axis analog outputs include an amplifier followed by a series 32 kΩ resistor and output to the XOUT, the YOUT, and the ZOUT pins, respectively. 

The ADXL355 provides an internal 20-bit, Σ-Δ ADC to digitize the filtered analog signal. Additional digital filtering (beyond the analog, low-pass, antialiasing filter) consists of a low-pass digital decimation filter and a bypassable high-pass filter that supports output data rates between 4 kHz and 3.9 Hz. The decimation filter consists of two stages. The first stage is fixed decimation with a 4 kHz ODR and a low-pass filter cutoff (3 dB) at about 1 kHz. A variable second stage decimation filter is used for the 2 kHz output data rate and below (it is bypassed for 4 kHz ODR). Figure 61 shows the low-pass filter response with a 1 kHz corner (4 kHz ODR) for the ADXL355. Note that Figure 61 does not include the fixed frequency analog, low-pass, antialiasing filter with a fixed 3 dB bandwidth of approximately 1.5 kHz. 

The ADXL355 pass band of the signal path relates to the combined filter responses, including the analog filter previously described, and the digital decimation filter/ODR setting. Table 10 shows the 

delay associated with the decimation filter for each setting and provides the attenuation at the ODR/4 corner. 

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0<br>–10<br>–20<br>–30<br>–40<br>–50<br>–60<br>–70<br>1 10 100 1k 10k<br>INPUT FREQUENCY (Hz)<br>DIGITAL LPF RESPONSE (dB)<br>14205-023<br>**----- End of picture text -----**<br>


_Figure 61. ADXL355 Digital LPF Response for 4 kHz ODR_ 

The ADXL355 also includes an optional digital high-pass filter with a programmable corner frequency. By default, the highpass filter is disabled. The high-pass corner frequency, where the output is attenuated by 50%, is related to the ODR, and the HPF_CORNER setting in the filter register (Register 0x28, Bits[6:4]). Table 11 shows the HPF_CORNER response. Figure 62 and Figure 63 show the simulated high-pass filter pass-band and delay responses for a 9.88 Hz cutoff. 

**==> picture [226 x 343] intentionally omitted <==**

**----- Start of picture text -----**<br>
0<br>–3<br>–10<br>–20<br>–30<br>–40<br>–50<br>0 9.8801 100<br>FREQUENCY (Hz)<br>Figure 62. High-Pass Filter Pass-Band Response for a 4 kHz ODR and an<br>HPF_CORNER Setting of 001 (Register 0x28, Bits[6:4])<br>40<br>32.2122<br>30<br>20<br>10<br>1<br>0<br>0 9.8801 100<br>FREQUENCY (Hz)<br>AMPLITUDE RELATIVE TO FULL SCALE (dB)<br>14205-024<br>DELAY (ODR CYCLES)<br>14205-025<br>**----- End of picture text -----**<br>


_Figure 63. High-Pass Filter Delay Response for a 4 kHz ODR and an HPF_CORNER Setting of 001 (Register 0x28, Bits[6:4])_ 

Rev. B | Page 24 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

The ADXL355 also includes an interpolation filter after the decimation filters that produces oversampled/upconverted data and provides an external synchronization option. See the Data Synchronization section for more details. Table 12 shows the delay and attenuation relative to the programmed ODR. 

Group delay is the digital filter delay from the input to the ADC until data is available at the interface (see the Filter section). This delay is the largest component of the total delay from sensor to serial interface. 

**Table 10. Digital Filter Group Delay and Profile** 

|**Programmed ODR (Hz)**|**Delay**|**Delay**|**Attenuation**|**Attenuation**|
|---|---|---|---|---|
||**ODR (Cycles)**|**Time (ms)**|**Decimator at ODR/4 (dB)**|**Full Path at ODR/4 (dB)**|
|4000<br>4000/2 = 2000<br>4000/4 = 1000<br>4000/8 = 500<br>4000/16 = 250<br>4000/32 = 125<br>4000/64 = 62.5<br>4000/128 ≈ 31<br>4000/256 ≈ 16<br>4000/512 ≈ 8<br>4000/1024 ≈ 4|2.52<br>2.00<br>1.78<br>1.63<br>1.57<br>1.54<br>1.51<br>1.49<br>1.50<br>1.50<br>1.50|0.63<br>1.00<br>1.78<br>3.26<br>6.27<br>12.34<br>24.18<br>47.59<br>96.25<br>189.58<br>384.31|−3.44<br>−2.21<br>−1.92<br>−1.83<br>−1.83<br>−1.83<br>−1.83<br>−1.83<br>−1.83<br>−1.83<br>−1.83|−3.63<br>−2.26<br>−1.93<br>−1.83<br>−1.83<br>−1.83<br>−1.83<br>−1.83<br>−1.83<br>−1.83<br>−1.83|



**Table 11. Digital High-Pass Filter Response** 

|**HPF_CORNER Register Setting**<br>**(Register 0x28, Bits[6:4])**|**HPF_CORNER Frequency, −3 dB Point Relative to ODR Setting**|**−3 dB at 4 kHz ODR (Hz)**|
|---|---|---|
|000<br>001<br>010<br>011<br>100<br>101<br>110|Not applicable, no high-pass filter enabled<br>24.7 × 10−4× ODR<br>6.2084 × 10−4× ODR<br>1.5545 × 10−4× ODR<br>0.3862 × 10−4× ODR<br>0.0954 × 10−4× ODR<br>0.0238 × 10−4× ODR|Off<br>9.88<br>2.48<br>0.62<br>0.1545<br>0.03816<br>0.00952|



**Table 12. Combined Digital Interpolation Filter and Decimation Filter Response** 

|**Interpolator Data Rate Resolution**<br>**Relative to 64 × ODR (Hz)**|**Combined Interpolator/**<br>**Decimator Delay (ODR Cycles)**|**Combined Interpolator/**<br>**Decimator Delay (ms)**|**Combined Interpolator/Decimator**<br>**Output Attenuation at ODR/4 (dB)**|
|---|---|---|---|
|64 × 4000 = 256,000<br>64 × 2000 = 128,000<br>64 × 1000 = 64,000<br>64 × 500 = 32,000<br>64 × 250 = 16,000<br>64 × 125 = 8000<br>64 × 62.5 = 4000<br>64 × 31.25 = 2000<br>64 × 15.625 = 1000<br>64 × 7.8125 = 500<br>64 × 3.90625 = 250|3.51661<br>3.0126<br>2.752<br>2.6346<br>2.5773<br>2.5473<br>2.53257<br>2.52452<br>2.52045<br>2.5194<br>2.51714|0.88<br>1.51<br>2.75<br>5.27<br>10.31<br>20.38<br>40.52<br>80.78<br>161.31<br>322.48<br>644.39|−6.18<br>−4.93<br>−4.66<br>−4.58<br>−4.55<br>−4.55<br>−4.55<br>−4.55<br>−4.55<br>−4.55<br>−4.55|



Rev. B | Page 25 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

## **SERIAL COMMUNICATIONS** 

The 4-wire serial interface communicates in either the SPI or I[2] C protocol. The interface affectively autodetects the format being used, requiring no configuration control to select the format. 

## **SPI BUS SHARING** 

Use a gated buffer on the SCLK line for the ADXL355 device to achieve the ultralow noise performance and possibly offset shift when the ADXL355 must share a SPI bus with another slave device. This gated SCLK allows the clock signal through only when the chip select (CS) line is low. See Figure 65 for the example circuit that provides this type of protection. 

The ADXL355 multifunction pins are referred to by a single function of the pin, for example, CS, when only that function is relevant. 

## **SPI PROTOCOL** 

**==> picture [201 x 103] intentionally omitted <==**

**----- Start of picture text -----**<br>
PROCESSOR ADXL355<br>CS<br>SS1<br>SS2<br>SCLK SCLK<br>SN74LVC1G125<br>TO SPI SLAVE 2 14205-064<br>**----- End of picture text -----**<br>


Wire the ADXL355 for SPI communication as shown in the connection diagram in Figure 64. The SPI protocol timing is shown in Figure 66 to Figure 69. The timing scheme follows the clock polarity (CPOL) = 0 and clock phase (CPHA) = 0. The SPI clock speed ranges from 100 kHz to 10 MHz. 

**==> picture [433 x 439] intentionally omitted <==**

**----- Start of picture text -----**<br>
ADXL355 PROCESSOR SN74LVC1G125<br>CS SS<br>MOSI MOSI TO SPI SLAVE 2<br>MISO MISO Figure 65. SCLK Protection Example<br>SCLK SCLK<br>Figure 64. 4-Wire SPI Connection<br>CS<br>1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16<br>SCLK<br>MOSI A6 A5 A4 A3 A2 A1 A0 RW<br>MISO D7 D6 D5 D4 D3 D2 D1 D0<br>Figure 66. SPI Timing Diagram—Single-Byte Read<br>CS<br>1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16<br>SCLK<br>MOSI A6 A5 A4 A3 A2 A1 A0 RW D7 D6 D5 D4 D3 D2 D1 D0<br>MISO<br>Figure 67. SPI Timing Diagram—Single-Byte Write<br>CS<br>1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17<br>SCLK<br>MOSI A6 A5 A4 A3 A2 A1 A0 RW<br>BYTE 1 BYTE n<br>MISO D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0<br>Figure 68. SPI Timing Diagram—Multibyte Read<br>CS<br>1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17<br>SCLK<br>BYTE 1 BYTE n<br>MOSI A6 A5 A4 A3 A2 A1 A0 RW D7 D6 D5 D4 D3 D2 D1 D0 D7 D0 D7 D6 D5 D4 D3 D2 D1 D0<br>MISO<br>14205-063<br>14205-027<br>14205-028<br>14205-029<br>14205-030<br>**----- End of picture text -----**<br>


_Figure 69. SPI Timing Diagram—Multibyte Write_ 

Rev. B | Page 26 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

## **I[2] C PROTOCOL** 

The ADXL355 supports point to point I[2] C communication. However, when sharing an SDA bus, the ADXL355 may prevent communication with other devices on that bus. If at any point, even when the ADXL355 is not being addressed, the 0x3A and 0x3B bytes (when the ADXL355 device address is set to 0x1D), or the 0xA6 and 0xA7 bytes (when the ADXL355 device address is set to 0x53) are transmitted on the SDA bus, the ADXL355 responds with an acknowledge bit and pulls the SDA line down. For example, this response can occur when reading or writing the data bytes (0x3A/0x3B or 0xA6/0xA7) to another sensor on the bus. When the ADXL355 pulls the SDA line down, communication with other devices on the bus may be interrupted. To resolve this interruption, the ADXL355 must be connected to a separate SDA bus, or the CS/SCL pin must be switched high when communication with the ADXL355 is not desired (it is normally grounded). 

The ADXL355 supports standard (100 kHz), fast (up to 1 MHz) and high speed (up to 3.4 MHz) data transfer modes when the bus parameters in Table 4 are met. There is no minimum SCL frequency, with the exception that, when reading data, the clock must be fast enough to read an entire sample set before new data overwrites it. Single-byte or multiple byte reads/writes are supported. With the MISO/ASEL pin low, the I[2] C address for the device is 0x1D and an alternate I[2] C address of 0x53 can be chosen by pulling the MISO/ASEL pin high. 

There are no internal pull-up or pull-down resistors for any unused pins. Therefore, there is no known state or default state for the pins if left floating or unconnected. It is required that SCLK/VSSIO be connected to ground when communicating to the ADXL355 using I[2] C. 

Due to communication speed limitations, the maximum output data rate when using the 400 kHz I[2] C mode is 800 Hz, and it scales linearly with a change in the I[2] C communication speed. For example, using I[2] C at 100 kHz limits the maximum ODR to 200 Hz. Operation at an output data rate above the recommended 

maximum may result in an undesirable effect on the acceleration data, including missing samples or additional noise. 

Figure 70 to Figure 72 detail the I[2] C protocol timing. The I[2] C interface can be used on most buses operating in I[2] C standard mode (100 kHz), fast mode (400 kHz), fast mode plus (1 MHz), and high speed mode (3.4 MHz). The ADXL355 I[2] C device ID is as follows: 

- MISO/ASEL pin = 0, device address = 0x1D 

- MISO/ASEL pin = 1, device address = 0x53 

## **READING ACCELERATION OR TEMPERATURE DATA FROM THE INTERFACE** 

Acceleration data is left justified and has a register address order of most significant data to least significant data, which allows the user to use multibyte transfers and to take only as much data as required—8 bits, 16 bits, or 20 bits, plus the marker. Temperature data is 12 bits unsigned, right justified. The ADXL355 temperature value is split over two bytes, but is not double buffered, meaning the value can update between readings of the two registers. The data in XDATA, YDATA, and ZDATA is always the most recent available. It is not guaranteed that XDATA, YDATA, and ZDATA form a set corresponding to one sample point in time. The routine used to retrieve the data from the device controls this data set continuity. If data transfers are initiated when the DATA_RDY bit goes high and completes in a time approximately equal to 1/ODR, XDATA, YDATA, and ZDATA apply to the same data set. 

For multibyte read or write transactions through either serial interface, the internal register address auto-increments. When the top of the register address range, 0x3FF, is reached, the autoincrement stops and does not wrap back to Address 0x00. 

The address auto-increment function disables when the FIFO address is used, so that data can be read continuously from the FIFO as a multibyte transaction. In cases where the starting address of a multibyte transaction is less than the FIFO address, the address auto-increments until reaching the FIFO address, and then stops at the FIFO address. 

**1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 SCL REPEAT START DEVICE ADDRESS REGISTER ADDRESS START DEVICE ADDRESS DATA BYTE STOP SDA A6 A5 A4 A3 A2 A1 A0 RW AK 0 A6 A5 A4 A3 A2 A1 A0 AK A6 A5 A4 A3 A2 A1 A0 RW AK 0 D6 D5 D4 D3 D2 D1 D0 AK SINGLE BYTE READ INDICATE SDA IS CONTROLLED BY ADXL355** _Figure 70. I[2] C Timing Diagram—Single-Byte Read_ **1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 SCL START DEVICE ADDRESS REGISTER ADDRESS DATA BYTE STOP SDA A6 A5 A4 A3 A2 A1 A0 RW AK 0 A6 A5 A4 A3 A2 A1 A0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK** 

_Figure 71. I[2] C Timing Diagram—Single-Byte Write_ **1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 19 SCL START DEVICE ADDRESS REGISTER ADDRESS DATA BYTE 1 DATA BYTE n SDA A6 A5 A4 A3 A2 A1 A0 RW AK 0 A6 A5 A4 A3 A2 A1 A0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK D7 D0 AK D7 D6 D5 D4 D3 D2 D1 D0 AK** 

_Figure 72. I[2] C Timing Diagram—Multibyte Write_ 

Rev. B | Page 27 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

## **FIFO** 

The FIFO operates in a stream mode. That is, when the FIFO overruns, new data overwrites the oldest data in the FIFO. A read from the FIFO address guarantees that the three bytes associated with the acceleration measurement on an axis all pertain to the same measurement. The FIFO never overflows, and the data is always taken out in sets (multiples of three data points). 

There are 96 21-bit locations in the FIFO. Each location contains 20 bits of data and a marker bit for the x-axis data. A single-byte read from the FIFO address pops one location from the FIFO. A multibyte read to the FIFO location pops the FIFO on the read of the first byte and every third byte read thereafter. 

Figure 73 shows the organization of the data in the FIFO. The acceleration data is twos complement, 20-bit data. The FIFO 

control logic inserts the two virtual bits (0b00) between the data bits and the empty indicator bit. Bit 1 indicates that an attempt was made to read an empty FIFO, and that the data is not valid acceleration data. Bit 0 is a marker bit to identify the x-axis, which allows a user to verify that the FIFO data was correctly read. An acceleration data point for a given axis occupies one FIFO location. The read pointer, RD_PTR, points to the oldest stored data that was not read already from the interface (see Figure 73). There are no physical x-acceleration, y-acceleration, or z-acceleration data registers. The data read from data registers (Register 0x08 to Register 0x10) also comes directly from the most recent data set in the FIFO, which is pointed to by the z pointer, Z_PTR, (see Figure 73). 

**==> picture [477 x 224] intentionally omitted <==**

**----- Start of picture text -----**<br>
Z_PTR + 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1<br>t L| Le Le<br>Z_PTR Z19 Z18 Z17 Z16 Z15 Z14 Z13 Z12 Z11 Z10 Z9 Z8 Z7 Z6 Z5 Z4 Z3 Z2 Z1 Z0 0 0<br>r oe| Le Le<br>Z_PTR – 1 Y19 Y18 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 0 0<br>T L LeI Le<br>Z_PTR – 2 | } X19 X18 X17 X16 X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1— = X0 0 1<br>Z19 Z18 Z17 Z16 Z15 Z14 213 Z12 Z11.Z10 Z9 Z8 Z7 Z6 Z5 Z4 Z3 22 Z1 ZO 0 0<br>Y19 Y18 Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 YO 0 0<br>RD_PTR >| } X19 X18 X17 X16 X15 X14 X13. X12 X11. X10 X9 X8 X7 X6 X5_ X4<br>VIRTUAL BITS<br>ACCELERATION DATA (NOT ALLOCATED IN THE FIFO)<br>EMPTY INDICATOR<br>X-AXIS MARKER<br>ee<br>ASCENDING SPI ADDRESSES<br>Figure 73. FIFO Data Organization<br>ASCENDING<br>SPI ADDRESSES<br>ASCENDING FIFO ADDRESSES<br>DATA SET. SAMPLE POINT  IS THE SAME ACROSS A SINGLE X-AXIS, Y-AXIS, AND Z-AXIS DATA SET.<br>14205-035<br>**----- End of picture text -----**<br>


Rev. B | Page 28 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

## **INTERRUPTS** 

The status register (Register 0x04) contains five individual bits, four of which can be mapped to the INT1 pin, the INT2 pin, or both. The polarity of the interrupt, active high or active low, is also selectable via the INT_POL bit in the range (Register 0x2C) register. In general, the status register clears when read, but this is not the case if the condition that caused the interrupt persists after the read of the register. The definition of persist varies slightly in each case, but it is described in the DATA_RDY, DRDY Pin, FIFO_FULL, FIFO_OVR, and Activity sections. The DRDY pin is similar to an interrupt pins (INTx) but clears differently. This case is also described. 

## **DATA_RDY** 

The DATA_RDY bit is set when new acceleration data is available to the interface and clears on a read of the status register. This bit is not set again until acceleration data that is newer than the status register read is available. 

Special logic on the clearing of the DATA_RDY bit covers the corner case where new data arrives during the read of the status register. In this case, the data ready condition may be missed completely. This logic results in a delay of the clearing of DATA_RDY of up to four 512 kHz cycles. 

## **DRDY PIN** 

The DRDY pin is not a status register bit. DRDY instead behaves similar to an unmaskable interrupt. DRDY is set when new acceleration data is available to the interface. DRDY clears on a read of the FIFO, on a read of XDATA, YDATA, or ZDATA, or by an autoclear function that occurs approximately halfway between output acceleration data sets. 

DRDY is always active high. The INT_POL bit does not affect DRDY. In external synchronization modes (EXT_SYNC = 01, EXT_SYNC = 10), the first few DRDY pulses after initial synchronization can be lost or corrupted. The length of this potential corruption is equal to or less than the group delay. Therefore, the samples within one group delay is lost or corrupted after the first synchronization signal. Depending on the decimation setting and interpolation setting (see Table 12), between one and three samples after the first synchronization pulse is lost, provided that all the restrictions set in the External Synchronization and Interpolation section is met. 

## **FIFO_FULL** 

The FIFO_FULL bit is set when the entries in the FIFO are equal to the setting of the FIFO_SAMPLES bits. FIFO_FULL clears as follows: 

- If the number of entries in the FIFO is less than the number of samples indicated by the FIFO_SAMPLES bits, which is only the case if sufficient data is read from the FIFO. 

## **FIFO_OVR** 

The FIFO_OVR bit is set when the FIFO is so far overrange that data is lost. The specified size of the FIFO is 96 locations. The FIFO_OVR bit is set only when there is an attempt to write past this 96-location limit. 

A read of the status register clears FIFO_OVR. FIFO_OVR is not set again until data is lost subsequent to this status register read. 

## **ACTIVITY** 

The activity bit (Register 0x04, Bit 3) is set when the measured acceleration on any axis is above the value set in the ACT_ THRESH bits for ACT_COUNT consecutive measurements. An overthreshold condition can shift from one axis to another on successive measurements and is still counted toward the consecutive ACT_COUNT count. 

A read of the status register clears the activity bit (Register 0x04, Bit 3), but the bit sets again at the end of the next measurement if the activity bit (Register 0x04, Bit 3) conditions are still satisfied. 

## **NVM_BUSY** 

The NVM_BUSY bit indicates that the nonvolatile memory (NVM) controller is busy and, therefore, the NVM cannot be accessed to read or write. The interrupt functionality requires the NVM_BUSY bit to be cleared to function. 

A status register read that occurs after the NVM controller is no longer busy clears NVM_BUSY. 

## **EXTERNAL SYNCHRONIZATION AND INTERPOLATION** 

There are four possible synchronization options for the ADXL355, three of which are shown in Figure 74 to Figure 76. For clarity, the clock frequencies and delays are drawn to scale. The labels in Figure 74 to Figure 76 are defined as follows: 

- Internal ODR is the alignment of the decimated output data based on the internal clock. 

- ADC modulator clock shows the internal master clock rate. 

- DRDY is an output indicator signaling a sample is ready. 

The four possible synchronization options are as follows: 

   - No external synchronization (internal clocks used) 

   - Synchronization with an external synchronization signal and internal clock, interpolation filter enabled 

   - Synchronization with external synchronization and clock signals, no interpolation filter 

   - Synchronization with external synchronization and clock signals, interpolation filter enabled 

- On a read of the status register, but only when the entries in the FIFO are less than the FIFO_SAMPLES bits. 

Rev. B | Page 29 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

## _**EXT_SYNC = 00, EXT_CLK = 0—No External Synchronization or Interpolation**_ 

This is the default mode of operation for the device. The sensor runs on an internal ODR and an internal clock that is generated by an internal oscillator. The internal ODR serves as the synchronization master, which generates the data. Register 0x28 is used to program the ODR. No external signals are required, and this mode is used typically when the external processor retrieves data from the device asynchronously and absolute synchronization to an external source is not required. 

The device outputs DRDY (active high) to signal that a new sample is available, and data is retrieved from the real-time registers or the FIFO. The group delay is based on the decimation setting, as shown in Table 10. This mode is shown in Figure 74. 

## _**EXT_SYNC = 10, EXT_CLK = 0—External Synchronization with Interpolation**_ 

Synchronization using interpolation filters and an external ODR clock is commonly used when the external processor can provide a synchronization signal that is asynchronous to the internal clock, SYNC, at the desired ODR. In this case, an interpolation filter provides additional time resolution of 64 times the programmed ODR (see Table 12). Synchronization with the interpolation filter enabled (EXT_SYNC = 10) allows the sensor to operate on an internal clock and output data most closely associated with the SYNC rising edge. 

The advantage of this mode is that data is available at an arbitrary user defined SYNC sample rate and is asynchronous to the internal clock oscillator. The maximum sample rate cannot exceed 4000 SPS. The disadvantage of this mode is that the group delay is increased, with increased attenuation at the band edge. Additionally, because there is a limit to the time resolution, there is some distortion related to the mismatch of the external synchronization relative to the internal clock oscillator. This mismatch degrades spectral performance. The group delay is based on the decimation setting and interpolation setting (see Table 12). Figure 75 schematically shows the timings in this mode, and Table 13 shows the delay between the SYNC signal (input) and DRDY (output). 

## _**EXT_SYNC = 01, EXT_CLK = 1—External Synchronization and External Clock, No Interpolation Filter**_ 

When configured for EXT_SYNC = 01 and EXT_CLK = 1 (sync register, see Table 47), the user must supply an external clock (enabled via the EXT_CLK bit) at 1.024 MHz on the INT2 pin (Pin 13) and an external synchronization signal, SYNC, on the DRDY pin (Pin 14), as shown in Table 14. If configured in this mode and an external clock is not supplied, the device does not process any data and reading from the output results in null values. This mode is schematically shown in Figure 76. 

Special restrictions when using this mode include the following: 

- The external clock frequency on INT2 (Pin 13, see Table 14) must be 1.024 MHz. 

- The pulse width of the SYNC signal must be at least 3.91 μs, which represents four cycles of the external clock (4 ÷ 1.024 MHz = ~3.91 μs). 

- The phase of SYNC must meet an approximate 25 ns setup time to the external clock rising edge. 

When using the EXT_SYNC mode and without providing the SYNC signal, the device runs on its own internal ODR. Similarly, after external synchronization, the device continues to run synchronized to the last SYNC pulse it received, which means that EXT_SYNC = 01 mode can be used with only a single synchronization pulse. 

For more information about the lost sample in Figure 76, see the DRDY Pin section. 

## _**EXT_SYNC = 10, EXT_CLK = 1—External Synchronization and External Clock, with Interpolation Filter**_ 

This mode can be used to run the device on an external clock and synchronization with an arbitrary sample rate set by the SYNC signal rate. Conditions for external SYNC and external clock signals is the same as EXT_SYNC = 01, EXT_CLK = 1 mode. The interpolation filter provides a frequency resolution related to the ODR (see Table 12). In this case, the data provided corresponds to the external SYNC signal, which can be greater than the set ODR and less than 4000 SPS, but the output pass band remains the same it was prior to the interpolation filter. 

**Table 13. EXT_SYNC = 10, DRDY Delay** 

|**ODR_LPF**|**SYNC to DRDY Delay (Oscillator Cycles)**|
|---|---|
|0x0<br>0x1<br>0x2<br>0x3<br>0x4<br>0x5<br>0x6<br>0x7<br>0x8<br>0x9<br>0xA|8<br>10<br>14<br>22<br>38<br>70<br>134<br>262<br>1031<br>2054<br>4102|



Rev. B | Page 30 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

**Table 14. Multiplexing of INT2 and DRDY** 

||**Register or Bit Fields**<br>**Pins**<br>**EXT_SYNC,**<br>**Bits[1:0]**<br>**INT_MAP,**<br>**Bits[7:4]**<br>**INT2**<br>**(Pin 13)**<br>**DRDY**<br>**(Pin 14)**<br>**Co**|**mments**|
|---|---|---|
|**EXT_CLK**|||
|0<br>0<br>1<br>1|00<br>0000<br>Low<br>DRDY<br>Syn<br>cloc<br>00<br>Not 0000<br>INT2<br>DRDY<br>00<br>0000<br>EXT_CLK<br>DRDY<br>00<br>Not 00001<br>EXT_CLK<br>DRDY|chronization is to the internal clocks, and there is no external<br>k synchronization.|
|0<br>0|01<br>0000<br>DRDY2<br>SYNC<br>The<br>pul<br>013<br>Not 0000<br>INT2<br>SYNC|se options reset the digital filters on every synchronization<br>se and are not recommended.|
|1<br>1|013<br>0000<br>EXT_CLK<br>SYNC<br>Ext<br>hig<br>gro<br>013<br>Not 00001<br>EXT_CLK<br>SYNC|ernal synchronization, no interpolation filter, and DRDY (active<br>h) signals that data is ready. Data represents a sample point<br>updelayearlier in time.|
|0<br>0<br>1<br>1|10<br>0000<br>DRDY2<br>SYNC<br>Ext<br>hig<br>tim<br>103<br>Not 0000<br>INT2<br>SYNC<br>103<br>0000<br>EXT_CLK<br>SYNC<br>103<br>Not 0000<br>EXT_CLK<br>SYNC|ernal synchronization, interpolation filter, and DRDY (active<br>h) signals that data is ready. Data sample group delay earlier in<br>e.|



1 No INT2, even though it is enabled. 

2 DRDY routing through the INT_MAP register takes precedence over the default, per Table 14. 3 No DRDY. 

**==> picture [477 x 257] intentionally omitted <==**

**----- Start of picture text -----**<br>
SAMPLE POINT GROUP DELAY<br>(FIXED RELATIVE TO DRDY)<br>INTERNAL ODR<br>ADC MODULATOR CLOCK<br>DRDY<br>Figure 74. EXT_SYNC = 00, EXT_CLK = 0, Internal Synchronization, Internal Clock<br>GROUP DELAY<br>SAMPLE POINT (FIXED RELATIVE TO SYNC) INTERFACE SYNCHRONIZATION DELAY<br>INTERNAL ODR<br>INTERPOLATOR<br>64× ODR<br>SYNC<br>110% ODR<br>DRDY<br>Figure 75. EXT_SYNC = 10, EXT_CLK = 0, External Synchronization, Internal Clock, Interpolation Filter<br>SAMPLE POINT GROUP DELAY<br>(FIXED RELATIVE TO SYNC)<br>INTERNAL ODR<br>EXTERNAL CLOCK<br>1.024MHz<br>SYNCHRONIZE<br>SYNC<br>LOST SAMPLE<br>DRDY<br>14205-036<br>14205-037<br>14205-038<br>**----- End of picture text -----**<br>


_Figure 76. EXT_SYNC = 01, EXT_CLK = 1, External Synchronization, External Clock, No Interpolation Filter_ 

Rev. B | Page 31 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

## **ADXL355 REGISTER MAP** 

Note that while configuring the ADXL355 in an application, all configuration registers must be programmed before enabling measurement mode in the POWER_CTL register. When the ADXL355 is in measurement mode, only the following configurations can change: the HPF_CORNER bits in the filter register, the INT_MAP register, the ST1 and ST2 bits in the SELF_TEST register, and the reset register. 

**Table 15. ADXL355 Register Map** 

|**Hex.**<br>**Addr.**|**Register Name**|**Bit 7**|**Bit 6**|**Bit 5**|**Bit 4**|**Bit 3**|**Bit 2**|**Bit 1**|**Bit 0**|**Reset**|**R/W**|
|---|---|---|---|---|---|---|---|---|---|---|---|
|0x00|DEVID_AD|DEVID_AD||||||||0xAD|R|
|0x01|DEVID_MST|DEVID_MST||||||||0x1D|R|
|0x02|PARTID|PARTID||||||||0xED|R|
|0x03|REVID|REVID||||||||0x01|R|
|0x04|Status|Reserved|||NVM_BUSY|Activity|FIFO_OVR|FIFO_FULL|DATA_RDY|0x00|R|
|0x05|FIFO_ENTRIES|Reserved|FIFO_ENTRIES|||||||0x00|R|
|0x06|TEMP2|Reserved||||Temperature, Bits[11:8]||||0x00|R|
|0x07|TEMP1|Temperature, Bits[7:0]||||||||0x00|R|
|0x08|XDATA3|XDATA, Bits[19:12]||||||||0x00|R|
|0x09|XDATA2|XDATA, Bits[11:4]||||||||0x00|R|
|0x0A|XDATA1|XDATA, Bits[3:0]||||Reserved||||0x00|R|
|0x0B|YDATA3|YDATA, Bits[19:12]||||||||0x00|R|
|0x0C|YDATA2|YDATA, Bits[11:4]||||||||0x00|R|
|0x0D|YDATA1|YDATA, Bits[3:0]||||Reserved||||0x00|R|
|0x0E|ZDATA3|ZDATA, Bits[19:12]||||||||0x00|R|
|0x0F|ZDATA2|ZDATA, Bits[11:4]||||||||0x00|R|
|0x10|ZDATA1|ZDATA, Bits[3:0]||||Reserved||||0x00|R|
|0x11|FIFO_DATA|FIFO_DATA||||||||0x00|R|
|0x1E|OFFSET_X_H|OFFSET_X, Bits[15:8]||||||||0x00|R/W|
|0x1F|OFFSET_X_L|OFFSET_X, Bits[7:0]||||||||0x00|R/W|
|0x20|OFFSET_Y_H|OFFSET_Y, Bits[15:8]||||||||0x00|R/W|
|0x21|OFFSET_Y_L|OFFSET_Y, Bits[7:0]||||||||0x00|R/W|
|0x22|OFFSET_Z_H|OFFSET_Z, Bits[15:8]||||||||0x00|R/W|
|0x23|OFFSET_Z_L|OFFSET_Z, Bits[7:0]||||||||0x00|R/W|
|0x24|ACT_EN|Reserved|||||ACT_Z|ACT_Y|ACT_X|0x00|R/W|
|0x25|ACT_THRESH_H|ACT_THRESH, Bits[15:8]||||||||0x00|R/W|
|0x26|ACT_THRESH_L|ACT_THRESH, Bits[7:0]||||||||0x00|R/W|
|0x27|ACT_COUNT|ACT_COUNT||||||||0x01|R/W|
|0x28|Filter|Reserved|HPF_CORNER|||ODR_LPF||||0x00|R/W|
|0x29|FIFO_SAMPLES|Reserved|FIFO_SAMPLES|||||||0x60|R/W|
|0x2A|INT_MAP|ACT_EN2|OVR_EN2|FULL_EN2|RDY_EN2|ACT_EN1|OVR_EN1|FULL_EN1|RDY_EN1|0x00|R/W|
|0x2B|Sync|Reserved|||||EXT_CLK|EXT_SYNC||0x00|R/W|
|0x2C|Range|I2C_HS|INT_POL|Reserved||||Range||0x81|R/W|
|0x2D|POWER_CTL|Reserved|||||DRDY_OFF|TEMP_OFF|Standby|0x01|R/W|
|0x2E|SELF_TEST|Reserved||||||ST2|ST1|0x00|R/W|
|0x2F|Reset|Reset||||||||0x00|W|



Rev. B | Page 32 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

## **REGISTER DEFINITIONS** 

This section describes the functions of the ADXL355 registers. The ADXL355 powers up with the default register values, as shown in the reset column of Table 15. 

## **ANALOG DEVICES ID REGISTER** 

This register contains the Analog Devices ID, 0xAD. 

## _**Address: 0x00, Reset: 0xAD, Name: DEVID_AD**_ 

## **Table 16. Bit Descriptions for DEVID_AD** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|DEVID_AD||AnalogDevices ID|0xAD|R|



## **ANALOG DEVICES MEMS ID REGISTER** 

This register contains the Analog Devices MEMS ID, 0x1D. 

## _**Address: 0x01, Reset: 0x1D, Name: DEVID_MST**_ 

## **Table 17. Bit Descriptions for DEVID_MST** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|DEVID_MST||AnalogDevices MEMS ID|0x1D|R|



## **DEVICE ID REGISTER** 

This register contains the device ID, 0xED (355 octal). 

## _**Address: 0x02, Reset: 0xED, Name: PARTID**_ 

## **Table 18. Bit Descriptions for PARTID** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|PARTID||Device ID (355 octal)|0xED|R|



## **PRODUCT REVISION ID REGISTER** 

This register contains the product revision ID, beginning with 0x00 and incrementing for each subsequent revision. 

## _**Address: 0x03, Reset: 0x01, Name: REVID**_ 

## **Table 19. Bit Descriptions for REVID** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|REVID||Mask revision|0x01|R|



## **STATUS REGISTER** 

This register includes bits that describe the various conditions of the ADXL355. _**Address: 0x04, Reset: 0x00, Name: Status**_ 

**Table 20. Bit Descriptions for Status** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:5]|Reserved||Reserved.|0x0|R|
|4|NVM_BUSY||NVM controller is busywith a refresh,programming, or a built in self test (BIST).|0x0|R|
|3|Activity||Activity, as defined in the ACT_THRESH_x and ACT_COUNT registers, is detected.|0x0|R|
|2|FIFO_OVR||FIFO has overrun, and the oldest data is lost.|0x0|R|
|1|FIFO_FULL||FIFO watermark is reached.|0x0|R|
|0|DATA_RDY||A complete x-axis,y-axis, and z-axis measurement was made and results can be read.|0x0|R|



Rev. B | Page 33 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

## **FIFO ENTRIES REGISTER** 

This register indicates the number of valid data samples present in the FIFO buffer. This number ranges from 0 to 96. 

## _**Address: 0x05, Reset: 0x00, Name: FIFO_ENTRIES**_ 

**Table 21. Bit Descriptions for FIFO_ENTRIES** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|7|Reserved||Reserved|0x0|R|
|[6:0]|FIFO_ENTRIES||Number of data samples stored in the FIFO|0x0|R|



## **TEMPERATURE DATA REGISTERS** 

These two registers contain the uncalibrated temperature data. The nominal intercept is 1885 LSB at 25°C and the nominal slope is −9.05 LSB/°C. TEMP2 contains the four most significant bits, and TEMP1 contains the eight least significant bits of the 12-bit value. The ADXL355 temperature value is not double buffered, meaning the value can update between reading of the two registers. 

## _**Address: 0x06, Reset: 0x00, Name: TEMP2**_ 

**Table 22. Bit Descriptions for TEMP2** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:4]|Reserved||Reserved.|||
|[3:0]|Temperature, Bits[11:8]||Uncalibrated temperature data|0x0|R|



## _**Address: 0x07, Reset: 0x00, Name: TEMP1**_ 

## **Table 23. Bit Descriptions for TEMP1** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|Temperature, Bits[7:0]||Uncalibrated temperature data|0x00|R|



## **X-AXIS DATA REGISTERS** 

These three registers contain the x-axis acceleration data. Data is left justified and formatted as twos complement. 

## _**Address: 0x08, Reset: 0x00, Name: XDATA3**_ 

**Table 24. Bit Descriptions for XDATA3** 

|**Table 24. Bit**|**Descriptions for XDATA3**|||||
|---|---|---|---|---|---|
|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|[7:0]|XDATA, Bits[19:12]||X-axis data|0x00|R|



## _**Address: 0x09, Reset: 0x00, Name: XDATA2**_ 

## **Table 25. Bit Descriptions for XDATA2** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|XDATA, Bits[11:4]||X-axis data|0x00|R|



## _**Address: 0x0A, Reset: 0x00, Name: XDATA1**_ 

**Table 26. Bit Descriptions for XDATA1** 

|**Table 26. Bit**|**Descriptions for XDATA1**|||||
|---|---|---|---|---|---|
|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|[7:4]|XDATA, Bits[3:0]||X-axis data|0x0|R|
|[3:0]|Reserved||Reserved|0x0|R|



Rev. B | Page 34 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

## **Y-AXIS DATA REGISTERS** 

These three registers contain the y-axis acceleration data. Data is left justified and formatted as twos complement. 

## _**Address: 0x0B, Reset: 0x00, Name: YDATA3**_ 

## **Table 27. Bit Descriptions for YDATA3** 

|**Table 27. Bit**|**Descriptions for YDATA3**|||||
|---|---|---|---|---|---|
|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|[7:0]|YDATA, Bits[19:12]||Y-axis data|0x00|R|



## _**Address: 0x0C, Reset: 0x00, Name: YDATA2**_ 

## **Table 28. Bit Descriptions for YDATA2** 

|**Table 28. Bit**|**Descriptions for YDATA2**|||||
|---|---|---|---|---|---|
|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|[7:0]|YDATA, Bits[11:4]||Y-axis data|0x00|R|



## _**Address: 0x0D, Reset: 0x00, Name: YDATA1**_ 

## **Table 29. Bit Descriptions for YDATA1** 

|**Table 29. Bit**|**Descriptions for YDATA1**|||||
|---|---|---|---|---|---|
|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|[7:4]|YDATA, Bits[3:0]||Y-axis data|0x0|R|
|[3:0]|Reserved||Reserved|0x0|R|



## **Z-AXIS DATA REGISTERS** 

These three registers contain the z-axis acceleration data. Data is left justified and formatted as twos complement. 

## _**Address: 0x0E, Reset: 0x00, Name: ZDATA3**_ 

## **Table 30. Bit Descriptions for ZDATA3** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|ZDATA, Bits[19:12]||Z-axis data|0x00|R|



## _**Address: 0x0F, Reset: 0x00, Name: ZDATA2**_ 

## **Table 31. Bit Descriptions for ZDATA2** 

|**Table 31. Bit**|**Descriptions for ZDATA2**|||||
|---|---|---|---|---|---|
|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|[7:0]|ZDATA, Bits[11:4]||Z-axis data|0x00|R|



## _**Address: 0x10, Reset: 0x00, Name: ZDATA1**_ 

## **Table 32. Bit Descriptions for ZDATA1** 

|**Table 32. Bit**|**Descriptions for ZDATA1**|||||
|---|---|---|---|---|---|
|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|[7:4]|ZDATA, Bits[3:0]||Z-axis data|0x0|R|
|[3:0]|Reserved||Reserved|0x0|R|



Rev. B | Page 35 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

## **FIFO ACCESS REGISTER** 

## _**Address: 0x11, Reset: 0x00, Name: FIFO_DATA**_ 

Read this register to access data stored in the FIFO. 

**Table 33. Bit Descriptions for FIFO_DATA** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|FIFO_DATA||FIFO data is formatted to 24 bits, three bytes, most significant byte first. A read to this<br>address pops an effective three equal byte words of axis data from the FIFO. Two<br>subsequent reads or a multibyte read completes the transaction of this data onto the<br>interface. Continued reading or a sustained multibyte read of this field continues to<br>pop the FIFO every third byte. Multibyte reads to this address do not increment the<br>address pointer. If this address is read due to an auto-increment from the previous<br>address, it does not pop the FIFO. Instead, it returns zeros and increments on to the<br>next address.|0x0|R|



## **X-AXIS OFFSET TRIM REGISTERS** 

## _**Address: 0x1E, Reset: 0x00, Name: OFFSET_X_H**_ 

**Table 34. Bit Descriptions for OFFSET_X_H** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|OFFSET_X,<br>Bits[15:8]||Offset added to x-axis data after all other signal processing. Data is in twos complement<br>format. The significance of OFFSET_X, Bits[15:0] matches the significance of XDATA,<br>Bits[19:4].|0x0|R/W|



## _**Address: 0x1F, Reset: 0x00, Name: OFFSET_X_L**_ 

**Table 35. Bit Descriptions for OFFSET_X_L** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|OFFSET_X,<br>Bits[7:0]||Offset added to x-axis data after all other signal processing. Data is in twos complement<br>format. The significance of OFFSET_X, Bits[15:0] matches the significance of XDATA,<br>Bits[19:4].|0x0|R/W|



## **Y-AXIS OFFSET TRIM REGISTERS** 

## _**Address: 0x20, Reset: 0x00, Name: OFFSET_Y_H**_ 

**Table 36. Bit Descriptions for OFFSET_Y_H** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|OFFSET_Y,<br>Bits[15:8]||Offset added to y-axis data after all other signal processing. Data is in twos complement<br>format. The significance of OFFSET_Y, Bits[15:0] matches the significance of YDATA,<br>Bits[19:4].|0x0|R/W|



## _**Address: 0x21, Reset: 0x00, Name: OFFSET_Y_L**_ 

**Table 37. Bit Descriptions for OFFSET_Y_L** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|OFFSET_Y,<br>Bits[7:0]||Offset added to y-axis data after all other signal processing. Data is in twos complement<br>format. The significance of OFFSET_Y, Bits[15:0] matches the significance of YDATA,<br>Bits[19:4].|0x0|R/W|



Rev. B | Page 36 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

## **Z-AXIS OFFSET TRIM REGISTERS** _**Address: 0x22, Reset: 0x00, Name: OFFSET_Z_H**_ 

**Table 38. Bit Descriptions for OFFSET_Z_H** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|OFFSET_Z,<br>Bits[15:8]||Offset added to z-axis data after all other signal processing. Data is in twos complement<br>format. The significance of OFFSET_Z, Bits[15:0] matches the significance of ZDATA,<br>Bits[19:4].|0x0|R/W|



## _**Address: 0x23, Reset: 0x00, Name: OFFSET_Z_L**_ 

**Table 39. Bit Descriptions for OFFSET_Z_L** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|OFFSET_Z,<br>Bits[7:0]||Offset added to z-axis data after all other signal processing. Data is in twos complement<br>format. The significance of OFFSET_Z, Bits[15:0] matches the significance of ZDATA,<br>Bits[19:4].|0x0|R/W|



## **ACTIVITY ENABLE REGISTER** 

## _**Address: 0x24, Reset: 0x00, Name: ACT_EN**_ 

**Table 40. Bit Descriptions for ACT_EN** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:3]|Reserved||Reserved.|0x0|R|
|2|ACT_Z||Z-axis data is a component of the activitydetection algorithm.|0x0|R/W|
|1|ACT_Y||Y-axis data is a component of the activitydetection algorithm.|0x0|R/W|
|0|ACT_X||X-axis data is a component of the activitydetection algorithm.|0x0|R/W|



## **ACTIVITY THRESHOLD REGISTERS** 

## _**Address: 0x25, Reset: 0x00, Name: ACT_THRESH_H**_ 

**Table 41. Bit Descriptions for ACT_THRESH_H** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|ACT_THRESH,<br>Bits[15:8]||Threshold for activity detection. Acceleration magnitude must be above<br>ACT_THRESH to trigger the activity counter. ACT_THRESH is an unsigned<br>magnitude. The significance of ACT_THRESH, Bits[15:0] matches the<br>significance of Bits[18:3] of XDATA, YDATA, and ZDATA.|0x0|R/W|



## _**Address: 0x26, Reset: 0x00, Name: ACT_THRESH_L**_ 

**Table 42. Bit Descriptions for ACT_THRESH_L** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|ACT_THRESH,<br>Bits[7:0]||Threshold for activity detection. The acceleration magnitude must be greater<br>than the value in ACT_THRESH to trigger the activity counter. ACT_THRESH is<br>an unsigned magnitude. The significance of ACT_THRESH, Bits[15:0] matches<br>the significance of Bits[18:3] of XDATA, YDATA, and ZDATA.|0x0|R/W|



## **ACTIVITY COUNT REGISTER** 

## _**Address: 0x27, Reset: 0x01, Name: ACT_COUNT**_ 

**Table 43. Bit Descriptions for ACT_COUNT** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|ACT_COUNT||Number of consecutive events above threshold (from ACT_THRESH) required to<br>detect activity|0x1|R/W|



Rev. B | Page 37 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

## **FILTER SETTINGS REGISTER** 

## _**Address: 0x28, Reset: 0x00, Name: Filter**_ 

Use this register to specify parameters for the internal high-pass and low-pass filters. 

**Table 44. Bit Descriptions for Filter** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|7|Reserved||Reserved|0x0|R|
|[6:4]|HPF_CORNER|000<br>001<br>010<br>011<br>100<br>101<br>110|−3 dB filter corner for the first-order, high-pass filter relative to the ODR<br>Not applicable, no high-pass filter enabled<br>24.7 × 10−4× ODR<br>6.2084 × 10−4× ODR<br>1.5545 × 10−4× ODR<br>0.3862 × 10−4× ODR<br>0.0954 × 10−4× ODR<br>0.0238 × 10−4× ODR|0x0|R/W|
|[3:0]|ODR_LPF|0000<br>0001<br>0010<br>0011<br>0100<br>0101<br>0110<br>0111<br>1000<br>1001<br>1010|ODR and low-pass filter corner<br>4000 Hz and 1000 Hz<br>2000 Hz and 500 Hz<br>1000 Hz and 250 Hz<br>500 Hz and 125 Hz<br>250 Hz and 62.5 Hz<br>125 Hz and 31.25 Hz<br>62.5 Hz and 15.625 Hz<br>31.25 Hz and 7.813 Hz<br>15.625 Hz and 3.906 Hz<br>7.813 Hz and 1.953 Hz<br>3.906 Hz and 0.977 Hz|0x0|R/W|



## **FIFO SAMPLES REGISTER** 

## _**Address: 0x29, Reset: 0x60, Name: FIFO_SAMPLES**_ 

Use the FIFO_SAMPLES value to specify the number of samples to store in the FIFO. The default value of this register is 0x60 to avoid triggering the FIFO watermark interrupt. 

**Table 45. Bit Descriptions for FIFO_SAMPLES** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|7|Reserved||Reserved.|0x0|R|
|[6:0]|FIFO_SAMPLES||Watermark number of samples stored in the FIFO that triggers a FIFO_FULL condition.<br>Values range from 1 to 96.|0x60|R/W|



## **INTERRUPT PIN (INTx) FUNCTION MAP REGISTER** 

## _**Address: 0x2A, Reset: 0x00, Name: INT_MAP**_ 

The INT_MAP register configures the interrupt pins. Bits[7:0] select which functions generate an interrupt on the INT1 and INT2 pins. Multiple events can be configured. If the corresponding bit is set to 1, the function generates an interrupt on the interrupt pins. 

**Table 46. Bit Descriptions for INT_MAP** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|7|ACT_EN2||Activityinterrupt enable on INT2|0x0|R/W|
|6|OVR_EN2||FIFO_OVR interrupt enable on INT2|0x0|R/W|
|5|FULL_EN2||FIFO_FULL interrupt enable on INT2|0x0|R/W|
|4|RDY_EN2||DATA_RDY interrupt enable on INT2|0x0|R/W|
|3|ACT_EN1||Activityinterrupt enable on INT1|0x0|R/W|
|2|OVR_EN1||FIFO_OVR interrupt enable on INT1|0x0|R/W|
|1|FULL_EN1||FIFO_FULL interrupt enable on INT1|0x0|R/W|
|0|RDY_EN1||DATA_RDY interrupt enable on INT1|0x0|R/W|



Rev. B | Page 38 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

## **DATA SYNCHRONIZATION** 

## _**Address: 0x2B, Reset: 0x00, Name: Sync**_ 

Use this register to control the external timing triggers. 

**Table 47. Bit Descriptions for Sync** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:3]|Reserved||Reserved.|0x0|R|
|2|EXT_CLK||Enable external clock. See Table 14 for configuration details.|0x0|R/W|
|[1:0]|EXT_SYNC|00<br>01<br>10<br>11|Enable external synchronization control.<br>Internal synchronization.<br>External synchronization, no interpolation filter. After synchronization, and for<br>EXT_SYNC within specification, DATA_RDY occurs on EXT_SYNC.<br>External synchronization, interpolation filter, next available data indicated by<br>DATA_RDY 14 to 8204 oscillator cycles later (longer delay for higher ODR_LPF setting),<br>data represents a sample point group delay earlier in time.<br>Reserved.|0x0|R/W|



## **I[2] C SPEED, INTERRUPT POLARITY, AND RANGE REGISTER** _**Address: 0x2C, Reset: 0x81, Name: Range**_ 

## **Table 48. Bit Descriptions for Range** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|7|I2C_HS|1<br>0|I2C speed.<br>High speed mode.<br>Fast mode.|0x1|R/W|
|6|INT_POL|0<br>1|Interrupt polarity.<br>INT1 and INT2 are active low.<br>INT1 and INT2 are active high.|0x0|R/W|
|[5:2]|Reserved||Reserved.|0x0|R|
|[1:0]|Range|01<br>10<br>11|Range.<br>±2_g_.<br>±4_g_.<br>±8_g_.|0x1|R/W|



## **POWER CONTROL REGISTER** 

## _**Address: 0x2D, Reset: 0x01, Name: POWER_CTL**_ 

**Table 49. Bit Descriptions for POWER_CTL** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:3]|Reserved||Reserved.|0x0|R|
|2|DRDY_OFF||Set to 1 to force the DRDY output to 0 in modes where it is normallysignal data ready.|0x0|R/W|
|1|TEMP_OFF||Set to 1 to disable temperature processing. Temperature processing is also disabled<br>when standby= 1.|0x0|R/W|
|0|Standby|1<br>0|Standby or measurement mode.<br> <br>Standby mode. In standby mode, the device is in a low power state, and the<br>temperature and acceleration datapaths are not operating. In addition, digital<br>functions, including FIFO pointers, reset. Changes to the configuration setting of the<br>device must be made when standby = 1. An exception is a high-pass filter that can be<br>changed when the device is operating.<br> <br>Measurement mode.|0x1|R/W|



Rev. B | Page 39 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

## **SELF TEST REGISTER** 

## _**Address: 0x2E, Reset: 0x00, Name: SELF_TEST**_ 

Refer to the Self Test section for more information on the operation of the self test feature. 

**Table 50. Bit Descriptions for SELF_TEST** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:2]|Reserved||Reserved.|0x0|R|
|1|ST2||Set to 1 to enable self test force|0x0|R/W|
|0|ST1||Set to 1 to enable self test mode|0x0|R/W|



## **RESET REGISTER** 

## _**Address: 0x2F, Reset: 0x00, Name: Reset**_ 

## **Table 51. Bit Descriptions for Reset** 

|**Bits**|**Bit Name**|**Settings **|**Description**|**Reset**|**Access**|
|---|---|---|---|---|---|
|[7:0]|Reset||Write Code 0x52 to reset the device, similar to apower-on reset (POR)|0x0|W|



In case of a software reset, an unlikely race condition may occur in products with REVID = 0x01 or earlier. If the race condition occurs, some factory settings in the NVM load incorrectly to shadow registers (the registers from which the internal logic configures the sensor and calculates the output after a power-on or a software reset). The incorrect loading of the NVM affects overall performance of the sensor, such as an incorrect _0 g_ bias and other performance issues. The incorrect loading of NVM does not occur from a power-on or after a power cycle. To guarantee reliable operation of the sensor after a software reset, the user can access the shadow registers after a power-on, read and store the values on the host microprocessor, and compare the values read from the same shadow registers after a software reset. This method guarantees proper operation in all devices and under all conditions. The recommended steps are as follows: 

1. Read the shadow registers, Register 0x50 to Register 0x54 (five 8-bit registers) after power-up, but before any software reset. 

2. Store these values in a host device (for example, a host microprocessor). 

3. After each software reset, read the same five registers. If the values differ, perform a software reset again until they match. 

Rev. B | Page 40 of 42 

**Data Sheet** 

**ADXL354/ADXL355** 

## **PCB FOOTPRINT PATTERN** 

Figure 77 shows the PCB footprint pattern and dimensions in millimeters. 

**==> picture [398 x 254] intentionally omitted <==**

**----- Start of picture text -----**<br>
3.22mm<br>0.68mm<br>0.70mm 0.70mm<br>TRIANGULAR MARKER, DETAIL A, POINTS TO PIN 1,<br>WHICH IS NOT ROUTED INTERNALLY AND DOES NOT<br>NEED TO BE GROUNDED<br>14 PLCS<br>1.8mm × 0.68mm<br>3.80mm<br>Figure 77. PCB Footprint Pattern and Dimensions in Millimeters<br>4.5mm 3.80mm<br>14205-040<br>**----- End of picture text -----**<br>


Rev. B | Page 41 of 42 

**ADXL354/ADXL355** 

**Data Sheet** 

## **OUTLINE DIMENSIONS** 

**==> picture [337 x 152] intentionally omitted <==**

**----- Start of picture text -----**<br>
DETAIL A<br>0.80<br>6.25 2.25 BSC<br>6.00 SQ 2.05<br>1.674 BSC<br>5.85 1.85 0.510 REF<br>| e . e| me l 11 12 UW i 14 1 0.30 SQ(PIN 1 INDEX) Na<br>DETAIL A<br>5.60 re v4<br>(14 PLCS)R 0.103 SQ 3.81REF 0.508<br>BSC<br>8 4<br>7 5<br>R 0.25 Sf TOP VIEW | | SIDE VIEW BOTTOM VIEW ! [1 ! = 0.914<br>(4 PLCS)R 0.203 0.10 BSC an 0.15BSC dey 2.20 REF 2.54 REF ml BSC<br>(14 PLCS)<br>PKG-004554 05-27-2016-B<br>**----- End of picture text -----**<br>


_Figure 78. 14-Terminal Ceramic Leadless Chip Carrier [LCC] (E-14-1) Dimensions shown in millimeters_ 

## **ORDERING GUIDE** 

|**Model1**|**Output**<br>**Mode**|**Measurement**<br>**Range (****_g_) **|**Specified**<br>**Voltage (V)**|**Temperature Range **|**Package Description**|**Package**<br>**Option**|
|---|---|---|---|---|---|---|
|ADXL354BEZ<br>ADXL354BEZ-RL<br>ADXL354BEZ-RL7<br>ADXL354CEZ<br>ADXL354CEZ-RL<br>ADXL354CEZ-RL7|Analog<br>Analog<br>Analog<br>Analog<br>Analog<br>Analog|±2, ±4<br>±2, ±4<br>±2, ±4<br>±2, ±8<br>±2, ±8<br>±2, ±8|3.3<br>3.3<br>3.3<br>3.3<br>3.3<br>3.3|−40°C to +125°C<br>−40°C to +125°C<br>−40°C to +125°C<br>−40°C to +125°C<br>−40°C to +125°C<br>−40°C to +125°C|14-Terminal LCC<br>14-Terminal LCC<br>14-Terminal LCC<br>14-Terminal LCC<br>14-Terminal LCC<br>14-Terminal LCC|E-14-1<br>E-14-1<br>E-14-1<br>E-14-1<br>E-14-1<br>E-14-1|
|ADXL355BEZ<br>ADXL355BEZ-RL<br>ADXL355BEZ-RL7|Digital<br>Digital<br>Digital|±2, ±4, ±8<br>±2, ±4, ±8<br>±2, ±4, ±8|3.3<br>3.3<br>3.3|−40°C to +125°C<br>−40°C to +125°C<br>−40°C to +125°C|14-Terminal LCC<br>14-Terminal LCC<br>14-Terminal LCC|E-14-1<br>E-14-1<br>E-14-1|
|EVAL-ADXL354BZ<br>EVAL-ADXL354CZ<br>EVAL-ADXL355Z|||||Evaluation Board for ADXL354BEZ<br>Evaluation Board for ADXL354CEZ<br>Evaluation Board for ADXL355BEZ||



1 Z = RoHS-Compliant Part. 

I[2] C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). 

**©2016–2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D14205-6/20(B)** 

Rev. B | Page 42 of 42
Updated at April 28, 2026
Since its inception in 1965, Analog Devices has established itself as a global leader in the design and manufacturing of high-performance analog, mixed-signal, and digital signal processing (DSP) integrated circuits. The company is renowned for solving complex engineering challenges by providing critical technologies that seamlessly convert real-world phenomena into precise electrical signals for the industrial, automotive, communications, and consumer markets. Within its extensive portfolio, Analog Devices provides highly reliable clock, timing, and frequency management solutions, featuring a comprehensive array of precision timers, oscillators, and pulse generators. Complementing this core lineup is a robust offering of driver and interface ICs, particularly high-performance I/O expanders that enable seamless connectivity and streamline complex electronic system architectures. Beyond these foundational integrated circuits, Analog Devices leads the industry in sensor innovation, delivering advanced MEMS accelerometers and integrated MEMS modules designed for exceptional precision in motion sensing. To support complete hardware designs, the company's specialized offerings also encompass discrete bipolar transistors, sub-2.4GHz RF transceivers, temperature-compensated oscillators, and dedicated power management components such as DC/DC converters and LED driver ICs.
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