ADXL345BCCZ-RL7

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## Data Sheet 

## 3-Axis, ±2 g/±4 g/±8 g/±16 g Di ital Accelerometer g ADXL345 

## **FEATURES** 

## **Ultralow power: as low as 23 µA in measurement mode and 0.1 µA in standby mode at VS = 2.5 V (typical) Power consumption scales automatically with bandwidth User-selectable resolution** 

## **Fixed 10-bit resolution** 

**Full resolution, where resolution increases with g range, up to 13-bit resolution at ±16 g (maintaining 4 mg/LSB scale factor in all g ranges)** 

## **Embedded memory management system with FIFO technology minimizes host processor load Single tap/double tap detection Activity/inactivity monitoring Free-fall detection** 

## **Supply voltage range: 2.0 V to 3.6 V I/O voltage range: 1.7 V to VS** 

## **SPI (3- and 4-wire) and I[2] C digital interfaces Flexible interrupt modes mappable to either interrupt pin Measurement ranges selectable via serial command Bandwidth selectable via serial command** 

**Wide temperature range (−40°C to +85°C) 10,000 g shock survival** 

**Pb free/RoHS compliant Small and thin: 3 mm × 5 mm × 1 mm LGA package** 

## **APPLICATIONS** 

## **GENERAL DESCRIPTION** 

The ADXL345 is a small, thin, ultralow power, 3-axis accelerometer with high resolution (13-bit) measurement at up to ±16 g. Digital output data is formatted as 16-bit twos complement and is accessible through either a SPI (3- or 4-wire) or I[2] C digital interface. 

The ADXL345 is well suited for mobile device applications. It measures the static acceleration of gravity in tilt-sensing applications, as well as dynamic acceleration resulting from motion or shock. Its high resolution (3.9 mg/LSB) enables measurement of inclination changes less than 1.0°. 

Several special sensing functions are provided. Activity and inactivity sensing detect the presence or lack of motion by comparing the acceleration on any axis with user-set thresholds. Tap sensing detects single and double taps in any direction. Freefall sensing detects if the device is falling. These functions can be mapped individually to either of two interrupt output pins. An integrated memory management system with a 32-level first in, first out (FIFO) buffer can be used to store data to minimize host processor activity and lower overall system power consumption. 

Low power modes enable intelligent motion-based power management with threshold sensing and active acceleration measurement at extremely low power dissipation. 

The ADXL345 is supplied in a small, thin, 3 mm × 5 mm × 1 mm, 14-lead, plastic package. 

## **Handsets** 

**Medical instrumentation Gaming and pointing devices Industrial instrumentation Personal navigation devices Hard disk drive (HDD) protection** 

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FUNCTIONAL BLOCK DIAGRAM<br>VS VDD I/O<br>ADXL345 POWER<br>MANAGEMENT<br>CONTROL INT1<br>SENSE ADC AND<br>ELECTRONICS DIGITAL INTERRUPT<br>3-AXIS FILTER LOGIC INT2<br>SENSOR<br>SDA/SDI/SDIO<br>32 LEVELFIFO SERIAL I/O SDO/ALT<br>ADDRESS<br>SCL/SCLK<br>GND CS<br>Figure 1.<br>07925-001<br>**----- End of picture text -----**<br>


**Rev. E Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.** 

**One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2009–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com** 

## **ADXL345* Product Page Quick Links** 

Last Content Update: 09/23/2016 

## Comparable Parts 

View a parametric search of comparable parts 

## Reference Designs 

- CN0133 

## Evaluation Kits 

- ADXL345 Datalogger / Development Board 

- ADXL345Z Breakout Board 

- Real Time Eval System for Digital Output Sensor 

## Documentation 

## **Application Notes** 

- AN-1025: Utilization of the First In, First Out (FIFO) Buffer in Analog Devices, Inc. Digital Accelerometers 

- AN-1057: Using an Accelerometer for Inclination Sensing 

- AN-1063: Oversampling Technique to Improve ADXL345 Output Resolution 

- AN-1077: ADXL345 Quick Start Guide 

- AN-688: Phase and Frequency Response of iMEMS® Accelerometers and Gyros 

## **Data Sheet** 

- ADXL345-EP: Enhanced Product Data Sheet 

- ADXL345: 3-Axis, ±2 g/±4 g/±8 g/±16 g Digital Accelerometer Data Sheet 

## **User Guides** 

- UG-015: _i_ MEMS ADXL345 Inertial Sensor Evaluation System 

- UG-065: Evaluation Board User Guide for ADXL345 

## Reference Materials 

## **Analog Dialogue** 

- Detecting Human Falls with a 3-Axis Digital Accelerometer 

- Full-Featured Pedometer Design Realized with 3-Axis Digital Accelerometer 

## **Informational** 

- Wireless Sensor Network (WSN) Demo System 

## **Press** 

- Analog Devices’ 256-Channel, 16-Bit Digital X-Ray Analog Front End Delivers Industry’s Best Combination of Noise, Power and Image Quality 

## **Technical Articles** 

- Human Fall Detection Using New MEMS Accelerometer Technology 

## **White Papers** 

- The Five Motion Senses: MEMS Inertial Sensing to Transform Applications 

## Design Resources 

- ADXL345 Material Declaration 

- PCN-PDN Information 

- Quality And Reliability 

- Symbols and Footprints 

## Software and Systems Requirements 

- ADXL345 - No-OS Driver for Microchip Microcontroller Platforms 

- ADXL345 - No-OS Driver for Renesas Microcontroller Platforms 

- ADXL345 Input 3-Axis Digital Accelerometer Linux Driver 

- ADXL345 Pmod Xilinx FPGA Reference Design 

## Tools and Simulations 

## Discussions 

View all ADXL345 EngineerZone Discussions 

## Sample and Buy 

Visit the product page to see pricing options 

## Technical Support 

Submit a technical question or find your regional support number 

- ADXL345/6 Accelerometer FIFO Over-sampling Calculator 

- Op Amp Stability with Capacitive Load 

* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. This content may be frequently modified. 

ADXL345 

Data Sheet 

## TABLE OF CONTENTS 

Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 3 Specifications ..................................................................................... 4 Absolute Maximum Ratings ............................................................ 6 Thermal Resistance ...................................................................... 6 Package Information .................................................................... 6 ESD Caution .................................................................................. 6 Pin Configuration and Function Descriptions ............................. 7 Typical Performance Characteristics ............................................. 8 Theory of Operation ...................................................................... 13 Power Sequencing ...................................................................... 13 Power Savings ............................................................................. 14 Serial Communications ................................................................. 15 SPI ................................................................................................. 15 I[2] C ................................................................................................. 18 Interrupts ..................................................................................... 20 FIFO ............................................................................................. 21 

Self-Test ....................................................................................... 22 Register Map ................................................................................... 23 Register Definitions ................................................................... 24 Applications Information .............................................................. 28 Power Supply Decoupling ......................................................... 28 Mechanical Considerations for Mounting .............................. 28 Tap Detection .............................................................................. 28 Threshold .................................................................................... 29 Link Mode ................................................................................... 29 Sleep Mode vs. Low Power Mode............................................. 30 Offset Calibration ....................................................................... 30 Using Self-Test ............................................................................ 31 Data Formatting of Upper Data Rates ..................................... 32 Noise Performance ..................................................................... 33 Operation at Voltages Other Than 2.5 V ................................ 33 Offset Performance at Lowest Data Rates ............................... 34 Axes of Acceleration Sensitivity ............................................... 35 Layout and Design Recommendations ................................... 36 Outline Dimensions ....................................................................... 37 Ordering Guide .......................................................................... 37 

Rev. E | Page 2 of 40 

Data Sheet 

ADXL345 

## **REVISION HISTORY** 

## **6/15—Rev. D to Rev. E** 

Changes to Features Section and General Description Section ........................................................................... 1 Change to Figure 36 ........................................................................ 15 Change to FIFO Section ................................................................. 21 

## **2/13—Rev. C to Rev. D** 

Changes to Figure 13, Figure 14, and Figure 15 ............................ 9 Change to Table 15 .......................................................................... 22 

## **5/11—Rev. B to Rev. C** 

Added Preventing Bus Traffic Errors Section  ............................ 15 Changes to Figure 37, Figure 38, Figure 39 ................................. 16 Changes to Table 12 ........................................................................ 19 Changes to Using Self-Test Section ............................................... 31 Changes to Axes of Acceleration Sensitivity Section .................. 35 

**11/10—Rev. A to Rev. B** Change to 0 g Offset vs. Temperature for Z-Axis Parameter, Table 1 ................................................................................................. 4 Changes to Figure 10 to Figure 15 .................................................. 9 Changes to Ordering Guide ........................................................... 37 

## **4/10—Rev. 0 to Rev. A** 

Changes to Features Section and General Description Section ........................................................................... 1 Changes to Specifications Section ................................................... 3 Changes to Table 2 and Table 3 ....................................................... 5 Added Package Information Section, Figure 2, and Table 4; Renumbered Sequentially ................................................................ 5 Changes to Pin 12 Description, Table 5 ......................................... 6 Added Typical Performance Characteristics Section ................... 7 Changes to Theory of Operation Section and Power Sequencing Section .............................................................................................. 12 Changes to Powers Savings Section, Table 7, Table 8, Auto Sleep Mode Section, and Standby Mode Section .................................. 13 Changes to SPI Section ................................................................... 14 

Changes to Figure 36 to Figure 38 ................................................ 15 Changes to Table 9 and Table 10 ................................................... 16 Changes to I[2] C Section and Table 11 ............................................ 17 Changes to Table 12 ........................................................................ 18 Changes to Interrupts Section, Activity Section, Inactivity Section, and FREE_FALL Section ................................................. 19 Added Table 13 ................................................................................ 19 Changes to FIFO Section ............................................................... 20 Changes to Self-Test Section and Table 15 to Table 18 .............. 21 Added Figures 42 and Table 14 ..................................................... 21 Changes to Table 19 ........................................................................ 22 Changes to Register 0x1D—THRESH_TAP (Read/Write) Section, Register 0x1E, Register 0x1F, Register 0x20—OFSX, OFSY, OSXZ (Read/Write) Section, Register 0x21—DUR (Read/Write) Section, Register 0x22—Latent (Read/Write) Section, and Register 0x23—Window (Read/Write) Section ... 23 Changes to ACT_X Enable Bits and INACT_X Enable Bit Section, Register 0x28—THRESH_FF (Read/Write) Section, Register 0x29—TIME_FF (Read/Write) Section, Asleep Bit Section, and AUTO_SLEEP Bit Section ....................................... 24 Changes to Sleep Bit Section ......................................................... 25 Changes to Power Supply Decoupling Section, Mechanical Considerations for Mounting Section, and Tap Detection Section .............................................................................................. 27 Changes to Threshold Section ....................................................... 28 Changes to Sleep Mode vs. Low Power Mode Section ............... 29 Added Offset Calibration Section ................................................. 29 Changes to Using Self-Test Section .............................................. 30 Added Data Formatting of Upper Data Rates Section, Figure 48, and Figure 49 ................................................................................... 31 Added Noise Performance Section, Figure 50 to Figure 52, and Operation at Voltages Other Than 2.5 V Section ....................... 32 Added Offset Performance at Lowest Data Rates Section and Figure 53 to Figure 55 ..................................................................... 33 

**6/09—Revision 0: Initial Version** 

Rev. E | Page 3 of 40 

ADXL345 

Data Sheet 

## SPECIFICATIONS 

TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V, acceleration = 0 g, CS = 10 µF tantalum, CI/O = 0.1 µF, output data rate (ODR) = 800 Hz, unless otherwise noted. All minimum and maximum specifications are guaranteed. Typical specifications are not guaranteed. **Table 1.** 

|**Table 1.**||||
|---|---|---|---|
|**Parameter**|**Test Conditions**|**Min**<br>**Typ1**<br>**Max**|**Unit**|
|SENSOR INPUT<br>Measurement Range<br>Nonlinearity<br>Inter-Axis Alignment Error<br>Cross-Axis Sensitivity2|Each axis<br>User selectable<br>Percentage of full scale|±2, ±4, ±8, ±16<br>±0.5<br>±0.1<br>±1|g<br>%<br>Degrees<br>%|
|OUTPUT RESOLUTION<br>AllgRanges<br>±2gRange<br>±4gRange<br>±8gRange<br>±16gRange|Each axis<br>10-bit resolution<br>Full resolution<br>Full resolution<br>Full resolution<br>Full resolution|10<br>10<br>11<br>12<br>13|Bits<br>Bits<br>Bits<br>Bits<br>Bits|
|SENSITIVITY<br>Sensitivity at XOUT, YOUT, ZOUT<br>Sensitivity Deviation from Ideal<br>Scale Factor at XOUT, YOUT, ZOUT<br>SensitivityChange Due to Temperature|Each axis<br>Allg-ranges, full resolution<br>±2g, 10-bit resolution<br>±4g, 10-bit resolution<br>±8g,10-bit resolution<br>±16g,10-bit resolution<br>Allg-ranges<br>Allg-ranges, full resolution<br>±2g, 10-bit resolution<br>±4g,10-bit resolution<br>±8g,10-bit resolution<br>±16g,10-bit resolution|230<br>256<br>282<br>230<br>256<br>282<br>115<br>128<br>141<br>57<br>64<br>71<br>29<br>32<br>35<br>±1.0<br>3.5<br>3.9<br>4.3<br>3.5<br>3.9<br>4.3<br>7.1<br>7.8<br>8.7<br>14.1<br>15.6<br>17.5<br>28.6<br>31.2<br>34.5<br>±0.01|LSB/g<br>LSB/g<br>LSB/g<br>LSB/g<br>LSB/g<br>%<br>mg/LSB<br>mg/LSB<br>mg/LSB<br>mg/LSB<br>mg/LSB<br>%/°C|
|0gOFFSET<br>0gOutput for XOUT, YOUT<br>0gOutput for ZOUT<br>0gOutput Deviation from Ideal, XOUT, YOUT<br>0gOutput Deviation from Ideal, ZOUT<br>0gOffset vs. Temperature for X-, Y-Axes<br>0gOffset vs. Temperature for Z-Axis|Each axis|−150<br>0<br>+150<br>−250<br>0<br>+250<br>±35<br>±40<br>±0.4<br>±1.2|mg<br>mg<br>mg<br>mg<br>mg/°C<br>mg/°C|
|NOISE<br>X-, Y-Axes<br>Z-Axis|ODR = 100 Hz for ±2g, 10-bit resolution or<br>allg-ranges, full resolution<br>ODR = 100 Hz for ±2g, 10-bit resolution or<br>allg-ranges, full resolution|0.75<br>1.1|LSB rms<br>LSB rms|
|OUTPUT DATA RATE AND BANDWIDTH<br>Output Data Rate (ODR)3, 4, 5|User selectable|0.1<br>3200|Hz|
|SELF-TEST6<br>Output Change in X-Axis<br>Output Change in Y-Axis<br>Output Change in Z-Axis||0.20<br>2.10<br>−2.10<br>−0.20<br>0.30<br>3.40|g<br>g<br>g|
|POWER SUPPLY<br>Operating Voltage Range (VS)<br>Interface Voltage Range (VDD I/O)<br>Supply Current<br>Standby Mode Leakage Current<br>Turn-On and Wake-UpTime7|ODR ≥ 100 Hz<br>ODR < 10 Hz<br>ODR = 3200 Hz|2.0<br>2.5<br>3.6<br>1.7<br>1.8<br>VS<br>140<br>30<br>0.1<br>1.4|V<br>V<br>µA<br>µA<br>µA<br>ms|



Rev. E | Page 4 of 40 

Data Sheet ADXL345 

|**Parameter**|**Test Conditions**|**Min**<br>**Typ1**<br>**Max**|**Unit**|
|---|---|---|---|
|TEMPERATURE<br>OperatingTemperature Range||−40<br>+85|°C|
|WEIGHT<br>Device Weight||30|mg|



- 1 The typical specifications shown are for at least 68% of the population of parts and are based on the worst case of mean ±1 σ, except for 0 g output and sensitivity, which represents the target value. For 0 g offset and sensitivity, the deviation from the ideal describes the worst case of mean ±1 σ. 

- 2 Cross-axis sensitivity is defined as coupling between any two axes. 

- 3 Bandwidth is the −3 dB frequency and is half the output data rate, bandwidth = ODR/2. 

- 4 The output format for the 3200 Hz and 1600 Hz ODRs is different than the output format for the remaining ODRs. This difference is described in the Data Formatting of Upper Data Rates section. 

- 5 Output data rates below 6.25 Hz exhibit additional offset shift with increased temperature, depending on selected output data rate. Refer to the Offset Performance at Lowest Data Rates section for details. 

- 6 Self-test change is defined as the output (g) when the SELF_TEST bit = 1 (in the DATA_FORMAT register, Address 0x31) minus the output (g) when the SELF_TEST bit = 0. Due to device filtering, the output reaches its final value after 4 × τ when enabling or disabling self-test, where τ = 1/(data rate). The part must be in normal power operation (LOW_POWER bit = 0 in the BW_RATE register, Address 0x2C) for self-test to operate correctly. 

7 Turn-on and wake-up times are determined by the user-defined bandwidth. At a 100 Hz data rate, the turn-on and wake-up times are each approximately 11.1 ms. For other data rates, the turn-on and wake-up times are each approximately τ + 1.1 in milliseconds, where τ = 1/(data rate). 

Rev. E | Page 5 of 40 

ADXL345 

Data Sheet 

## ABSOLUTE MAXIMUM RATINGS 

## **Table 2.** 

|**Table 2.**||
|---|---|
|**Parameter**|**Rating**|
|Acceleration<br>Any Axis, Unpowered<br>Any Axis, Powered<br>VS<br>VDD I/O<br>Digital Pins<br>All Other Pins<br>Output Short-Circuit Duration<br>(Any Pin to Ground)<br>Temperature Range<br>Powered<br>Storage|10,000g<br>10,000g<br>−0.3 V to +3.9 V<br>−0.3 V to +3.9 V<br>−0.3 V to VDD I/O+ 0.3 V or 3.9 V,<br>whichever is less<br>−0.3 V to +3.9 V<br>Indefinite<br>−40°C to +105°C<br>−40°C to +105°C|



Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. 

## **THERMAL RESISTANCE** 

**Table 3. Package Characteristics** 

|**Package Type **|**θJA**|**θJC**|**Device Weight**|
|---|---|---|---|
|14-Terminal LGA|150°C/W|85°C/W|30 mg|



## **PACKAGE INFORMATION** 

The information in Figure 2 and Table 4 provide details about the package branding for the ADXL345. For a complete listing of product availability, see the Ordering Guide section. 

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3 4 5 B<br># y w w<br>v v v v<br>C N T Y<br>07925-102<br>**----- End of picture text -----**<br>


Figure 2. Product Information on Package (Top View) 

**Table 4. Package Branding Information** 

|**Branding Key**|**Field Description**|
|---|---|
|345B<br>#<br>yww<br>vvvv<br>CNTY|Part identifier forADXL345<br>RoHS-compliant designation<br>Date code<br>Factory lot code<br>Countryof origin|



## **ESD CAUTION** 

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Rev. E | Page 6 of 40 

Data Sheet 

ADXL345 

## PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 

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ADXL345<br>TOP VIEW<br>(Not to Scale)<br>SCL/SCLK<br>VDD I/O 1 14 13 SDA/SDI/SDIO<br>GND 2 12 SDO/ALT ADDRESS<br>RESERVED 3 11 RESERVED<br>+x<br>GND 4 10 NC<br>+y<br>+z<br>GND 5 9 INT2<br>VS 6 7 8 INT1<br>CS<br>NOTES<br>1. NC = NO INTERNAL CONNECTION. 07925-002<br>**----- End of picture text -----**<br>


Figure 3. Pin Configuration (Top View) 

**Table 5. Pin Function Descriptions** 

|**Pin No.**|**Mnemonic**|**Description**|
|---|---|---|
|1<br>2<br>3<br>4<br>5<br>6<br>7<br>8<br>9<br>10<br>11<br>12<br>13<br>14|VDD I/O<br>GND<br>RESERVED<br>GND<br>GND<br>VS<br>CS<br>INT1<br>INT2<br>NC<br>RESERVED<br>SDO/ALT ADDRESS<br>SDA/SDI/SDIO<br>SCL/SCLK|Digital Interface Supply Voltage.<br>This pin must be connected to ground.<br>Reserved. This pin must be connected to VSor left open.<br>This pin must be connected to ground.<br>This pin must be connected to ground.<br>Supply Voltage.<br>Chip Select.<br>Interrupt 1 Output.<br>Interrupt 2 Output.<br>Not Internally Connected.<br>Reserved. This pin must be connected to ground or left open.<br>Serial Data Output (SPI 4-Wire)/Alternate I2C Address Select (I2C).<br>Serial Data (I2C)/Serial Data Input (SPI 4-Wire)/Serial Data Input and Output (SPI 3-Wire).<br>Serial Communications Clock. SCL is the clock for I2C, and SCLK is the clock for SPI.|



Rev. E | Page 7 of 40 

ADXL345 

Data Sheet 

## TYPICAL PERFORMANCE CHARACTERISTICS 

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20<br>18<br>16<br>14<br>12<br>10<br>8<br>6<br>4<br>2<br>0<br>–150 –100 –50 0 50 100 150<br>ZERO  g  OFFSET (m g )<br>PERCENT OF POPULATION (%)<br>07925-204<br>**----- End of picture text -----**<br>


Figure 4. X-Axis Zero g Offset at 25°C, VS = 2.5 V 

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20<br>18<br>16<br>14<br>12<br>10<br>8<br>6<br>4<br>2<br>0<br>–150 –100 –50 0 50 100 150<br>ZERO  g  OFFSET (m g )<br>PERCENT OF POPULATION (%)<br>07925-205<br>**----- End of picture text -----**<br>


Figure 5. Y-Axis Zero g Offset at 25°C, VS = 2.5 V 

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20<br>18<br>16<br>14<br>12<br>10<br>8<br>6<br>4<br>2<br>0<br>–150 –100 –50 0 50 100 150<br>ZERO  g  OFFSET (m g )<br>Figure 6. Z-Axis Zero g Offset at 25°C, VS = 2.5 V<br>PERCENT OF POPULATION (%)<br>07925-206<br>**----- End of picture text -----**<br>


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20<br>18<br>16<br>14<br>12<br>10<br>8<br>6<br>4<br>2<br>0<br>–150 –100 –50 0 50 100 150<br>ZERO  g  OFFSET (m g )<br>Figure 7. X-Axis Zero g Offset at 25°C, VS = 3.3 V<br>PERCENT OF POPULATION (%)<br>07925-207<br>**----- End of picture text -----**<br>


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20<br>18<br>16<br>14<br>12<br>10<br>8<br>6<br>4<br>2<br>0<br>–150 –100 –50 0 50 100 150<br>ZERO  g  OFFSET (m g )<br>Figure 8. Y-Axis Zero g Offset at 25°C, VS = 3.3 V<br>20<br>18<br>16<br>14<br>12<br>10<br>8<br>6<br>4<br>2<br>0<br>–150 –100 –50 0 50 100 150<br>ZERO  g  OFFSET (m g )<br>Figure 9. Z-Axis Zero g Offset at 25°C, VS = 3.3 V<br>PERCENT OF POPULATION (%)<br>07925-208<br>PERCENT OF POPULATION (%)<br>07925-209<br>**----- End of picture text -----**<br>


Rev. E | Page 8 of 40 

Data Sheet 

ADXL345 

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30<br>25<br>20<br>15<br>10<br>5<br>0<br>–2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0<br>ZERO  g  OFFSET TEMPERATURE COEFFICIENT (m g /°C)<br>Figure 10. X-Axis Zero g Offset Temperature Coefficient, VS = 2.5 V g Offset Temperature Coefficient, VS = 2.5 V  Offset Temperature Coefficient, VS = 2.5 V S = 2.5 V  = 2.5 V<br>30<br>25<br>20<br>15<br>10<br>5<br>0<br>–2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0<br>ZERO  g  OFFSET TEMPERATURE COEFFICIENT (m g /°C)<br>PERCENT OF POPULATION (%)<br>07925-210<br>PERCENT OF POPULATION (%)<br>07925-211<br>**----- End of picture text -----**<br>


Figure 10. X-Axis Zero g Offset Temperature Coefficient, VS = 2.5 V g Offset Temperature Coefficient, VS = 2.5 V  Offset Temperature Coefficient, VS = 2.5 V S = 2.5 V  = 2.5 V 

Figure 11. Y-Axis Zero g Offset Temperature Coefficient, VS = 2.5 V 

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25<br>20<br>15<br>10<br>5<br>0<br>–2.0 –1.5 –1.0 –0.5 0 0.5 1.0 1.5 2.0<br>ZERO  g  OFFSET TEMPERATURE COEFFICIENT (m g /°C)<br>PERCENT OF POPULATION (%)<br>07925-212<br>**----- End of picture text -----**<br>


Figure 12. Z-Axis Zero g Offset Temperature Coefficient, VS = 2.5 V 

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150<br>100<br>50<br>0<br>–50<br>–100<br>–150<br>–60 –40 –20 0 20 40 60 80 100<br>TEMPERATURE (°C)<br>Figure 13. X-Axis Zero g Offset vs. Temperature—<br>45 Parts Soldered to PCB, VS = 2.5 V<br>150<br>100<br>50<br>0<br>–50<br>–100<br>–150<br>–60 –40 –20 0 20 40 60 80 100<br>TEMPERATURE (°C)<br>Figure 14. Y-Axis Zero g Offset vs. Temperature—<br>45 Parts Soldered to PCB, VS = 2.5 V<br>1250<br>1200<br>1150<br>1100<br>1050<br>1000<br>950<br>900<br>850<br>800<br>750<br>–60 –40 –20 0 20 40 60 80 100<br>TEMPERATURE (°C)<br>) g<br>OUTPUT (m<br>07925-213<br>) g<br>OUTPUT (m<br>07925-214<br>) g<br>OUTPUT (m<br>07925-215<br>**----- End of picture text -----**<br>


Figure 15. Z-Axis One g Offset vs. Temperature— 45 Parts Soldered to PCB, VS = 2.5 V 

Rev. E | Page 9 of 40 

ADXL345 

Data Sheet 

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55<br>50<br>45<br>40<br>35<br>30<br>25<br>20<br>15<br>10<br>5<br>0<br>230 234 238 242 246 250 254 258 262 266 270 274 278 282<br>SENSITIVITY (LSB/ g )<br>Figure 16. X-Axis Sensitivity at 25°C, VS = 2.5 V, Full Resolution<br>55<br>50<br>45<br>40<br>35<br>30<br>25<br>20<br>15<br>10<br>5<br>0<br>230 234 238 242 246 250 254 258 262 266 270 274 278 282<br>SENSITIVITY (LSB/ g )<br>Figure 17. Y-Axis Sensitivity at 25°C, VS = 2.5 V, Full Resolution<br>55<br>50<br>45<br>40<br>35<br>30<br>25<br>20<br>15<br>10<br>5<br>0<br>230 234 238 242 246 250 254 258 262 266 270 274 278 282<br>SENSITIVITY (LSB/ g )<br> PERCENT OF POPULATION (%)<br>07925-216<br> PERCENT OF POPULATION (%)<br>07925-217<br> PERCENT OF POPULATION (%)<br>07925-218<br>**----- End of picture text -----**<br>


Figure 18. Z-Axis Sensitivity at 25°C, VS = 2.5 V, Full Resolution 

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**----- Start of picture text -----**<br>
40<br>35<br>30<br>25<br>20<br>15<br>10<br>5<br>0<br>–0.02 –0.01 0 0.01 0.02<br>SENSITIVITY TEMPERATURE COEFFICIENT (%/°C)<br>Figure 19. X-Axis Sensitivity Temperature Coefficient, VS = 2.5 V<br>40<br>35<br>30<br>25<br>20<br>15<br>10<br>5<br>0<br>–0.02 –0.01 0 0.01 0.02<br>SENSITIVITY TEMPERATURE COEFFICIENT (%/°C)<br>Figure 20. Y-Axis Sensitivity Temperature Coefficient, VS = 2.5 V<br>40<br>35<br>30<br>25<br>20<br>15<br>10<br>5<br>0<br>–0.02 –0.01 0 0.01 0.02<br>SENSITIVITY TEMPERATURE COEFFICIENT (%/°C)<br>PERCENT OF POPULATION (%)<br>07925-219<br>PERCENT OF POPULATION (%)<br>07925-220<br>PERCENT OF POPULATION (%)<br>07925-221<br>**----- End of picture text -----**<br>


Figure 21. Z-Axis Sensitivity Temperature Coefficient, VS = 2.5 V 

Rev. E | Page 10 of 40 

ADXL345 

## Data Sheet 

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**----- Start of picture text -----**<br>
280<br>275<br>270<br>265<br>260<br>255<br>250<br>245<br>240<br>235<br>230<br>–40 –20 0 20 40 60 80 100 120<br>TEMPERATURE (°C)<br>Figure 22. X-Axis Sensitivity vs. Temperature—<br>Eight Parts Soldered to PCB, VS = 2.5 V, Full Resolution<br>280<br>275<br>270<br>265<br>260<br>255<br>250<br>245<br>240<br>235<br>230<br>–40 –20 0 20 40 60 80 100 120<br>TEMPERATURE (°C)<br>Figure 23. Y-Axis Sensitivity vs. Temperature—<br>Eight Parts Soldered to PCB, VS = 2.5 V, Full Resolution<br>280<br>275<br>270<br>265<br>260<br>255<br>250<br>245<br>240<br>235<br>230<br>–40 –20 0 20 40 60 80 100 120<br>TEMPERATURE (°C)<br>) g<br>SENSITIVITY (LSB/<br>07925-222<br>) g<br>SENSITIVITY (LSB/<br>07925-223<br>) g<br>SENSITIVITY (LSB/<br>07925-224<br>**----- End of picture text -----**<br>


Figure 24. Z-Axis Sensitivity vs. Temperature— Eight Parts Soldered to PCB, VS = 2.5 V, Full Resolution 

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**----- Start of picture text -----**<br>
280<br>275<br>270<br>265<br>260<br>255<br>250<br>245<br>240<br>235<br>230<br>–40 –20 0 20 40 60 80 100 120<br>TEMPERATURE (°C)<br>Figure 25. X-Axis Sensitivity vs. Temperature—<br>Eight Parts Soldered to PCB, VS = 3.3 V, Full Resolution<br>280<br>275<br>270<br>265<br>260<br>255<br>250<br>245<br>240<br>235<br>230<br>–40 –20 0 20 40 60 80 100 120<br>TEMPERATURE (°C)<br>Figure 26. Y-Axis Sensitivity vs. Temperature—<br>Eight Parts Soldered to PCB, VS = 3.3 V, Full Resolution<br>280<br>275<br>270<br>265<br>260<br>255<br>250<br>245<br>240<br>235<br>230<br>–40 –20 0 20 40 60 80 100 120<br>TEMPERATURE (°C)<br>Figure 27. Z-Axis Sensitivity vs. Temperature—<br>Eight Parts Soldered to PCB, VS = 3.3 V, Full Resolution<br>) g<br>SENSITIVITY (LSB/<br>07925-225<br>) g<br>SENSITIVITY (LSB/<br>07925-226<br>) g<br>SENSITIVITY (LSB/<br>07925-227<br>**----- End of picture text -----**<br>


Rev. E | Page 11 of 40 

ADXL345 

Data Sheet 

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60<br>50<br>40<br>30<br>20<br>10<br>0<br>0.2 0.5 0.8 1.1 1.4 1.7 2.0<br>SELF-TEST RESPONSE ( g )<br>PERCENT OF POPULATION (%)<br>07925-228<br>**----- End of picture text -----**<br>


Figure 28. X-Axis Self-Test Response at 25°C, VS = 2.5 V 

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60<br>50<br>40<br>30<br>20<br>10<br>0<br>–0.2 –0.5 –0.8 –1.1 –1.4 –1.7 –2.0<br>SELF-TEST RESPONSE ( g )<br>PERCENT OF POPULATION (%)<br>07925-229<br>**----- End of picture text -----**<br>


Figure 29. Y-Axis Self-Test Response at 25°C, VS = 2.5 V 

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60<br>50<br>40<br>30<br>20<br>10<br>0<br>0.3 0.9 1.5 2.1 2.7 3.3<br>SELF-TEST RESPONSE ( g )<br>PERCENT OF POPULATION (%)<br>07925-230<br>**----- End of picture text -----**<br>


Figure 30. Z-Axis Self-Test Response at 25°C, VS = 2.5 V 

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**----- Start of picture text -----**<br>
25<br>20<br>15<br>10<br>5<br>0<br>100 110 120 130 140 150 160 170 180 190 200<br>CURRENT CONSUMPTION (µA)<br>Figure 31. Current Consumption at 25°C, 100 Hz Output Data Rate, VSS = 2.5 V<br>160<br>140<br>120<br>100<br>80<br>60<br>40<br>20<br>0<br>1.60 3.12 6.25 12.50 25 50 100 200 400 800 1600 3200<br>OUTPUT DATA RATE (Hz)<br>Figure 32. Current Consumption vs. Output Data Rate at 25°C—10 Parts,<br>VS = 2.5 V S = 2.5 V  = 2.5 V<br>200<br>150<br>100<br>50<br>0<br>2.0 2.4 2.8 3.2 3.6<br>SUPPLY VOLTAGE (V)<br> PERCENT OF POPULATION (%)<br>07925-231<br>CURRENT CONSUMPTION (µA)<br>07925-232<br>SUPPLY CURRENT (µA)<br>07925-233<br>**----- End of picture text -----**<br>


Figure 31. Current Consumption at 25°C, 100 Hz Output Data Rate, VSS = 2.5 V 

Figure 32. Current Consumption vs. Output Data Rate at 25°C—10 Parts, VS = 2.5 V S = 2.5 V  = 2.5 V 

Figure 33. Supply Current vs. Supply Voltage, VS at 25°C 

Rev. E | Page 12 of 40 

Data Sheet 

ADXL345 

## THEORY OF OPERATION 

The ADXL345 is a complete 3-axis acceleration measurement system with a selectable measurement range of ±2 g, ±4 g, ±8 g, or ±16 g. It measures both dynamic acceleration resulting from motion or shock and static acceleration, such as gravity, that allows the device to be used as a tilt sensor. 

The sensor is a polysilicon surface-micromachined structure built on top of a silicon wafer. Polysilicon springs suspend the structure over the surface of the wafer and provide a resistance against forces due to applied acceleration. 

Deflection of the structure is measured using differential capacitors that consist of independent fixed plates and plates attached to the moving mass. Acceleration deflects the proof mass and unbalances the differential capacitor, resulting in a sensor output whose amplitude is proportional to acceleration. Phase-sensitive demodulation is used to determine the magnitude and polarity of the acceleration. 

## **POWER SEQUENCING** 

Power can be applied to VS or VDD I/O in any sequence without damaging the ADXL345. All possible power-on modes are summarized in Table 6. The interface voltage level is set with the interface supply voltage, VDD I/O, which must be present to ensure that the ADXL345 does not create a conflict on the communication bus. For single-supply operation, VDD I/O can be the same as the main supply, VS. In a dual-supply application, however, VDD I/O can differ from VS to accommodate the desired interface voltage, as long as VS is greater than or equal to VDD I/O. 

After VS is applied, the device enters standby mode, where power consumption is minimized and the device waits for VDD I/O to be applied and for the command to enter measurement mode to be received. (This command can be initiated by setting the measure bit (Bit D3) in the POWER_CTL register (Address 0x2D).) In addition, while the device is in standby mode, any register can be written to or read from to configure the part. It is recommended to configure the device in standby mode and then to enable measurement mode. Clearing the measure bit returns the device to the standby mode. 

**Table 6. Power Sequencing** 

|**Condition**|**VS**|**VDD I/O**|**Description**|
|---|---|---|---|
|Power Off<br>Bus Disabled<br>Bus Enabled<br>Standby or Measurement|Off<br>On<br>Off<br>On|Off<br>Off<br>On<br>On|The device is completely off, but there is a potential for a communication bus conflict.<br>The device is on in standby mode, but communication is unavailable and creates a conflict on<br>the communication bus. The duration of this state should be minimized during power-up to<br>prevent a conflict.<br>No functions are available, but the device does not create a conflict on the communication bus.<br>At power-up, the device is in standby mode, awaiting a command to enter measurement<br>mode, and all sensor functions are off. After the device is instructed to enter measurement<br>mode, all sensor functions are available.|



Rev. E | Page 13 of 40 

Data Sheet 

## ADXL345 

## **POWER SAVINGS** 

## **Power Modes** 

The ADXL345 automatically modulates its power consumption in proportion to its output data rate, as outlined in Table 7. If additional power savings is desired, a lower power mode is available. In this mode, the internal sampling rate is reduced, allowing for power savings in the 12.5 Hz to 400 Hz data rate range at the expense of slightly greater noise. To enter low power mode, set the LOW_POWER bit (Bit 4) in the BW_RATE register (Address 0x2C). Table 8 shows the current consumption in low power mode for cases where there is an advantage to using low power mode. Use of low power mode for a data rate not shown in Table 8 does not provide any advantage over the same data rate in normal power mode. Therefore, it is recommended that only data rates shown in Table 8 be used in low power mode. The current consumption values shown in Table 7 and Table 8 are for a VS of 2.5 V. 

**Table 7. Typical Current Consumption vs. Data Rate (TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)** 

|**(TA = 25°C, VS =**|**2.5 V, VDD I/O = 1.8 V**|**)**||
|---|---|---|---|
|**Output Data**<br>**Rate (Hz)**|**Bandwidth (Hz)**|**Rate Code**|**IDD (µA)**|
|3200<br>1600<br>800<br>400<br>200<br>100<br>50<br>25<br>12.5<br>6.25<br>3.13<br>1.56<br>0.78<br>0.39<br>0.20<br>0.10|1600<br>800<br>400<br>200<br>100<br>50<br>25<br>12.5<br>6.25<br>3.13<br>1.56<br>0.78<br>0.39<br>0.20<br>0.10<br>0.05|1111<br>1110<br>1101<br>1100<br>1011<br>1010<br>1001<br>1000<br>0111<br>0110<br>0101<br>0100<br>0011<br>0010<br>0001<br>0000|140|
||||90|
||||140|
||||140|
||||140|
||||140|
||||90|
||||60|
||||50|
||||45|
||||40|
||||34|
||||23|
||||23|
||||23|
||||23|



**Table 8. Typical Current Consumption vs. Data Rate, Low Power Mode (TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)** 

|**Low Power Mo**|**e(TA = 25C, VS = 2.**|**V, VDD I/O = 1.**|**V)**|
|---|---|---|---|
|**Output Data**<br>**Rate (Hz)**|**Bandwidth (Hz)**|**Rate Code**|**IDD (µA)**|
|400<br>200<br>100<br>50<br>25<br>12.5|200<br>100<br>50<br>25<br>12.5<br>6.25|1100<br>1011<br>1010<br>1001<br>1000<br>0111|90<br>60<br>50<br>45<br>40<br>34|



## **Auto Sleep Mode** 

Additional power can be saved if the ADXL345 automatically switches to sleep mode during periods of inactivity. To enable this feature, set the THRESH_INACT register (Address 0x25) and the TIME_INACT register (Address 0x26) each to a value that signifies inactivity (the appropriate value depends on the application), and then set the AUTO_SLEEP bit (Bit D4) and the link bit (Bit D5) in the POWER_CTL register (Address 0x2D). Current consumption at the sub-12.5 Hz data rates that are used in this mode is typically 23 µA for a VS of 2.5 V. 

## **Standby Mode** 

For even lower power operation, standby mode can be used. In standby mode, current consumption is reduced to 0.1 µA (typical). In this mode, no measurements are made. Enter standby mode by clearing the measure bit (Bit D3) in the POWER_CTL register (Address 0x2D). Placing the device into standby mode preserves the contents of FIFO. 

Rev. E | Page 14 of 40 

Data Sheet 

ADXL345 

## SERIAL COMMUNICATIONS 

I[2] C and SPI digital communications are available. In both cases, the ADXL345 operates as a slave. I[2] C mode is enabled if the CS pin is tied high to VDD I/O. The CS pin should always be tied high to VDD I/O or be driven by an external controller because there is no default mode if the CS pin is left unconnected. Therefore, not taking these precautions may result in an inability to communicate with the part. In SPI mode, the CS pin is controlled by the bus master. In both SPI and I[2] C modes of operation, data transmitted from the ADXL345 to the master device should be ignored during writes to the ADXL345. 

## **SPI** 

For SPI, either 3- or 4-wire configuration is possible, as shown in the connection diagrams in Figure 34 and Figure 35. Clearing the SPI bit (Bit D6) in the DATA_FORMAT register (Address 0x31) selects 4-wire mode, whereas setting the SPI bit selects 3-wire mode. The maximum SPI clock speed is 5 MHz with 100 pF maximum loading, and the timing scheme follows clock polarity (CPOL) = 1 and clock phase (CPHA) = 1. If power is applied to the ADXL345 before the clock polarity and phase of the host processor are configured, the CS pin should be brought high before changing the clock polarity and phase. When using 3-wire SPI, it is recommended that the SDO pin be either pulled up to VDD I/O or pulled down to GND via a 10 kΩ resistor. 

**==> picture [140 x 152] intentionally omitted <==**

**----- Start of picture text -----**<br>
ADXL345 PROCESSOR<br>CS D OUT<br>SDIO D IN/OUT<br>SDO<br>SCLK D OUT<br>Figure 34. 3-Wire SPI Connection Diagram<br>ADXL345 PROCESSOR<br>CS D OUT<br>SDI D OUT<br>SDO D IN<br>SCLK D OUT<br>07925-004<br>07925-003<br>**----- End of picture text -----**<br>


Figure 35. 4-Wire SPI Connection Diagram 

CS is the serial port enable line and is controlled by the SPI master. This line must go low at the start of a transmission and high at the end of a transmission, as shown in Figure 37. SCLK is the serial port clock and is supplied by the SPI master. SCLK should idle high during a period of no transmission. SDI and SDO are the serial data input and output, respectively. Data is updated on the falling edge of SCLK and should be sampled on the rising edge of SCLK. 

To read or write multiple bytes in a single transmission, the multiple-byte bit, located after the R/W bit in the first byte transfer (MB in Figure 37 to Figure 39), must be set. After the register addressing and the first byte of data, each subsequent set of clock pulses (eight clock pulses) causes the ADXL345 to point to the next register for a read or write. This shifting continues until the clock pulses cease and CS is deasserted. To perform reads or writes on different, nonsequential registers, CS must be deasserted between transmissions and the new register must be addressed separately. 

The timing diagram for 3-wire SPI reads or writes is shown in Figure 39. The 4-wire equivalents for SPI writes and reads are shown in Figure 37 and Figure 38, respectively. For correct operation of the part, the logic thresholds and timing parameters in Table 9 and Table 10 must be met at all times. 

Use of the 3200 Hz and 1600 Hz output data rates is only recommended with SPI communication rates greater than or equal to 2 MHz. The 800 Hz output data rate is recommended only for communication speeds greater than or equal to 400 kHz, and the remaining data rates scale proportionally. For example, the minimum recommended communication speed for a 200 Hz output data rate is 100 kHz. Operation at an output data rate above the recommended maximum may result in undesirable effects on the acceleration data, including missing samples or additional noise. 

## **Preventing Bus Traffic Errors** 

The ADXL346 CS pin is used both for initiating SPI transactions, and for enabling I[2] C mode. When the ADXL346 is used on a SPI bus with multiple devices, its CS pin is held high while the master communicates with the other devices. There may be conditions where a SPI command transmitted to another device looks like a valid I[2] C command. In this case, the ADXL346 would interpret this as an attempt to communicate in I[2] C mode, and could interfere with other bus traffic. Unless bus traffic can be adequately controlled to assure such a condition never occurs, it is recommended to add a logic gate in front of the SDI pin as shown in Figure 36. This OR gate will hold the SDA line high when CS is high to prevent SPI bus traffic at the ADXL346 from appearing as an I[2] C start command. 

**==> picture [140 x 66] intentionally omitted <==**

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ADXL345 PROCESSOR<br>CS D OUT<br>SDIO D IN/OUT<br>SDO<br>SCLK D OUT<br>07925-104<br>**----- End of picture text -----**<br>


Figure 36. Recommended SPI Connection Diagram when Using Multiple SPI Devices on a Single Bus 

Rev. E | Page 15 of 40 

ADXL345 

Data Sheet 

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**----- Start of picture text -----**<br>
CS<br>tDELAY tSCLK tM tS tQUIET tCS,DIS<br>SCLK<br>tSETUP tHOLD<br>SDI W MB A5 A0 D7 D0<br>tSDO ADDRESS BITS DATA BITS tDIS<br>SDO X X X X X X<br>Figure 37. SPI 4-Wire Write<br>CS<br>tDELAY tSCLK tM tS tQUIET tCS,DIS<br>SCLK<br>tSETUP tHOLD<br>SDI R MB A5 A0 X X<br>tSDO ADDRESS BITS tDIS<br>SDO X X X X D7 D0<br>DATA BITS<br>Figure 38. SPI 4-Wire Read<br>CS<br>tDELAY tSCLK tM tS tQUIET tCS,DIS<br>SCLK<br>tSETUP tHOLD tSDO<br>SDIO R/W MB A5 A0 D7 D0<br>ADDRESS BITS DATA BITS<br>SDO<br>NOTES<br>1. tSDO IS ONLY PRESENT DURING READS.<br>07925-017<br>07925-018<br>**----- End of picture text -----**<br>


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07925-019<br>**----- End of picture text -----**<br>


Figure 39. SPI 3-Wire Read/Write 

Rev. E | Page 16 of 40 

ADXL345 

## Data Sheet 

**Table 9. SPI Digital Input/Output** 

|**Table 9. SPI Digital Input/Output**||||
|---|---|---|---|
|**Parameter**|**Test Conditions**|**Limit1**<br>**Min**<br>**Max**|**Unit**|
|Digital Input<br>Low Level Input Voltage (VIL)<br>High Level Input Voltage (VIH)<br>Low Level Input Current (IIL)<br>High Level Input Current (IIH)<br>Digital Output<br>Low Level Output Voltage (VOL)<br>High Level Output Voltage (VOH)<br>Low Level Output Current (IOL)<br>High Level Output Current (IOH)<br>Pin Capacitance|VIN= VDD I/O<br>VIN= 0 V<br>IOL= 10 mA<br>IOH= −4 mA<br>VOL= VOL, max<br>VOH= VOH, min<br>fIN= 1 MHz, VIN= 2.5 V|0.3 × VDD I/O<br>0.7 × VDD I/O<br>0.1<br>−0.1<br>0.2 × VDD I/O<br>0.8 × VDD I/O<br>10<br>−4<br>8|V<br>V<br>µA<br>µA<br>V<br>V<br>mA<br>mA<br>pF|



1 Limits based on characterization results, not production tested. 

**Table 10. SPI Timing (TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)[1]** 

|**Table 10. SPI**|**iming (TA = 25C, VS**|**= 2.5 V,**|**VDD I/O = 1.8 V)**|
|---|---|---|---|
|**Parameter**|**Limit2, 3**<br>**Min**<br>**Max**|**Unit**|**Description**|
|fSCLK<br>tSCLK<br>tDELAY<br>tQUIET<br>tDIS<br>tCS,DIS<br>tS<br>tM<br>tSETUP<br>tHOLD<br>tSDO<br>tR4<br>tF4|5<br>200<br>5<br>5<br>10<br>150<br>0.3 × tSCLK<br>0.3 × tSCLK<br>5<br>5<br>40<br>20<br>20|MHz<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns<br>ns|SPI clock frequency<br>1/(SPI clock frequency) mark-space ratio for the SCLK input is 40/60 to 60/40<br>CS<br>falling edge to SCLK falling edge<br>SCLK rising edge to CS<br>rising edge<br>CS<br>rising edge to SDO disabled<br>CS<br>deassertion between SPI communications<br>SCLK low pulse width (space)<br>SCLK high pulse width (mark)<br>SDI valid before SCLK rising edge<br>SDI valid after SCLK rising edge<br>SCLK falling edge to SDO/SDIO output transition<br>SDO/SDIO output high to output low transition<br>SDO/SDIO output low to output high transition|



1 The CS, SCLK, SDI, and SDO pins are not internally pulled up or down; they must be driven for proper operation. 

2 Limits based on characterization results, characterized with fSCLK = 5 MHz and bus load capacitance of 100 pF; not production tested. 

3 The timing values are measured corresponding to the input thresholds (VIL and VIH) given in Table 9. 

4 Output rise and fall times measured with capacitive load of 150 pF. 

Rev. E | Page 17 of 40 

ADXL345 

Data Sheet 

## **I[2] C** 

With CS tied high to VDD I/O, the ADXL345 is in I[2] C mode, requiring a simple 2-wire connection, as shown in Figure 40. The ADXL345 conforms to the UM10204 I[2] C-Bus Specification and User Manual, Rev. 03—19 June 2007, available from NXP Semiconductors. It supports standard (100 kHz) and fast (400 kHz) data transfer modes if the bus parameters given in Table 11 and Table 12 are met. Single- or multiple-byte reads/writes are supported, as shown in Figure 41. With the ALT ADDRESS pin high, the 7-bit I[2] C address for the device is 0x1D, followed by the R/W bit. This translates to 0x3A for a write and 0x3B for a read. An alternate I[2] C address of 0x53 (followed by the R/W bit) can be chosen by grounding the ALT ADDRESS pin (Pin 12). This translates to 0xA6 for a write and 0xA7 for a read. 

There are no internal pull-up or pull-down resistors for any unused pins; therefore, there is no known state or default state for the CS or ALT ADDRESS pin if left floating or unconnected. It is required that the CS pin be connected to VDD I/O and that the ALT ADDRESS pin be connected to either VDD I/O or GND when using I[2] C. 

Due to communication speed limitations, the maximum output data rate when using 400 kHz I[2] C is 800 Hz and scales linearly with a change in the I[2] C communication speed. For example, using I[2] C at 100 kHz would limit the maximum ODR to 200 Hz. Operation at an output data rate above the recommended maxi-mum may result in undesirable effect on the acceleration data, including missing samples or additional noise. 

**==> picture [159 x 99] intentionally omitted <==**

**----- Start of picture text -----**<br>
VDD I/O<br>ADXL345 RP RP PROCESSOR<br>CS<br>SDA D IN/OUT<br>ALT ADDRESS<br>SCL D OUT 07925-008<br>**----- End of picture text -----**<br>


Figure 40. I[2] C Connection Diagram (Address 0x53) 

If other devices are connected to the same I[2] C bus, the nominal operating voltage level of these other devices cannot exceed VDD I/O by more than 0.3 V. External pull-up resistors, RP, are necessary for proper I[2] C operation. Refer to the UM10204 I[2] C-Bus Specification and User Manual, Rev. 03—19 June 2007, when selecting pull-up resistor values to ensure proper operation. 

**Table 11. I[2] C Digital Input/Output** 

|**Parameter**|**Test Conditions**|**Limit1**<br>**Min**<br>**Max**|**Unit**|
|---|---|---|---|
|Digital Input<br>Low Level Input Voltage (VIL)<br>High Level Input Voltage (VIH)<br>Low Level Input Current (IIL)<br>High Level Input Current (IIH)<br>Digital Output<br>Low Level Output Voltage (VOL)<br>Low Level Output Current (IOL)<br>Pin Capacitance|VIN= VDD I/O<br>VIN= 0 V<br>VDD I/O< 2 V, IOL= 3 mA<br>VDD I/O≥ 2 V, IOL= 3 mA<br>VOL= VOL, max<br>fIN= 1 MHz, VIN= 2.5 V|0.3 × VDD I/O<br>0.7 × VDD I/O<br>0.1<br>−0.1<br>0.2 × VDD I/O<br>400<br>3<br>8|V<br>V<br>µA<br>µA<br>V<br>mV<br>mA<br>pF|



- 1 Limits based on characterization results; not production tested. 

**==> picture [482 x 134] intentionally omitted <==**

**----- Start of picture text -----**<br>
SINGLE-BYTE WRITE<br>MASTER START SLAVE ADDRESS + WRITE REGISTER ADDRESS DATA STOP<br>SLAVE ACK ACK ACK<br>MULTIPLE-BYTE WRITE<br>MASTER START SLAVE ADDRESS + WRITE REGISTER ADDRESS DATA DATA STOP<br>SLAVE ACK ACK ACK ACK<br>SINGLE-BYTE READ<br>MASTER START SLAVE ADDRESS + WRITE REGISTER ADDRESS START [1] SLAVE ADDRESS + READ NACK STOP<br>SLAVE ACK ACK ACK DATA<br>MULTIPLE-BYTE READ<br>MASTER START SLAVE ADDRESS + WRITE REGISTER ADDRESS START [1] SLAVE ADDRESS + READ ACK NACK STOP<br>SLAVE ACK ACK ACK DATA DATA<br>NOTES<br>1. THIS START IS EITHER A RESTART OR A STOP FOLLOWED BY A START.<br>2. THE SHADED AREAS REPRESENT WHEN THE DEVICE IS LISTENING. 07925-033<br>**----- End of picture text -----**<br>


Figure 41. I[2] C Device Addressing 

Rev. E | Page 18 of 40 

ADXL345 

## Data Sheet 

**Table 12. I[2] C Timing** (TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V) 

|**Table 12. I2C Timing **(|TA= 25°C, VS= 2.5 V, VDD I/O=|1.8 V)||
|---|---|---|---|
|**Parameter**|**Limit1, 2**<br>**Min**<br>**Max**|**Unit**|**Description**|
|fSCL<br>t1<br>t2<br>t3<br>t4<br>t5<br>t63, 4, 5, 6<br>t7<br>t8<br>t9<br>t10<br>t11<br>Cb|400<br>2.5<br>0.6<br>1.3<br>0.6<br>100<br>0<br>0.9<br>0.6<br>0.6<br>1.3<br>300<br>0<br>300<br>250<br>400|kHz<br>µs<br>µs<br>µs<br>µs<br>ns<br>µs<br>µs<br>µs<br>µs<br>ns<br>ns<br>ns<br>ns<br>pF|SCL clock frequency<br>SCL cycle time<br>tHIGH, SCL high time<br>tLOW, SCL low time<br>tHD, STA, start/repeated start condition hold time<br>tSU, DAT, data setup time<br>tHD, DAT, data hold time<br>tSU, STA, setup time for repeated start<br>tSU, STO, stop condition setup time<br>tBUF, bus-free time between a stop condition and a start condition<br>tR, rise time of both SCL and SDA when receiving<br>tR, rise time of both SCL and SDA when receiving or transmitting<br>tF, fall time of SDA when receiving<br>tF, fall time of both SCL and SDA when transmitting<br>Capacitive load for each bus line|



1 Limits based on characterization results, with fSCL = 400 kHz and a 3 mA sink current; not production tested. 

2 All values referred to the VIH and the VIL levels given in Table 11. 

3 t6 is the data hold time that is measured from the falling edge of SCL. It applies to data in transmission and acknowledge. 

4 A transmitting device must internally provide an output hold time of at least 300 ns for the SDA signal (with respect to VIH(min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. 

5 The maximum t6 value must be met only if the device does not stretch the low period (t3) of the SCL signal. 

6 The maximum value for t6 is a function of the clock low time (t3), the clock rise time (t10), and the minimum data setup time (t5(min)). This value is calculated as t6(max) = t3 − t10 − t5(min). 

**==> picture [503 x 107] intentionally omitted <==**

**----- Start of picture text -----**<br>
SDA<br>t9 t3 t10 t11 t4<br>SCL<br>t4 t6 t2 t5 t7 t1 t8<br>START REPEATED STOP<br>CONDITION START CONDITION<br>CONDITION 07925-034<br>**----- End of picture text -----**<br>


Figure 42. I[2] C Timing Diagram 

Rev. E | Page 19 of 40 

Data Sheet 

## ADXL345 

## **INTERRUPTS** 

The ADXL345 provides two output pins for driving interrupts: INT1 and INT2. Both interrupt pins are push-pull, low impedance pins with output specifications shown in Table 13. The default configuration of the interrupt pins is active high. This can be changed to active low by setting the INT_INVERT bit in the DATA_FORMAT (Address 0x31) register. All functions can be used simultaneously, with the only limiting feature being that some functions may need to share interrupt pins. 

Interrupts are enabled by setting the appropriate bit in the INT_ENABLE register (Address 0x2E) and are mapped to either the INT1 pin or the INT2 pin based on the contents of the INT_MAP register (Address 0x2F). When initially configuring the interrupt pins, it is recommended that the functions and interrupt mapping be done before enabling the interrupts. When changing the configuration of an interrupt, it is recommended that the interrupt be disabled first, by clearing the bit corresponding to that function in the INT_ENABLE register, and then the function be reconfigured before enabling the interrupt again. Configuration of the functions while the interrupts are disabled helps to prevent the accidental generation of an interrupt before desired. 

The interrupt functions are latched and cleared by either reading the data registers (Address 0x32 to Address 0x37) until the interrupt condition is no longer valid for the data-related interrupts or by reading the INT_SOURCE register (Address 0x30) for the remaining interrupts. This section describes the interrupts that can be set in the INT_ENABLE register and monitored in the INT_SOURCE register. 

## **DATA_READY** 

The DATA_READY bit is set when new data is available and is cleared when no new data is available. 

## **SINGLE_TAP** 

The SINGLE_TAP bit is set when a single acceleration event that is greater than the value in the THRESH_TAP register (Address 0x1D) occurs for less time than is specified in the DUR register (Address 0x21). 

## **DOUBLE_TAP** 

The DOUBLE_TAP bit is set when two acceleration events that are greater than the value in the THRESH_TAP register (Address 0x1D) occur for less time than is specified in the DUR register (Address 0x21), with the second tap starting after the time specified by the latent register (Address 0x22) but within the time specified in the window register (Address 0x23). See the Tap Detection section for more details. 

## **Activity** 

The activity bit is set when acceleration greater than the value stored in the THRESH_ACT register (Address 0x24) is experienced on any participating axis, set by the ACT_INACT_CTL register (Address 0x27). 

## **Inactivity** 

The inactivity bit is set when acceleration of less than the value stored in the THRESH_INACT register (Address 0x25) is experienced for more time than is specified in the TIME_INACT register (Address 0x26) on all participating axes, as set by the ACT_INACT_CTL register (Address 0x27). The maximum value for TIME_INACT is 255 sec. 

## **FREE_FALL** 

The FREE_FALL bit is set when acceleration of less than the value stored in the THRESH_FF register (Address 0x28) is experienced for more time than is specified in the TIME_FF register (Address 0x29) on all axes (logical AND). The FREE_FALL interrupt differs from the inactivity interrupt as follows: all axes always participate and are logically AND’ed, the timer period is much smaller (1.28 sec maximum), and the mode of operation is always dc-coupled. 

## **Watermark** 

The watermark bit is set when the number of samples in FIFO equals the value stored in the samples bits (Register FIFO_CTL, Address 0x38). The watermark bit is cleared automatically when FIFO is read, and the content returns to a value below the value stored in the samples bits. 

## **Table 13. Interrupt Pin Digital Output** 

|**Table 13. Interrupt Pin Digital Output**||||
|---|---|---|---|
|**Parameter**|**Test Conditions**|**Limit1**<br>**Min**<br>**Max**|**Unit**|
|Digital Output<br>Low Level Output Voltage (VOL)<br>High Level Output Voltage (VOH)<br>Low Level Output Current (IOL)<br>High Level Output Current (IOH)<br>Pin Capacitance<br>Rise/Fall Time<br>Rise Time (tR)2<br>Fall Time (tF)3|IOL= 300 µA<br>IOH= −150 µA<br>VOL= VOL, max<br>VOH= VOH, min<br>fIN= 1 MHz, VIN= 2.5 V<br>CLOAD= 150 pF<br>CLOAD= 150pF|0.2 × VDD I/O<br>0.8 × VDD I/O<br>300<br>−150<br>8<br>210<br>150|V<br>V<br>µA<br>µA<br>pF<br>ns<br>ns|



1 Limits based on characterization results, not production tested. 

2 Rise time is measured as the transition time from VOL, max to VOH, min of the interrupt pin. 

3 Fall time is measured as the transition time from VOH, min to VOL, max of the interrupt pin. 

Rev. E | Page 20 of 40 

Data Sheet 

ADXL345 

## **Overrun** 

The overrun bit is set when new data replaces unread data. The precise operation of the overrun function depends on the FIFO mode. In bypass mode, the overrun bit is set when new data replaces unread data in the DATAX, DATAY, and DATAZ registers (Address 0x32 to Address 0x37). In all other modes, the overrun bit is set when FIFO is filled. The overrun bit is automatically cleared when the contents of FIFO are read. 

## **FIFO** 

The ADXL345 contains technology for an embedded memory management system with 32-level FIFO that can be used to minimize host processor burden. This buffer has four modes: bypass, FIFO, stream, and trigger (see FIFO Modes). Each mode is selected by the settings of the FIFO_MODE bits (Bits[D7:D6]) in the FIFO_CTL register (Address 0x38). 

## **Bypass Mode** 

In bypass mode, FIFO is not operational and, therefore, remains empty. 

## **FIFO Mode** 

In FIFO mode, data from measurements of the x-, y-, and z-axes are stored in FIFO. When the number of samples in FIFO equals the level specified in the samples bits of the FIFO_CTL register (Address 0x38), the watermark interrupt is set. FIFO continues accumulating samples until it is full (32 samples from measurements of the x-, y-, and z-axes) and then stops collecting data. After FIFO stops collecting data, the device continues to operate; therefore, features such as tap detection can be used after FIFO is full. The watermark interrupt continues to occur until the number of samples in FIFO is less than the value stored in the samples bits of the FIFO_CTL register. 

## **Stream Mode** 

In stream mode, data from measurements of the x-, y-, and z- axes are stored in FIFO. When the number of samples in FIFO equals the level specified in the samples bits of the FIFO_CTL register (Address 0x38), the watermark interrupt is set. FIFO continues accumulating samples and holds the latest 32 samples from measurements of the x-, y-, and z-axes, discarding older data as new data arrives. The watermark interrupt continues occurring until the number of samples in FIFO is less than the value stored in the samples bits of the FIFO_CTL register. 

## **Trigger Mode** 

In trigger mode, FIFO accumulates samples, holding the latest 32 samples from measurements of the x-, y-, and z-axes. After a trigger event occurs and an interrupt is sent to the INT1 or INT2 pin (determined by the trigger bit in the FIFO_CTL register), FIFO keeps the last n samples (where n is the value specified by the samples bits in the FIFO_CTL register) and then operates in FIFO mode, collecting new samples only when FIFO is not full. A delay of at least 5 µs should be present between the trigger event occurring and the start of reading data from the FIFO to allow the FIFO to discard and retain the necessary samples. Additional trigger events cannot be recognized until the trigger mode is reset. To reset the trigger mode, set the device to bypass mode and then set the device back to trigger mode. Note that the FIFO data should be read first because placing the device into bypass mode clears FIFO. 

## **Retrieving Data from FIFO** 

The FIFO data is read through the DATAX, DATAY, and DATAZ registers (Address 0x32 to Address 0x37). When the FIFO is in FIFO, stream, or trigger mode, reads to the DATAX, DATAY, and DATAZ registers read data stored in the FIFO. Each time data is read from the FIFO, the oldest x-, y-, and z-axes data are placed into the DATAX, DATAY and DATAZ registers. 

If a single-byte read operation is performed, the remaining bytes of data for the current FIFO sample are lost. Therefore, all axes of interest should be read in a burst (or multiple-byte) read operation. To ensure that the FIFO has completely popped (that is, that new data has completely moved into the DATAX, DATAY, and DATAZ registers), there must be at least 5 µs between the end of reading the data registers and the start of a new read of the FIFO or a read of the FIFO_STATUS register (Address 0x39). The end of reading a data register is signified by the transition from Register 0x37 to Register 0x38 or by the CS pin going high. 

For SPI operation at 1.6 MHz or less, the register addressing portion of the transmission is a sufficient delay to ensure that the FIFO has completely popped. For SPI operation greater than 1.6 MHz, it is necessary to deassert the CS pin to ensure a total delay of 5 µs; otherwise, the delay is not sufficient. The total delay necessary for 5 MHz operation is at most 3.4 µs. This is not a concern when using I[2] C mode because the communication rate is low enough to ensure a sufficient delay between FIFO reads. 

Rev. E | Page 21 of 40 

Data Sheet 

## ADXL345 

## **SELF-TEST** 

The ADXL345 incorporates a self-test feature that effectively tests its mechanical and electronic systems simultaneously. When the self-test function is enabled (via the SELF_TEST bit in the DATA_FORMAT register, Address 0x31), an electrostatic force is exerted on the mechanical sensor. This electrostatic force moves the mechanical sensing element in the same manner as acceleration, and it is additive to the acceleration experienced by the device. This added electrostatic force results in an output change in the x-, y-, and z-axes. Because the electrostatic force is proportional to VS[2] , the output change varies with VS. This effect is shown in Figure 43. The scale factors shown in Table 14 can be used to adjust the expected self-test output limits for different supply voltages, VS. The self-test feature of the ADXL345 also exhibits a bimodal behavior. However, the limits shown in Table 1 and Table 15 to Table 18 are valid for both potential selftest values due to bimodality. Use of the self-test feature at data rates less than 100 Hz or at 1600 Hz may yield values outside these limits. Therefore, the part must be in normal power operation (LOW_POWER bit = 0 in BW_RATE register, Address 0x2C) and be placed into a data rate of 100 Hz through 800 Hz or 3200 Hz for the self-test function to operate correctly. 

**==> picture [208 x 173] intentionally omitted <==**

**----- Start of picture text -----**<br>
6<br>4<br>2<br>0<br>–2<br>X HIGH<br>X LOW<br>Y HIGH<br>–4<br>Y LOW<br>Z HIGH<br>Z LOW<br>–6<br>2.0 2.5 3.3 3.6<br>VS (V)<br>)SELF-TEST SHIFT LIMIT ( g<br>07925-242<br>**----- End of picture text -----**<br>


**Table 14. Self-Test Output Scale Factors for Different Supply Voltages, VS** 

|**Voltages, VS**|||
|---|---|---|
|**Supply Voltage, VS (V)**|**X-Axis, Y-Axis**|**Z-Axis**|
|2.00<br>2.50<br>3.30<br>3.60|0.64<br>1.00<br>1.77<br>2.11|0.8<br>1.00<br>1.47<br>1.69|



**Table 15. Self-Test Output in LSB for ±2 g, 10-Bit or Full Resolution (TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)** 

|**Resolution(T**|**A = 25C, VS = 2.**|**V, VDD I/O = 1.8**|**)**|
|---|---|---|---|
|**Axis**|**Min**|**Max**|**Unit**|
|X<br>Y<br>Z|50<br>−540<br>75|540<br>−50<br>875|LSB<br>LSB<br>LSB|



**Table 16. Self-Test Output in LSB for ±4 g, 10-Bit Resolution (TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)** 

|**(TA = 25°C, VS**|**= 2.5 V, VDD I/O =**|**1.8 V)**||
|---|---|---|---|
|**Axis**|**Min**|**Max**|**Unit**|
|X<br>Y<br>Z|25<br>−270<br>38|270<br>−25<br>438|LSB<br>LSB<br>LSB|



**Table 17. Self-Test Output in LSB for ±8 g, 10-Bit Resolution (TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)** 

|**(TA = 25C, VS**|**= 2.5 V, VDD I/O =**|**1.8 V)**||
|---|---|---|---|
|**Axis**|**Min**|**Max**|**Unit**|
|X<br>Y<br>Z|12<br>−135<br>19|135<br>−12<br>219|LSB<br>LSB<br>LSB|



**Table 18. Self-Test Output in LSB for ±16 g, 10-Bit Resolution (TA = 25°C, VS = 2.5 V, VDD I/O = 1.8 V)** 

|**(TA = 25°C, VS**|**= 2.5 V, VDD I/O =**|**1.8 V)**||
|---|---|---|---|
|**Axis**|**Min**|**Max**|**Unit**|
|X<br>Y<br>Z|6<br>−67<br>10|67<br>−6<br>110|LSB<br>LSB<br>LSB|



Figure 43. Self-Test Output Change Limits vs. Supply Voltage 

Rev. E | Page 22 of 40 

Data Sheet 

ADXL345 

## REGISTER MAP 

**Table 19.** 

|**Table 19.**|**Table 19.**|||||
|---|---|---|---|---|---|
|**Address**||**Name**|**Type **|**Reset Value**|**Description**|
|**Hex**|**Dec**|||||
|0x00<br>0x01 to 0x1C<br>0x1D<br>0x1E<br>0x1F<br>0x20<br>0x21<br>0x22<br>0x23<br>0x24<br>0x25<br>0x26<br>0x27<br>0x28<br>0x29<br>0x2A<br>0x2B<br>0x2C<br>0x2D<br>0x2E<br>0x2F<br>0x30<br>0x31<br>0x32<br>0x33<br>0x34<br>0x35<br>0x36<br>0x37<br>0x38<br>0x39|0<br>1 to 28<br>29<br>30<br>31<br>32<br>33<br>34<br>35<br>36<br>37<br>38<br>39<br>40<br>41<br>42<br>43<br>44<br>45<br>46<br>47<br>48<br>49<br>50<br>51<br>52<br>53<br>54<br>55<br>56<br>57|DEVID<br>Reserved<br>THRESH_TAP<br>OFSX<br>OFSY<br>OFSZ<br>DUR<br>Latent<br>Window<br>THRESH_ACT<br>THRESH_INACT<br>TIME_INACT<br>ACT_INACT_CTL<br>THRESH_FF<br>TIME_FF<br>TAP_AXES<br>ACT_TAP_STATUS<br>BW_RATE<br>POWER_CTL<br>INT_ENABLE<br>INT_MAP<br>INT_SOURCE<br>DATA_FORMAT<br>DATAX0<br>DATAX1<br>DATAY0<br>DATAY1<br>DATAZ0<br>DATAZ1<br>FIFO_CTL<br>FIFO_STATUS|R<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R<br>R/W<br>R/W<br>R/W<br>R/W<br>R<br>R/W<br>R<br>R<br>R<br>R<br>R<br>R<br>R/W<br>R|11100101<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000<br>00001010<br>00000000<br>00000000<br>00000000<br>00000010<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000<br>00000000|Device ID<br>Reserved; do not access<br>Tap threshold<br>X-axis offset<br>Y-axis offset<br>Z-axis offset<br>Tap duration<br>Tap latency<br>Tap window<br>Activity threshold<br>Inactivity threshold<br>Inactivity time<br>Axis enable control for activity and inactivity detection<br>Free-fall threshold<br>Free-fall time<br>Axis control for single tap/double tap<br>Source of single tap/double tap<br>Data rate and power mode control<br>Power-saving features control<br>Interrupt enable control<br>Interrupt mapping control<br>Source of interrupts<br>Data format control<br>X-Axis Data 0<br>X-Axis Data 1<br>Y-Axis Data 0<br>Y-Axis Data 1<br>Z-Axis Data 0<br>Z-Axis Data 1<br>FIFO control<br>FIFO status|



Rev. E | Page 23 of 40 

Data Sheet 

## ADXL345 

## **REGISTER DEFINITIONS** 

## **Register 0x00—DEVID (Read Only)** 

|**D7**|**D6**|**D5**|**D4**|**D3**|**D2**|**D1**|**D0**|
|---|---|---|---|---|---|---|---|
|1|1|1|0|0|1|0|1|



The DEVID register holds a fixed device ID code of 0xE5 (345 octal). 

## **Register 0x1D—THRESH_TAP (Read/Write)** 

The THRESH_TAP register is eight bits and holds the threshold value for tap interrupts. The data format is unsigned, therefore, the magnitude of the tap event is compared with the value in THRESH_TAP for normal tap detection. The scale factor is 62.5 mg/LSB (that is, 0xFF = 16 g). A value of 0 may result in undesirable behavior if single tap/double tap interrupts are enabled. 

## **Register 0x1E, Register 0x1F, Register 0x20—OFSX, OFSY, OFSZ (Read/Write)** 

The OFSX, OFSY, and OFSZ registers are each eight bits and offer user-set offset adjustments in twos complement format with a scale factor of 15.6 mg/LSB (that is, 0x7F = 2 g). The value stored in the offset registers is automatically added to the acceleration data, and the resulting value is stored in the output data registers. For additional information regarding offset calibration and the use of the offset registers, refer to the Offset Calibration section. 

## **Register 0x21—DUR (Read/Write)** 

The DUR register is eight bits and contains an unsigned time value representing the maximum time that an event must be above the THRESH_TAP threshold to qualify as a tap event. The scale factor is 625 µs/LSB. A value of 0 disables the single tap/ double tap functions. 

## **Register 0x22—Latent (Read/Write)** 

The latent register is eight bits and contains an unsigned time value representing the wait time from the detection of a tap event to the start of the time window (defined by the window register) during which a possible second tap event can be detected. The scale factor is 1.25 ms/LSB. A value of 0 disables the double tap function. 

## **Register 0x23—Window (Read/Write)** 

The window register is eight bits and contains an unsigned time value representing the amount of time after the expiration of the latency time (determined by the latent register) during which a second valid tap can begin. The scale factor is 1.25 ms/LSB. A value of 0 disables the double tap function. 

## **Register 0x24—THRESH_ACT (Read/Write)** 

## **Register 0x25—THRESH_INACT (Read/Write)** 

The THRESH_INACT register is eight bits and holds the threshold value for detecting inactivity. The data format is unsigned, so the magnitude of the inactivity event is compared with the value in the THRESH_INACT register. The scale factor is 62.5 mg/LSB. A value of 0 may result in undesirable behavior if the inactivity interrupt is enabled. 

## **Register 0x26—TIME_INACT (Read/Write)** 

The TIME_INACT register is eight bits and contains an unsigned time value representing the amount of time that acceleration must be less than the value in the THRESH_INACT register for inactivity to be declared. The scale factor is 1 sec/LSB. Unlike the other interrupt functions, which use unfiltered data (see the Threshold section), the inactivity function uses filtered output data. At least one output sample must be generated for the inactivity interrupt to be triggered. This results in the function appearing unresponsive if the TIME_INACT register is set to a value less than the time constant of the output data rate. A value of 0 results in an interrupt when the output data is less than the value in the THRESH_INACT register. 

## **Register 0x27—ACT_INACT_CTL (Read/Write)** 

|**D7**<br>ACT ac/dc|**D6**<br>ACT_X enable|**D5**<br>ACT_Y enable|**D4**<br>ACT_Z enable|
|---|---|---|---|
|**D3**<br>INACT ac/dc|**D2**<br>INACT_X enable|**D1**<br>INACT_Y enable|**D0**<br>INACT_Z enable|



## **ACT AC/DC and INACT AC/DC Bits** 

A setting of 0 selects dc-coupled operation, and a setting of 1 enables ac-coupled operation. In dc-coupled operation, the current acceleration magnitude is compared directly with THRESH_ACT and THRESH_INACT to determine whether activity or inactivity is detected. 

In ac-coupled operation for activity detection, the acceleration value at the start of activity detection is taken as a reference value. New samples of acceleration are then compared to this reference value, and if the magnitude of the difference exceeds the THRESH_ACT value, the device triggers an activity interrupt. 

Similarly, in ac-coupled operation for inactivity detection, a reference value is used for comparison and is updated whenever the device exceeds the inactivity threshold. After the reference value is selected, the device compares the magnitude of the difference between the reference value and the current acceleration with THRESH_INACT. If the difference is less than the value in THRESH_INACT for the time in TIME_INACT, the device is considered inactive and the inactivity interrupt is triggered. 

The THRESH_ACT register is eight bits and holds the threshold value for detecting activity. The data format is unsigned, so the magnitude of the activity event is compared with the value in the THRESH_ACT register. The scale factor is 62.5 mg/LSB. A value of 0 may result in undesirable behavior if the activity interrupt is enabled. 

Rev. E | Page 24 of 40 

Data Sheet 

ADXL345 

## **ACT_x Enable Bits and INACT_x Enable Bits** 

A setting of 1 enables x-, y-, or z-axis participation in detecting activity or inactivity. A setting of 0 excludes the selected axis from participation. If all axes are excluded, the function is disabled. For activity detection, all participating axes are logically OR’ed, causing the activity function to trigger when any of the participating axes exceeds the threshold. For inactivity detection, all participating axes are logically AND’ed, causing the inactivity function to trigger only if all participating axes are below the threshold for the specified time. 

## **Register 0x28—THRESH_FF (Read/Write)** 

The THRESH_FF register is eight bits and holds the threshold value, in unsigned format, for free-fall detection. The acceleration on all axes is compared with the value in THRESH_FF to determine if a free-fall event occurred. The scale factor is 62.5 mg/LSB. Note that a value of 0 mg may result in undesirable behavior if the freefall interrupt is enabled. Values between 300 mg and 600 mg (0x05 to 0x09) are recommended. 

## **Register 0x29—TIME_FF (Read/Write)** 

The TIME_FF register is eight bits and stores an unsigned time value representing the minimum time that the value of all axes must be less than THRESH_FF to generate a free-fall interrupt. The scale factor is 5 ms/LSB. A value of 0 may result in undesirable behavior if the free-fall interrupt is enabled. Values between 100 ms and 350 ms (0x14 to 0x46) are recommended. 

## **Register 0x2A—TAP_AXES (Read/Write)** 

|**D7**|**D6**|**D5**|**D4**|**D3**|**D2**|**D1**|**D0**|
|---|---|---|---|---|---|---|---|
|0|0|0|0|Suppress|TAP_X<br>enable|TAP_Y<br>enable|TAP_Z<br>enable|



## **Suppress Bit** 

Setting the suppress bit suppresses double tap detection if acceleration greater than the value in THRESH_TAP is present between taps. See the Tap Detection section for more details. 

## **TAP_x Enable Bits** 

A setting of 1 in the TAP_X enable, TAP_Y enable, or TAP_Z enable bit enables x-, y-, or z-axis participation in tap detection. A setting of 0 excludes the selected axis from participation in tap detection. 

## **Register 0x2B—ACT_TAP_STATUS (Read Only)** 

|**D7**|**D6**|**D5**|**D4**|**D3**|**D2**|**D1**|**D0**|
|---|---|---|---|---|---|---|---|
|0|ACT_X<br>source|ACT_Y<br>source|ACT_Z<br>source|Asleep|TAP_X<br>source|TAP_Y<br>source|TAP_Z<br>source|



## **ACT_x Source and TAP_x Source Bits** 

These bits indicate the first axis involved in a tap or activity event. A setting of 1 corresponds to involvement in the event, and a setting of 0 corresponds to no involvement. When new data is available, these bits are not cleared but are overwritten by the new data. The ACT_TAP_STATUS register should be read before clearing the interrupt. Disabling an axis from participation clears the corresponding source bit when the next activity or single tap/double tap event occurs. 

## **Asleep Bit** 

A setting of 1 in the asleep bit indicates that the part is asleep, and a setting of 0 indicates that the part is not asleep. This bit toggles only if the device is configured for auto sleep. See the AUTO_SLEEP Bit section for more information on autosleep mode. 

## **Register 0x2C—BW_RATE (Read/Write)** 

|**D7**|**D6**|**D5**|**D4**|**D3**|**D2**|**D1**|**D0**|
|---|---|---|---|---|---|---|---|
|0|0|0|LOW_POWER|Rate||||



## **LOW_POWER Bit** 

A setting of 0 in the LOW_POWER bit selects normal operation, and a setting of 1 selects reduced power operation, which has somewhat higher noise (see the Power Modes section for details). 

## **Rate Bits** 

These bits select the device bandwidth and output data rate (see Table 7 and Table 8 for details). The default value is 0x0A, which translates to a 100 Hz output data rate. An output data rate should be selected that is appropriate for the communication protocol and frequency selected. Selecting too high of an output data rate with a low communication speed results in samples being discarded. 

|**Register 0x2D—POWER_CTL(Read/Write)**|**Register 0x2D—POWER_CTL(Read/Write)**|**Register 0x2D—POWER_CTL(Read/Write)**|**Register 0x2D—POWER_CTL(Read/Write)**|**Register 0x2D—POWER_CTL(Read/Write)**|**Register 0x2D—POWER_CTL(Read/Write)**|||
|---|---|---|---|---|---|---|---|
|**D7**|**D6**|**D5**|**D4**|**D3**|**D2**|**D1**|**D0**|
|0|0|Link|AUTO_SLEEP|Measure|Sleep|Wakeup||



## **Link Bit** 

A setting of 1 in the link bit with both the activity and inactivity functions enabled delays the start of the activity function until inactivity is detected. After activity is detected, inactivity detection begins, preventing the detection of activity. This bit serially links the activity and inactivity functions. When this bit is set to 0, the inactivity and activity functions are concurrent. Additional information can be found in the Link Mode section. 

When clearing the link bit, it is recommended that the part be placed into standby mode and then set back to measurement mode with a subsequent write. This is done to ensure that the device is properly biased if sleep mode is manually disabled; otherwise, the first few samples of data after the link bit is cleared may have additional noise, especially if the device was asleep when the bit was cleared. 

## **AUTO_SLEEP Bit** 

If the link bit is set, a setting of 1 in the AUTO_SLEEP bit enables the auto-sleep functionality. In this mode, the ADXL345 automatically switches to sleep mode if the inactivity function is enabled and inactivity is detected (that is, when acceleration is below the THRESH_INACT value for at least the time indicated by TIME_INACT). If activity is also enabled, the ADXL345 automatically wakes up from sleep after detecting activity and returns to operation at the output data rate set in the BW_RATE register. A setting of 0 in the AUTO_SLEEP bit disables automatic switching to sleep mode. See the description of the Sleep Bit in this section for more information on sleep mode. 

Rev. E | Page 25 of 40 

ADXL345 

Data Sheet 

If the link bit is not set, the AUTO_SLEEP feature is disabled and setting the AUTO_SLEEP bit does not have an impact on device operation. Refer to the Link Bit section or the Link Mode section for more information on utilization of the link feature. 

When clearing the AUTO_SLEEP bit, it is recommended that the part be placed into standby mode and then set back to measurement mode with a subsequent write. This is done to ensure that the device is properly biased if sleep mode is manually disabled; otherwise, the first few samples of data after the AUTO_SLEEP bit is cleared may have additional noise, especially if the device was asleep when the bit was cleared. 

## **Measure Bit** 

A setting of 0 in the measure bit places the part into standby mode, and a setting of 1 places the part into measurement mode. The ADXL345 powers up in standby mode with minimum power consumption. 

## **Sleep Bit** 

A setting of 0 in the sleep bit puts the part into the normal mode of operation, and a setting of 1 places the part into sleep mode. Sleep mode suppresses DATA_READY, stops transmission of data to FIFO, and switches the sampling rate to one specified by the wakeup bits. In sleep mode, only the activity function can be used. When the DATA_READY interrupt is suppressed, the output data registers (Register 0x32 to Register 0x37) are still updated at the sampling rate set by the wakeup bits (D1:D0). 

When clearing the sleep bit, it is recommended that the part be placed into standby mode and then set back to measurement mode with a subsequent write. This is done to ensure that the device is properly biased if sleep mode is manually disabled; otherwise, the first few samples of data after the sleep bit is cleared may have additional noise, especially if the device was asleep when the bit was cleared. 

## **Wakeup Bits** 

These bits control the frequency of readings in sleep mode as described in Table 20. 

**Table 20. Frequency of Readings in Sleep Mode** 

|**Setting**|**Setting**|**Frequency (Hz)**|
|---|---|---|
|**D1**|**D0**||
|0<br>0<br>1<br>1|0<br>1<br>0<br>1|8<br>4<br>2<br>1|



## **Register 0x2E—INT_ENABLE (Read/Write)** 

|**D7**<br>DATA_READY|**D6**<br>SINGLE_TAP|**D5**<br>DOUBLE_TAP|**D4**<br>Activity|
|---|---|---|---|
|**D3**<br>Inactivity|**D2**<br>FREE_FALL|**D1**<br>Watermark|**D0**<br>Overrun|



Setting bits in this register to a value of 1 enables their respective functions to generate interrupts, whereas a value of 0 prevents the functions from generating interrupts. The DATA_READY, watermark, and overrun bits enable only the interrupt output; the functions are always enabled. It is recommended that interrupts be configured before enabling their outputs. 

## **Register 0x2F—INT_MAP (R/W)** 

|**D7**<br>DATA_READY|**D6**<br>SINGLE_TAP|**D5**<br>DOUBLE_TAP|**D4**<br>Activity|
|---|---|---|---|
|**D3**<br>Inactivity|**D2**<br>FREE_FALL|**D1**<br>Watermark|**D0**<br>Overrun|



Any bits set to 0 in this register send their respective interrupts to the INT1 pin, whereas bits set to 1 send their respective interrupts to the INT2 pin. All selected interrupts for a given pin are OR’ed. 

## **Register 0x30—INT_SOURCE (Read Only)** 

|**D7**<br>DATA_READY|**D6**<br>SINGLE_TAP|**D5**<br>DOUBLE_TAP|**D4**<br>Activity|
|---|---|---|---|
|**D3**<br>Inactivity|**D2**<br>FREE_FALL|**D1**<br>Watermark|**D0**<br>Overrun|



Bits set to 1 in this register indicate that their respective functions have triggered an event, whereas a value of 0 indicates that the corresponding event has not occurred. The DATA_READY, watermark, and overrun bits are always set if the corresponding events occur, regardless of the INT_ENABLE register settings, and are cleared by reading data from the DATAX, DATAY, and DATAZ registers. The DATA_READY and watermark bits may require multiple reads, as indicated in the FIFO mode descriptions in the FIFO section. Other bits, and the corresponding interrupts, are cleared by reading the INT_SOURCE register. 

|are cleared by reading the INT_SOURCE register.|are cleared by reading the INT_SOURCE register.|are cleared by reading the INT_SOURCE register.|are cleared by reading the INT_SOURCE register.|are cleared by reading the INT_SOURCE register.|are cleared by reading the INT_SOURCE register.|||
|---|---|---|---|---|---|---|---|
|**Register 0x31—DATA_FORMAT(Read/Write)**||||||||
|**D7**|**D6**|**D5**|**D4**|**D3**|**D2**|**D1**|**D0**|
|SELF_TEST|SPI|INT_INVERT|0|FULL_RES|Justify|Range||



The DATA_FORMAT register controls the presentation of data to Register 0x32 through Register 0x37. All data, except that for the ±16 g range, must be clipped to avoid rollover. 

## **SELF_TEST Bit** 

A setting of 1 in the SELF_TEST bit applies a self-test force to the sensor, causing a shift in the output data. A value of 0 disables the self-test force. 

## **SPI Bit** 

A value of 1 in the SPI bit sets the device to 3-wire SPI mode, and a value of 0 sets the device to 4-wire SPI mode. 

Rev. E | Page 26 of 40 

Data Sheet 

ADXL345 

## **INT_INVERT Bit** 

A value of 0 in the INT_INVERT bit sets the interrupts to active high, and a value of 1 sets the interrupts to active low. 

## **FULL_RES Bit** 

When this bit is set to a value of 1, the device is in full resolution mode, where the output resolution increases with the g range set by the range bits to maintain a 4 mg/LSB scale factor. When the FULL_RES bit is set to 0, the device is in 10-bit mode, and the range bits determine the maximum g range and scale factor. 

## **Justify Bit** 

A setting of 1 in the justify bit selects left-justified (MSB) mode, and a setting of 0 selects right-justified mode with sign extension. 

## **Range Bits** 

These bits set the g range as described in Table 21. 

**Table 21. g Range Setting** 

|**Table 21.g Range Se**|**Table 21.g Range Se**|**tting**|
|---|---|---|
|**Setting**||**g Range **|
|**D1**|**D0**||
|0<br>0<br>1<br>1|0<br>1<br>0<br>1|±2g<br>±4g<br>±8g<br>±16g|



## **Register 0x32 to Register 0x37—DATAX0, DATAX1, DATAY0, DATAY1, DATAZ0, DATAZ1 (Read Only)** 

These six bytes (Register 0x32 to Register 0x37) are eight bits each and hold the output data for each axis. Register 0x32 and Register 0x33 hold the output data for the x-axis, Register 0x34 and Register 0x35 hold the output data for the y-axis, and Register 0x36 and Register 0x37 hold the output data for the z-axis. The output data is twos complement, with DATAx0 as the least significant byte and DATAx1 as the most significant byte, where x represent X, Y, or Z. The DATA_FORMAT register (Address 0x31) controls the format of the data. It is recommended that a multiple-byte read of all registers be performed to prevent a change in data between reads of sequential registers. 

## **Register 0x38—FIFO_CTL (Read/Write)** 

|**D7**|**D6**|**D5**|**D4**|**D3**|**D2**|**D1**|**D0**|
|---|---|---|---|---|---|---|---|
|FIFO_MODE||Trigger|Samples|||||



## **FIFO_MODE Bits** 

These bits set the FIFO mode, as described in Table 22. 

## **Table 22. FIFO Modes** 

|**Setting**|**Setting**|**Mode**|**Function**|
|---|---|---|---|
|**D7**|**D6**|||
|0<br>0<br>1<br>1|0<br>1<br>0<br>1|Bypass<br>FIFO<br>Stream<br>Trigger|FIFO is bypassed.<br>FIFO collects up to 32 values and then<br>stops collecting data, collecting new data<br>only when FIFO is not full.<br>FIFO holds the last 32 data values. When<br>FIFO is full, the oldest data is overwritten<br>with newer data.<br>When triggered by the trigger bit, FIFO<br>holds the last data samples before the<br>trigger event and then continues to collect<br>data until full. New data is collected only<br>when FIFO is not full.|



## **Trigger Bit** 

A value of 0 in the trigger bit links the trigger event of trigger mode to INT1, and a value of 1 links the trigger event to INT2. 

## **Samples Bits** 

The function of these bits depends on the FIFO mode selected (see Table 23). Entering a value of 0 in the samples bits immediately sets the watermark status bit in the INT_SOURCE register, regardless of which FIFO mode is selected. Undesirable operation may occur if a value of 0 is used for the samples bits when trigger mode is used. 

**Table 23. Samples Bits Functions** 

|**FIFO Mode**|**Samples Bits Function**|
|---|---|
|Bypass<br>FIFO<br>Stream<br>Trigger|None.<br>Specifies how many FIFO entries are needed to<br>trigger a watermark interrupt.<br>Specifies how many FIFO entries are needed to<br>trigger a watermark interrupt.<br>Specifies how many FIFO samples are retained in<br>the FIFO buffer before a trigger event.|



|trigger a watermark interrupt.<br>Stream<br>Specifies how many FIFO entries are needed to<br>trigger a watermark interrupt.<br>Trigger<br>Specifies how many FIFO samples are retained in<br>the FIFO buffer before a trigger event.|trigger a watermark interrupt.<br>Stream<br>Specifies how many FIFO entries are needed to<br>trigger a watermark interrupt.<br>Trigger<br>Specifies how many FIFO samples are retained in<br>the FIFO buffer before a trigger event.|trigger a watermark interrupt.<br>Stream<br>Specifies how many FIFO entries are needed to<br>trigger a watermark interrupt.<br>Trigger<br>Specifies how many FIFO samples are retained in<br>the FIFO buffer before a trigger event.|trigger a watermark interrupt.<br>Stream<br>Specifies how many FIFO entries are needed to<br>trigger a watermark interrupt.<br>Trigger<br>Specifies how many FIFO samples are retained in<br>the FIFO buffer before a trigger event.|trigger a watermark interrupt.<br>Stream<br>Specifies how many FIFO entries are needed to<br>trigger a watermark interrupt.<br>Trigger<br>Specifies how many FIFO samples are retained in<br>the FIFO buffer before a trigger event.|trigger a watermark interrupt.<br>Stream<br>Specifies how many FIFO entries are needed to<br>trigger a watermark interrupt.<br>Trigger<br>Specifies how many FIFO samples are retained in<br>the FIFO buffer before a trigger event.|trigger a watermark interrupt.<br>Stream<br>Specifies how many FIFO entries are needed to<br>trigger a watermark interrupt.<br>Trigger<br>Specifies how many FIFO samples are retained in<br>the FIFO buffer before a trigger event.|trigger a watermark interrupt.<br>Stream<br>Specifies how many FIFO entries are needed to<br>trigger a watermark interrupt.<br>Trigger<br>Specifies how many FIFO samples are retained in<br>the FIFO buffer before a trigger event.|
|---|---|---|---|---|---|---|---|
|**��������0x39—FIFO_STATUS(Read Only)**||||||||
|**D7**|**D6**|**D5**|**D4**|**D3**|**D2**|**D1**|**D0**|
|FIFO_TRIG|0|Entries||||||



## **FIFO_TRIG Bit** 

A 1 in the FIFO_TRIG bit corresponds to a trigger event occurring, and a 0 means that a FIFO trigger event has not occurred. 

## **Entries Bits** 

These bits report how many data values are stored in FIFO. Access to collect the data from FIFO is provided through the DATAX, DATAY, and DATAZ registers. FIFO reads must be done in burst or multiple-byte mode because each FIFO level is cleared after any read (single- or multiple-byte) of FIFO. FIFO stores a maximum of 32 entries, which equates to a maximum of 33 entries available at any given time because an additional entry is available at the output filter of the device. 

Rev. E | Page 27 of 40 

Data Sheet 

## ADXL345 

## APPLICATIONS INFORMATION 

## **POWER SUPPLY DECOUPLING** 

A 1 µF tantalum capacitor (CS) at VS and a 0.1 µF ceramic capacitor (CI/O) at VDD I/O placed close to the ADXL345 supply pins is recommended to adequately decouple the accelerometer from noise on the power supply. If additional decoupling is necessary, a resistor or ferrite bead, no larger than 100 Ω, in series with VS may be helpful. Additionally, increasing the bypass capacitance on VS to a 10 µF tantalum capacitor in parallel with a 0.1 µF ceramic capacitor may also improve noise. 

Care should be taken to ensure that the connection from the ADXL345 ground to the power supply ground has low impedance because noise transmitted through ground has an effect similar to noise transmitted through VS. It is recommended that VS and VDD I/O be separate supplies to minimize digital clocking noise on the VS supply. If this is not possible, additional filtering of the supplies, as previously mentioned, may be necessary. 

**==> picture [222 x 109] intentionally omitted <==**

**----- Start of picture text -----**<br>
VS VDD I/O<br>CS CIO<br>VS VDD I/O<br>ADXL345<br>SDA/SDI/SDIO<br>INTERRUPT INT1 SDO/ALT ADDRESS 3- OR 4-WIRESPI OR I [2] C<br>CONTROL INT2 SCL/SCLK INTERFACE<br>GND CS 07925-016<br>**----- End of picture text -----**<br>


Figure 44. Application Diagram 

## **MECHANICAL CONSIDERATIONS FOR MOUNTING** 

The ADXL345 should be mounted on the PCB in a location close to a hard mounting point of the PCB to the case. Mounting the ADXL345 at an unsupported PCB location, as shown in Figure 45, may result in large, apparent measurement errors due to undampened PCB vibration. Locating the accelerometer near a hard mounting point ensures that any PCB vibration at the accelerometer is above the accelerometer’s mechanical sensor resonant frequency and, therefore, effectively invisible to the accelerometer. Multiple mounting points, close to the sensor, and/or a thicker PCB also help to reduce the effect of system resonance on the performance of the sensor. 

## **TAP DETECTION** 

The tap interrupt function is capable of detecting either single or double taps. The following parameters are shown in Figure 46 for a valid single and valid double tap event: 

- The tap detection threshold is defined by the THRESH_TAP register (Address 0x1D). 

- The maximum tap duration time is defined by the DUR register (Address 0x21). 

- The tap latency time is defined by the latent register (Address 0x22) and is the waiting period from the end of the first tap until the start of the time window, when a second tap can be detected, which is determined by the value in the window register (Address 0x23). 

- The interval after the latency time (set by the latent register) is defined by the window register. Although a second tap must begin after the latency time has expired, it need not finish before the end of the time defined by the window register. 

**==> picture [225 x 149] intentionally omitted <==**

**----- Start of picture text -----**<br>
FIRST TAP SECOND TAP<br>THRESHOLD<br>(THRESH_TAP)<br>TIME LIMIT FOR<br>TAPS (DUR)<br>LATENCY TIME WINDOW FOR<br>TIME SECOND TAP (WINDOW)<br>(LATENT)<br>SINGLE TAP DOUBLE TAP<br>INTERRUPT INTERRUPT<br>HI BW<br>X<br>INTERRUPTS 07925-037<br>**----- End of picture text -----**<br>


Figure 46. Tap Interrupt Function with Valid Single and Double Taps 

If only the single tap function is in use, the single tap interrupt is triggered when the acceleration goes below the threshold, as long as DUR has not been exceeded. If both single and double tap functions are in use, the single tap interrupt is triggered when the double tap event has been either validated or invalidated. 

**==> picture [180 x 64] intentionally omitted <==**

**----- Start of picture text -----**<br>
ACCELEROMETERS<br>PCB<br>MOUNTING POINTS 07925-036<br>**----- End of picture text -----**<br>


Figure 45. Incorrectly Placed Accelerometers 

Rev. E | Page 28 of 40 

ADXL345 

## Data Sheet 

Several events can occur to invalidate the second tap of a double tap event. First, if the suppress bit in the TAP_AXES register (Address 0x2A) is set, any acceleration spike above the threshold during the latency time (set by the latent register) invalidates the double tap detection, as shown in Figure 47. 

**==> picture [242 x 109] intentionally omitted <==**

**----- Start of picture text -----**<br>
INVALIDATES DOUBLE TAP IF<br>SUPRESS BIT SET<br>TIME LIMIT<br>FOR TAPS LATENCY TIME WINDOW FOR SECOND<br>(DUR) TIME (LATENT) TAP (WINDOW)<br>HI BW<br>X<br>07925-038<br>**----- End of picture text -----**<br>


Figure 47. Double Tap Event Invalid Due to High g Event When the Suppress Bit Is Set 

A double tap event can also be invalidated if acceleration above the threshold is detected at the start of the time window for the second tap (set by the window register). This results in an invalid double tap at the start of this window, as shown in Figure 48. Additionally, a double tap event can be invalidated if an acceleration exceeds the time limit for taps (set by the DUR register), resulting in an invalid double tap at the end of the DUR time limit for the second tap event, also shown in Figure 48. 

**==> picture [242 x 257] intentionally omitted <==**

**----- Start of picture text -----**<br>
INVALIDATES DOUBLE TAP<br>AT START OF WINDOW<br>TIME LIMIT<br>FOR TAPS<br>(DUR)<br>TIME LIMIT<br>FOR TAPS(DUR) LATENCYTIME SECOND TAP (WINDOW)TIME WINDOW FOR<br>(LATENT)<br>TIME LIMIT<br>FOR TAPS<br>(DUR)<br>INVALIDATES<br>DOUBLE TAP AT<br>END OF DUR<br>HI BW<br>X<br>HI BW<br>X<br>07925-039<br>**----- End of picture text -----**<br>


Figure 48. Tap Interrupt Function with Invalid Double Taps 

Single taps, double taps, or both can be detected by setting the respective bits in the INT_ENABLE register (Address 0x2E). Control over participation of each of the three axes in single tap/ double tap detection is exerted by setting the appropriate bits in the TAP_AXES register (Address 0x2A). For the double tap function to operate, both the latent and window registers must be set to a nonzero value. 

Every mechanical system has somewhat different single tap/ double tap responses based on the mechanical characteristics of the system. Therefore, some experimentation with values for the DUR, latent, window, and THRESH_TAP registers is required. In general, a good starting point is to set the DUR register to a value greater than 0x10 (10 ms), the latent register to a value greater than 0x10 (20 ms), the window register to a value greater than 0x40 (80 ms), and the THRESH_TAP register to a value greater than 0x30 (3 g). Setting a very low value in the latent, window, or THRESH_TAP register may result in an unpredictable response due to the accelerometer picking up echoes of the tap inputs. 

After a tap interrupt has been received, the first axis to exceed the THRESH_TAP level is reported in the ACT_TAP_STATUS register (Address 0x2B). This register is never cleared but is overwritten with new data. 

## **THRESHOLD** 

The lower output data rates are achieved by decimating a common sampling frequency inside the device. The activity, free-fall, and single tap/double tap detection functions without improved tap enabled are performed using undecimated data. Because the bandwidth of the output data varies with the data rate and is lower than the bandwidth of the undecimated data, the high frequency and high g data that is used to determine activity, free-fall, and single tap/double tap events may not be present if the output of the accelerometer is examined. This may result in functions triggering when acceleration data does not appear to meet the conditions set by the user for the corresponding function. 

## **LINK MODE** 

The function of the link bit is to reduce the number of activity interrupts that the processor must service by setting the device to look for activity only after inactivity. For proper operation of this feature, the processor must still respond to the activity and inactivity interrupts by reading the INT_SOURCE register (Address 0x30) and, therefore, clearing the interrupts. If an activity interrupt is not cleared, the part cannot go into autosleep mode. The asleep bit in the ACT_TAP_STATUS register (Address 0x2B) indicates if the part is asleep. 

Rev. E | Page 29 of 40 

Data Sheet 

## ADXL345 

## **SLEEP MODE VS. LOW POWER MODE** 

In applications where a low data rate and low power consumption is desired (at the expense of noise performance), it is recommended that low power mode be used. The use of low power mode preserves the functionality of the DATA_READY interrupt and the FIFO for postprocessing of the acceleration data. Sleep mode, while offering a low data rate and power consumption, is not intended for data acquisition. 

However, when sleep mode is used in conjunction with the AUTO_SLEEP mode and the link mode, the part can automatically switch to a low power, low sampling rate mode when inactivity is detected. To prevent the generation of redundant inactivity interrupts, the inactivity interrupt is automatically disabled and activity is enabled. When the ADXL345 is in sleep mode, the host processor can also be placed into sleep mode or low power mode to save significant system power. When activity is detected, the accelerometer automatically switches back to the original data rate of the application and provides an activity interrupt that can be used to wake up the host processor. Similar to when inactivity occurs, detection of activity events is disabled and inactivity is enabled. 

## **OFFSET CALIBRATION** 

Accelerometers are mechanical structures containing elements that are free to move. These moving parts can be very sensitive to mechanical stresses, much more so than solid-state electronics. The 0 g bias or offset is an important accelerometer metric because it defines the baseline for measuring acceleration. Additional stresses can be applied during assembly of a system containing an accelerometer. These stresses can come from, but are not limited to, component soldering, board stress during mounting, and application of any compounds on or over the component. If calibration is deemed necessary, it is recommended that calibration be performed after system assembly to compensate for these effects. 

A simple method of calibration is to measure the offset while assuming that the sensitivity of the ADXL345 is as specified in Table 1. The offset can then be automatically accounted for by using the built-in offset registers. This results in the data acquired from the DATA registers already compensating for any offset. 

In a no-turn or single-point calibration scheme, the part is oriented such that one axis, typically the z-axis, is in the 1 g field of gravity and the remaining axes, typically the x- and y-axis, are in a 0 g field. The output is then measured by taking the average of a series of samples. The number of samples averaged is a choice of the system designer, but a recommended starting point is 0.1 sec worth of data for data rates of 100 Hz or greater. This corresponds to 10 samples at the 100 Hz data rate. For data rates less than 100 Hz, it is recommended that at least 10 samples be averaged together. These values are stored as X0g, Y0g, and Z+1g for the 0 g measurements on the x- and y-axis and the 1 g measurement on the z-axis, respectively. 

The values measured for X0g and Y0g correspond to the x- and y-axis offset, and compensation is done by subtracting those values from the output of the accelerometer to obtain the actual acceleration: 

**==> picture [81 x 9] intentionally omitted <==**

**==> picture [79 x 9] intentionally omitted <==**

Because the z-axis measurement was done in a +1 g field, a no-turn or single-point calibration scheme assumes an ideal sensitivity, SZ for the z-axis. This is subtracted from Z+1g to attain the z-axis offset, which is then subtracted from future measured values to obtain the actual value: 

**==> picture [54 x 9] intentionally omitted <==**

**==> picture [78 x 10] intentionally omitted <==**

The ADXL345 can automatically compensate the output for offset by using the offset registers (Register 0x1E, Register 0x1F, and Register 0x20). These registers contain an 8-bit, twos complement value that is automatically added to all measured acceleration values, and the result is then placed into the DATA registers. Because the value placed in an offset register is additive, a negative value is placed into the register to eliminate a positive offset and vice versa for a negative offset. The register has a scale factor of 15.6 mg/LSB and is independent of the selected g-range. 

As an example, assume that the ADXL345 is placed into fullresolution mode with a sensitivity of typically 256 LSB/g. The part is oriented such that the z-axis is in the field of gravity and x-, y-, and z-axis outputs are measured as +10 LSB, −13 LSB, and +9 LSB, respectively. Using the previous equations, X0g is +10 LSB, Y0g is −13 LSB, and Z0g is +9 LSB. Each LSB of output in full-resolution is 3.9 mg or one-quarter of an LSB of the offset register. Because the offset register is additive, the 0 g values are negated and rounded to the nearest LSB of the offset register: 

**==> picture [128 x 9] intentionally omitted <==**

**==> picture [129 x 9] intentionally omitted <==**

**==> picture [124 x 9] intentionally omitted <==**

These values are programmed into the OFSX, OFSY, and OFXZ registers, respectively, as 0xFD, 0x03 and 0xFE. As with all registers in the ADXL345, the offset registers do not retain the value written into them when power is removed from the part. Power-cycling the ADXL345 returns the offset registers to their default value of 0x00. 

Because the no-turn or single-point calibration method assumes an ideal sensitivity in the z-axis, any error in the sensitivity results in offset error. For instance, if the actual sensitivity was 250 LSB/g in the previous example, the offset would be 15 LSB, not 9 LSB. To help minimize this error, an additional measurement point can be used with the z-axis in a 0 g field and the 0 g measurement can be used in the ZACTUAL equation. 

Rev. E | Page 30 of 40 

Data Sheet 

ADXL345 

## **USING SELF-TEST** 

The self-test change is defined as the difference between the acceleration output of an axis with self-test enabled and the acceleration output of the same axis with self-test disabled (see Endnote 4 of Table 1). This definition assumes that the sensor does not move between these two measurements, because if the sensor moves, a non–self-test related shift corrupts the test. 

Proper configuration of the ADXL345 is also necessary for an accurate self-test measurement. The part should be set with a data rate of 100 Hz through 800 Hz, or 3200 Hz. This is done by ensuring that a value of 0x0A through 0x0D, or 0x0F is written into the rate bits (Bit D3 through Bit D0) in the BW_RATE register (Address 0x2C). The part also must be placed into normal power operation by ensuring the LOW_POWER bit in the BW_RATE register is cleared (LOW_POWER bit = 0) for accurate self-test measurements. It is recommended that the part be set to full-resolution, 16 g mode to ensure that there is sufficient dynamic range for the entire self-test shift. This is done by setting Bit D3 of the DATA_FORMAT register (Address 0x31) and writing a value of 0x03 to the range bits (Bit D1 and Bit D0) of the DATA_FORMAT register (Address 0x31). This results in a high dynamic range for measurement and a 3.9 mg/LSB scale factor. 

After the part is configured for accurate self-test measurement, several samples of x-, y-, and z-axis acceleration data should be retrieved from the sensor and averaged together. The number of samples averaged is a choice of the system designer, but a recommended starting point is 0.1 sec worth of data for data rates of 100 Hz or greater. This corresponds to 10 samples at the 100 Hz data rate. For data rates less than 100 Hz, it is recommended that at least 10 samples be averaged together. The averaged values should be stored and labeled appropriately as the self-test disabled data, that is, XST_OFF, YST_OFF, and ZST_OFF. 

Next, self-test should be enabled by setting Bit D7 (SELF_TEST) of the DATA_FORMAT register (Address 0x31). The output needs some time (about four samples) to settle after enabling self-test. After allowing the output to settle, several samples of the x-, y-, and z-axis acceleration data should be taken again and averaged. It is recommended that the same number of samples be taken for this average as was previously taken. These averaged values should again be stored and labeled appropriately as the value with selftest enabled, that is, XST_ON, YST_ON, and ZST_ON. Self-test can then be disabled by clearing Bit D7 (SELF_TEST) of the DATA_FORMAT register (Address 0x31). 

With the stored values for self-test enabled and disabled, the self-test change is as follows: 

**==> picture [79 x 24] intentionally omitted <==**

**==> picture [78 x 8] intentionally omitted <==**

Because the measured output for each axis is expressed in LSBs, XST, YST, and ZST are also expressed in LSBs. These values can be converted to g’s of acceleration by multiplying each value by the 3.9 mg/LSB scale factor, if configured for full-resolution mode. Additionally, Table 15 through Table 18 correspond to the self-test range converted to LSBs and can be compared with the measured self-test change when operating at a VS of 2.5 V. For other voltages, the minimum and maximum self-test output values should be adjusted based on (multiplied by) the scale factors shown in Table 14. If the part was placed into ±2 g, 10-bit or full-resolution mode, the values listed in Table 15 should be used. Although the fixed 10-bit mode or a range other than 16 g can be used, a different set of values, as indicated in Table 16 through Table 18, would need to be used. Using a range below 8 g may result in insufficient dynamic range and should be considered when selecting the range of operation for measuring self-test. 

If the self-test change is within the valid range, the test is considered successful. Generally, a part is considered to pass if the minimum magnitude of change is achieved. However, a part that changes by more than the maximum magnitude is not necessarily a failure. 

Another effective method for using the self-test to verify accelerometer functionality is to toggle the self test at a certain rate and then perform an FFT on the output. The FFT should have a corresponding tone at the frequency the self-test was toggled. Using an FFT like this removes the dependency of the test on supply voltage and on self-test magnitude, which can vary within a rather wide range. 

Rev. E | Page 31 of 40 

ADXL345 

Data Sheet 

## **DATA FORMATTING OF UPPER DATA RATES** 

Formatting of output data at the 3200 Hz and 1600 Hz output data rates changes depending on the mode of operation (fullresolution or fixed 10-bit) and the selected output range. 

When using the 3200 Hz or 1600 Hz output data rates in fullresolution or ±2 g, 10-bit operation, the LSB of the output dataword is always 0. When data is right justified, this corresponds to Bit D0 of the DATAx0 register, as shown in Figure 49. When data is left justified and the part is operating in ±2 g, 10-bit mode, the LSB of the output data-word is Bit D6 of the DATAx0 register. In full-resolution operation when data is left justified, the location of the LSB changes according to the selected output range. 

For a range of ±2 g, the LSB is Bit D6 of the DATAx0 register; for ±4 g, Bit D5 of the DATAx0 register; for ±8 g, Bit D4 of the DATAx0 register; and for ±16 g, Bit D3 of the DATAx0 register. This is shown in Figure 50. 

The use of 3200 Hz and 1600 Hz output data rates for fixed 10bit operation in the ±4 g, ±8 g, and ±16 g output ranges provides an LSB that is valid and that changes according to the applied acceleration. Therefore, in these modes of operation, Bit D0 is not always 0 when output data is right justified and Bit D6 is not always 0 when output data is left justified. Operation at any data rate of 800 Hz or lower also provides a valid LSB in all ranges and modes that changes according to the applied acceleration. 

**==> picture [323 x 103] intentionally omitted <==**

**----- Start of picture text -----**<br>
DATAx1 REGISTER DATAx0 REGISTER<br>D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0<br>D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 0<br>OUTPUT DATA-WORD FOR<br>OUTPUT DATA-WORD FOR ALL<br>±16 g , FULL-RESOLUTION MODE. 10-BIT MODES AND THE ±2 g ,<br>FULL-RESOLUTION MODE.<br>THE ±4 g  AND ±8 g  FULL-RESOLUTION MODES HAVE THE SAME LSB LOCATION AS THE ±2 g<br>AND ±16 g  FULL-RESOLUTION MODES, BUT THE MSB LOCATION CHANGES TO BIT D2 AND<br>BIT D3 OF THE DATAX1 REGISTER FOR ±4 g  AND ±8 g,  RESPECTIVELY.<br>07925-145<br>**----- End of picture text -----**<br>


Figure 49. Data Formatting of Full-Resolution and ±2 g, 10-Bit Modes of Operation When Output Data Is Right Justified 

|**DATAx1 REGISTER**||||||||||**DATAx0 REGISTER**|**DATAx0 REGISTER**|**DATAx0 REGISTER**|**DATAx0 REGISTER**|**DATAx0 REGISTER**|**DATAx0 REGISTER**||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|**D4**<br>**D5**<br>**D6**<br>**D7**|**D7**<br>**D0**<br>**D1**<br>**D2**<br>**D3**|**D6**||**D5**||**D4**||**D3**|||**D2**||**D1**||**D0**||
||||||||||||||||||
|**D4**<br>**D5**<br>**D6**<br>**D7**|**D7**<br>**D0**<br>**D1**<br>**D2**<br>**D3**|**D6**||**D5**||**D4**||**D3**|||**D2**||**D1**||**0**||
||**LSB FOR ±2****_g_, FULL-RESOLUTION**||||||||||||||||
|**MSB FOR ALL MODES**|**AND ±2****_g_, 10-BIT MODES.**||||||||||||||||
|**OF OPERATION WHEN**<br>**LEFT JUSTIFIED.**|**LSB FOR ±4****_g_, FULL-RESOLUTION MODE.**||||||||||||||||
||**LSB FOR ±8****_g_, FULL-RESOLUTION MODE.**||||||||||||||||
||**LSB FOR ±16****_g_, FULL-RESOLUTION MODE.**||||||||||||||||
|**FOR 3200Hz AND 1600Hz OUTPUT DATA RATES, THE LSB IN THESE MODES IS ALWAYS 0.**<br>**ADDITIONALLY, ANY BITS TO THE RIGHT OF THE LSB ARE ALWAYS 0 WHEN THE OUTPUT**<br>**DATA IS LEFT JUSTIFIED.**||||||||||||||||07925-146|



Figure 50. Data Formatting of Full-Resolution and ±2 g, 10-Bit Modes of Operation When Output Data Is Left Justified 

Rev. E | Page 32 of 40 

Data Sheet 

ADXL345 

## **NOISE PERFORMANCE** 

The specification of noise shown in Table 1 corresponds to the typical noise performance of the ADXL345 in normal power operation with an output data rate of 100 Hz (LOW_POWER bit (D4) = 0, rate bits (D3:D0) = 0xA in the BW_RATE register, Address 0x2C). For normal power operation at data rates below 100 Hz, the noise of the ADXL345 is equivalent to the noise at 100 Hz ODR in LSBs. For data rates greater than 100 Hz, the noise increases roughly by a factor of √2 per doubling of the data rate. For example, at 400 Hz ODR, the noise on the x- and y-axes is typically less than 1.5 LSB rms, and the noise on the z-axis is typically less than 2.2 LSB rms. 

For low power operation (LOW_POWER bit (D4) = 1 in the BW_RATE register, Address 0x2C), the noise of the ADXL345 is constant for all valid data rates shown in Table 8. This value is typically less than 1.8 LSB rms for the x- and y-axes and typically less than 2.6LSB rms for the z-axis. 

The trend of noise performance for both normal power and low power modes of operation of the ADXL345 is shown in Figure 51. 

Figure 52 shows the typical Allan deviation for the ADXL345. The 1/f corner of the device, as shown in this figure, is very low, allowing absolute resolution of approximately 100 µg (assuming that there is sufficient integration time). Figure 52 also shows that the noise density is 290 µg/√Hz for the x-axis and y-axis and 430 µg/√Hz for the z-axis. 

Figure 53 shows the typical noise performance trend of the ADXL345 over supply voltage. The performance is normalized to the tested and specified supply voltage, VS = 2.5 V. In general, noise decreases as supply voltage is increased. It should be noted, as shown in Figure 51, that the noise on the z-axis is typically higher than on the x-axis and y-axis; therefore, while they change roughly the same in percentage over supply voltage, the magnitude of change on the z-axis is greater than the magnitude of change on the x-axis and y-axis. 

**==> picture [210 x 167] intentionally omitted <==**

**----- Start of picture text -----**<br>
5.0<br>4.5 X-AXIS, LOW POWER<br>Y-AXIS, LOW POWER<br>4.0 ZX-AXIS, NORMAL POWER-AXIS, LOW POWER<br>Y-AXIS, NORMAL POWER<br>3.5 Z-AXIS, NORMAL POWER<br>3.0<br>2.5<br>2.0<br>1.5<br>1.0<br>0.5<br>0<br>3.13 6.25 12.50 25 50 100 200 400 800 1600 3200<br>OUTPUT DATA RATE (Hz)<br>OUTPUT NOISE (LSB rms)<br>07925-250<br>**----- End of picture text -----**<br>


**==> picture [215 x 348] intentionally omitted <==**

**----- Start of picture text -----**<br>
10k<br>X-AXIS<br>Y-AXIS<br>Z-AXIS<br>1k<br>100<br>10<br>0.01 0.1 1 10 100 1k 10k<br>AVERAGING PERIOD,  (s)<br>Figure 52. Root Allan Deviation<br>130<br>120<br>X-AXIS<br>110 Y-AXIS<br>Z-AXIS<br>100<br>90<br>80<br>70<br>2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6<br>SUPPLY VOLTAGE, VS (V)<br>) g<br>ALLAN DEVIATION (µ<br>07925-251<br>PERCENTAGE OF NORMALIZED NOISE (%)<br>07925-252<br>**----- End of picture text -----**<br>


Figure 53. Normalized Noise vs. Supply Voltage, VS 

## **OPERATION AT VOLTAGES OTHER THAN 2.5 V** 

The ADXL345 is tested and specified at a supply voltage of VS = 2.5 V; however, it can be powered with VS as high as 3.6 V or as low as 2.0 V. Some performance parameters change as the supply voltage changes: offset, sensitivity, noise, self-test, and supply current. 

Due to slight changes in the electrostatic forces as supply voltage is varied, the offset and sensitivity change slightly. When operating at a supply voltage of VS = 3.3 V, the x- and y-axis offset is typically 25 mg higher than at Vs = 2.5 V operation. The z-axis is typically 20 mg lower when operating at a supply voltage of 3.3 V than when operating at VS = 2.5 V. Sensitivity on the x- and y-axes typically shifts from a nominal 256 LSB/g (full-resolution or ±2 g, 10-bit operation) at VS = 2.5 V operation to 265 LSB/g when operating with a supply voltage of 3.3 V. The z-axis sensitivity is unaffected by a change in supply voltage and is the same at VS = 3.3 V operation as it is at VS = 2.5 V operation. Simple linear interpolation can be used to determine typical shifts in offset and sensitivity at other supply voltages. 

Figure 51. Noise vs. Output Data Rate for Normal and Low Power Modes, Full-Resolution (256 LSB/g) 

Rev. E | Page 33 of 40 

Data Sheet 

## ADXL345 

Changes in noise performance, self-test response, and supply current are discussed elsewhere throughout the data sheet. For noise performance, the Noise Performance section should be reviewed. The Using Self-Test section discusses both the operation of self-test over voltage, a square relationship with supply voltage, as well as the conversion of the self-test response in g’s to LSBs. Finally, Figure 33 shows the impact of supply voltage on typical current consumption at a 100 Hz output data rate, with all other output data rates following the same trend. 

## **OFFSET PERFORMANCE AT LOWEST DATA RATES** 

The ADXL345 offers a large number of output data rates and bandwidths, designed for a large range of applications. However, at the lowest data rates, described as those data rates below 6.25 Hz, the offset performance over temperature can vary significantly from the remaining data rates. Figure 54, Figure 55, and Figure 56 show the typical offset performance of the ADXL345 over temperature for the data rates of 6.25 Hz and lower. All plots are normalized to the offset at 100 Hz output data rate; therefore, a nonzero value corresponds to additional offset shift due to temperature for that data rate. 

When using the lowest data rates, it is recommended that the operating temperature range of the device be limited to provide minimal offset shift across the operating temperature range. Due to variability between parts, it is also recommended that calibration over temperature be performed if any data rates below 6.25 Hz are in use. 

**==> picture [214 x 166] intentionally omitted <==**

**----- Start of picture text -----**<br>
140<br>120<br>100<br>80<br>0.10Hz<br>0.20Hz<br>60 0.39Hz<br>0.78Hz<br>1.56Hz<br>40 3.13Hz<br>6.25Hz<br>20<br>0<br>25 35 45 55 65 75 85<br>TEMPERATURE (°C)<br>NORMALIZED OUTPUT (LSB)<br>07925-056<br>**----- End of picture text -----**<br>


**==> picture [214 x 356] intentionally omitted <==**

**----- Start of picture text -----**<br>
140<br>120<br>100<br>80<br>0.10Hz<br>0.20Hz<br>60 0.39Hz<br>0.78Hz<br>1.56Hz<br>40 3.13Hz<br>6.25Hz<br>20<br>0<br>25 35 45 55 65 75 85<br>TEMPERATURE (°C)<br>Figure 55. Typical Y-Axis Output vs. Temperature at Lower Data Rates,<br>Normalized to 100 Hz Output Data Rate, VS = 2.5 V S = 2.5 V  = 2.5 V<br>140<br>120<br>100<br>80<br>60 0.10Hz<br>0.20Hz<br>0.39Hz<br>40 0.78Hz<br>1.56Hz<br>3.13Hz<br>20<br>6.25Hz<br>0<br>–20<br>25 35 45 55 65 75 85<br>TEMPERATURE (°C)<br>NORMALIZED OUTPUT (LSB)<br>07925-057<br>NORMALIZED OUTPUT (LSB)<br>07925-058<br>**----- End of picture text -----**<br>


Figure 55. Typical Y-Axis Output vs. Temperature at Lower Data Rates, Normalized to 100 Hz Output Data Rate, VS = 2.5 V S = 2.5 V  = 2.5 V 

Figure 56. Typical Z-Axis Output vs. Temperature at Lower Data Rates, Normalized to 100 Hz Output Data Rate, VS = 2.5 V 

Figure 54. Typical X-Axis Output vs. Temperature at Lower Data Rates, Normalized to 100 Hz Output Data Rate, VS = 2.5 V 

Rev. E | Page 34 of 40 

Data Sheet 

ADXL345 

## **AXES OF ACCELERATION SENSITIVITY** 

**==> picture [189 x 150] intentionally omitted <==**

**----- Start of picture text -----**<br>
AZ<br>AY<br>AX 07925-021<br>**----- End of picture text -----**<br>


Figure 57. Axes of Acceleration Sensitivity (Corresponding Output Voltage Increases When Accelerated Along the Sensitive Axis) 

**==> picture [380 x 187] intentionally omitted <==**

**----- Start of picture text -----**<br>
XOUT = 1 g<br>YOUT = 0 g<br>ZOUT = 0 g<br>TOP<br>GRAVITY<br>XOUT = 0 g XOUT = 0 g<br>YOUT = –1 g YOUT = 1 g<br>ZOUT = 0 g ZOUT = 0 g<br>XOUT = –1 g<br>YOUT = 0 g<br>ZOUT = 0 g XOUT = 0 g XOUT = 0 g<br>YOUT = 0 g YOUT = 0 g<br>ZOUT = 1 g ZOUT = –1 g<br>TOP TOP<br>07925-022<br>TOP<br>**----- End of picture text -----**<br>


Figure 58. Output Response vs. Orientation to Gravity 

Rev. E | Page 35 of 40 

ADXL345 

Data Sheet 

## **LAYOUT AND DESIGN RECOMMENDATIONS** 

Figure 59 shows the recommended printed wiring board land pattern. Figure 60and Table 24 provide details about the recommended soldering profile. 

**==> picture [178 x 202] intentionally omitted <==**

**----- Start of picture text -----**<br>
3.3400<br>1.0500<br>0.5500<br>0.2500<br>3.0500<br>5.3400<br>0.2500<br>1.1450 07925-014<br>**----- End of picture text -----**<br>


Figure 59. Recommended Printed Wiring Board Land Pattern (Dimensions shown in millimeters) 

**==> picture [245 x 131] intentionally omitted <==**

**----- Start of picture text -----**<br>
CRITICAL ZONE<br>TP tP TL TO TP<br>RAMP-UP<br>TL TSMAX tL<br>TSMIN<br>PREHEATtS RAMP-DOWN<br>t25°C TO PEAK<br>TIME<br>TEMPERATURE<br>07925-015<br>**----- End of picture text -----**<br>


Figure 60. Recommended Soldering Profile 

**Table 24. Recommended Soldering Profile[1, 2]** 

|**Profile Feature**|**Condition**|**Condition**|
|---|---|---|
||**Sn63/Pb37**|**Pb-Free**|
|Average Ramp Rate from Liquid Temperature (TL) to Peak Temperature (TP)<br>Preheat<br>Minimum Temperature (TSMIN)<br>Maximum Temperature (TSMAX)<br>Time from TSMINto TSMAX(tS)<br>TSMAXto TLRamp-Up Rate<br>Liquid Temperature (TL)<br>Time Maintained Above TL(tL)<br>Peak Temperature (TP)<br>Time of Actual TP− 5°C (tP)<br>Ramp-Down Rate<br>Time 25°C to Peak Temperature|3°C/sec maximum<br>100°C<br>150°C<br>60 sec to 120 sec<br>3°C/sec maximum<br>183°C<br>60 sec to 150 sec<br>240 + 0/−5°C<br>10 sec to 30 sec<br>6°C/sec maximum<br>6 minutes maximum|3°C/sec maximum<br>150°C<br>200°C<br>60 sec to 180 sec<br>3°C/sec maximum<br>217°C<br>60 sec to 150 sec<br>260 + 0/−5°C<br>20 sec to 40 sec<br>6°C/sec maximum<br>8 minutes maximum|



1 Based on JEDEC Standard J-STD-020D.1. 

2 For best results, the soldering profile should be in accordance with the recommendations of the manufacturer of the solder paste used. 

Rev. E | Page 36 of 40 

Data Sheet 

ADXL345 

## OUTLINE DIMENSIONS 

**==> picture [295 x 207] intentionally omitted <==**

**----- Start of picture text -----**<br>
3.00<br>CORNERPAD A1 BSC 0.49 BOTTOM VIEW 0.813 × 0.50<br>13 14 1<br>5.00 0.80<br>BSC BSC<br>0.50<br>8 6<br>7<br>TOP VIEW 1.01<br>0.49<br>0.79<br>1.00<br>0.95 END VIEW 0.74 1.50<br>0.85 0.69<br>SEATING<br>PLANE<br>Figure 61. 14-Terminal Land Grid Array [LGA]<br>(CC-14-1)<br>Solder Terminations Finish Is Au over Ni<br>Dimensions shown in millimeters<br>PKG-003340 03-16-2010-A<br>**----- End of picture text -----**<br>


## **ORDERING GUIDE** 

|**Model1**|**Measurement**<br>**Range (g) **|**Specified**<br>**Voltage (V)**|**Temperature Range **|**Package Description**|**Package**<br>**Option**|
|---|---|---|---|---|---|
|ADXL345BCCZ<br>ADXL345BCCZ-RL<br>ADXL345BCCZ-RL7<br>EVAL-ADXL345Z<br>EVAL-ADXL345Z-DB<br>EVAL-ADXL345Z-M<br>EVAL-ADXL345Z-S|±2, ±4, ±8, ±16<br>±2, ±4, ±8, ±16<br>±2, ±4, ±8, ±16|2.5<br>2.5<br>2.5|−40°C to +85°C<br>−40°C to +85°C<br>−40°C to +85°C|14-Terminal Land Grid Array [LGA]<br>14-Terminal Land Grid Array [LGA]<br>14-Terminal Land Grid Array [LGA]<br>Evaluation Board<br>Evaluation Board<br>Analog Devices Inertial Sensor Evaluation<br>System, Includes ADXL345 Satellite<br>ADXL345 Satellite, Standalone|CC-14-1<br>CC-14-1<br>CC-14-1|



1 Z = RoHS Compliant Part. 

Rev. E | Page 37 of 40 

ADXL345 

Data Sheet 

## NOTES 

Rev. E | Page 38 of 40 

Data Sheet 

ADXL345 

## NOTES 

Rev. E | Page 39 of 40 

ADXL345 

Data Sheet 

## NOTES 

I[2] C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). 

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**==> picture [315 x 38] intentionally omitted <==**

**©2009–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.** 

**D07925-0-6/15(E)** 

Rev. E | Page 40 of 40