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570BAB000544DG
Oscillator Programmable, 10MHz to 810MHz, 61.5ppm, 3.3V Supply Nom, LVDS Output, SMD 7mm x 5mm
⚠️ Reference pricing provided. In case of supply shortages, we will connect you with our trusted procurement partners to ensure your project's continuity.
- Manufacturer: SILICON LABS
- Product type: Standard Oscillators
- Programmable Frequency Min:10MHz; Programmable Frequency Max:810MHz; Frequency Stability + / -:61.5ppm; Oscillator Case:SMD, 7mm x 5mm; Supply Voltage Nom:3.3V; Product Range:Si57
- SVHC: To Be Advised
- Product Range: Si570
- Supply Voltage Nom: 3.3V
- Frequency Stability + / -: 61.5ppm
- Operating Temperature Max: 85°C
- Operating Temperature Min: -40°C
- Oscillator Case / Package: SMD, 7mm x 5mm
- Programmable Frequency Max: 810MHz
- Programmable Frequency Min: 10MHz
- Oscillator Output Compatibility: LVDS
| Delivery and price | |
|---|---|
| Units per pack | 1 |
| Price | 17.86 € |
| Current stock | 10+ |
| Lead time | 30 days |
Datasheet
**Si570/Si571**
## **10 MH Z TO 1.4 GH Z I[2] C P ROGRAMMABLE XO/VCXO**
## **Features**
- Internal fixed crystal frequency ensures high reliability and low aging
- Any programmable output frequencies from 10 to 945 MHz and select frequencies to 1.4 GHz
-
- Available LVPECL, CMOS, LVDS, and CML outputs
- Industry-standard 5x7 mm package
- I[2] C serial interface
- 3rd generation DSPLL[®] with superior jitter performance
- 3x better frequency stability than SAW-based oscillators
- Pb-free/RoHS-compliant
- 1.8, 2.5, or 3.3 V supply
## **Applications**
- SONET/SDH
- xDSL
- High performance instrumentation
-
- 10 GbE LAN/WAN
- Low-jitter clock generation
- Optical modules Clock and data recovery
- ATE
**Ordering Information:** See page 31. ~~a~~
**Pin Assignments:**
See page 30.
## **Description**
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**----- Start of picture text -----**<br>
(Top View)<br>The Si570 XO/Si571 VCXO utilizes Skyworks Solutions’ advanced DSPLL [[®]]<br>SDA<br>circuitry to provide a low-jitter clock at any frequency. The Si570/Si571 are user-<br>programmable to any output frequency from 10 to 945 MHz and select frequencies 7<br>to 1400 MHz with <1 ppb resolution. The device is programmed via an I [[2]] C serial NC 1 6 VDD<br>interface. Unlike traditional XO/VCXOs where a different crystal is required for<br>each output frequency, the Si57x uses one fixed-frequency crystal and a DSPLL<br>OE 2 5 CLK–<br>clock synthesis IC to provide any-frequency operation. This IC-based approach<br>allows the crystal resonator to provide exceptional frequency stability and<br>reliability. In addition, DSPLL clock synthesis provides superior supply noise GND 3 4 CLK+<br>rejection, simplifying the task of generating low-jitter clocks in noisy environments 8<br>typically found in communication systems.<br>SCL<br>Functional Block Diagramgramram<br>Si570<br>CLK- CLK+<br>VDD<br>SDA<br>7<br>OE E A VC 1 6 VDD<br>Fixed 10-1400 MHz<br>Frequency DSPLL [] Clock<br>SDA XO Synthesis<br>SCL OE 2 5 CLK–<br>Si571 only |<br>GND 3 4 CLK+<br>ADC 8<br>*<br>aC ] | &<br>SCL<br>GND Si571<br>VC<br>**----- End of picture text -----**<br>
The Si570 XO/Si571 VCXO utilizes Skyworks Solutions’ advanced DSPLL[[®]] circuitry to provide a low-jitter clock at any frequency. The Si570/Si571 are userprogrammable to any output frequency from 10 to 945 MHz and select frequencies to 1400 MHz with <1 ppb resolution. The device is programmed via an I[[2]] C serial interface. Unlike traditional XO/VCXOs where a different crystal is required for each output frequency, the Si57x uses one fixed-frequency crystal and a DSPLL clock synthesis IC to provide any-frequency operation. This IC-based approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low-jitter clocks in noisy environments typically found in communication systems.
**Functional Block Diagramgramram**
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.6 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • March 4, 2022
**Si570/Si571**
## **TABLE OF C ONTENTS**
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||||
|---|---|---|
|Section|Page|
|1. Detailed Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3|
|2. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4|
|3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14|
|3.1. Programming a New Output Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14|
|3.2. Si570 Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18|
|3.3. Si570 Troubleshooting FAQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20|
|3.4. I|[2]|C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21|
|4. Serial Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22|
|5. Si570 (XO) Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29|
|6. Si571 (VCXO) Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30|
|7. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31|
|8. Si57x Mark Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32|
|9. Outline Diagram and Suggested Pad Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33|
|10. 8-Pin PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34|
|Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35|
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Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.6 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • March 4, 2022
2
**Si570/Si571**
## **1. Detailed Block Diagrams**
**==> picture [432 x 254] intentionally omitted <==**
**----- Start of picture text -----**<br>
VDD GND<br>fXTAL<br>M CLKOUT+<br>+ DCO ÷HS_DIV ÷N1<br>fosc CLKOUT–<br>RFREQ<br>Frequency<br>Control<br>OE Control<br>SDA<br>Interface<br>SCL<br>NVM RAM<br>**----- End of picture text -----**<br>
**Figure 1. Si570 Detailed Block Diagram**
**==> picture [432 x 253] intentionally omitted <==**
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VDD GND<br>fXTAL<br>M CLKOUT+<br>VC ADC + DCO ÷HS_DIV ÷N1<br>VCADC fosc CLKOUT–<br>RFREQ<br>Frequency<br>Control<br>OE Control<br>SDA<br>Interface<br>SCL<br>NVM RAM<br>**----- End of picture text -----**<br>
**Figure 2. Si571 Detailed Block Diagram**
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.6 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • March 4, 2022
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**Si570/Si571**
## **2. Electrical Specifications**
**Table 1. Recommended Operating Conditions**
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Supply Voltage1|VDD|3.3 V option|2.97|3.3|3.63|V|
|||2.5 V option|2.25|2.5|2.75||
|||1.8 V option|1.71|1.8|1.89||
|Supply Current|IDD|Output enabled<br>LVPECL<br>CML<br>LVDS<br>CMOS|—<br>—<br>—<br>—|120<br>108<br>99<br>90|130<br>117<br>108<br>98|mA|
|||TriState mode|—|60|75||
|Output Enable (OE)2,<br>Serial Data (SDA),<br>Serial Clock (SCL)||VIH|0.75 x VDD|—|—|V|
|||VIL|—|—|0.5||
|Operating Temperature Range|TA||–40|—|85|ºC|
|**Notes:**<br>**1.** Selectable parameter specified by part number. See Section "7. Ordering Information" on page 31 for further details.<br>**2.**OE pin includes a 17 kpullup resistor to VDD. See “7.Ordering Information”.|||||||
## **Notes:**
**1.** Selectable parameter specified by part number. See Section "7. Ordering Information" on page 31 for further details.
**2.** OE pin includes a 17 k pullup resistor to VDD. See “7.Ordering Information”.
**Table 2. VC Control Voltage Input (Si571)**
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Control Voltage Tuning Slope1,2,3|KV|VC10 to 90% of VDD|—|33<br>45<br>90<br>135<br>180<br>356|—|ppm/V|
|Control Voltage Linearity4|LVC|BSL|–5|±1|+5|%|
|||Incremental|–10|±5|+10||
|Modulation Bandwidth|BW||9.3|10.0|10.7|kHz|
|VCInput Impedance|ZVC||500|—|—|k|
|Nominal Control Voltage5|VCNOM|@ fO|—|VDD/2|—|V|
|Control Voltage Tuning Range|VC||0||VDD|V|
|**Notes:**<br>**1.** Positive slope; selectable option by part number. See "7. Ordering Information" on page 31.<br>**2.**For best jitter and phase noise performance, always choose the smallest KVthat meets the application’s minimum APR<br>requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.<br>**3.**KVvariation is ±10% of typical values.<br>**4.**BSL determined from deviation from best straight line fit with VCranging from 10 to 90% of VDD. Incremental slope is<br>determined with VCranging from 10 to 90% of VDD.<br>**5.**Nominal output frequency set by VCNOM= 1/2 x VDD.|||||||
## **Notes:**
**1.** Positive slope; selectable option by part number. See "7. Ordering Information" on page 31.
**2.** For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR requirements. See “AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR)” for more information.
**3.** KV variation is ±10% of typical values.
**4.** BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope is determined with VC ranging from 10 to 90% of VDD.
**5.** Nominal output frequency set by VCNOM = 1/2 x VDD.
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**Si570/Si571**
**Table 3. CLK± Output Frequency Characteristics**
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Programmable Frequency<br>Range1,2|fO|LVPECL/LVDS/CML|10|—|1417.5|MHz|
|||CMOS|10|—|160||
|Temperature Stability1,3||TA= –40 to +85 ºC|–7<br>–20<br>–50<br>–100|—<br>—<br>—<br>—|7<br>+20<br>+50<br>+100|ppm|
|Initial Accuracy|||—|1.5|—|ppm|
|Aging|fa|Frequency drift over first year|—|—|±3|ppm|
|||Frequency drift over 20-year life|—|—|±10|ppm|
|Total Stability||Temp stability = ±7 ppm|—|—|±20|ppm|
|||Temp stability = ±20 ppm|—|—|±31.5|ppm|
|||Temp stability = ±50 ppm|—|—|±61.5|ppm|
|Absolute Pull Range1,3|APR||±12|—|±375|ppm|
|Power up Time4|tOSC||—|—|10|ms|
|**Notes:**<br>**1.** See Section "7. Ordering Information" on page 31 for further details.<br>**2.**Specified at time of order by part number. Three speed grades available:<br>Grade A covers 10 to 945 MHz, 970 to 1134 MHz, and 1213 to 1417.5 MHz.<br>Grade B covers 10 to 810 MHz.<br>Grade C covers 10 to 280 MHz.<br>**3.**Selectable parameter specified by part number.<br>**4.**Time from power up or tristate mode to fO.|||||||
## **Notes:**
**1.** See Section "7. Ordering Information" on page 31 for further details.
**2.** Specified at time of order by part number. Three speed grades available: Grade A covers 10 to 945 MHz, 970 to 1134 MHz, and 1213 to 1417.5 MHz. Grade B covers 10 to 810 MHz. Grade C covers 10 to 280 MHz.
**3.** Selectable parameter specified by part number.
**4.** Time from power up or tristate mode to fO.
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**Si570/Si571**
**Table 4. CLK± Output Levels and Symmetry**
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|LVPECL Output Option1|VO|mid-level|VDD– 1.42|—|VDD– 1.25|V|
||VOD|swing (diff)|1.1|—|1.9|VPP|
||VSE|swing (single-ended)|0.55|—|0.95|VPP|
|LVDS Output Option2|VO|mid-level|1.125|1.20|1.275|V|
||VOD|swing (diff)|0.5|0.7|0.9|VPP|
|CML Output Option2|VO|2.5/3.3 V option mid-level|—|VDD– 1.30|—|V|
|||1.8 V option mid-level|—|VDD– 0.36|—|V|
||VOD|2.5/3.3 V option swing (diff)|1.10|1.50|1.90|VPP|
|||1.8 V option swing (diff)|0.35|0.425|0.50|VPP|
|CMOS Output Option3|VOH|IOH= 32 mA|0.8 x VDD|—|VDD|V|
||VOL|IOL= 32 mA|—|—|0.4|V|
|Rise/Fall time (20/80%)|tR,tF|LVPECL/LVDS/CML|—|—|350|ps|
|||CMOS with CL= 15 pF|—|1|—|ns|
|Symmetry (duty cycle)|SYM|LVPECL:<br>VDD– 1.3 V (diff)<br>LVDS:<br>1.25 V (diff)<br>CMOS:<br>VDD/2|45|—|55|%|
|**Notes:**<br>**1.** Rterm= 50to VDD– 2.0 V.<br>**2.**Rterm= 100(differential).<br>**3.**CL= 15 pF|||||||
## **Notes:**
**1.** Rterm = 50 to VDD – 2.0 V. **2.** Rterm = 100 (differential). **3.** CL = 15 pF
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.6 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • March 4, 2022
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**Si570/Si571**
**Table 5. CLK± Output Phase Jitter (Si570)**
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Phase Jitter (RMS)1<br>for FOUT><br> 500 MHz|J|12 kHz to 20 MHz (OC-48)|—|0.25|0.40|ps|
|||50 kHz to 80 MHz (OC-192)|—|0.26|0.37||
|Phase Jitter (RMS)1<br>for FOUTof 125 to 500 MHz|J|12 kHz to 20 MHz (OC-48)|—|0.36|0.50|ps|
|||50 kHz to 80 MHz (OC-192)2|—|0.34|0.42||
|Phase Jitter (RMS)<br>for FOUTof 10 to 160 MHz<br>CMOS Output Only|J|12 kHz to 20 MHz (OC-48)2|—|0.62|—|ps|
|||50 kHz to 20 MHz2|—|0.61|—||
|**Notes:**<br>**1.** Refer to AN256 for further information.<br>**2.**Max offset frequencies:<br>80 MHz for FOUT><br> 250 MHz<br>20 MHz for 50 MHz<<br> FOUT <250 MHz<br>2 MHz for 10 MHz<<br>FOUT <50 MHz.|||||||
## **Notes:**
**1.** Refer to AN256 for further information.
**2.** Max offset frequencies: 80 MHz for FOUT > 250 MHz 20 MHz for 50 MHz < FOUT <250 MHz 2 MHz for 10 MHz < FOUT <50 MHz.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.6 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • March 4, 2022
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**Si570/Si571**
**Table 6. CLK± Output Phase Jitter (Si571)**
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Phase Jitter (RMS)1,2,3<br>for FOUT><br> 500 MHz|J|Kv = 33 ppm/V<br>12 kHz to 20 MHz (OC-48)<br>50 kHz to 80 MHz (OC-192)|—<br>—|0.26<br>0.26|—<br>—|ps|
|||Kv = 45 ppm/V<br>12 kHz to 20 MHz (OC-48)<br>50 kHz to 80 MHz (OC-192)|—<br>—|0.27<br>0.26|—<br>—||
|||Kv = 90 ppm/V<br>12 kHz to 20 MHz (OC-48)<br>50 kHz to 80 MHz (OC-192)|—<br>—|0.32<br>0.26|—<br>—||
|||Kv = 135 ppm/V<br>12 kHz to 20 MHz (OC-48)<br>50 kHz to 80 MHz (OC-192)|—<br>—|0.40<br>0.27|—<br>—||
|||Kv = 180 ppm/V<br>12 kHz to 20 MHz (OC-48)<br>50 kHz to 80 MHz (OC-192)|—<br>—|0.49<br>0.28|—<br>—||
|||Kv = 356 ppm/V<br>12 kHz to 20 MHz (OC-48)<br>50 kHz to 80 MHz (OC-192)|—<br>—|0.87<br>0.33|—<br>—||
|**Notes:**<br>**1.** Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.<br>**2.**For best jitter and phase noise performance, always choose the smallest KVthat meets the application’s minimum APR<br>requirements. See “AN266: VCXO Tuning Slope (kV), Stability, and Absolute Pull Range (APR)” for more information.<br>**3.**See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply<br>rejection (PSR) advantage of Si55x versus SAW-based solutions.<br>**4.**Single ended mode: CMOS. Refer to the following application notes for further information:<br>“AN255: Replacing 622 MHz VCSO Devices with the Si55x VCXO”<br>“AN256: Integrated Phase Noise”<br>“AN266: VCXO Tuning Slope (kV), Stability, and Absolute Pull Range (APR)”<br>**5.**Max offset frequencies:<br>80 MHz for FOUT ><br> 250 MHz<br>20 MHz for 50 MHz<<br> FOUT<250 MHz<br>2 MHz for 10 MHz<<br>FOUT<50 MHz.|||||||
## **Notes:**
**1.** Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.
**2.** For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR requirements. See “AN266: VCXO Tuning Slope (kV), Stability, and Absolute Pull Range (APR)” for more information.
**3.** See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply rejection (PSR) advantage of Si55x versus SAW-based solutions.
**4.** Single ended mode: CMOS. Refer to the following application notes for further information: “AN255: Replacing 622 MHz VCSO Devices with the Si55x VCXO” “AN256: Integrated Phase Noise” “AN266: VCXO Tuning Slope (kV), Stability, and Absolute Pull Range (APR)”
**5.** Max offset frequencies: 80 MHz for FOUT > 250 MHz 20 MHz for 50 MHz < FOUT <250 MHz 2 MHz for 10 MHz < FOUT <50 MHz.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.6 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • March 4, 2022
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**Si570/Si571**
**Table 6. CLK± Output Phase Jitter (Si571) (Continued)**
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Phase Jitter (RMS)2,4,5<br>for FOUT10 to 160 MHz<br>CMOS Output Only|J|Kv = 33 ppm/V<br>12 kHz to 20 MHz (OC-48)<br>50 kHz to 20 MHz|—<br>—|0.63<br>0.62|—<br>—|ps|
|||Kv = 45 ppm/V<br>12 kHz to 20 MHz (OC-48)<br>50 kHz to 20 MHz|—<br>—|0.63<br>0.62|—<br>—||
|||Kv = 90 ppm/V<br>12 kHz to 20 MHz (OC-48)<br>50 kHz to 20 MHz|—<br>—|0.67<br>0.66|—<br>—||
|||Kv = 135 ppm/V<br>12 kHz to 20 MHz (OC-48)<br>50 kHz to 20 MHz|—<br>—|0.74<br>0.72|—<br>—||
|||Kv = 180 ppm/V<br>12 kHz to 20 MHz (OC-48)<br>50 kHz to 20 MHz|—<br>—|0.83<br>0.8|—<br>—||
|||Kv = 356 ppm/V<br>12 kHz to 20 MHz (OC-48)<br>50 kHz to 20 MHz|—<br>—|1.26<br>1.2|—<br>—||
|**Notes:**|||||||
|**1.** Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.<br>**2.**For best jitter and phase noise performance, always choose the smallest KVthat meets the application’s minimum APR<br>requirements. See “AN266: VCXO Tuning Slope (kV), Stability, and Absolute Pull Range (APR)” for more information.<br>**3.**See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply<br>rejection (PSR) advantage of Si55x versus SAW-based solutions.<br>**4.**Single ended mode: CMOS. Refer to the following application notes for further information:<br>“AN255: Replacing 622 MHz VCSO Devices with the Si55x VCXO”<br>“AN256: Integrated Phase Noise”<br>“AN266: VCXO Tuning Slope (kV), Stability, and Absolute Pull Range (APR)”<br>**5.**Max offset frequencies:<br>80 MHz for FOUT ><br> 250 MHz<br>20 MHz for 50 MHz<<br> FOUT<250 MHz<br>2 MHz for 10 MHz<<br>FOUT<50 MHz.|||||||
**1.** Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.
**2.** For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR requirements. See “AN266: VCXO Tuning Slope (kV), Stability, and Absolute Pull Range (APR)” for more information.
**3.** See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply rejection (PSR) advantage of Si55x versus SAW-based solutions.
**4.** Single ended mode: CMOS. Refer to the following application notes for further information: “AN255: Replacing 622 MHz VCSO Devices with the Si55x VCXO” “AN256: Integrated Phase Noise” “AN266: VCXO Tuning Slope (kV), Stability, and Absolute Pull Range (APR)”
**5.** Max offset frequencies: 80 MHz for FOUT > 250 MHz 20 MHz for 50 MHz < FOUT <250 MHz 2 MHz for 10 MHz < FOUT <50 MHz.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.6 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • March 4, 2022
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**Si570/Si571**
**Table 6. CLK± Output Phase Jitter (Si571) (Continued)**
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Phase Jitter (RMS)1,2,3,5<br>for FOUTof 125 to<br>500 MHz|J|Kv = 33 ppm/V<br>12 kHz to 20 MHz (OC-48)<br>50 kHz to 80 MHz (OC-192)|—<br>—|0.37<br>0.33|—<br>—|ps|
|||Kv = 45 ppm/V<br>12 kHz to 20 MHz (OC-48)<br>50 kHz to 80 MHz (OC-192)|—<br>—|0.37<br>0.33|—<br>—||
|||Kv = 90 ppm/V<br>12 kHz to 20 MHz (OC-48)<br>50 kHz to 80 MHz (OC-192)|—<br>—|0.43<br>0.34|—<br>—||
|||Kv = 135 ppm/V<br>12 kHz to 20 MHz (OC-48)<br>50 kHz to 80 MHz (OC-192)|—<br>—|0.50<br>0.34|—<br>—||
|||Kv = 180 ppm/V<br>12 kHz to 20 MHz (OC-48)<br>50 kHz to 80 MHz (OC-192)|—<br>—|0.59<br>0.35|—<br>—||
|||Kv = 356 ppm/V<br>12 kHz to 20 MHz (OC-48)<br>50 kHz to 80 MHz (OC-192)|—<br>—|1.00<br>0.39|—<br>—||
|**Notes:**<br>**1.** Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.<br>**2.**For best jitter and phase noise performance, always choose the smallest KVthat meets the application’s minimum APR<br>requirements. See “AN266: VCXO Tuning Slope (kV), Stability, and Absolute Pull Range (APR)” for more information.<br>**3.**See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply<br>rejection (PSR) advantage of Si55x versus SAW-based solutions.<br>**4.**Single ended mode: CMOS. Refer to the following application notes for further information:<br>“AN255: Replacing 622 MHz VCSO Devices with the Si55x VCXO”<br>“AN256: Integrated Phase Noise”<br>“AN266: VCXO Tuning Slope (kV), Stability, and Absolute Pull Range (APR)”<br>**5.**Max offset frequencies:<br>80 MHz for FOUT ><br> 250 MHz<br>20 MHz for 50 MHz<<br> FOUT<250 MHz<br>2 MHz for 10 MHz<<br>FOUT<50 MHz.|||||||
## **Notes:**
**1.** Differential Modes: LVPECL/LVDS/CML. Refer to AN255, AN256, and AN266 for further information.
**2.** For best jitter and phase noise performance, always choose the smallest KV that meets the application’s minimum APR requirements. See “AN266: VCXO Tuning Slope (kV), Stability, and Absolute Pull Range (APR)” for more information.
**3.** See “AN255: Replacing 622 MHz VCSO devices with the Si550 VCXO” for comparison highlighting power supply rejection (PSR) advantage of Si55x versus SAW-based solutions.
**4.** Single ended mode: CMOS. Refer to the following application notes for further information: “AN255: Replacing 622 MHz VCSO Devices with the Si55x VCXO” “AN256: Integrated Phase Noise”
- “AN266: VCXO Tuning Slope (kV), Stability, and Absolute Pull Range (APR)”
**5.** Max offset frequencies: 80 MHz for FOUT > 250 MHz 20 MHz for 50 MHz < FOUT <250 MHz 2 MHz for 10 MHz < FOUT <50 MHz.
**Table 7. CLK± Output Period Jitter**
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Period Jitter*|JPER|RMS|—|2|—|ps|
|||Peak-to-Peak|—|14|—||
|***Note:**Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to “AN279: Estimating Period Jitter<br>from Phase Noise” for further information.|||||||
- ***Note:** Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to “AN279: Estimating Period Jitter from Phase Noise” for further information.
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**Table 8. Typical CLK± Output Phase Noise (Si570)**
|**Offset Frequency (f)**|**120.00 MHz**<br>**LVDS**|**156.25 MHz**<br>**LVPECL**|**622.08 MHz**<br>**LVPECL**|**Unit**|
|---|---|---|---|---|
|100 Hz<br>1 kHz<br>10 kHz<br>100 kHz<br>1 MHz<br>10 MHz<br>100 MHz|–112<br>–122<br>–132<br>–137<br>–144<br>–150<br>n/a|–105<br>–122<br>–128<br>–135<br>–144<br>–147<br>n/a|–97<br>–107<br>–116<br>–121<br>–134<br>–146<br>–148|dBc/Hz|
**Table 9. Typical CLK± Output Phase Noise (Si571)**
|**Offset Frequency (f)**|**74.25 MHz**<br>**90 ppm/V**<br>**LVPECL**|**491.52 MHz**<br>**45 ppm/V**<br>**LVPECL**|**622.08 MHz**<br>**135 ppm/V**<br>**LVPECL**|**Unit**|
|---|---|---|---|---|
|100 Hz<br>1 kHz<br>10 kHz<br>100 kHz<br>1 MHz<br>10 MHz<br>100 MHz|–87<br>–114<br>–132<br>–142<br>–148<br>–150<br>n/a|–75<br>–100<br>–116<br>–124<br>–135<br>–146<br>–147|–65<br>–90<br>–109<br>–121<br>–134<br>–146<br>–147|dBc/Hz|
## **Table 10. Environmental Compliance**
(The Si570/571 meets the following qualification test requirements.)
|**Table 10. Environmental Compliance**<br>(The Si570/571 meets the following qualification test requirements.)||
|---|---|
|**Parameter**|**Conditions/Test Method**|
|Mechanical Shock|MIL-STD-883, Method 2002|
|Mechanical Vibration|MIL-STD-883, Method 2007|
|Solderability|MIL-STD-883, Method 2003|
|Gross and Fine Leak|MIL-STD-883, Method 1014|
|Resistance to Solder Heat|MIL-STD-883, Method 2036|
|Moisture Sensitivity Level|J-STD-020, MSL1|
|Contact Pads|Gold over Nickel|
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## **Table 11. Programming Constraints and Timing** (VDD = 3.3 V ±10%, TA = –40 to 85 ºC)
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Output Frequency Range|CKOF|HS_DIV x N1 > = 6|10|—|945|MHz|
|||HS_DIV = 5<br>N1 = 1|970|—|1134|MHz|
|||HS_DIV = 4<br>N1 = 1|1.2125|—|1.4175|GHz|
|Frequency Reprogramming<br>Resolution|MRES|fxtal= 114.285 MHz|—|0.09|—|ppb|
|Internal Oscillator Frequency|fOSC||4850|—|5670|MHz|
|Internal Crystal Frequency<br>Accuracy|fXTAL|Maximum variation is<br>±2000 ppm|—|114.285|—|MHz|
|Delta Frequency for<br>Continuous Output||From center frequency|–3500|—|+3500|ppm|
|Unfreeze to NewFreq<br>Timeout|||—|—|10|ms|
|Settling Time for Small<br>Frequency Change||<±3500 ppm from<br>center frequency|—|—|100|µs|
|Settling Time for Large<br>Frequency Change||>±3500 ppm from<br>center frequency after<br>setting NewFreq bit|—|—|10|ms|
## **Table 12. Thermal Characteristics**
(Typical values TA = 25 ºC, VDD = 3.3 V)
|**Table 12. Thermal Characteristics**<br>(Typical values TA = 25 ºC, VDD= 3.3 V)|||||||
|---|---|---|---|---|---|---|
|**Parameter**|**Symbol**|**Test Condition**|**Min**|**Typ**|**Max**|**Unit**|
|Thermal Resistance Junction to Ambient|JA|Still Air|—|84.6|—|°C/W|
|Thermal Resistance Junction to Case|JC|Still Air|—|38.8|—|°C/W|
|Ambient Temperature|TA||–40|—|85|°C|
|Junction Temperature|TJ||—|—|125|°C|
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## **Table 13. Absolute Maximum Ratings[1,2]**
|**Table 13. Absolute Maximum Ratings1,2**||||
|---|---|---|---|
|**Parameter**|**Symbol**|**Rating**|**Unit**|
|Supply Voltage, 1.8 V Option|VDD|–0.5 to +1.9|V|
|Supply Voltage, 2.5/3.3 V Option|VDD|–0.5 to +3.8|V|
|Input Voltage|VI|–0.5 to VDD+ 0.3|V|
|Storage Temperature|TS|–55 to +125|ºC|
|ESD Sensitivity (HBM, per JESD22-A114)|ESD|>2000|V|
|Soldering Temperature (Lead-free Profile)|TPEAK|260|ºC|
|Soldering Temperature Time @ TPEAK(Lead-free Profile)|tP|20–40|seconds|
|**Notes:**<br>**1.** Stresses beyond the absolute maximum ratings may cause permanent damage to the device. Functional operation or<br>specification compliance is not implied at these conditions.<br>**2.**The device is compliant with JEDEC J-STD-020. Refer to packaging FAQ available at<br>https://www.skyworksinc.com/Product_Certificate.aspxfor further information, including soldering profiles.||||
## **Notes:**
**1.** Stresses beyond the absolute maximum ratings may cause permanent damage to the device. Functional operation or specification compliance is not implied at these conditions.
**2.** The device is compliant with JEDEC J-STD-020. Refer to packaging FAQ available at https://www.skyworksinc.com/Product_Certificate.aspx for further information, including soldering profiles.
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## **3. Functional Description**
The Si570 XO and the Si571 VCXO are low-jitter oscillators ideally suited for applications requiring programmable frequencies. The Si57x can be programmed to generate virtually any output clock in the range of 10 MHz to 1.4 GHz. Output jitter performance complies with and exceeds the strict requirements of high-speed communication systems including OC-192/STM-64 and 10 Gigabit Ethernet (10 GbE).
The Si57x consists of a digitally-controlled oscillator (DCO) based on Skyworks Solutions' third-generation DSPLL technology, which is driven by an internal fixedfrequency crystal reference.
The device's default output frequency is set at the factory and can be reprogrammed through the two-wire I[2] C serial port. Once the device is powered down, it will return to its factory-set default output frequency.
While the Si570 outputs a fixed frequency, the Si571 has a pullable output frequency using the voltage control input pin. This makes the Si571 an ideal choice for high-performance, low-jitter, phase-locked loops.
## **3.1. Programming a New Output Frequency**
The output frequency (fout) is determined by programming the DCO frequency (fDCO) and the device's output dividers (HS_DIV, N1). The output frequency is calculated using the following equation:
**==> picture [170 x 23] intentionally omitted <==**
The DCO frequency is adjustable in the range of 4.85 to 5.67 GHz by setting the high-resolution 38-bit fractional multiplier (RFREQ). The DCO frequency is the product of the internal fixed-frequency crystal (fXTAL) and RFREQ.
The 38-bit resolution of RFREQ allows the DCO frequency to have a programmable frequency resolution of 0.09 ppb.
As shown in Figure 3, the device allows reprogramming of the DCO frequency up to ±3500 ppm from the center frequency configuration without interruption to the output clock. Changes greater than the ±3500 ppm window will cause the device to recalibrate its internal tuning circuitry, forcing the output clock to momentarily stop and start at any arbitrary point during a clock cycle. This re-calibration process establishes a new center frequency and can take up to 10 ms. Circuitry receiving a clock from the Si57x device that is sensitive to glitches or runt pulses may have to be reset once the recalibration process is complete.
## **3.1.1. Reconfiguring the Output Clock for a Small Change in Frequency**
For output changes less than ±3500 ppm from the center frequency configuration, the DCO frequency is the only value that needs reprogramming. Since fDCO = fXTAL x RFREQ, and that fXTAL is fixed, changing the DCO frequency is as simple as reconfiguring the RFREQ value as outlined below:
1. Using the serial port, read the current RFREQ value (addresses 7–12 for all Si571 devices and Si570 devices with 20 ppm and 50 ppm temperature stability; or addresses 13–18 for Si570 devices with 7 ppm temperature stability).
2. Calculate the new value of RFREQ given the change in frequency.
**==> picture [170 x 26] intentionally omitted <==**
3. Using the serial port, write the new RFREQ value (addresses 7–12 for all Si571 devices and Si570 devices with 20 ppm and 50 ppm temperature stability; or addresses 13–18 for Si570 devices with 7 ppm temperature stability).
## Example:
An Si570 generating a 148.35 MHz clock must be reconfigured "on-the-fly" to generate a 148.5 MHz clock. This represents a change of +1011.122 ppm, which is well within the ±3500 ppm window.
**==> picture [470 x 100] intentionally omitted <==**
**----- Start of picture text -----**<br>
Center<br>Frequency<br>Configuration small frequency changes can be made<br>“on-the-fly” without interruption to the<br>output clock<br>4.85 GHz -3500 ppm +3500 ppm 5.67 GHz<br>**----- End of picture text -----**<br>
## **Figure 3. DCO Frequency Range**
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A typical frequency configuration for this example: RFREQcurrent = 0x2EBB04CE0
Fout_current = 148.35 MHz
Fout_new = 148.50 MHz
Calculate RFREQnew to change the output frequency from 148.35 MHz to 148.5 MHz:
**==> picture [181 x 19] intentionally omitted <==**
= 0x2EC71D666
- **Note:** Performing calculations with RFREQ requires a minimum of 38-bit arithmetic precision.
Even relatively small changes in output frequency may require writing more than 1 RFREQ register. Such multiregister RFREQ writes can impact the output clock frequency on a register-by-register basis during updating.
Interim changes to the output clock during RFREQ writes can be prevented by using the following procedure:
1. Freeze the “M” value (Set Register 135 bit 5 = 1).
2. Write the new frequency configuration (RFREQ).
3. Unfreeze the “M” value (Set Register 135 bit 5 = 0)
## **3.1.2. Reconfiguring the Output Clock for Large Changes in Output Frequency**
For output frequency changes outside of ±3500 ppm from the center frequency, it is likely that both the DCO frequency and the output dividers need to be reprogrammed. Note that changing the DCO frequency outside of the ±3500 ppm window will cause the output to momentarily stop and restart at any arbitrary point in a clock cycle. Devices sensitive to glitches or runt pulses may have to be reset once reconfiguration is complete.
The process for reconfiguring the output frequency outside of a ±3500 ppm window first requires reading the current RFREQ, HSDIV, and N1 values. Next, calculate fXTAL for the device. Note that, due to slight variations of the internal crystal frequency from one device to another, each device may have a different RFREQ value or possibly even different HSDIV or N1 values to maintain the same output frequency. It is necessary to calculate fXTAL for each device. Third, write the new values back to the device using the appropriate registers (addresses 7–12 for all Si571 devices and Si570 devices with 20 ppm and 50 ppm temperature stability; or addresses 13–18 for Si570 devices with 7 ppm temperature stability) sequencing as described in “3.1.2.1.Writing the New Frequency Configuration”.
**==> picture [114 x 21] intentionally omitted <==**
Once fXTAL has been determined, new values for RFREQ, HSDIV, and N1 are calculated to generate a new output frequency (fout_new). New values can be calculated manually or with the Si57x-EVB software, which provides a user-friendly application to help find the optimum values.
The first step in manually calculating the frequency configuration is to determine new frequency divider values (HSDIV, N1). Given the desired output frequency (fout_new), find the frequency divider values that will keep the DCO oscillation frequency in the range of 4.85 to 5.67 GHz.
**==> picture [168 x 11] intentionally omitted <==**
Valid values of HSDIV are 4, 5, 6, 7, 9 or 11. N1 can be selected as 1 or any even number up to 128 (i.e. 1, 2, 4, 6, 8, 10 … 128). To help minimize the device's power consumption, the divider values should be selected to keep the DCO's oscillation frequency as low as possible. The lowest value of N1 with the highest value of HS_DIV also results in the best power savings.
Once HS_DIV and N1 have been determined, the next step is to calculate the reference frequency multiplier (RFREQ).
**==> picture [98 x 23] intentionally omitted <==**
RFREQ is programmable as a 38-bit binary fractional frequency multiplier with the first 10 most significant bits (MSBs) representing the integer portion of the multiplier, and the 28 least significant bits (LSBs) representing the fractional portion.
Before entering a fractional number into the RFREQ register, it must be converted to a 38-bit integer using a bitwise left shift operation by 28 bits, which effectively multiplies RFREQ by 2[28] .
## Example:
## RFREQ = 46.043042064d
## Multiply RFREQ by 2[28] = 12359584992.1
## Discard the fractional portion = 12359584992
## Convert to hexadecimal = 02E0B04CE0h
In the example above, the multiplication operation requires 38-bit precision. If 38-bit arithmetic precision is not available, then the fractional portion can be separated from the integer and shifted to the left by 28bits. The result is concatenated with the integer portion to form a full 38-bit word. An example of this operation is shown in Figure 4.
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**==> picture [371 x 182] intentionally omitted <==**
**----- Start of picture text -----**<br>
46.043042064<br>Multiply the fractional portion by 2 [28]<br>.043042064 x 2 [28] = 11554016.077<br>Convert integer portion to a 10-bit binary number Truncate the remaining fractional portion<br>46 = 00 0010 1110b = 11554016<br>Convert to a 28-bit binary number (pad 0s on the left)<br>0000 1011 0000 0100 1100 1110 0000<br>Concatenate the two results<br>00 0010 1110 0000 1011 0000 0100 1100 1110 0000b<br>**----- End of picture text -----**<br>
**==> picture [134 x 33] intentionally omitted <==**
**----- Start of picture text -----**<br>
Convert to Hex<br>02E0B04CE0h<br>**----- End of picture text -----**<br>
## **Figure 4. Example of RFREQ Decimal to Hexadecimal Conversion**
## **3.1.2.1. Writing the New Frequency Configuration**
Once the new values for RFREQ, HSDIV, and N1 are determined, they can be written directly into the device from the serial port using the following procedure:
1. Freeze the DCO (bit 4 of Register 137)
2. Write the new frequency configuration (RFREQ, HSDIV, and N1) to addresses 7–12 for all Si571 devices and Si570 devices with 20 ppm and 50 ppm temperature stability; or addresses 13–18 for Si570 devices with 7 ppm temperature stability.
3. Unfreeze the DCO and assert the NewFreq bit (bit 6 of Register 135) within the maximum Unfreeze to NewFreq Timeout specified in Table 11, “Programming Constraints and Timing,” on page 12.
The process of freezing and unfreezing the DCO will cause the output clock to momentarily stop and start at any arbitrary point during a clock cycle. This process can take up to 10 ms. Circuitry that is sensitive to glitches or runt pulses may have to be reset after the new frequency configuration is written.
## Example:
An Si570 generating 156.25 MHz must be re-configured to generate a 161.1328125 MHz clock (156.25 MHz x 66/64). This frequency change is greater than ±3500 ppm.
fout = 156.25 MHz
Read the current values for RFREQ, HS_DIV, N1:
RFREQcurrent = 0x2BC011EB8h = 11744124600d, 11744124600d x 2[28] = 43.7502734363d
HS_DIV = 4
N1 = 8
Calculate fXTAL, fDCO_current
fDCO_current = fout HSDV N1 = 5.000000000 GHz
**==> picture [163 x 24] intentionally omitted <==**
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Given fout_new = 161.1328125 MHz, choose output dividers that will keep fDCO within the range of 4.85 to 5.67 GHz. In this case, keeping the same output dividers will still keep fDCO within its range limits:
**==> picture [205 x 27] intentionally omitted <==**
Calculate the new value of RFREQ given the new DCO frequency:
**==> picture [165 x 39] intentionally omitted <==**
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## **3.2. Si570 Programming Procedure**
This following example was generated using _Si514/70/71/98/99 Programmable Oscillator Software_ V4.0.1 found under the **Tools** tab at the following web page.
https://www.skyworksinc.com/en/application-pages/Programmable-Oscillator-Software
On that same web page, the _AN334 Si57x I2C XO/VCXO ANSI C Reference Design_ contains example **C** code for calculating register settings on the fly.
1. Read start-up frequency configuration (RFREQ, HS_DIV, and N1) from the device after power-up or register reset.
```
Registers for the Current Configuration
Register Data
7 0x01
8 0xC2
9 0xBC
10 0x01
11 0x1E
12 0xB8
RFREQ = 0x2BC011EB8
= 0x2BC011EB8 / (2^28) = 43.75027344
HS_DIV = 0x0 = 4
N1 = 0x7 = 8
```
2. Calculate the actual nominal crystal frequency where f0 is the start-up output frequency.
```
fxtal = ( f0 x HS_DIV x N1 ) / RFREQ
= (156.250000000 MHz x 4 x 8) / 43.750273436
= 114.285000000 MHz
```
3. Choose the new output frequency (f1).
```
Output Frequency (f1) = 161.132812000 MHz
```
4. Choose the output dividers for the new frequency configuration (HS_DIV and N1) by ensuring the DCO oscillation frequency (fdco) is between 4.85 GHz and 5.67 GHz where fdco = f1 x HS_DIV x N1. See the Divider Combinations tab for more options.
```
HS_DIV = 0x0 = 4
N1 = 0x7 = 8
fdco = f1 x HS_DIV x N1
= 161.132812000 MHz x 4 x 8
= 5.156249984 GHz
```
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5. Calculate the new crystal frequency multiplication ratio (RFREQ) as RFREQ = fdco / fxtal
```
RFREQ = fdco / fxtal
= 5.156249984 GHz / 114.285000000 MHz
= 45.11746934
= 45.11746934 x (2^28) = 0x2D1E12788
```
6. Freeze the DCO by setting Freeze DCO = 1 (bit 4 of register 137).
7. Write the new frequency configuration (RFREQ, HS_DIV, and N1)
```
Registers for the New Configuration
Register Data
7 0x01
8 0xC2
9 0xD1
10 0xE1
11 0x27
12 0x88
```
8. Unfreeze the DCO by setting Freeze DCO = 0 and assert the NewFreq bit (bit 6 of register 135) within 10 ms.
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## **3.3. Si570 Troubleshooting FAQ**
## **1. Is the I[2] C bus working correctly and using the correct I[2] C address?**
Probing the device I[2] C pins with an oscilloscope can sometimes reveal signal integrity problems. Si570/Si571 I[2] C communication is normally very robust, so if other devices on the I[2] C bus are communicating successfully, then the Si570/Si571 should also work.
You can confirm the specific I[2] C address expected by an Si570/Si571 device by using the part number lookup utility available on the Skyworks Solutions web site.
https://www.skyworksinc.com/en/Application-Pages/Timing-Lookup-Customize
## **2. Is the correct register bank being written based on device stability?**
Si570/Si571 devices use different configuration registers for 7 ppm temperature stability devices than they do for 20 ppm or 50 ppm temperature stability devices. The temperature stability of a Si570/Si571 device can be confirmed using the part number lookup utility available on the Skyworks Solutions web site or by referencing the 2nd ordering option code in the part number.
https://www.skyworksinc.com/en/Application-Pages/Timing-Lookup-Customize
## 2nd Ordering Option Code:
A : 50 ppm temperature stability, 61.5 ppm total stability => Configuration Registers 7-12 B : 20 ppm temperature stability, 31.5 ppm total stability => Configuration Registers 7-12
C : 7 ppm temperature stability, 20 ppm total stability => Configuration Registers 13-18
## **3. Is the part-to-part variation in FXTAL included in calculations?**
It is required that one determine the internal crystal frequency for each individual part before calculating a new output frequency. The procedure for determining the internal crystal frequency from the register values of a device is described elsewhere in this data sheet. See Section 3.2.
```
FXTAL = (FOUT x HSDIV x N1) / RFREQ <= note that RFREQ used here is the
register value divided by 2^28
```
It is a common error to calculate the internal crystal frequency for one device and then use that same crystal frequency for all later devices. This will lead to offset errors in the output frequency accuracy from part-to-part. The internal crystal frequency must be calculated for each individual device.
## **4. Is the Unfreeze to NewFreq timeout spec being exceeded?**
The Si570/Si571 requires the DCO to be 'frozen' when changing register values and then 'unfrozen' and a calibration initiated by writing the 'NewFreq' bit to restart it properly. If the 'unfreeze' and 'NewFreq' writes are delayed by 10 ms or more, the internal state machine can timeout and cause the configuration to revert to default values.
This 'unfreeze' and 'NewFreq' timing requirement is not usually a problem since the writes are done back-to-back, but if there is an interrupt or other system delay that may cause this 10 ms timing to be exceeded, it should be considered as a possible source of issues reprogramming the Si570/Si571.
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## **3.4. I[2] C Interface**
The control interface to the Si570 is an I[2] C-compatible 2-wire bus for bidirectional communication. The bus consists of a bidirectional serial data line (SDA) and a serial clock input (SCL). Both lines must be connected to the positive supply via an external pullup. Fast mode operation is supported for transfer rates up to 400 kbps as specified in the I[2] C-Bus Specification standard.
Figure 5 shows the command format for both read and write access. Data is always sent MSB. Data length is 1 byte. Read and write commands support 1 or more data bytes as illustrated. The master must send a Not Acknowledge and a Stop after the last read data byte to terminate the read command. The timing specifications and timing diagram for the I[2] C bus can be found in the I[2] C-Bus Specification standard (fast mode operation). The device I[2] C address is specified in the part number.
**==> picture [492 x 73] intentionally omitted <==**
**----- Start of picture text -----**<br>
S Slave Address 0 A Byte Address A Data A Data A P<br>Write Command<br>(Optional 2 [nd] data byte and acknowledge illustrated)<br>S Slave Address 0 A Byte Address A S Slave Address 1 A Data A Data N P<br>**----- End of picture text -----**<br>
Read Command
(Optional data byte and acknowledge before the last data byte and not acknowledge illustrated)
From master to slave From slave to master
- A – Acknowledge (SDA LOW)
- N – Not Acknowledge (SDA HIGH).
Required after the last data byte to signal the end of the read comand to the slave.
- S – START condition
- P – STOP condition
## **Figure 5. I[2] C Command Format**
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**Si570/Si571**
## **4. Serial Port Registers**
**Note:** Any register not listed here is reserved and must not be written. All bits are R/W unless otherwise noted.
|**Register**|**Name**|**Bit 7**|**Bit 6**|**Bit 5**|**Bit 4**|**Bit 3**|**Bit 2**|**Bit 1**|**Bit 0**|
|---|---|---|---|---|---|---|---|---|---|
|7|High Speed/<br>N1 Dividers|HS_DIV[2:0]|||N1[6:2]|||||
|8|Reference<br>Frequency|N1[1:0]||RFREQ[37:32]||||||
|9|Reference<br>Frequency|RFREQ[31:24]||||||||
|10|Reference<br>Frequency|RFREQ[23:16]||||||||
|11|Reference<br>Frequency|RFREQ[15:8]||||||||
|12|Reference<br>Frequency|RFREQ[7:0]||||||||
|13|High Speed/<br>N1 Dividers|HS_DIV_7PPM[2:0]|||N1_7PPM[6:2]|||||
|14|Reference<br>Frequency|N1_7PPM[1:0]||RFREQ_7PPM[37:32]||||||
|15|Reference<br>Frequency|RFREQ_7PPM[31:24]||||||||
|16|Reference<br>Frequency|RFREQ_7PPM[23:16]||||||||
|17|Reference<br>Frequency|RFREQ_7PPM[15:8]||||||||
|18|Reference<br>Frequency|RFREQ_7PPM[7:0]||||||||
|135|Reset/Freeze/M<br>emory Control|RST_REG|NewFreq|Freeze M|Freeze<br>VCADC||||RECALL|
|137|Freeze DCO||||Freeze<br>DCO|||||
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## **Register 7. High Speed/N1 Dividers**
|**Bit**|**Bit**|**D7**|**D6**|**D6**|**D5**|**D4**|**D3**|**D2**|**D1**|**D0**|
|---|---|---|---|---|---|---|---|---|---|---|
|**Name**||HS_DIV[2:0]||||N1[6:2]|||||
|**Type**||R/W<br>R/W|||||||||
||||||||||||
|**Bit**|**Name**|||**Function**|||||||
|7:5|HS_DIV[2:0]|||**DCO High Speed Divider.**<br>Sets value for high speed divider that takes the DCO output fOSCas its clock input.<br>000 = 4<br>001 = 5<br>010 = 6<br>011 = 7<br>100 = Not used.<br>101 = 9<br>110 = Not used.<br>111 = 11|||||||
|4:0|N1[6:2]|||**CLKOUT Output Divider.**<br>Sets value for CLKOUT output divider. Allowed values are [1] and [2, 4, 6, ..., 27]. Illegal<br>odd divider values will be rounded up to the nearest even value. The value for the N1 reg-<br>ister can be calculated by taking the divider ratio minus one. For example, to divide by 10,<br>write 0001001 (9 decimal) to the N1 registers.<br>0000000 = 1<br>1111111 = 27|||||||
**Register 8. Reference Frequency**
|**Bit**|**Bit**|**D7**|**D6**|**D6**|**D5**|**D4**|**D3**|**D2**|**D1**|**D0**|
|---|---|---|---|---|---|---|---|---|---|---|
|**Name**||N1[1:0]|||RFREQ[37:32]||||||
|**Type**||R/W<br>R/W|||||||||
||||||||||||
|**Bit**|**Name**|||**Function**|||||||
|7:6|N1[1:0]|||**CLKOUT Output Divider.**<br>Sets value for CLKOUT output divider. Allowed values are [1, 2, 4, 6, ..., 27]. Illegal odd<br>divider values will be rounded up to the nearest even value. The value for the N1 regis-<br>ter can be calculated by taking the divider ratio minus one. For example, to divide by<br>10, write 0001001 (9 decimal) to the N1 registers.<br>0000000 = 1<br>1111111 = 27|||||||
|5:0|RFREQ[37:32]|||**Reference Frequency.**<br>Frequency control input to DCO.|||||||
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## **Register 9. Reference Frequency**
|**Bit**|**Bit**|**D7**|**D6**|**D6**|**D5**|**D4**|**D3**|**D2**|**D1**|**D0**|
|---|---|---|---|---|---|---|---|---|---|---|
|**Name**||RFREQ[31:24]|||||||||
|**Type**||R/W|||||||||
||||||||||||
|**Bit**|**Name**|||**Function**|||||||
|7:0|RFREQ[31:24]|||**Reference Frequency.**<br>Frequency control input to DCO.|||||||
## **Register 10. Reference Frequency**
|**Bit**|**Bit**|**D7**|**D6**|**D6**|**D5**|**D4**|**D3**|**D2**|**D1**|**D0**|
|---|---|---|---|---|---|---|---|---|---|---|
|**Name**||RFREQ[23:16]|||||||||
|**Type**||R/W|||||||||
||||||||||||
|**Bit**|**Name**|||**Function**|||||||
|7:0|RFREQ[23:16]|||**Reference Frequency.**<br>Frequency control input to DCO.|||||||
## **Register 11. Reference Frequency**
|**Bit**|**Bit**|**D7**|**D6**|**D6**|**D5**|**D4**|**D3**|**D2**|**D1**|**D0**|
|---|---|---|---|---|---|---|---|---|---|---|
|**Name**||RFREQ[15:8]|||||||||
|**Type**||R/W|||||||||
||||||||||||
|**Bit**|**Name**|||**Function**|||||||
|7:0|RFREQ[15:8]|||**Reference Frequency.**<br>Frequency control input to DCO.|||||||
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**Register 12. Reference Frequency**
|**Bit**|**Bit**|**D7**|**D6**|**D6**|**D5**|**D4**|**D3**|**D2**|**D1**|**D0**|
|---|---|---|---|---|---|---|---|---|---|---|
|**Name**||RFREQ[7:0]|||||||||
|**Type**||R/W|||||||||
||||||||||||
|**Bit**|**Name**|||**Function**|||||||
|7:0|RFREQ[7:0]|||**Reference Frequency.**<br>Frequency control input to DCO.|||||||
## **Register 13. High Speed/N1 Dividers**
|**Bit**|**Bit**|**D7**|**D6**|**D6**|**D5**|**D4**|**D3**|**D2**|**D1**|**D0**|
|---|---|---|---|---|---|---|---|---|---|---|
|**Name**||HS_DIV_7PPM[2:0]||||N1_7PPM[6:2]|||||
|**Type**||R/W<br>R/W|||||||||
||||||||||||
|**Bit**|**Name**|||**Function**|||||||
|7:5|HS_DIV_7PPM[2:0]|||**DCO High Speed Divider.**<br>Sets value for high speed divider that takes the DCO output fOSCas its clock input.<br>000 = 4<br>001 = 5<br>010 = 6<br>011 = 7<br>100 = Not used.<br>101 = 9<br>110 = Not used.<br>111 = 11|||||||
|4:0|N1_7PPM[6:2]|||**CLKOUT Output Divider.**<br>Sets value for CLKOUT output divider. Allowed values are [1] and [2, 4, 6, ..., 27]. Ille-<br>gal odd divider values will be rounded up to the nearest even value. The value for the<br>N1 register can be calculated by taking the divider ratio minus one. For example, to<br>divide by 10, write 0001001 (9 decimal) to the N1 registers.<br>0000000 = 1<br>1111111 = 27|||||||
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## **Register 14. Reference Frequency**
|**Bit**|**Bit**|**D7**|**D6**|**D6**|**D5**|**D4**|**D3**|**D2**|**D1**|**D0**|
|---|---|---|---|---|---|---|---|---|---|---|
|**Name**||N1_7PPM[1:0]|||RFREQ_7PPM[37:32]||||||
|**Type**||R/W<br>R/W|||||||||
||||||||||||
|**Bit**|**Name**|||**Function**|||||||
|7:6|N1_7PPM[1:0]|||**CLKOUT Output Divider.**<br>Sets value for CLKOUT output divider. Allowed values are [1, 2, 4, 6, ..., 27]. Illegal<br>odd divider values will be rounded up to the nearest even value. The value for the<br>N1 register can be calculated by taking the divider ratio minus one. For example, to<br>divide by 10, write 0001001 (9 decimal) to the N1 registers.<br>0000000 = 1<br>1111111 = 27|||||||
|5:0|RFREQ_7PPM[37:32]|||**Reference Frequency.**<br>Frequency control input to DCO.|||||||
## **Register 15. Reference Frequency**
|**Bit**|**Bit**|**D7**|**D6**|**D6**|**D5**|**D4**|**D3**|**D2**|**D1**|**D0**|
|---|---|---|---|---|---|---|---|---|---|---|
|**Name**||RFREQ_7PPM[31:24]|||||||||
|**Type**||R/W|||||||||
||||||||||||
|**Bit**|**Name**|||**Function**|||||||
|7:0|RFREQ_7PPM[31:24]|||**Reference Frequency.**<br>Frequency control input to DCO.|||||||
## **Register 16. Reference Frequency**
|**Bit**|**Bit**|**D7**|**D6**|**D6**|**D5**|**D4**|**D3**|**D2**|**D1**|**D0**|
|---|---|---|---|---|---|---|---|---|---|---|
|**Name**||RFREQ_7PPM[23:16]|||||||||
|**Type**||R/W|||||||||
||||||||||||
|**Bit**|**Name**|||**Function**|||||||
|7:0|RFREQ_7PPM[23:16]|||**Reference Frequency.**<br>Frequency control input to DCO.|||||||
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**Si570/Si571**
## **Register 17. Reference Frequency**
|**Bit**|**Bit**|**D7**|**D6**|**D6**|**D5**|**D4**|**D3**|**D2**|**D1**|**D0**|
|---|---|---|---|---|---|---|---|---|---|---|
|**Name**||RFREQ_7PPM[15:8]|||||||||
|**Type**||R/W|||||||||
||||||||||||
|**Bit**|**Name**|||**Function**|||||||
|7:0|RFREQ_7PPM[15:8]|||**Reference Frequency.**<br>Frequency control input to DCO.|||||||
## **Register 18. Reference Frequency**
|**Bit**|**Bit**|**D7**|**D6**|**D6**|**D5**|**D4**|**D3**|**D2**|**D1**|**D0**|
|---|---|---|---|---|---|---|---|---|---|---|
|**Name**||RFREQ_7PPM[7:0]|||||||||
|**Type**||R/W|||||||||
||||||||||||
|**Bit**|**Name**|||**Function**|||||||
|7:0|RFREQ_7PPM[7:0]|||**Reference Frequency.**<br>Frequency control input to DCO.|||||||
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## **Register 135. Reset/Freeze/Memory Control**
|**Bit**|**D7**|**D6**|**D5**|**D4**|**D3**|**D2**|**D1**|**D0**|
|---|---|---|---|---|---|---|---|---|
|**Name**|RST_REG|NewFreq|Freeze M|Freeze VCADC|N/A|||RECALL|
|**Type**|R/W<br>R/W<br>R/W<br>R/W<br>R/W<br>R/W||||||||
Reset settings = 00xx xx00
|**Bit**|**Name**|**Function**|
|---|---|---|
|7|RST_REG|**Internal Reset.**<br>0 = Normal operation.<br>1 = Reset of all internal logic. Output tristated during reset.<br>Upon completion of internal logic reset, RST_REG is internally reset to zero.<br>**Note:** Asserting RST_REG will interrupt the I2C state machine. It is not the recommended<br>approach for starting from initial conditions.|
|6|NewFreq|**New Frequency Applied.**<br>Alerts the DSPLL that a new frequency configuration has been applied. This bit will<br>clear itself when the new frequency is applied.|
|5|Freeze M|**Freezes the M Control Word.**<br>Prevents interim frequency changes when writing RFREQ registers.|
|4|Freeze<br>VCADC|**Freezes the VC ADC Output Word.**<br>May be used to hold the nominal output frequency of an Si571.|
|3:1|N/A|Always Zero.|
|0|RECALL|**Recall NVM into RAM.**<br>0 = No operation.<br>1 = Write NVM bits into RAM. Bit is internally reset following completion of operation.<br>**Note:** Asserting RECALL reloads the NVM contents in to the operating registers without<br>interrupting the I2C state machine. It is the recommended approach for starting from<br>initial conditions.|
## **Register 137. Freeze DCO**
|**Bit**|**D7**|**D6**|**D5**|**D4**|**D3**|**D2**|**D1**|**D0**|
|---|---|---|---|---|---|---|---|---|
|**Name**||||Freeze<br>DCO|||||
|**Type**|R/W||||||||
Reset settings = 00xx xx00
|**Bit**|**Name**|**Function**|
|---|---|---|
|7:5|Reserved||
|4|Freeze DCO|**Freeze DCO.**<br>Freezes the DSPLL so the frequency configuration can be modified.|
|3:0|Reserved||
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## **5. Si570 (XO) Pin Descriptions**
**==> picture [48 x 11] intentionally omitted <==**
**----- Start of picture text -----**<br>
(Top View)<br>**----- End of picture text -----**<br>
**==> picture [131 x 135] intentionally omitted <==**
**----- Start of picture text -----**<br>
SDA<br>7<br>NC 1 6 VDD<br>OE 2 5 CLK–<br>GND 3 4 CLK+<br>8<br>SCL<br>**----- End of picture text -----**<br>
**Table 14. Si570 Pin Descriptions**
|**Pin**|**Name**|**Type**|**Function**|
|---|---|---|---|
|1|NC|N/A|No Connect. Make no external connection to this pin.|
|2|OE|Input|Output Enable:<br>See "7. Ordering Information" on page 31.|
|3|GND|Ground|Electrical and Case Ground.|
|4|CLK+|Output|Oscillator Output.|
|5|CLK–<br>(NC for CMOS*)|Output<br>(N/A for CMOS*)|Complementary Output.<br>(NC for CMOS*).|
|6|VDD|Power|Power Supply Voltage.|
|7|SDA|Bidirectional<br>Open Drain|I2C Serial Data.|
|8|SCL|Input|I2C Serial Clock.|
|***Note:**CMOS output option only: make no external connection to this pin.||||
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**Si570/Si571**
## **6. Si571 (VCXO) Pin Descriptions**
(Top View)
**==> picture [131 x 136] intentionally omitted <==**
**----- Start of picture text -----**<br>
SDA<br>7<br>VC 1 6 VDD<br>OE 2 5 CLK–<br>GND 3 4 CLK+<br>8<br>SCL<br>**----- End of picture text -----**<br>
**Table 15. Si571 Pin Descriptions**
|**Pin**|**Name**|**Type**|**Function**|
|---|---|---|---|
|1|VC|Analog Input|Control Voltage|
|2|OE|Input|Output Enable:<br>See "7. Ordering Information" on page 31.|
|3|GND|Ground|Electrical and Case Ground|
|4|CLK+|Output|Oscillator Output|
|5|CLK–<br>(NC for CMOS*)|Output<br>(N/A for CMOS*)|Complementary Output.<br>(NC for CMOS*).|
|6|VDD|Power|Power Supply Voltage|
|7|SDA|Bidirectional<br>Open Drain|I2C Serial Data|
|8|SCL|Input|I2C Serial Clock|
|***Note:**CMOS output option only: make no external connection to this pin.||||
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**Si570/Si571**
## **7. Ordering Information**
The Si570/Si571 supports a wide variety of options including frequency range, start-up frequency, temperature stability, tuning slope, output format, and VDD. Specific device configurations are programmed into the Si570/Si571 at time of shipment. Configurations are specified using the Part Number Configuration chart shown below. Skyworks Solutions provides a web browser-based part number configuration utility to simplify this process. Refer to https://www.skyworksinc.com/en/Products/Timing to access this tool and for further ordering instructions. The Si570/Si571 XO/VCXO series is supplied in an industry-standard, RoHS compliant, 8-pad, 5 x 7 mm package. Tape and reel packaging is an ordering option.
**==> picture [441 x 498] intentionally omitted <==**
**----- Start of picture text -----**<br>
57x X X X XXX XXX D G R<br>R = Tape and Reel<br>Blank = Coil Tape<br>Operating Temp Range (°C)<br>570 Programmable G –�to +85 °C<br>XO Product Family<br>571 Programmable Device Revision Letter<br>VCXO Product Family Six-Digit Start-up Frequency/I [2] C Address Designator<br>The Si57x supports a user-defined start-up frequency within the following bands<br>of frequencies: �–��MHz, � –�� MHz, and �� –�� MHz. The start-up<br>1st Option Code frequency must be in the same frequency range as that specified by the<br>Frequency Grade 3 [rd] option code.<br>The Si57x supports a user-defined I [2] C 7-bit address. Each unique start-up<br>V D D Output Format Output Enable Polarity frequency/I [2] C address combination is assigned a six-digit numerical code. This<br>A 3.3 LVPECL High code can be requested during the part number request process. Refer to https://<br>B 3.3 LVDS High www.skyworksinc.com/en/application-pages/timing-lookup-customizer to request<br>C 3.3 CMOS High an Si57x part number.<br>D 3.3 CML High<br>E 2.5 LVPECL High 3 [rd] Option Code<br>F 2.5 LVDS High Frequency Grade<br>G 2.5 CMOS High<br>H 2.5 CML High Code Frequency Range Supported (MHz)<br>J 1.8 CMOS High A 10-945, 970-1134, 1213-1417.5<br>K 1.8 CML High B 10-810<br>M 3.3 LVPECL Low C 10-280 (CMOS available to 160 MHz)<br>N 3.3 LVDS Low<br>P 3.3 CMOS Low<br>QR 2.53.3 LVPECLCML LowLow 2 [nd] Option Code<br>Code Temperature Stability (ppm, max, ±) Total Stablility (ppm, max, ±)<br>S 2.5 LVDS Low Si570 A 50 61.5<br>T 2.5 CMOS Low B 20 31.5<br>U 2.5 CML Low C 7 20<br>V 1.8 CMOS Low 2 [nd] Option Code<br>W 1.8 CML Low<br>Temperature Tuning Slope Minimum APR<br>Note: Stability Kv (±ppm) for VDD @<br>CMOS available to 160 MHz. Code ± ppm (max) ppm/V (typ) 3.3 V 2.5 V 1.8 V<br>A 100 180 100 75 25<br>B 100 90 30 Note 6 Note 6<br>C 50 180 150 125 75<br>D 50 90 80 30 25<br>E 20 45 25 Note 6 Note 6<br>F 50 135 100 75 50<br>G 20 356 375 300 235<br>H 20 180 185 145 105<br>J 20 135 130 104 70<br>K 100 356 295 220 155<br>Si571 M 20 33 12 Note 6 Note 6<br>Notes:<br>1. For best jitter and phase noise performance, always choose the smallest Kv that meets<br>the applications minimum APR requirements. Unlike SAW-based solutions which<br>require higher higher Kv values to account for their higher temperature dependence,<br>the Si55x series provides lower Kv options to minimize noise coupling and jitter in real-<br>world PLL designs. See AN255 and AN266 for more information.<br>2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an<br>APR of ±25 ppm is able to lock to a clock with a ±25 ppm stability over 15 years over all<br>operating conditions.<br>3. Nominal Pull range (±) = 0.5 x VDD x tuning slope.<br>4. Nominal Absolute Pull Range ( ± APR) = Pull range – stability – lifetime aging<br>= 0.5 x VDD x tuning slope – stability – �ppm<br>5. Minimum APR values noted above include worst case values for all parameters.<br>6. Combination not available.<br>**----- End of picture text -----**<br>
**Figure 6. Part Number Convention**
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**Si570/Si571**
## **8. Si57x Mark Specification**
Figure 7 illustrates the mark specification for the Si57x. Table 16 lists the line information.
## **Figure 7. Mark Specification Table 16. Si57x Top Mark Description**
|||**Table 16. Si57x Top Mark Description**|
|---|---|---|
|**Line**|**Position**|**Description**|
|1|1–10|Part Family Number, 57x (First 3 characters in part number where x = 0 indicates<br>a 570 device and x = 1 indicates a 571 device)|
|2|1–10|Si570, Si571: Option1 + Option2 + Option3 + ConfigNum(6) + Temp|
|3|**Trace Code**||
||Position 1|Pin 1 orientation mark (dot)|
||Position 2|Product Revision (D)|
||Position 3–6|Tiny Trace Code (4 alphanumeric characters per assembly release instructions)|
||Position 7|Year (least significant year digit), to be assigned by assembly site (ex: 2007 = 7)|
||Position 8–9|Calendar Work Week number (1–53), to be assigned by assembly site|
||Position 10|“+” to indicate Pb-Free and RoHS-compliant|
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**Si570/Si571**
## **9. Outline Diagram and Suggested Pad Layout**
Figure 8 illustrates the package details for the Si570/Si571. Table 17 lists the values for the dimensions shown in the illustration.
**Figure 8. Si570/Si571 Outline Diagram**
**Table 17. Package Diagram Dimensions (mm)**
|**ension**<br>**Min**|**Nom**|**Max**|
|---|---|---|
|A<br>1.50|1.65|1.80|
|b<br>1.30|1.40|1.50|
|b1<br>0.90|1.00|1.10|
|c<br>0.50|0.60|0.70|
|c1<br>0.30|—|0.60|
|D<br>5.00 BSC|||
|D1<br>4.30|4.40|4.50|
|e<br>2.54 BSC|||
|E<br>7.00 BSC|||
|E1<br>6.10|6.20|6.30|
|H<br>0.55|0.65|0.75|
|L<br>1.17|1.27|1.37|
|L1<br>1.07|1.17|1.27|
|p<br>1.80|—|2.60|
|R<br>0.70 REF|||
|aa<br>—|—|0.15|
|bb<br>—|—|0.15|
|ccc<br>—|—|0.10|
|dd<br>—|—|0.10|
|ee<br>—|—|0.05|
|l dimensions shown are in millimeters (mm) unless otherwise noted.<br>mensioning and Tolerancing per ANSI Y14.5M-1994.|||
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.6 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • March 4, 2022
33
**Si570/Si571**
## **10. 8-Pin PCB Land Pattern**
Figure 9 illustrates the 8-pin PCB land pattern for the Si570/Si571. Table 18 lists the values for the dimensions shown in the illustration.
**==> picture [154 x 147] intentionally omitted <==**
**Figure 9. Si570/Si571 PCB Land Pattern**
**Table 18. PCB Land Pattern Dimensions (mm)**
|**Dimension**|**Min**|**Max**|
|---|---|---|
|D2|5.08 REF||
|D3|5.705 REF||
|e|2.54 BSC||
|E2|4.20 REF||
|GD|0.84|—|
|GE|2.00|—|
|VD|8.20 REF||
|VE|7.30 REF||
|X1|1.70 TYP||
|X2|1.545 TYP||
|Y1|2.15 REF||
|Y2|1.3 REF||
|ZD|—|6.78|
|ZE|—|6.30|
|**Note:**<br>**1.** Dimensioning and tolerancing per the ANSI Y14.5M-1994<br>specification.<br>**2.**Land pattern design follows IPC-7351 guidelines.<br>**3.**All dimensions shown are at maximum material condition<br>(MMC).<br>**4.**Controlling dimension is in millimeters (mm).|||
**Note:**
**1.** Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification.
**2.** Land pattern design follows IPC-7351 guidelines.
**3.** All dimensions shown are at maximum material condition (MMC).
**4.** Controlling dimension is in millimeters (mm).
34 Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.6 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • March 4, 2022
**Si570/Si571**
## **REVISION HISTORY**
## **Revision 1.6**
June, 2018
- Changed “Trays” to “Coil Tape” in "7. Ordering Information" on page 31.
## **Revision 1.5**
- Added Section 3.2 and 3.3.
## **Revision 1.4**
- Added Table 12, “Thermal Characteristics,” on page 12.
## **Revision 1.3**
- Updated Table 3 on page 5 to include 7 ppm temperature stability and 20 ppm to stability parameters. Also changed aging test condition (frequency drift over life) from 15 years to 20 years.
- Updated 2.5 V/3.3 V and 1.8 V CML output level specification for Table 4 on page 6.
- Added footnotes clarifying max offset frequency test conditions in Table 5 on page 7.
- Updated ESD HBM sensitivity rating and the JEDEC standard in Note 2 in Table 13 on page 13.
- Updated Table 10 on page 11 to include "Moisture Sensitivity Level" and "Contact Pads" rows.
- Added Si570 7 ppm Total Stability Ordering Option to Figure 6 on page 31.
- Updated Figure 7 and Table 16 on page 32 to reflect specific marking information. Previously, Figure 7 was generic.
- Clarified "3.1.2. Reconfiguring the Output Clock for Large Changes in Output Frequency" on page 15 and added new registers 13-18 in "4. Serial Port Registers" on page 22 for the Si570 7 ppm temperature stability / 20 ppm total stability ordering option.
- Added text to "3. Functional Description" on page 14, paragraph 1, to state that the total output jitter complies to and exceeds strict requirements of various high-speed communication systems.
## **Revision 1.2**
- Replaced “Unfreeze to Newfreq Delay” with the clearer terminology “Unfreeze to Newfreq Timeout” on page 15 and in Table 11 on page 12.
- Added Freeze M procedure on page 14 for preventing output clock changes during small frequency change multi-register RFREQ writes.
- Added Freeze M, Freeze VCADC, and RST_REG versus RECALL information to Register 135 references in "4. Serial Port Registers" on pages 17 and 20.
- Added Si570 20 ppm Total Stability Ordering Option to Figure 6 on page 31.
- Updated Figure 8 and Table 17 on page 33 to include production test sidepads. This change is for reference only as the sidepads are raised above the seating plane and do not impact PCB layout.
- Corrected errors in Table 10 on page 11.
## **Revision 1.1**
- Restored programming constraint information on page 15 and in Table 12, page 12.
- Clarified NC (No Connect) pin designations in Tables 13–14 on pages 22–23.
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • sales@skyworksinc.com • www.skyworksinc.com Rev. 1.6 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • March 4, 2022
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## **Copyright © 2022 Skyworks Solutions, Inc. All Rights Reserved.**
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