545BAA250M000BAG

**Si545 Data Sheet** Ultra Low Jitter Any-Frequency XO (80 fs), 0.2 to 800 MHz The Si545 utilizes Silicon Laboratories’ advanced 4[th] generation DSPLL technology to provide an ultra-low jitter, low phase noise clock at any output frequency. The device is factory-programmed to any frequency from 0.2 to 800 MHz with <1 ppb resolution and maintains exceptionally low jitter for both integer and fractional frequencies across its operating range. The Si545 offers excellent reliability and frequency stability as well as guaranteed aging performance. On-chip power supply filtering provides industry-leading power supply noise rejection, simplifying the task of generating low jitter clocks in noisy systems that use switched-mode power supplies. Offered in a small, industry-standard 3.2×5 mm footprint, the Si545 has a dramatically simplified supply chain that enables Silicon Labs to ship custom frequency samples one week after receipt of order. Unlike a traditional XO, where a different crystal is required for each output frequency, the Si545 uses one simple crystal and a DSPLL IC-based approach to provide the desired output frequency. This process also guarantees 100% electrical testing of every device. The Si545 is factory-configurable for a wide variety of user specifications, including frequency, output format, and OE pin location/ polarity. Specific configurations are factory-programmed at time of shipment, eliminating the long lead times associated with custom oscillators. **Pin Assignments** OE/NC 1 6 VDD NC/OE 2 5 CLKGND 3 4 CLK+ ; 

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Pin Assignments<br>OE/NC 1 6 VDD<br>NC/OE 2 5 CLK-<br>GND 3 4 CLK+<br>(Top View)<br>**----- End of picture text -----**<br>


## **KEY FEATURES** 

- Available with any frequency from 0.2 MHz to 800 MHz 

- Ultra low jitter: 80 fs Typ ≥200 MHz RMS (12 kHz – 20 MHz) 

- Excellent PSRR and supply noise immunity: –80 dBc Typ 

- 3x tighter stability than SAW oscillators 

- 3.3 V, 2.5 V and 1.8 V VDD supply operation from the same part number 

- LVPECL, LVDS, CML, HCSL, CMOS, and Dual CMOS output options 

- 3.2×5 mm package footprint 

- Any custom frequency available with 1 week lead times 

## **APPLICATIONS** 

- 100G/400G OTN, coherent optics 

- 10G/40G/100G optical ethernet 

- 3G-SDI/12G-SDI/24G-SDI broadcast video 

- Datacenter 

- Test and measurement 

- Clock and data recovery 

- FPGA/ASIC clocking 

|**Pin #**|**Descriptions**|
|---|---|
|1, 2|_Selectable via ordering option_<br>OE = Output enable; NC = No connect|
|3|GND = Ground|
|4|CLK+ = Clock output|
|5|CLK- = Complementary clock output|
|6|VDD = Power supply|



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Preliminary Rev. 0.3 

Si545 Data Sheet Ordering Guide 

## **1.  Ordering Guide** 

The Si545 XO supports a variety of options including frequency, output format, and OE pin location/polarity, as shown in the chart below. Specific device configurations are programmed into the part at time of shipment, and samples are available in less than two weeks. Silicon Laboratories provides an online part number configuration utility to simplify this process. Refer to www.silabs.com/oscillators to access this tool and for further ordering instructions. 

|**XO Series**|**Description**|**Description**||||**Temp Stability**|**Temp Stability**|**Total Stability 2**||||**Package**|**Package**|||**Temperature Grade**|
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
|545|Single Frequency||||A|20 ppm||50 ppm|||B|3.2x5 mm|||G|-40 to 85 °C|
|-<br>-<br>-<br>-<br>-<br>-<br>B<br>A<br>G<br>-<br>A<br>A<br>A<br>545<br>R<br>**Device Revision**<br>Tape and Reel<br>**Reel**<br>R<br>Cut Tape<br><Blank><br>**OE Polarity**<br>**OE Pin**<br>Active High<br>Pin 1<br>A<br>Active Low<br>Pin 1<br>B<br>Active High<br>Pin 2<br>C<br>Active Low<br>Pin 2<br>D<br>**Frequency Code**<br>**Description**<br>Mxxxxxx<br>FCLK< 1 MHz<br>xMxxxxx<br>1 MHz ≤FCLK< 10 MHz<br>xxMxxxx<br>10 MHz ≤FCLK< 100 MHz<br>xxxMxxx<br>100 MHz ≤FCLK< 800 MHz<br>**Order**<br>**Option**<br>**VDD Range**<br>**Signal Format**<br>A<br>2.5, 3.3 V<br>LVPECL<br>B<br>1.8, 2.5, 3.3 V<br>LVDS<br>C<br>1.8, 2.5, 3.3 V<br>CMOS<br>D<br>1.8, 2.5, 3.3 V<br>CML<br>E<br>1.8, 2.5, 3.3 V<br>HCSL<br>F<br>1.8, 2.5, 3.3 V<br>Dual CMOS<br>(In-Phase)<br>G<br>1.8, 2.5, 3.3 V<br>Dual CMOS<br>(Complementary)<br>**3**|||||||||||||||||
|**Signal Format**||**VDD Range**||**Order**<br>**Option**|||||||||||||
|LVPECL||2.5, 3.3 V||A<br>|||||||||||||
|LVDS||1.8, 2.5, 3.3 V||B<br>|||||||||||||
|CMOS||1.8, 2.5, 3.3 V||C<br>|||||||||||||
|CML||1.8, 2.5, 3.3 V||D<br>|||||||||||||
|||||||||||**Frequency Code**<br>**3**|||**Description**||||
|HCSL||1.8, 2.5, 3.3 V||E<br>|||||||||||||
|||||||||||Mxxxxxx|||<br>FCLK< 1 MHz||||
|Dual CMOS<br>(In-Phase)||1.8, 2.5, 3.3 V||F<br>|||||||||||||
|||||||||||xMxxxxx|||<br>1 MHz ≤FCLK< 10 MHz||||
|Dual CMOS<br>(Complementary)||1.8, 2.5, 3.3 V||G<br>||||||xxMxxxx|||<br>10 MHz ≤FCLK< 100 MHz||||
|||||||||||xxxMxxx|||<br>100 MHz ≤FCLK< 800 MHz||||
|Custom1||1.8, 2.5, 3.3 V||X<br>||||||xxxxxx|||<br>Custom code if FCLK> 6 digits||||



## **Notes:** 

1. Contact Silicon Labs for non-standard configurations. 

2. Total stability includes temp stability, initial accuracy, load pulling, VDD variation, and 10 year aging at 70 °C. 

3. For example: 156.25 MHz = 156M250; 25 MHz = 25M0000. Get custom frequency codes at www.silabs.com/oscillators. 

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Preliminary Rev. 0.3  |  1 

Si545 Data Sheet Electrical Specifications 

## **2.  Electrical Specifications** 

## **Table 2.1.  Electrical Specifications** 

VDD = 1.8 V, 2.5 or 3.3 V ± 5%, TA = –40 to 85 ºC 

|**Parameter**|**Symbol**|**Test Condition/Comment**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|Temperature Range|TA||–40|—|85|ºC|
|Frequency Range|FCLK|LVPECL, LVDS, CML|0.2|—|800|MHz|
|||HCSL|0.2|—|400|MHz|
|||CMOS, Dual CMOS|0.2|—|250|MHz|
|Supply Voltage|VDD|3.3 V|3.135|3.3|3.465|V|
|||2.5 V|2.375|2.5|2.625|V|
|||1.8 V|1.71|1.8|1.89|V|
|Supply Current|IDD|LVPECL (output enabled)|—|103|—|mA|
|||LVDS/CML (output enabled)|—|81|—|mA|
|||HCSL (output enabled)|—|98|—|mA|
|||CMOS (output enabled)|—|83|—|mA|
|||Dual CMOS (output enabled)|—|83|—|mA|
|||Tristate Hi-Z (output disabled)|—|68|—|mA|
|Temperature Stability||Frequency stability Grade A|–20|—|20|ppm|
|Total Stability1|FSTAB|Frequency stability Grade A|–50|—|50|ppm|
|Rise/Fall Time<br>(20% to 80% VDD)|TR/TF|LVPECL/LVDS/CML|—|—|350|ps|
|||CMOS / Dual CMOS<br>(CL= 15 pF)|0.8|—|2.5|ns|
|||HCSL, FCLK>50 MHz|—|—|700|ps|
|Phase Jitter (RMS), 12kHz – 20MHz<br>Differential formats|ϕJ|FCLK≥ 200 MHz|—|80|150|fs|
|||100 MHz ≤ FCLK< 200 MHz|—|110|150|fs|
|Duty Cycle|DC|All formats|45|—|55|%|
|Output Enable (OE)2|VIH||0.75 × VDD|—|—|V|
||VIL||—|—|0.5|V|
||TD|Output Disable Time|—|—|3|µs|
||TE|Output Enable Time|—|—|20|µs|
|Powerup Time|tOSC|Time until output frequency (FCLK)<br>within spec|—|—|10|ms|
|LVPECL Output Option3|VOC|Mid-level|VDD– 1.42|—|VDD– 1.25|V|
||VO|Swing (diff)|1.1|—|1.9|VPP|
|LVDS Output Option4|VOC|Mid-level|1.125|1.20|1.275|V|
||VO|Swing (diff)|0.5|0.7|0.9|VPP|



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Preliminary Rev. 0.3  |  2 

Si545 Data Sheet Electrical Specifications 

|**Parameter**|**Symbol**|**Test Condition/Comment**|**Min**|**Typ**|**Max**|**Unit**|
|---|---|---|---|---|---|---|
|HCSL Output Option5|VOH|Output voltage high|TBD|700|850|mV|
||VOL|Output voltage low|–150|0|150|mV|
||VSE|Swing (single-ended)|660|700|850|mV|
||VC|Crossing voltage|250|350|550|mV|
|CMOS Output Option|VOH||0.90 × VDD|—|—|V|
||VOL||—|—|0.10 × VDD|V|
|**Notes:**<br>1. Total Stability includes ±20 ppm temperature stability, initial accuracy, load pulling, VDD variation, and aging for 10 yrs at 70 ºC.<br>2. OE includes a 50 kΩ pull-up to VDD for OE active high. Includes a 50 kΩ pull-down to GND for OE active low.<br>3. 50 Ω to VDD– 2.0 V.<br>4. Rterm= 100 Ω (differential).<br>5. 50 Ω to GND.|||||||



## **Table 2.2.  Environmental Compliance and Package Information** 

|**Parameter**|**Test Condition**|
|---|---|
|Mechanical Shock|MIL-STD-883, Method 2002|
|Mechanical Vibration|MIL-STD-883, Method 2007|
|Solderability|MIL-STD-883, Method 2003|
|Gross and Fine Leak|MIL-STD-883, Method 1014|
|Resistance to Solder Heat|MIL-STD-883, Method 2036|
|Moisture Sensitivity Level (MSL)|1|
|Contact Pads|Gold over Nickel|
|**Note:**<br>1. For additional product information not listed in the data sheet (e.g. RoHS Certifications, MDDS data, qualification data, REACH<br>Declarations, ECCN codes, etc.), refer to our "Corporate Request For Information" portal found here:www.silabs.com/support/<br>quality/Pages/RoHSInformation.aspx.||



**Table 2.3.  Thermal Conditions** 

|**Package**|**Symbol**|**Test Condition**|**Value**|**Unit**|
|---|---|---|---|---|
|3.2×5 mm 6-pin CLCC|ΘJA|Still air|TBD|ºC/W|
||ΘJB|Still air|TBD|ºC/W|
||ΘJC|Still air|TBD|ºC/W|



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Preliminary Rev. 0.3  |  3 

Si545 Data Sheet Electrical Specifications 

## **Table 2.4.  Absolute Maximum Ratings[1]** 

|**Parameter**|**Symbol**|**Rating**|**Unit**|
|---|---|---|---|
|Maximum Operating Temp.|TAMAX|95|ºC|
|Storage Temperature|TS|–55 to 125|ºC|
|Supply Voltage|VDD|–0.5 to 3.8|ºC|
|Input Voltage|VIN|0.5 to VDD+ 0.3|V|
|ESD HBM (JESD22-A114)|HBM|2.0|kV|
|Solder Temperature2|TPEAK|260|ºC|
|Solder Time at TPEAK2|TP|20–40|sec|
|**Notes:**<br>1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specification<br>compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device<br>reliability.<br>2. The device is compliant with JEDEC J-STD-020.||||



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Preliminary Rev. 0.3  |  4 

Si545 Data Sheet Dual CMOS Buffer 

## **3.  Dual CMOS Buffer** 

Dual CMOS output format ordering options support either complementary or in-phase output signals. This feature enables replacement of multiple XOs with a single Si545 device. 

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~<br>Complementary<br>Outputs<br>~<br>In-Phase<br>Outputs<br>**----- End of picture text -----**<br>


**Figure 3.1.  Integrated 1:2 CMOS Buffer Supports Complementary or In-Phase Outputs** 

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Preliminary Rev. 0.3  |  5 

Si545 Data Sheet Package Outline 

## **4.  Package Outline** 

The figure below illustrates the package details for the 3.2 × 5 mm Si545. The table below lists the values for the dimensions shown in the illustration. 

**Figure 4.1.  Si545 Outline Diagram** 

**Table 4.1.  Package Diagram Dimensions (mm)** 

|**Dimension**|**Min**|**Nom**|**Max**|
|---|---|---|---|
|A|1.06|1.17|1.28|
|b|0.54|0.64|0.74|
|c|0.35|0.45|0.55|
|D|3.20 BSC|||
|D1|2.55|2.60|2.65|
|e|1.27 BSC|||
|E|5.00 BSC|||
|E1|4.35|4.40|4.45|
|H|0.45|0.55|0.65|
|L|0.90|1.00|1.10|
|L1|0.05|0.10|0.15|
|p|1.17|1.27|1.37|
|R|0.32 REF|||
|aaa|0.15|||
|bbb|0.15|||
|ccc|0.10|||
|ddd|0.10|||
|eee|0.05|||
|**Notes:**<br>1. All dimensions shown are in millimeters (mm) unless otherwise noted.<br>2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.||||



## **Notes:** 

1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 

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Preliminary Rev. 0.3  |  6 

Si545 Data Sheet PCB Land Pattern 

## **5.  PCB Land Pattern** 

The figure below illustrates the 3.2 × 5.0 mm PCB land pattern for the Si545. The table below lists the values for the dimensions shown in the illustration. 

**Figure 5.1.  Si545 PCB Land Pattern** 

**Table 5.1.  PCB Land Pattern Dimensions (mm)** 

|**Dimension**|**(mm)**|
|---|---|
|C1|2.60|
|E|1.27|
|X1|0.80|
|Y1|1.70|



## **Notes:** 

General 

1. All dimensions shown are in millimeters (mm) unless otherwise noted. 

2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 

3. This Land Pattern Design is based on the IPC-7351 guidelines. 

4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. 

## Solder Mask Design 

5. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. 

## Stencil Design 

6. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 

7. The stencil thickness should be 0.125 mm (5 mils). 

8. The ratio of stencil aperture to land pad size should be 1:1. 

## Card Assembly 

9. A No-Clean, Type-3 solder paste is recommended. 

10. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. 

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Preliminary Rev. 0.3  |  7 

Si545 Data Sheet Top Marking 

## **6.  Top Marking** 

The figure below illustrates the mark specification for the Si545. The table below lists the line information. 

**Figure 6.1.  Mark Specification** 

**Table 6.1.  Si545 Top Mark Description** 

|**Line**|**Position**|**Description**|
|---|---|---|
|1|1–8<br>|"Si545", xxx = Ordering Option 1, Option 2, Option 3 (e.g. Si545AAA)|
|2|1–7<br> <br>|Frequency Code<br>(e.g. 100M000 or 6-digit custom code as described in the Ordering Guide)|
|3|**Trace Code**||
||Position 1<br>|Pin 1 orientation mark (dot)|
||Position 2<br>|x = Product Revision (A)|
||Position 3–5<br>|Tiny Trace Code (3 alphanumeric characters per assembly release instructions)|
||Position 6–7<br>|Year (last two digits of the year), to be assigned by assembly site (ex: 2017 = 17)|
||Position 8–9<br>|Calendar Work Week number (1–53), to be assigned by assembly site|



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Preliminary Rev. 0.3  |  8 

Si545 Data Sheet Revision History 

## **7.  Revision History** 

## **7.1  Revision 0.3** 

April 12, 2017 

- Initial release. 

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Preliminary Rev. 0.3  |  9 

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